A performance evaluation method, device, apparatus and storage medium
By acquiring CPU architecture load data and normalized computation load, the computing performance indicators of different hardware platforms are evaluated, solving the problem of hardware adaptation complexity of terminal devices and realizing cross-platform performance evaluation and optimization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2025-01-20
- Publication Date
- 2026-07-21
AI Technical Summary
The complexity of load characteristics and hardware compatibility between terminal devices from different manufacturers and different models from the same manufacturer makes it difficult to quickly migrate flagship model technology to mid-to-low-end models, affecting the performance consistency and optimization of the overall product line.
This paper provides a performance evaluation method that obtains CPU architecture load data, calculates normalized load and frame length, evaluates computing performance indicators of different hardware platforms, including CPU core frequency and GPU computing power, and achieves cross-platform load performance evaluation.
It improves the accuracy of terminal device load performance assessment, helps enterprises adapt to ever-changing chip architectures and market demands, and ensures performance consistency and optimization across different hardware platforms.
Smart Images
Figure CN122431996A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of terminal technology, and in particular to a performance evaluation method, apparatus, device and storage medium. Background Technology
[0002] In recent years, the mobile terminal market has evolved rapidly, with manufacturers generally adopting a "mass marketing strategy," launching a large number of diverse models to seize market share. Most R&D resources and funds are concentrated on developing flagship models to showcase technological strength and market competitiveness. However, this has also brought new challenges: how to quickly transfer the advanced technologies and features of flagship models to mid-range and low-end models, achieving technology sharing and balanced development of the overall product line.
[0003] Because different manufacturers use different chip architectures, and even different models from the same manufacturer may be based on different processor platforms, this leads to complexity in terms of load characteristics and hardware compatibility of terminal devices. To ensure consistent and optimized performance across different hardware platforms, there is an urgent need for a method that can quickly assess load performance across platforms. Summary of the Invention
[0004] The purpose of this application is to provide a performance evaluation method, apparatus, device, and storage medium to solve the technical problems in the prior art.
[0005] In a first aspect, embodiments of this application provide a performance evaluation method, the method comprising: acquiring load data of a target frame image of a current central processing unit (CPU) architecture; acquiring the computing power of a first core frequency, a second core frequency, and the computing power of a GPU in the target CPU architecture; obtaining a normalized load of the target frame image based on the load data; obtaining a first frame length based on the target thread, normalized load, and first core frequency corresponding to the target frame image; obtaining a second frame length based on the non-target thread, normalized load, and second core frequency corresponding to the target frame image; obtaining a third frame length based on the computing power of the GPU; and obtaining a first computing power performance index of the target CPU architecture based on the first frame length, the second frame length, and the third frame length.
[0006] In this application embodiment, a load performance evaluation method applicable to different hardware platforms is constructed, which improves the accuracy of the load performance evaluation method for terminal devices. Through efficient performance simulation methods, enterprises can adapt to the ever-changing chip architecture and market demands.
[0007] In some possible embodiments, the load data includes: computing power at each frequency point, runtime at each frequency point, and a normalized load of the target frame image obtained from the load data, including: obtaining the computing power and runtime of each frequency point from the load data; obtaining the load of each frequency point based on the computing power and runtime of the frequency point; obtaining the normalized load based on the load of each frequency point and the computing power of the target frequency point; the target frequency point is the frequency point with the highest computing power of the large core in the current CPU architecture.
[0008] In this embodiment of the application, the load of the critical thread is normalized to the specified computing power by calculating the normalized load.
[0009] In some possible embodiments, before obtaining the first frame length based on the target thread corresponding to the target frame image and the first core frequency point, the method further includes: obtaining the first load of the first thread and the second load of the second thread corresponding to the target frame image; if the first load is greater than the second load, then the first thread is taken as the target thread and the second thread is taken as a non-target thread; if the first load is less than or equal to the second load, then the second thread is taken as the target thread and the first thread is taken as a non-target thread.
[0010] In this embodiment of the application, by identifying the target thread and non-target threads, the target thread is scheduled to run at the target frequency with the highest computing power, thereby enabling the evaluation of the performance ceiling of the target architecture.
[0011] In some possible embodiments, obtaining the first frame length based on the target thread corresponding to the target frame image and the first core frequency point includes: processing the target frame image using the target thread at the first core frequency point to obtain the first frame length.
[0012] In some possible embodiments, the second frame length is obtained based on the non-target thread corresponding to the target frame image and the second core frequency point, including: processing the target frame image using the non-target thread at the second core frequency point to obtain the second frame length.
[0013] In some possible embodiments, after obtaining the normalized load of the target frame image based on the load data, the method further includes: obtaining the average computing power supply ratio of the current CPU architecture based on the normalized load; obtaining the first CPU core computing power of the target CPU architecture; obtaining the releaseable computing power corresponding to the target CPU architecture based on the average computing power supply ratio and the first CPU core computing power; obtaining the frame length corresponding to each thread under the target CPU architecture based on the releaseable computing power; and obtaining the second computing power performance index of the target CPU architecture based on the frame length corresponding to each thread under the target CPU architecture.
[0014] In this embodiment of the application, the performance evaluation of the CPU architecture under the current scheduling scheme is achieved through the above method.
[0015] In some possible embodiments, obtaining the frame length corresponding to each thread under the target CPU architecture based on the releasable computing power includes: determining the frame length of the first thread and the frame length of the second thread based on the releasable computing power; obtaining the GPU computing power of the target CPU architecture; obtaining the frame length of the GPU of the target CPU architecture based on the releasable computing power and the GPU computing power of the target CPU architecture; and using the frame length of the first thread, the frame length of the second thread, and the frame length of the GPU of the target CPU architecture as the frame length corresponding to each thread under the target CPU architecture.
[0016] In this embodiment of the application, the frame length of each thread is calculated to obtain the frame length of each thread after the change in computing power, and then the performance of the target CPU architecture can be evaluated based on the frame length.
[0017] In some possible embodiments, the average computing power supply ratio of the current CPU architecture is obtained based on the normalized load, including: obtaining the runtime of each frequency point from the load information; obtaining the cumulative duration based on the runtime of each frequency point; obtaining the average computing power based on the normalized load and the cumulative duration; and obtaining the average computing power supply ratio based on the average computing power and the computing power of the target frequency point, wherein the target frequency point is the frequency point with the highest computing power of the large cores in the current CPU architecture.
[0018] In this embodiment, the average computing power supply ratio is calculated to keep the average computing power supply ratio constant. The frame length of each thread under different computing power conditions is calculated, and the performance of the target CPU architecture under the current scheduling scheme is evaluated by comparing the frame length of each thread.
[0019] In some possible embodiments, after obtaining the normalized load of the target frame image based on the load data, the method further includes: obtaining the available frequency points in the current CPU architecture; determining the frame length corresponding to each available frequency point; obtaining a first frequency point based on the frame length corresponding to each available frequency point; determining the CPU computing power and GPU computing power of the target CPU architecture at the first frequency point; processing the first thread using the first frequency point based on the CPU computing power to obtain a fourth frame length; and processing the second thread using the first frequency point based on the CPU computing power to obtain a fifth frame length; and obtaining a sixth frame length corresponding to the GPU based on the GPU computing power; and obtaining a third computing power performance index of the target CPU architecture based on the fourth frame length, the fifth frame length, and the sixth frame length.
[0020] In this embodiment, the frame length of each thread under different computing power conditions is calculated, thereby enabling the performance evaluation of the target CPU architecture under the current scheduling scheme by comparing the frame lengths of each thread.
[0021] In some possible embodiments, obtaining the first frequency point based on the frame length of each available frequency point includes: taking the frequency points with a frame length less than a preset frame length among the available frequency points as the second frequency points; obtaining the power consumption characteristic value corresponding to each second frequency point based on the computing power of each second frequency point and the frame length corresponding to each second frequency point; and obtaining the first frequency point based on the power consumption characteristic value corresponding to each second frequency point.
[0022] Secondly, embodiments of this application also provide a performance evaluation apparatus, the apparatus comprising:
[0023] The acquisition module is used to acquire the load data of the target frame image of the current central processing unit (CPU) architecture; and to acquire the computing power of the first core frequency, the computing power of the second core frequency, and the computing power of the GPU in the target CPU architecture.
[0024] The normalization module is used to obtain the normalized load of the target frame image based on the load data;
[0025] The frame length determination module is used to obtain the first frame length based on the target thread, normalized load, and first core frequency point corresponding to the target frame image; and,
[0026] The second frame length is obtained based on the non-target thread corresponding to the target frame image, the normalized load, and the second core frequency; and the third frame length is obtained based on the computing power of the GPU.
[0027] The performance evaluation module is used to obtain the first computing power performance index of the target CPU architecture based on the first frame length, the second frame length, and the third frame length.
[0028] In some possible embodiments, the frame length determination module is specifically used to: obtain the computing power and runtime of each frequency point from the load data; for each frequency point, obtain the load of the frequency point based on the computing power and runtime of the frequency point; obtain the normalized load based on the load of each frequency point and the computing power of the target frequency point; the target frequency point is the frequency point with the highest computing power of the large core in the current CPU architecture.
[0029] In some possible embodiments, the frame length determination module is further configured to: obtain the first load of the first thread and the second load of the second thread corresponding to the target frame image; if the first load is greater than the second load, then the first thread is designated as the target thread and the second thread as a non-target thread; if the first load is less than or equal to the second load, then the second thread is designated as the target thread and the first thread as a non-target thread.
[0030] In some possible embodiments, the frame length determination module is specifically used to: process the target frame image using the target thread at the first core frequency point to obtain the first frame length.
[0031] In some possible embodiments, the frame length determination module is specifically used to: process the target frame image using a non-target thread at the second core frequency point to obtain the second frame length.
[0032] In some possible embodiments, the frame length determination module is further configured to: obtain the average computing power supply ratio of the current CPU architecture based on the normalized load; obtain the first CPU core computing power of the target CPU architecture; obtain the releaseable computing power corresponding to the target CPU architecture based on the average computing power supply ratio and the first CPU core computing power; obtain the frame length corresponding to each thread under the target CPU architecture based on the releaseable computing power; the performance evaluation module is further configured to obtain the second computing power performance index of the target CPU architecture based on the frame length corresponding to each thread under the target CPU architecture.
[0033] In some possible embodiments, the frame length determination module is specifically used to: determine the frame length of the first thread and the frame length of the second thread based on the available computing power; obtain the GPU computing power of the target CPU architecture; obtain the frame length of the GPU of the target CPU architecture based on the available computing power and the GPU computing power of the target CPU architecture; and use the frame length of the first thread, the frame length of the second thread, and the frame length of the GPU of the target CPU architecture as the frame length corresponding to each thread under the target CPU architecture.
[0034] In some possible embodiments, the frame length determination module is specifically used to: obtain the runtime of each frequency point from the load information; obtain the cumulative duration based on the runtime of each frequency point; obtain the average computing power according to the normalized load and the cumulative duration; and obtain the average computing power supply ratio according to the average computing power and the computing power of the target frequency point, wherein the target frequency point is the frequency point with the highest computing power of the large core in the current CPU architecture.
[0035] In some possible embodiments, the frame length determination module is further configured to: obtain available frequency points in the current CPU architecture; determine the frame length corresponding to each available frequency point; obtain a first frequency point based on the frame length corresponding to each available frequency point; determine the CPU computing power and GPU computing power of the target CPU architecture at the first frequency point; process the first thread using the first frequency point based on the CPU computing power to obtain a fourth frame length; and process the second thread using the first frequency point based on the CPU computing power to obtain a fifth frame length; and obtain a sixth frame length corresponding to the GPU based on the GPU computing power; and obtain a third computing power performance index of the target CPU architecture based on the fourth frame length, the fifth frame length, and the sixth frame length.
[0036] In some possible embodiments, the frame length determination module is specifically used to: take the available frequency points with a frame length less than a preset frame length as the second frequency points; obtain the power consumption characteristic value corresponding to each second frequency point based on the computing power of each second frequency point and the frame length corresponding to each second frequency point; and obtain the first frequency point based on the power consumption characteristic value corresponding to each second frequency point.
[0037] Fifthly, another embodiment of this application also provides an electronic device, including at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform any of the methods provided in the first or second aspect of this application.
[0038] Sixthly, another embodiment of this application also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program for causing a computer to perform any of the methods provided in the first or second aspect of this application.
[0039] In a seventh aspect, another embodiment of this application also provides a computer program product, the computer program product comprising: computer program code, which, when run on a computer, causes the computer to perform any of the methods provided in the first or second aspect embodiments described above.
[0040] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description
[0041] Figure 1 This is a schematic diagram illustrating an application scenario of a performance evaluation method provided in an embodiment of this application;
[0042] Figure 2 This is a schematic diagram of the overall process of a performance evaluation method provided in an embodiment of this application;
[0043] Figure 3 A schematic representation of the energy efficiency of a CPU for a performance evaluation method provided in this application embodiment;
[0044] Figure 4 A schematic diagram illustrating the process of obtaining the normalized load of a target frame image based on load data in a performance evaluation method provided in this application embodiment;
[0045] Figure 5 A schematic diagram of the current CPU architecture and the target CPU architecture for a performance evaluation method provided in this application embodiment;
[0046] Figure 6 A schematic diagram of thread scheduling for a performance evaluation method provided in this application embodiment;
[0047] Figure 7This is a flowchart illustrating the performance evaluation method for a target CPU architecture under the current scheduling scheme, provided in an embodiment of this application.
[0048] Figure 8 A schematic diagram illustrating the process of obtaining the average computing power supply ratio of the current CPU architecture based on normalized load, as provided in an embodiment of this application;
[0049] Figure 9 Another schematic diagram of thread scheduling for a performance evaluation method provided in this application embodiment;
[0050] Figure 10 A flowchart illustrating the performance limit of a target CPU architecture under acceptable power consumption, provided in an embodiment of this application;
[0051] Figure 11 Another schematic diagram of thread scheduling for a performance evaluation method provided in this application embodiment;
[0052] Figure 12 A schematic diagram of an apparatus for a performance evaluation method provided in an embodiment of this application;
[0053] Figure 13 This is a performance evaluation diagram illustrating a performance evaluation method provided in an embodiment of this application;
[0054] Figure 14 This is a schematic diagram of an electronic device for a performance evaluation method provided in an embodiment of this application. Detailed Implementation
[0055] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0056] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.
[0057] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.
[0058] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.
[0059] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.
[0060] In recent years, the mobile terminal market has evolved rapidly, with manufacturers generally adopting a "mass marketing strategy," launching a large number of diverse models to seize market share. Most R&D resources and funds are concentrated on developing flagship models to showcase technological strength and market competitiveness. However, this has also brought new challenges: how to quickly transfer the advanced technologies and features of flagship models to mid-range and low-end models, achieving technology sharing and balanced development of the overall product line.
[0061] Because different manufacturers use different chip architectures, and even different models from the same manufacturer may be based on different processor platforms, this leads to complexity in terms of load characteristics and hardware compatibility of terminal devices. To ensure consistent and optimized performance across different hardware platforms, there is an urgent need for a method that can quickly assess load performance across platforms.
[0062] Meanwhile, terminal chip architecture is constantly evolving. With advancements in semiconductor technology and continuous improvements in chip computing power, balancing high performance, low power consumption, and cost control has become increasingly important. Future terminal devices will need to maintain high performance while minimizing energy consumption and manufacturing costs.
[0063] In view of this, embodiments of this application provide a performance evaluation method, apparatus, device, and storage medium to solve the above-mentioned problems. The inventive concept of this application can be summarized as follows: acquiring load data of a target frame image based on the current Central Processing Unit (CPU) architecture; and acquiring the computing power of a first core frequency, a second core frequency, and the computing power of a Graphics Processing Unit (GPU) in the target CPU architecture; obtaining a normalized load of the target frame image based on the load data; obtaining a first frame length based on the target thread corresponding to the target frame image, the normalized load, and the first core frequency; obtaining a second frame length based on the non-target thread corresponding to the target frame image, the normalized load, and the second core frequency; obtaining a third frame length based on the GPU computing power; and obtaining a first computing power performance index of the target CPU architecture based on the first frame length, the second frame length, and the third frame length.
[0064] In this application embodiment, a load performance evaluation method applicable to different hardware platforms is constructed, which improves the accuracy of the load performance evaluation method for terminal devices. Through efficient performance simulation methods, enterprises can adapt to the ever-changing chip architecture and market demands.
[0065] For ease of understanding, the performance evaluation method provided by an embodiment of this application will be described in detail below with reference to the accompanying drawings:
[0066] First, such as Figure 1 As shown, the application scenario of a performance evaluation method provided in this application embodiment is illustrated, such as... Figure 1 As shown: the load data of the target frame image of the current CPU architecture is obtained, the load data is obtained through the energy efficiency table corresponding to different CPU architectures, the load data corresponding to the CPU architecture in different scenarios is obtained, and the obtained relevant load data is input into a performance evaluation method provided in the embodiment of this application. The output is the computing power performance index corresponding to different CPU architectures in the corresponding scenario.
[0067] The description in this application focuses on a single CPU, but those skilled in the art should understand that the CPU shown is intended to illustrate the operation of the CPU involved in the technical solutions of this application, and is not intended to imply any limitation on the number, type, or location of CPUs. It should be noted that adding additional modules to or removing individual modules from the illustrated environment will not change the underlying concept of the exemplary embodiments of this application.
[0068] It should be noted that the performance evaluation method proposed in this application is not only applicable to... Figure 1 The application scenarios shown are also applicable to any device that requires performance evaluation.
[0069] like Figure 2 The diagram shown is a schematic representation of the overall process of a performance evaluation method provided in an embodiment of this application, wherein:
[0070] In step 201: obtain the load data of the target frame image of the current CPU architecture; and obtain the computing power of the first core frequency, the computing power of the second core frequency, and the GPU computing power in the target CPU architecture.
[0071] In this embodiment, load data can be obtained through a pre-set CPU energy efficiency table. Load data includes, but is not limited to: computing power at each frequency, runtime at each frequency, number of CPU cores, CPU core type, CPU frequency, and power consumption at each frequency. The target CPU architecture is the CPU architecture for which performance evaluation is required. The first core frequency is the frequency with the highest computing power in the target CPU architecture, and the second core frequency is the frequency with the second highest computing power. Different CPU cores may have the same frequency; therefore, when obtaining the CPU frequency and related information, it is necessary to obtain each frequency within each CPU core and its related information.
[0072] For example: Figure 3 As shown, the CPU energy efficiency table includes: CPU core type (cpu_type), CPU frequency (frequency_khz), computing power per frequency (capacity_mhz), computing power per core (capacity_dmips_mhz), normalized computing power (capacity), normalized computing power per core at the maximum frequency (scale_cpu), and power consumption per frequency (power_mw).
[0073] In step 202: the normalized load of the target frame image is obtained based on the load data.
[0074] In this embodiment of the application, the normalized load corresponding to the target frame image can be determined based on the computing power of each frequency point in the load data and the runtime of each frequency point.
[0075] In some possible embodiments, the normalized load of the target frame image is obtained based on the load data, specifically as follows: Figure 4 The steps shown are as follows:
[0076] In step 401: Obtain the computing power and runtime of each frequency point from the load data.
[0077] In the embodiments of this application, normalized load is a parameter that normalizes the load of critical threads to a specified computing power at the frame level, and describes the size of the load with a unified metric.
[0078] In step 402: For each frequency point, the load of the frequency point is obtained based on the computing power and runtime of the frequency point.
[0079] In this embodiment, the product of computing power and runtime at each frequency point is used as the load of each frequency point. In this embodiment, the computing power of frequency point i is denoted as capacity. i Runtime is denoted as t i .
[0080] In step 403: the normalized load is obtained based on the load of each frequency point and the computing power of the target frequency point; the target frequency point is the frequency point with the highest computing power of the large core in the current CPU architecture.
[0081] In the embodiments of this application, Formula 1 can be used to characterize Figure 4 The process shown, wherein:
[0082]
[0083] Among them, load thread For normalized load, t i The runtime of frequency point i, capacity i For the computing power at frequency i, capacity base This represents the computing power at the highest frequency of the large cores in the current CPU architecture.
[0084] In other embodiments, besides using Formula 1 to obtain the normalized load, the load can also be... thread *capacity base As a normalized load.
[0085] In step 203: the first frame length is obtained based on the target thread, normalized load and first core frequency point corresponding to the target frame image.
[0086] In the embodiment of the application, the time taken to process the target frame image using the target thread at the first core frequency point is used as the first frame length. After obtaining the target thread and the first core frequency point, the target thread is scheduled to be processed at the first core frequency point.
[0087] In step 204: the second frame length is obtained based on the non-target thread, normalized load, and second core frequency corresponding to the target frame image, and the third frame length is obtained based on the computing power of the GPU.
[0088] In this embodiment, the time taken to process the target frame image using a non-target thread at the second core frequency is taken as the second frame duration, and the time taken by the GPU to process the target frame image is taken as the third frame duration. After obtaining the non-target thread and the second core frequency, the non-target thread is scheduled to be processed at the second core frequency.
[0089] It is understood that this application does not limit the execution order of steps 203 and 204. Step 203 can be executed first and then step 204, or step 204 can be executed first and then step 203, or steps 203 and 204 can be executed simultaneously.
[0090] In step 205: Based on the first frame length, the second frame length, and the third frame length, the first computing power performance index of the target CPU architecture is obtained.
[0091] In this embodiment of the application, after obtaining the first frame length, the second frame length and the third frame length, the obtained frame length can be compared with the preset target frame length to determine whether frame dropping has occurred. Then, the performance limit of the target CPU architecture can be evaluated by the frequency and degree of frame dropping, i.e., the first computing power performance index.
[0092] To facilitate a further understanding of the above Figure 2 The steps are described in detail below:
[0093] In some possible embodiments, step 203 can specifically use Formula 2 to obtain the first frame length, where:
[0094]
[0095] Where T1 is the length of the first frame, and capacity basem1 The load is the computing power at the highest frequency of the large cores in the target CPU architecture. thread To normalize the load, sleep1 is the sleep duration of the target thread.
[0096] In some possible embodiments, step 204 can specifically use Formula 3 to obtain the second frame length, where:
[0097]
[0098] Where T2 is the length of the first frame, and capacity basem2 For the computing power of the second highest frequency point of the large core in the target CPU architecture, load thread To normalize the load, sleep2 is the sleep duration for non-target threads.
[0099] In some possible embodiments, determining the third frame length corresponding to the GPU can be implemented as follows: obtaining the computing power and runtime of each frequency point in the GPU; the load of each frequency point in the GPU can be obtained based on the computing power and runtime of each frequency point; the GPU load can be obtained by accumulating the load of each frequency point in the GPU; obtaining the computing power of the core frequency point in the GPU; the GPU runtime can be obtained based on the GPU load and the computing power of the core frequency point in the GPU; and the third frame length can be obtained based on the GPU runtime and the GPU sleep time.
[0100] In some possible implementations, in order to assess the performance ceiling of the target CPU architecture, it is necessary to schedule the thread with the highest load (the target thread) to the frequency with the highest computing power in the target CPU architecture (i.e., the first core frequency). Therefore, in implementation... Figure 2 Before step 203, it is necessary to first determine the target thread and the non-target thread. Specifically, this can be implemented as follows: obtain the first load of the first thread and the second load of the second thread corresponding to the target frame image; if the first load is greater than the second load, then the first thread is regarded as the target thread and the second thread is regarded as the non-target thread; if the first load is less than or equal to the second load, then the second thread is regarded as the target thread and the first thread is regarded as the non-target thread.
[0101] In this embodiment, the thread with the highest load is designated as the target thread, and the thread with the lowest load is designated as a non-target thread. This application does not limit the specific types of the first and second threads, which include, but are not limited to: the HarmonyOS single-framework application graphics rendering service thread (RS) and the application interaction processing thread (User Interface Thread, UI).
[0102] For ease of understanding, the following is... Figure 2 The method shown is illustrated with examples, such as: Figure 5 As shown, the current CPU architecture includes a small core (Clock1), a medium core (Clock2), and a large core (Clock3). The target CPU architecture includes a small core (Clock1), a medium core (Clock2), a large core (Clock3), and a super-large core (Clock4), as follows: Figure 6 As shown, the UI is currently running at the frequency of the large core, and the RS is running at the frequency of the medium core. It is determined that the UI is not the target thread and the RS is the target thread. It is determined that the first core frequency is in the super large core and the second core frequency is in the second largest core. Then, the RS is scheduled to run at the first core frequency and the UI is scheduled to run at the second core frequency. The first frame length corresponding to the RS and the second frame length corresponding to the UI are determined at this time. At the same time, the third frame length corresponding to the GPU in the target architecture can be obtained. Then, the performance limit of the target CPU architecture can be evaluated based on the first frame length, the second frame length and the third frame length.
[0103] In some possible embodiments, this application also provides a method for evaluating the performance of a target CPU architecture under a current scheduling scheme, which can be implemented as follows: Figure 7 The steps shown are as follows:
[0104] In step 701: the average computing power supply ratio of the current CPU architecture is obtained based on the normalized load.
[0105] In this embodiment of the application, by Figure 2Following step 202, the average computing power supply ratio corresponding to the current CPU architecture can be obtained based on the normalized load. By keeping the average computing power supply ratio constant, the frame length of each thread under different computing power conditions is calculated. The performance of the target CPU architecture under the current scheduling scheme is evaluated by comparing the frame lengths of each thread. The average computing power supply ratio refers to the ratio of the average computing power of the frame to the computing power at the highest frequency point of the large cores in the CPU architecture.
[0106] In some possible embodiments, the average computing power supply ratio of the current CPU architecture is obtained based on the normalized load, which can be specifically implemented as follows: Figure 8 The steps shown are as follows:
[0107] In step 801: Obtain the runtime of each frequency point from the load information.
[0108] The specific implementation method of this step is the same as that of step 201, and will not be described again here.
[0109] In step 802: the cumulative duration is obtained based on the running time of each frequency point.
[0110] In this embodiment of the application, after obtaining the runtime of each frequency point, the runtime of each frequency point is accumulated, and the accumulated value is used as the cumulative duration.
[0111] In step 803: the average computing power is obtained based on the normalized load and the cumulative duration.
[0112] In this embodiment of the application, after obtaining the cumulative duration, the ratio of normalized load to cumulative duration is used as the average computing power.
[0113] In step 804: the average computing power supply ratio is obtained based on the average computing power and the computing power of the target frequency. The target frequency is the frequency with the highest computing power of the large core in the current CPU architecture.
[0114] In this embodiment of the application, after obtaining the average computing power, the ratio of the average computing power to the computing power of the target frequency point is used as the average computing power supply ratio.
[0115] In step 702: Obtain the computing power of the first CPU core of the target CPU architecture.
[0116] In this embodiment of the application, the first CPU is the CPU with the highest computing power in the target CPU architecture, and the computing power of the first CPU core can be obtained according to the CPU energy efficiency table corresponding to the target CPU architecture.
[0117] In step 703: Based on the average computing power supply ratio and the computing power of the first CPU core, the releaseable computing power corresponding to the target CPU architecture is obtained.
[0118] In this embodiment of the application, the product of the average computing power supply ratio and the computing power of the first CPU core is used as the releaseable computing power corresponding to the target CPU architecture.
[0119] In step 704: the frame length corresponding to each thread under the target CPU architecture is obtained based on the releasable computing power.
[0120] In this application embodiment, the threads under the target COU architecture include, but are not limited to: the first thread, the second thread, and the GPU.
[0121] In some possible embodiments, the frame length corresponding to each thread under the target CPU architecture is obtained based on the releasable computing power. Specifically, this can be implemented as follows: determine the frame length of the first thread and the frame length of the second thread based on the releasable computing power; obtain the GPU computing power of the target CPU architecture; obtain the frame length of the GPU of the target CPU architecture based on the releasable computing power and the GPU computing power of the target CPU architecture; and use the frame length of the first thread, the frame length of the second thread, and the frame length of the GPU of the target CPU architecture as the frame length corresponding to each thread under the target CPU architecture.
[0122] In this embodiment, the process of obtaining the GPU frame length based on the releasable computing power is the same as the process of obtaining the third frame length of the GPU described above. The GPU frame length is obtained by replacing the GPU core frequency computing power with the releasable computing power during the calculation of the third frame length. The releasable computing power can replace the capacity in Formula 2 above. basem1 This allows us to obtain the frame length of the first thread. Similarly, we can replace the capacity in formula 3 with the releasable computing power. basem2 This allows us to obtain the frame length of the second thread.
[0123] In step 705: Based on the frame length corresponding to each thread under the target CPU architecture, the second computing power performance index of the target CPU architecture is obtained.
[0124] After obtaining the frame lengths of the first thread, the second thread, and the GPU, these frame lengths can be compared with pre-set frame lengths to determine the performance of the target CPU architecture under the current scheduling scheme, i.e., the second computing power performance indicator.
[0125] For example: Figure 9 As shown, the target CPU architecture processes the UI with a frame length of L1 and the RS with a frame length of L2. If... Figure 7 After scheduling as shown, the frame length for processing the UI on the target CPU architecture is determined to be L11, and the frame length for processing the RS is determined to be L22. Since the frame lengths for both UI and RS processing on the target CPU architecture are reduced, it can be concluded that the computing power of the target CPU architecture has been improved. If... Figure 7After scheduling in the manner shown, the frame length for processing the UI of the target CPU architecture is determined to be L111, and the frame length for processing the RS is determined to be L222. Since the frame lengths for processing both the UI and RS of the target CPU architecture have increased, it can be determined that the computing power of the target CPU architecture has decreased.
[0126] In some possible embodiments, this application also provides a method for evaluating the performance ceiling of a target CPU architecture when power consumption is acceptable, specifically implemented as follows: Figure 10 The steps shown are as follows:
[0127] In step 1001: Obtain the available frequency points in the current CPU architecture.
[0128] In this embodiment of the application, in order to evaluate the performance limit when the power consumption is acceptable, it is necessary to limit the use of large cores in the CPU, that is, to schedule threads to run at frequencies with lower power consumption. Therefore, the available frequencies can be some preset frequencies of medium cores or some preset frequencies of small cores in the CPU.
[0129] In step 1002: For each available frequency point, determine the frame length corresponding to the available frequency point.
[0130] In this embodiment of the application, the frame length corresponding to each available frequency point can be obtained through a preset CPU energy efficiency table.
[0131] In step 1003: the first frequency point is obtained based on the frame length corresponding to each available frequency point.
[0132] In this embodiment of the application, if the frame length of the available frequency point is too long, it may not meet the performance requirements. Therefore, it is necessary to filter the available frequency points and select the available frequency point that meets the performance requirements as the first frequency point.
[0133] In some possible embodiments, the first frequency point is obtained based on the frame length of each available frequency point. Specifically, this can be implemented as follows: the frequency points with a frame length less than a preset frame length among the available frequency points are used as the second frequency points; the power consumption characteristic value corresponding to each second frequency point is obtained based on the computing power of each second frequency point and the frame length corresponding to each second frequency point; and the first frequency point is obtained based on the power consumption characteristic value corresponding to each second frequency point.
[0134] In this embodiment, available frequency points are filtered based on the frame length of available frequency points and a preset frame length. Available frequency points with a frame length less than the preset frame length are designated as second frequency points. The power consumption characteristic value of each second frequency point is obtained based on its computing power and frame length. The second frequency point with the smallest power consumption characteristic value is designated as the first frequency point.
[0135] In step 1004: Determine the CPU computing power and GPU computing power of the target CPU architecture at the first frequency point.
[0136] In this embodiment of the application, CPU computing power and GPU computing power can be obtained through a preset energy efficiency table.
[0137] In step 1005: Based on the CPU computing power, the first thread is processed using the first frequency point to obtain the fourth frame length.
[0138] In step 1006: The second thread is processed using the first frequency point based on the CPU computing power to obtain the fifth frame length.
[0139] In step 1007: the sixth frame length corresponding to the GPU is obtained based on the GPU computing power.
[0140] In this embodiment, the process of obtaining the sixth frame length corresponding to the GPU based on GPU computing power is the same as the process of obtaining the third frame length of the GPU described above. In calculating the third frame length, simply replacing the GPU core frequency computing power with the GPU computing power yields the sixth frame length corresponding to the GPU. Similarly, replacing the capacity in formula 2 with CPU computing power yields the sixth frame length. basem1 This allows us to obtain the fourth frame length. Similarly, we can replace the capacity in formula 3 with CPU computing power. basem2 This allows us to obtain the length of the fifth frame.
[0141] In step 1008: the third computing power performance index of the target CPU architecture is obtained based on the fourth frame length, the fifth frame length, and the sixth frame length.
[0142] In this application, after obtaining the fourth frame length, the fifth frame length, and the sixth frame length, the fourth frame length, the fifth frame length, and the sixth frame length can be compared with the frame lengths corresponding to the first thread, the second thread, and the GPU before scheduling, respectively, to obtain the third computing power performance index.
[0143] For example: Figure 11 As shown, the frame length corresponding to processing the UI using the large cores of the target CPU architecture is L1, and the frame length corresponding to processing the RS using the medium cores is L2. Figure 10 After scheduling as shown, the frame length corresponding to processing the UI using the mid-core of the target CPU architecture is determined to be L11, and the frame length corresponding to processing the RS using the mid-core is L22. The frame length for processing the UI using the target CPU architecture becomes longer, while the frame length for processing the RS decreases.
[0144] In some possible embodiments, the frame length corresponding to the target frame image for each thread can be obtained through the above method. By comparing the frame length with the target frame length, it can be determined whether six frames have been dropped, and the performance of the target CPU architecture can be comprehensively evaluated based on the number of dropped six frames. Dropping six frames means that the frame length exceeds 99.6 milliseconds, and dropping six frames will cause users to have a noticeable stuttering experience in most scenarios.
[0145] For example: Figure 12 As shown, the frame lengths corresponding to chip A and chip B can be determined using the above method, and then the number of frames dropped can be determined. The number of frames dropped by chip A is determined to be 500, and the number of frames dropped by chip B is determined to be 600. Based on the number of frames dropped by each chip, the performance indicators corresponding to each chip can be obtained.
[0146] Based on the same inventive concept, embodiments of this application also provide a performance evaluation device, such as... Figure 13 As shown, the device includes:
[0147] The acquisition module 13001 is used to acquire the load data of the target frame image of the current central processing unit (CPU) architecture; and to acquire the computing power of the first core frequency, the computing power of the second core frequency, and the computing power of the GPU in the target CPU architecture.
[0148] The normalization module 13002 is used to obtain the normalized load of the target frame image based on the load data;
[0149] The frame length determination module 13003 is used to obtain the first frame length based on the target thread, normalized load, and first core frequency point corresponding to the target frame image; and,
[0150] The second frame length is obtained based on the non-target thread corresponding to the target frame image, the normalized load, and the second core frequency; and the third frame length is obtained based on the computing power of the GPU.
[0151] The performance evaluation module 13004 is used to obtain the first computing power performance index of the target CPU architecture based on the first frame length, the second frame length, and the third frame length.
[0152] In some possible embodiments, the frame length determination module 13003 is specifically used to: obtain the computing power and runtime of each frequency point from the load data; for each frequency point, obtain the load of the frequency point based on the computing power and runtime of the frequency point; obtain the normalized load based on the load of each frequency point and the computing power of the target frequency point; the target frequency point is the frequency point with the highest computing power of the large core in the current CPU architecture.
[0153] In some possible embodiments, the frame length determination module 13003 is further configured to: obtain the first load of the first thread and the second load of the second thread corresponding to the target frame image; if the first load is greater than the second load, then the first thread is designated as the target thread and the second thread as a non-target thread; if the first load is less than or equal to the second load, then the second thread is designated as the target thread and the first thread as a non-target thread.
[0154] In some possible embodiments, the frame length determination module 13003 is specifically used to: process the target frame image using the target thread at the first core frequency point to obtain the first frame length.
[0155] In some possible embodiments, the frame length determination module 13003 is specifically used to: process the target frame image using a non-target thread at the second core frequency point to obtain the second frame length.
[0156] In some possible embodiments, the frame length determination module 13003 is further configured to: obtain the average computing power supply ratio of the current CPU architecture based on the normalized load; obtain the first CPU core computing power of the target CPU architecture; obtain the releaseable computing power corresponding to the target CPU architecture based on the average computing power supply ratio and the first CPU core computing power; obtain the frame length corresponding to each thread under the target CPU architecture based on the releaseable computing power; the performance evaluation module 13004 is further configured to obtain the second computing power performance index of the target CPU architecture based on the frame length corresponding to each thread under the target CPU architecture.
[0157] In some possible embodiments, the frame length determination module 13003 is specifically used to: determine the frame length of the first thread and the frame length of the second thread based on the available computing power; obtain the GPU computing power of the target CPU architecture; obtain the frame length of the GPU of the target CPU architecture based on the available computing power and the GPU computing power of the target CPU architecture; and use the frame length of the first thread, the frame length of the second thread, and the frame length of the GPU of the target CPU architecture as the frame length corresponding to each thread under the target CPU architecture.
[0158] In some possible embodiments, the frame length determination module 13003 is specifically used to: obtain the runtime of each frequency point from the load information; obtain the cumulative duration based on the runtime of each frequency point; obtain the average computing power according to the normalized load and the cumulative duration; and obtain the average computing power supply ratio according to the average computing power and the computing power of the target frequency point, wherein the target frequency point is the frequency point with the highest computing power of the large core in the current CPU architecture.
[0159] In some possible embodiments, the frame length determination module 13003 is further configured to: obtain available frequency points in the current CPU architecture; determine the frame length corresponding to each available frequency point; obtain a first frequency point based on the frame length corresponding to each available frequency point; determine the CPU computing power and GPU computing power of the target CPU architecture at the first frequency point; process the first thread using the first frequency point based on the CPU computing power to obtain a fourth frame length; and process the second thread using the first frequency point based on the CPU computing power to obtain a fifth frame length; and obtain a sixth frame length corresponding to the GPU based on the GPU computing power; and obtain a third computing power performance index of the target CPU architecture based on the fourth frame length, the fifth frame length, and the sixth frame length.
[0160] In some possible embodiments, the frame length determination module 13003 is specifically used to: take the available frequency points with a frame length less than a preset frame length as the second frequency points; obtain the power consumption characteristic value corresponding to each second frequency point based on the computing power of each second frequency point and the frame length corresponding to each second frequency point; and obtain the first frequency point based on the power consumption characteristic value corresponding to each second frequency point.
[0161] Corresponding to the above embodiments, this application also provides an electronic device. Figure 14 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. The electronic device 1400 may include a processor 1401, a memory 1402, and a communication unit 1403. These components communicate through one or more buses. Those skilled in the art will understand that the structure of the electronic device shown in the figure does not constitute a limitation on the embodiment of the present invention. It may be a bus topology or a star topology, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.
[0162] The communication unit 1403 is used to establish a communication channel, enabling the electronic device to communicate with other devices. It receives user data from other devices or sends user data to other devices.
[0163] The processor 1401 serves as the control center of the electronic device, connecting various parts of the device via interfaces and lines. It executes software programs and / or modules stored in the memory 1402 and retrieves data stored in the memory to perform various functions and / or process data. The processor may be composed of integrated circuits (ICs), such as a single packaged IC or multiple packaged ICs with the same or different functions connected together. For example, the processor 1401 may consist only of a central processing unit (CPU). In this embodiment, the CPU may have a single processing core or include multiple processing cores.
[0164] The memory 1402 is used to store the execution instructions of the processor 1401. The memory 1402 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.
[0165] When the execution instructions in memory 1402 are executed by processor 1401, the electronic device 1400 is able to perform its functions. Figure 2 Some or all of the steps in the illustrated embodiments.
[0166] In a specific implementation, the present invention also provides a computer storage medium, wherein the computer storage medium may store a program, which, when executed, may include some or all of the steps of the various embodiments of the performance evaluation method provided by the present invention. The storage medium may be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.
[0167] In some possible implementations, various aspects of the terminal device control method provided in this application can also be implemented in the form of a program product, which includes program code. When the program product is run on a computer device, the program code is used to cause the computer device to perform the steps in the terminal device control method according to the various exemplary embodiments of this application described above.
[0168] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.
[0169] The program product for controlling a terminal device according to embodiments of this application may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on an electronic device. However, the program product of this application is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.
[0170] Those skilled in the art will clearly understand that the techniques in the embodiments of the present invention can be implemented using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments of the present invention.
[0171] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the device embodiments and terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.
Claims
1. A performance evaluation method, characterized in that, The method includes: Obtain the load data of the target frame image of the current central processing unit (CPU) architecture; and obtain the computing power of the first core frequency, the computing power of the second core frequency, and the computing power of the GPU in the target CPU architecture. The normalized load of the target frame image is obtained based on the load data; The first frame length is obtained based on the target thread corresponding to the target frame image, the normalized load, and the first core frequency point; and... The second frame length is obtained based on the non-target thread corresponding to the target frame image, the normalized load, and the second core frequency; and the third frame length is obtained based on the computing power of the GPU. Based on the first frame length, the second frame length, and the third frame length, the first computing power performance index of the target CPU architecture is obtained.
2. The method according to claim 1, characterized in that, The load data includes: computing power at each frequency point, runtime at each frequency point, and obtaining the normalized load of the target frame image based on the load data includes: The computing power and runtime of each frequency point are obtained from the load data. For each frequency point, the load of that frequency point is obtained based on its computing power and runtime. The normalized load is obtained based on the load at each frequency point and the computing power at the target frequency point; the target frequency point is the frequency point with the highest computing power of the large core in the current CPU architecture.
3. The method according to claim 1, characterized in that, Before obtaining the first frame length based on the target thread corresponding to the target frame image and the first core frequency point, the method further includes: Obtain the first load of the first thread and the second load of the second thread corresponding to the target frame image; If the first load is greater than the second load, then the first thread is designated as the target thread and the second thread is designated as the non-target thread. If the first load is less than or equal to the second load, then the second thread is designated as the target thread and the first thread is designated as the non-target thread.
4. The method according to claim 1, characterized in that, The step of obtaining the first frame length based on the target thread corresponding to the target frame image and the first core frequency point includes: The target frame image is processed using the target thread at the first core frequency point to obtain the first frame length.
5. The method according to claim 1, characterized in that, The step of obtaining the second frame length based on the non-target thread corresponding to the target frame image and the second core frequency point includes: The target frame image is processed using the non-target thread at the second core frequency point to obtain the second frame length.
6. The method according to claim 1, characterized in that, After obtaining the normalized load of the target frame image based on the load data, the method further includes: The average computing power supply ratio of the current CPU architecture is obtained based on the normalized load. Obtain the computing power of the first CPU core of the target CPU architecture; Based on the average computing power supply ratio and the computing power of the first CPU core, the releaseable computing power corresponding to the target CPU architecture is obtained. Based on the releasable computing power, the frame length corresponding to each thread under the target CPU architecture is obtained; Based on the frame length corresponding to each thread under the target CPU architecture, the second computing power performance index of the target CPU architecture is obtained.
7. The method according to claim 6, characterized in that, The step of obtaining the frame length corresponding to each thread under the target CPU architecture based on the releasable computing power includes: The frame length of the first thread and the frame length of the second thread are determined based on the releasable computing power. Obtain the GPU computing power of the target CPU architecture; The frame length of the GPU of the target CPU architecture is obtained based on the releasable computing power and the GPU computing power of the target CPU architecture. The frame length of the first thread, the frame length of the second thread, and the frame length of the GPU of the target CPU architecture are taken as the frame lengths corresponding to each thread under the target CPU architecture.
8. The method according to claim 6, characterized in that, The process of obtaining the average computing power supply ratio of the current CPU architecture based on the normalized load includes: Obtain the runtime of each frequency point from the load information; The cumulative duration is obtained based on the runtime of each frequency point; The average computing power is obtained based on the normalized load and the cumulative duration. The average computing power supply ratio is obtained based on the average computing power and the computing power of the target frequency, wherein the target frequency is the frequency with the highest computing power of the large core in the current CPU architecture.
9. The method according to claim 1, characterized in that, After obtaining the normalized load of the target frame image based on the load data, the method further includes: Obtain the available frequency points in the current CPU architecture; For each available frequency point, determine the frame length corresponding to that available frequency point; The first frequency point is obtained based on the frame length corresponding to each of the available frequency points; Determine the CPU computing power and GPU computing power of the target CPU architecture at the first frequency point; Based on the CPU computing power, the first thread is processed using the first frequency point to obtain a fourth frame length; and, Based on the CPU computing power, the second thread is processed using the first frequency point to obtain a fifth frame length; and, The sixth frame length corresponding to the GPU is obtained based on the GPU computing power; The third computing power performance index of the target CPU architecture is obtained based on the fourth frame length, the fifth frame length, and the sixth frame length.
10. The method according to claim 9, characterized in that, The step of obtaining the first frequency point based on the frame length of each available frequency point includes: The frequency points with a frame length shorter than the preset frame length among the available frequency points are designated as the second frequency points; Based on the computing power of each second frequency point and the frame length corresponding to each second frequency point, the power consumption characteristic value corresponding to each second frequency point is obtained. The first frequency point is obtained based on the power consumption characteristic value corresponding to each second frequency point.
11. A performance evaluation device, characterized in that, The device includes: The acquisition module is used to acquire the load data of the target frame image of the current central processing unit (CPU) architecture; and to acquire the computing power of the first core frequency, the computing power of the second core frequency, and the computing power of the GPU in the target CPU architecture. The normalization module is used to obtain the normalized load of the target frame image based on the load data; The frame length determination module is used to obtain the first frame length based on the target thread, normalized load, and first core frequency point corresponding to the target frame image; and, The second frame length is obtained based on the non-target thread corresponding to the target frame image, the normalized load, and the second core frequency; and the third frame length is obtained based on the computing power of the GPU. The performance evaluation module is used to obtain the first computing power performance index of the target CPU architecture based on the first frame length, the second frame length, and the third frame length.
12. An electronic device, characterized in that, It includes a memory for storing computer program instructions and a processor for executing the program instructions, wherein when the computer program instructions are executed by the processor, the electronic device is triggered to perform the method of any one of claims 1-10.
13. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein, when the program is executed, it controls the device on which the computer-readable storage medium is located to perform the method according to any one of claims 1-10.
14. A computer program product, characterized in that, The computer program product includes: computer program code, which, when run on a computer, causes the computer to perform the method described in any one of claims 1-10.