A flexible direct current fault recording, control and protection method and system

Abstract

The application belongs to the field of fault recording, and particularly relates to a flexible DC fault recording, control protection method and system. The system comprises: setting three data buffers in a shared memory between a first processor core and another processor core in the same processor as the first processor core; realizing flexible DC power transmission control protection through the other processor core; writing, through the other processor core, recording wave data generated in a current recording wave cycle into a data buffer with a label of an idle state, and modifying the label of the data buffer to a full storage state after writing is completed; finding, through the first processor core, the data buffer with the label of the full storage state and modifying the label to a reading state, then reading the recording wave data in the data buffer and writing into a storage unit for realizing local storage of the recording wave data to save as a recording wave file; and modifying the label of the data buffer to the idle state after the recording wave file is saved.

Description

Technical Field

[0001] This invention belongs to the field of fault recording, specifically relating to a flexible DC fault recording, control and protection method and system. Background Technology

[0002] Flexible DC transmission projects have highly diverse application scenarios, covering typical modes such as offshore wind power grid connection, multi-terminal DC grids, transmission from desert and wasteland renewable energy bases, and urban photovoltaic-storage DC-flexible distribution networks. Different scenarios have varying requirements for system dynamic response, fault ride-through capability, and protection speed, resulting in a high degree of adaptability and complexity in control strategies and protection algorithms, significantly increasing the difficulty of system design and on-site commissioning. Therefore, control and protection devices (or systems) need to have real-time built-in fault recording functions to record key data of the system's transient operation in real time, enabling rapid verification of control and protection logic and rapid evaluation of dynamic performance based on the recorded data analysis.

[0003] Currently, existing flexible DC control and protection systems with multi-processor architecture and built-in fault recording implementation schemes include both hardware and software components. For example... Figure 1 As shown, its hardware mainly consists of a processor board (i.e., CPU) and I / O boards. Each processor board has a high-capacity BGA-packaged SATA storage chip to enable built-in fault recording and local storage functionality. Its software implementation is as follows: a) A multi-tasking operating system is used as the software platform for the control and protection system; considering that the critical control and protection operation is the most important operation during fault handling, this operation must be executed in a high-priority task; considering that the operation of storing data into SATA through the built-in fault recorder will consume a lot of system resources, this operation is usually placed in a low-priority task.

[0004] b) Two ping-pong data buffers are allocated in memory. The high-priority task executes the control and protection function, while writing critical data during the execution cycle into the idle data buffer. When the low-priority task is executed, the ping-pong data buffer that is full of data is located, and the data is written to the SATA device in the waveform recording Comtrade format and saved as a waveform recording file.

[0005] However, when the CPU load on the processor board is high, the above execution logic causes high-priority tasks to preempt the CPU usage rights of low-priority tasks, gaining priority in execution. Low-priority tasks do not receive sufficient CPU time slices, resulting in the inability of their waveform recording function to achieve real-time waveform recording, leading to the loss of critical transient process information. Compared with traditional DC transmission, flexible DC transmission places higher demands on system response speed and control accuracy in terms of sampling period, control period, and fault ride-through. Typically, the controller's operating cycle is required to be within hundreds of microseconds; for example, the Guangdong-Hong Kong-Macao Greater Bay Area flexible DC project requires a control cycle of 50µs. As future flexible DC systems continue to evolve towards shorter control cycles (10µs level), the shorter the cycle, the more exacerbates the problem of not being able to record waveforms in real time. Traditional fault waveform recording systems face a core contradiction between insufficient task execution logic and inadequate waveform recording integrity, severely impacting the rapid verification of control and protection logic and the rapid evaluation of dynamic performance. Summary of the Invention

[0006] The purpose of this invention is to provide a flexible DC fault recording, control and protection method and system to solve the problem that the recording function in low-priority tasks in the prior art cannot achieve real-time recording, resulting in the loss of key transient process information.

[0007] To achieve the above objectives, the present invention provides a flexible DC fault recording method, the method comprising: Three data buffers are set up in the shared memory between the first processor core and another processor core in the same processor core as the first processor core; Flexible DC power transmission control and protection are achieved through the other processor core; The other processor core writes the waveform data generated by the control protection in the current waveform recording cycle into a data buffer marked as idle, and modifies the data buffer to a full state after the writing is completed. The first processor core locates the data buffer marked as full and changes its mark to read. Then, it reads the waveform data in the data buffer and writes it to the storage unit used to implement local storage of waveform data to save it as a waveform file. After the waveform file is saved, the mark of the data buffer is changed to idle.

[0008] Beneficial effects: This invention provides a novel flexible DC fault recording method, which mainly employs three data buffers and one processor core. This processor core is only responsible for reading and writing the recording file and does not involve any control or protection functions; control and protection are handled by a separate processor core.

[0009] Based on the above architecture, when there is a free buffer (i.e. a buffer marked as free) among the three data buffers that has not been written to, the waveform data of the current waveform recording cycle is written to the free buffer. After the waveform data is written, the data buffer is marked as full. This step is equivalent to sealing the data buffer after writing the waveform data of the current waveform recording cycle, and no more data is written to it. Marking it as full makes it easier to find the buffer later.

[0010] The first processor core identifies the data buffer marked as full (this buffer contains the waveform recording data for a complete recording cycle, without any other data mixed in), and reads the data from this buffer. Before reading, it must be ensured that the buffer is marked as being read; this status is distinct from the idle and full states, preventing duplicate data writing and repeated readings from the same full buffer. After the read waveform recording data is written to the storage unit, the data buffer is cleared. Then, the buffer's status is changed back to idle, thus completing the state rotation among the three buffers.

[0011] In summary, this method decouples the core contradiction of insufficient waveform recording integrity by using different kernels to handle high-priority operations (i.e., control and protection) and low-priority operations (i.e., reading and writing waveform files), which were originally handled by the same processor core. (A specific kernel is only responsible for reading and writing waveform files, while control and protection functions are handled by other kernels; the task logic of each kernel is isolated from each other, and there is no priority relationship.) Based on this, a lock-free round-robin mechanism between three data buffers can avoid the loss of transient process information, thus achieving lossless waveform recording throughout the entire cycle.

[0012] Furthermore, the first processor core includes a processor core that runs a Linux system based on Preempt-RT real-time.

[0013] Furthermore, methods for determining the length of the data buffer include: determining the length of the data buffer based on the product of the horizontal width and the vertical width of the data buffer; The horizontal width of the data buffer is determined based on the sum of the number of analog and status quantity channels; The vertical width of the data buffer is determined based on the number of recording points.

[0014] The present invention also provides a flexible DC fault recording system, which includes a first processor core and three data buffers for being set in an inter-core shared memory; the inter-core shared memory is shared between the first processor core and another processor core in the same processor core for implementing flexible DC transmission control and protection; The other processor core is also used to write the waveform data generated by the control protection in the current waveform recording cycle into a data buffer marked as idle, and modify the data buffer to a full state after the writing is completed; The first processor core is used to locate the data buffer marked as full and change its mark to read. Then, it reads the waveform data in the data buffer and writes it to the storage unit used to implement local storage of the waveform data to save it as a waveform file. After the waveform file is saved, the mark of the data buffer is changed to idle.

[0015] Furthermore, the first processor core includes a processor core that runs a Linux system based on Preempt-RT real-time.

[0016] Furthermore, methods for determining the length of the data buffer include: determining the length of the data buffer based on the product of the horizontal width and the vertical width of the data buffer; The horizontal width of the data buffer is determined based on the sum of the number of analog and status quantity channels; The vertical width of the data buffer is determined based on the number of recording points.

[0017] Beneficial effects: The flexible DC fault recording system adopts the above-mentioned flexible DC fault recording method and has the same beneficial effects as the flexible DC fault recording method.

[0018] The present invention also provides a flexible DC control and protection method, the method comprising: Three data buffers are set up in the shared memory between the first processor core and the second processor core on the same processor; Flexible DC transmission control and protection are implemented through a second processor core; The second processor core writes the waveform data generated by the control protection in the current waveform recording cycle into the data buffer marked as idle, and modifies the data buffer to full state after the writing is completed. The first processor core locates the data buffer marked as full and changes its mark to read. Then, it reads the waveform data in the data buffer and writes it to the storage unit used to implement local storage of waveform data to save it as a waveform file. After the waveform file is saved, the mark of the data buffer is changed to idle.

[0019] Furthermore, the first processor core includes: a processor core running a Linux system based on Preempt-RT real-time; The second processor core includes: a processor core that runs an embedded real-time operating system; One way to determine the length of a data buffer is by multiplying its horizontal width by its vertical width. The horizontal width of the data buffer is determined based on the sum of the number of analog and status quantity channels; The vertical width of the data buffer is determined based on the number of recording points.

[0020] Beneficial effects: This flexible DC control and protection method can perform control and protection of flexible DC transmission while simultaneously recording fault waveforms using the aforementioned flexible DC fault recording method. This method achieves the same beneficial effects in fault recording as the flexible DC fault recording method.

[0021] The present invention also provides a flexible DC control and protection system, which includes a processor; The processor includes: a first processor core, a second processor core, and three data buffers set in the inter-core shared memory with the first and second processor cores; The second processor core is used to execute control and protection for flexible DC transmission, and is also used to write the recorded data generated by the control and protection in the current recording cycle into a data buffer marked as idle, and modify the data buffer to full state after the recorded data is written. The first processor core is used to locate the data buffer marked as full and change its mark to read. Then, it reads the waveform data in the data buffer and uses it as a storage unit for local storage of fault waveforms. After the waveform file is saved, the mark of the data buffer is changed to idle.

[0022] Furthermore, the first processor core includes: a processor core running a Linux system based on Preempt-RT real-time; The second processor core includes: a processor core that runs an embedded real-time operating system; One way to determine the length of a data buffer is by multiplying its horizontal width by its vertical width. The horizontal width of the data buffer is determined based on the sum of the number of analog and status quantity channels; The vertical width of the data buffer is determined based on the number of recording points.

[0023] Beneficial effects: The flexible DC control and protection system adopts the above-mentioned flexible DC control and protection method and has the same beneficial effects as the flexible DC control and protection method. Attached Figure Description

[0024] Figure 1 This is a hardware architecture diagram of an existing flexible DC control and protection system in the background art of this invention; Figure 2 This is a hardware architecture diagram of the flexible DC fault recording system in an embodiment of the present invention. Figure 3 This is a software architecture diagram of the flexible DC fault recording system in an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0026] Implementation of Flexible DC Control and Protection Method This embodiment presents a technical solution for a flexible DC control and protection method. The main idea of ​​this method is to process the control and protection operation and the reading and writing operation of the waveform recording file using different kernels, so that the task logic of each kernel is isolated from each other and there is no priority relationship; at the same time, a lock-free rotation mechanism between three data buffers is adopted to avoid losing transient process information, realize distortion-free waveform recording throughout the entire cycle, and thus achieve accurate and reliable control and protection.

[0027] In this embodiment, the method is implemented collaboratively through hardware and software components. In a specific embodiment, the architecture of the hardware component is as follows: Figure 2 As shown, the processor board is equipped with BGA-packaged SATA storage chips (i.e., storage units), and each processor board has an independent built-in fault recording function. The processor board chip has a built-in multi-core processor, and each core shares the board's DDR memory, SATA storage, network and other resources. The overall architecture adopts an asymmetric multiprocessor (AMP) collaborative computing architecture. The cores can interact with each other through inter-core shared memory. The data communication rate of inter-core shared memory is high and the data read and write latency is low. At the same time, each core runs a different operating system and task relatively independently, and each pair of cores is isolated from each other and will not interfere with each other's functions.

[0028] refer to Figure 3 The architecture of the software portion of this system is as follows: Three data buffers are set up in the shared memory between the first processor core and the second processor core on the same processor; Flexible DC transmission control and protection are implemented through a second processor core; The second processor core controls the protection to write the waveform data generated in the current waveform recording cycle into the data buffer marked as idle, and modifies the data buffer to full state after the writing is completed. The first processor core locates the data buffer marked as full and changes its mark to read. Then, it reads the waveform data in the data buffer and writes it to the storage unit used to implement local storage of waveform data to save it as a waveform file. After the waveform file is saved, the mark of the data buffer is changed to idle.

[0029] Specifically, this method employs three data buffers, two processor cores, and one storage unit (i.e., a SATA storage chip). These three data buffers are independent of each other, and there is no data interaction between different data buffers; the two processor cores are Core 1 (i.e., the first processor core) and Core 2 (i.e., the second processor core).

[0030] Core 2's function is to locate a data buffer marked FREE (i.e., idle state) while performing control and protection. It then writes the waveform recording data for the current recording cycle into this data buffer and, after writing the data, changes the buffer's mark to FULL (i.e., full state). Marking it FREE means that no data is stored in the data buffer, and data can be written to it. After writing data for one recording cycle, regardless of whether the data buffer's memory is full, the mark is changed to FULL. After being marked FULL, no further data is written to avoid mixing in data from other recording cycles. Core 1's function is to locate a data buffer marked FULL, mark it as PEND (i.e., reading state), read the waveform recording data stored in the data buffer, and write the read waveform recording data to the SATA storage chip. Marking it FULL means that the data buffer contains waveform recording data for one recording cycle, and it can be read. In a specific embodiment, Core 1 writes the waveform recording data to the SATA storage chip in waveform recording Comtrade format to save it as a waveform recording file.

[0031] Before reading data, the data buffer's flag is changed to PEND to prevent it from being repeatedly identified as FULL and read repeatedly. After reading the data, it is written to the SATA storage chip to save it as a waveform file. The data buffer is also cleared after the data reading is complete. Therefore, after the file is saved, the buffer's state is changed to FREE. At this point, the data buffer can be found again by core 2 and data can be written to it. This allows for a state rotation through the three data buffers. It is important to note that the data reading cycle of core 1 should be kept as short as possible to avoid a situation where the next data cannot be written because the previous data reading has not finished.

[0032] like Figure 3As shown, the first processor core includes a processor kernel running a Preempt-RT real-time Linux system (i.e., RT Linux). The Preempt-RT patch significantly improves the system's responsiveness by enhancing the kernel's preemptibility and timing determinism.

[0033] The second processor core includes a processor core running an embedded real-time operating system (RTOS). The RTOS is capable of processing waveform data at a sufficiently high speed and can ensure that the processing results are controlled and protected within a time window.

[0034] Specifically, the kernels of this system communicate with each other through inter-kernel shared memory. Using inter-kernel shared memory to transfer data not only ensures a high communication rate and low data read / write latency, but also ensures that each kernel runs different operating systems and tasks relatively independently, and that the kernels are isolated from each other and do not interfere with each other's functions.

[0035] In this embodiment, the method for determining the length of the data buffer includes: determining the length of the data buffer based on the product of the horizontal width and the vertical width of the data buffer; The horizontal width of the data buffer is determined based on the sum of the number of analog and status quantity channels; The vertical width of the data buffer is determined based on the number of recording points.

[0036] Implementation of Flexible DC Control and Protection System This embodiment provides a technical solution for a flexible DC control and protection system. The main concept of this method is consistent with the flexible DC control and protection method in the embodiment of the flexible DC control and protection method.

[0037] In this embodiment, the system includes a first processor core and three data buffers for setting in the inter-core shared memory; the inter-core shared memory is shared between the first processor core and another processor core in the same processor core for implementing flexible DC transmission control and protection; The other processor core is also used to write the waveform data generated by the control protection in the current waveform recording cycle into the data buffer marked as idle, and modify the data buffer to be full after the writing is completed; The first processor core is used to locate the data buffer marked as full and change its mark to read. Then, it reads the waveform data in the data buffer and writes it to the storage unit used to implement local storage of the waveform data to save it as a waveform file. After the waveform file is saved, the mark of the data buffer is changed to idle.

[0038] In this embodiment, the system includes hardware and software components. In one specific embodiment, a processor board is equipped with a BGA-packaged SATA storage chip (i.e., a storage unit), and each processor board has an independent built-in fault recording function. The processor board chip has a built-in multi-core processor, and each core shares the board's DDR memory, SATA storage, network, and other resources. The overall architecture adopts an asymmetric multiprocessor (AMP) collaborative computing architecture. The cores can interact with each other through inter-core shared memory, which has a high data communication rate and low data read / write latency. At the same time, each core runs a different operating system and task relatively independently, and each pair of cores is isolated from each other and will not interfere with each other's functions.

[0039] Specifically, the architecture of the software portion of this system is as follows: Three data buffers are set up in the shared memory between the first processor core and the second processor core on the same processor; Flexible DC transmission control and protection are implemented through a second processor core; The second processor core controls the protection to write the waveform data generated in the current waveform recording cycle into the data buffer marked as idle, and modifies the data buffer to full state after the writing is completed. The first processor core locates the data buffer marked as full and changes its mark to read. Then, it reads the waveform data in the data buffer and writes it to the storage unit used to implement local storage of waveform data to save it as a waveform file. After the waveform file is saved, the mark of the data buffer is changed to idle.

[0040] Specifically, this method employs three data buffers, two processor cores, and one storage unit (i.e., a SATA storage chip). These three data buffers are independent of each other, and there is no data interaction between different data buffers; the two processor cores are Core 1 (i.e., the first processor core) and Core 2 (i.e., the second processor core).

[0041] Core 2's function is to locate a data buffer marked FREE (i.e., idle state) while performing control and protection. It then writes the waveform recording data for the current recording cycle into this data buffer and, after writing the data, changes the buffer's mark to FULL (i.e., full state). Marking it FREE means that no data is stored in the data buffer, and data can be written to it. After writing data for one recording cycle, regardless of whether the data buffer's memory is full, the mark is changed to FULL. After being marked FULL, no further data is written to avoid mixing in data from other recording cycles. Core 1's function is to locate a data buffer marked FULL, mark it as PEND (i.e., reading state), read the waveform recording data stored in the data buffer, and write the read waveform recording data to the SATA storage chip. Marking it FULL means that the data buffer contains waveform recording data for one recording cycle, and it can be read. In a specific embodiment, Core 1 writes the waveform recording data to the SATA storage chip in waveform recording Comtrade format to save it as a waveform recording file.

[0042] Before reading data, the data buffer's flag is changed to PEND to prevent it from being repeatedly identified as FULL and read repeatedly. After reading the data, it is written to the SATA storage chip to save it as a waveform file. The data buffer is also cleared after the data reading is complete. Therefore, after the file is saved, the buffer's state is changed to FREE. At this point, the data buffer can be found again by core 2 and data can be written to it. This allows for a state rotation through the three data buffers. It is important to note that the data reading cycle of core 2 should ideally not exceed the data writing cycle of core 1 to avoid situations where the next data cannot be written because the previous data read has not finished.

[0043] In this embodiment, the first processor core includes a processor kernel running a Preempt-RT real-time Linux system (i.e., RT Linux). The Preempt-RT patch significantly improves the system's responsiveness by enhancing the kernel's preemptibility and timing determinism.

[0044] The second processor core includes a processor core running an embedded real-time operating system (RTOS). The RTOS is capable of processing waveform data at a sufficiently high speed and can ensure that the processing results are controlled and protected within a time window.

[0045] Specifically, the kernels of this system communicate with each other through inter-kernel shared memory. Using inter-kernel shared memory to transfer data not only ensures a high communication rate and low data read / write latency, but also ensures that each kernel runs different operating systems and tasks relatively independently, and that the kernels are isolated from each other and do not interfere with each other's functions.

[0046] In this embodiment, the method for determining the length of the data buffer includes: determining the length of the data buffer based on the product of the horizontal width and the vertical width of the data buffer; The horizontal width of the data buffer is determined based on the sum of the number of analog and status quantity channels; The vertical width of the data buffer is determined based on the number of recording points.

[0047] Implementation of Flexible DC Fault Recording Method This embodiment presents a technical solution for a flexible DC fault recording method. The main idea of ​​this method is to set up a processor core that is only used to perform read and write operations on the recording file, and to isolate the task logic of this core from that of another processor core used to perform control and protection, thereby avoiding the problem of failure to write normally due to priority differences, which would cause the loss of key transient process information.

[0048] In this embodiment, the flexible DC fault recording method includes: Three data buffers are set up in the shared memory between the first processor core and another processor core in the same processor core as the first processor core; Flexible DC transmission control and protection are implemented through another processor core; Another processor core controls the protection to write the waveform data generated in the current waveform recording cycle into a data buffer marked as idle, and modifies the data buffer to a full state after the write is completed; The first processor core locates the data buffer marked as full and changes its mark to read. Then, it reads the waveform data in the data buffer and writes it to the storage unit used to implement local storage of waveform data to save it as a waveform file. After the waveform file is saved, the mark of the data buffer is changed to idle.

[0049] In this embodiment, the method is implemented through the collaboration of hardware and software components. In a specific embodiment, a processor board is equipped with a BGA-packaged SATA storage chip (i.e., a storage unit), and each processor board has an independent built-in fault recording function. The processor board chip has a built-in multi-core processor, and each core shares the board's DDR memory, SATA storage, network, and other resources. The overall architecture adopts an asymmetric multiprocessor (AMP) collaborative computing architecture. The cores can interact with each other through inter-core shared memory, which has a high data communication rate and low data read / write latency. At the same time, each core runs a different operating system and task relatively independently, and each pair of cores is isolated from each other and will not interfere with each other's functions.

[0050] Specifically, the architecture of the software portion of this system is as follows: Three data buffers are set up in the shared memory between the first processor core and the second processor core on the same processor; Flexible DC transmission control and protection are implemented through a second processor core; The second processor core controls the protection to write the waveform data generated in the current waveform recording cycle into the data buffer marked as idle, and modifies the data buffer to full state after the writing is completed. The first processor core locates the data buffer marked as full and changes its mark to read. Then, it reads the waveform data in the data buffer and writes it to the storage unit used to implement local storage of waveform data to save it as a waveform file. After the waveform file is saved, the mark of the data buffer is changed to idle.

[0051] Specifically, this method employs three data buffers, two processor cores, and one storage unit (i.e., a SATA storage chip). These three data buffers are independent of each other, and there is no data interaction between different data buffers; the two processor cores are Core 1 (i.e., the first processor core) and Core 2 (i.e., the second processor core).

[0052] Core 2's function is to locate a data buffer marked FREE (i.e., idle state) while performing control and protection. It then writes the waveform recording data for the current recording cycle into this data buffer and, after writing the data, changes the buffer's mark to FULL (i.e., full state). Marking it FREE means that no data is stored in the data buffer, and data can be written to it. After writing data for one recording cycle, regardless of whether the data buffer's memory is full, the mark is changed to FULL. After being marked FULL, no further data is written to avoid mixing in data from other recording cycles. Core 1's function is to locate a data buffer marked FULL, mark it as PEND (i.e., reading state), read the waveform recording data stored in the data buffer, and write the read waveform recording data to the SATA storage chip. Marking it FULL means that the data buffer contains waveform recording data for one recording cycle, and it can be read. In a specific embodiment, Core 1 writes the waveform recording data to the SATA storage chip in waveform recording Comtrade format to save it as a waveform recording file.

[0053] Before reading data, the data buffer's flag is changed to PEND to prevent it from being repeatedly identified as FULL and read repeatedly. After reading the data, it is written to the SATA storage chip to save it as a waveform file. The data buffer is also cleared after the data reading is complete. Therefore, after the file is saved, the buffer's state is changed to FREE. At this point, the data buffer can be found again by core 2 and data can be written to it. This allows for a state rotation through the three data buffers. It is important to note that the data reading cycle of core 1 should be kept as short as possible to avoid a situation where the next data cannot be written because the previous data reading has not finished.

[0054] In this embodiment, the first processor core includes a processor kernel running a Preempt-RT real-time Linux system (i.e., RT Linux). The Preempt-RT patch significantly improves the system's responsiveness by enhancing the kernel's preemptibility and timing determinism.

[0055] The second processor core includes a processor core running an embedded real-time operating system (RTOS). The RTOS is capable of processing waveform data at a sufficiently high speed and can ensure that the processing results are controlled and protected within a time window.

[0056] Specifically, the kernels of this system communicate with each other through inter-kernel shared memory. Using inter-kernel shared memory to transfer data not only ensures a high communication rate and low data read / write latency, but also ensures that each kernel runs different operating systems and tasks relatively independently, and that the kernels are isolated from each other and do not interfere with each other's functions.

[0057] In this embodiment, the method for determining the length of the data buffer includes: determining the length of the data buffer based on the product of the horizontal width and the vertical width of the data buffer; The horizontal width of the data buffer is determined based on the sum of the number of analog and status quantity channels; The vertical width of the data buffer is determined based on the number of recording points.

[0058] Implementation of Flexible DC Fault Recording System In this embodiment, a first processor core and three data buffers are included for setting in the inter-core shared memory; the inter-core shared memory is shared between the first processor core and another processor core in the same processor core for implementing flexible DC transmission control and protection. The other processor core is also used to write the waveform data generated by the control protection in the current waveform recording cycle into the data buffer marked as idle, and modify the data buffer to be full after the writing is completed; The first processor core is used to locate the data buffer marked as full and change its mark to read. Then, it reads the waveform data in the data buffer and writes it to the storage unit used to implement local storage of the waveform data to save it as a waveform file. After the waveform file is saved, the mark of the data buffer is changed to idle.

[0059] In one specific embodiment, a processor board is equipped with a BGA-packaged SATA storage chip (i.e., a storage unit). Each processor board has an independent built-in fault recording function. The processor board chip has a built-in multi-core processor. Each core shares the board's DDR memory, SATA storage, network and other resources. The overall architecture adopts an asymmetric multiprocessor (AMP) collaborative computing architecture. The cores can interact with each other through inter-core shared memory. The data communication rate of inter-core shared memory is high and the data read and write latency is low. At the same time, each core runs a different operating system and task relatively independently. Every two cores are isolated from each other and will not interfere with each other's functions.

[0060] Specifically, the architecture of the software portion of this system is as follows: Three data buffers are set up in the shared memory between the first processor core and the second processor core on the same processor; Flexible DC transmission control and protection are implemented through a second processor core; The second processor core controls the protection to write the waveform data generated in the current waveform recording cycle into the data buffer marked as idle, and modifies the data buffer to full state after the writing is completed. The first processor core locates the data buffer marked as full and changes its mark to read. Then, it reads the waveform data in the data buffer and writes it to the storage unit used to implement local storage of waveform data to save it as a waveform file. After the waveform file is saved, the mark of the data buffer is changed to idle.

[0061] Specifically, this method employs three data buffers, two processor cores, and one storage unit (i.e., a SATA storage chip). These three data buffers are independent of each other, and there is no data interaction between different data buffers; the two processor cores are Core 1 (i.e., the first processor core) and Core 2 (i.e., the second processor core).

[0062] Core 2's function is to locate a data buffer marked FREE (i.e., idle state) while performing control and protection. It then writes the waveform recording data for the current recording cycle into this data buffer and, after writing the data, changes the buffer's mark to FULL (i.e., full state). Marking it FREE means that no data is stored in the data buffer, and data can be written to it. After writing data for one recording cycle, regardless of whether the data buffer's memory is full, the mark is changed to FULL. After being marked FULL, no further data is written to avoid mixing in data from other recording cycles. Core 1's function is to locate a data buffer marked FULL, mark it as PEND (i.e., reading state), read the waveform recording data stored in the data buffer, and write the read waveform recording data to the SATA storage chip. Marking it FULL means that the data buffer contains waveform recording data for one recording cycle, and it can be read. In a specific embodiment, Core 1 writes the waveform recording data to the SATA storage chip in waveform recording Comtrade format to save it as a waveform recording file.

[0063] Before reading data, the data buffer's flag is changed to PEND to prevent it from being repeatedly identified as FULL and read repeatedly. After reading the data, it is written to the SATA storage chip to save it as a waveform file. The data buffer is also cleared after the data reading is complete. Therefore, after the file is saved, the buffer's state is changed to FREE. At this point, the data buffer can be found again by core 2 and data can be written to it. This allows for a state rotation through the three data buffers. It is important to note that the data reading cycle of core 2 should ideally not exceed the data writing cycle of core 1 to avoid situations where the next data cannot be written because the previous data read has not finished.

[0064] In this embodiment, the first processor core includes a processor kernel running a Preempt-RT real-time Linux system (i.e., RT Linux). The Preempt-RT patch significantly improves the system's responsiveness by enhancing the kernel's preemptibility and timing determinism.

[0065] The second processor core includes a processor core running an embedded real-time operating system (RTOS). The RTOS is capable of processing waveform data at a sufficiently high speed and can ensure that the processing results are controlled and protected within a time window.

[0066] Specifically, the kernels of this system communicate with each other through inter-kernel shared memory. Using inter-kernel shared memory to transfer data not only ensures a high communication rate and low data read / write latency, but also ensures that each kernel runs different operating systems and tasks relatively independently, and that the kernels are isolated from each other and do not interfere with each other's functions.

[0067] In this embodiment, the method for determining the length of the data buffer includes: determining the length of the data buffer based on the product of the horizontal width and the vertical width of the data buffer; The horizontal width of the data buffer is determined based on the sum of the number of analog and status quantity channels; The vertical width of the data buffer is determined based on the number of recording points.

[0068] It should be understood that the above-described specific embodiments of the present invention are merely illustrative or explanatory of the principles of the present invention, and do not constitute a limitation thereof.

Claims

1. A flexible DC fault recording method, characterized in that, include: Three data buffers are set up in the shared memory between the first processor core and another processor core in the same processor core as the first processor core; Flexible DC power transmission control and protection are achieved through the other processor core; The other processor core writes the waveform data generated by the control protection in the current waveform recording cycle into a data buffer marked as idle, and modifies the data buffer to a full state after the writing is completed. The first processor core locates the data buffer marked as full and changes its mark to read. Then, it reads the waveform data in the data buffer and writes it to the storage unit used to implement local storage of waveform data to save it as a waveform file. After the waveform file is saved, the mark of the data buffer is changed to idle.

2. The flexible DC fault recording method according to claim 1, characterized in that, The first processor core includes a processor core that runs a Linux system based on Preempt-RT real-time.

3. The flexible DC fault recording method according to claim 1 or 2, characterized in that, One way to determine the length of a data buffer is by multiplying its horizontal width by its vertical width. The horizontal width of the data buffer is determined based on the sum of the number of analog and status quantity channels; The vertical width of the data buffer is determined based on the number of recording points.

4. A flexible DC fault recording system, characterized in that, It includes a first processor core and three data buffers for setting in inter-core shared memory; the inter-core shared memory is shared between the first processor core and another processor core in the same processor core for implementing flexible DC transmission control and protection; The other processor core is also used to write the waveform data generated by the control protection in the current waveform recording cycle into a data buffer marked as idle, and modify the data buffer to a full state after the writing is completed; The first processor core is used to locate the data buffer marked as full and change its mark to read. Then, it reads the waveform data in the data buffer and writes it to the storage unit used to implement local storage of the waveform data to save it as a waveform file. After the waveform file is saved, the mark of the data buffer is changed to idle.

5. The flexible DC fault recording system according to claim 4, characterized in that, The first processor core includes a processor core that runs a Linux system based on Preempt-RT real-time.

6. The flexible DC fault recording system according to claim 4 or 5, characterized in that, One way to determine the length of a data buffer is by multiplying its horizontal width by its vertical width. The horizontal width of the data buffer is determined based on the sum of the number of analog and status quantity channels; The vertical width of the data buffer is determined based on the number of recording points.

7. A flexible DC control and protection method, characterized in that, include: Three data buffers are set up in the shared memory between the first processor core and the second processor core on the same processor; Flexible DC transmission control and protection are implemented through a second processor core; The second processor core writes the waveform data generated by the control protection in the current waveform recording cycle into the data buffer marked as idle, and modifies the data buffer to full state after the writing is completed. The first processor core locates the data buffer marked as full and changes its mark to read. Then, it reads the waveform data in the data buffer and writes it to the storage unit used to implement local storage of waveform data to save it as a waveform file. After the waveform file is saved, the mark of the data buffer is changed to idle.

8. The flexible DC control and protection method according to claim 7, characterized in that, The first processor core includes: a processor core that runs a Linux system based on Preempt-RT real-time; The second processor core includes: a processor core that runs an embedded real-time operating system; One way to determine the length of a data buffer is by multiplying its horizontal width by its vertical width. The horizontal width of the data buffer is determined based on the sum of the number of analog and status quantity channels; The vertical width of the data buffer is determined based on the number of recording points.

9. A flexible DC control and protection system, characterized in that, Including the processor; The processor includes: a first processor core, a second processor core, and three data buffers set in the inter-core shared memory with the first and second processor cores; The second processor core is used to execute control and protection for flexible DC transmission, and is also used to write the recorded data generated by the control and protection in the current recording cycle into a data buffer marked as idle, and modify the data buffer to full state after the recorded data is written. The first processor core is used to locate the data buffer marked as full and change its mark to read. Then, it reads the waveform data in the data buffer and uses it as a storage unit for local storage of fault waveforms. After the waveform file is saved, the mark of the data buffer is changed to idle.

10. The flexible DC control and protection system according to claim 9, characterized in that, The first processor core includes: a processor core that runs a Linux system based on Preempt-RT real-time; The second processor core includes: a processor core that runs an embedded real-time operating system; One way to determine the length of a data buffer is by multiplying its horizontal width by its vertical width. The horizontal width of the data buffer is determined based on the sum of the number of analog and status quantity channels; The vertical width of the data buffer is determined based on the number of recording points.

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