A motherboard multi-interface compatibility automatic test optimization method

Abstract

The application belongs to the technical field of mainboard testing, and particularly relates to a mainboard multi-interface compatibility automatic testing optimization method, which comprises the following steps: S1, mainboard interface feature library construction and updating; based on new mainboard model import, test standard updating or fault data feedback triggering, interface information and industry test standards are acquired in a mode combining automatic acquisition and manual completion, and a standardized feature library is constructed after data cleaning and index optimization, supporting cross-mainboard model adaptation and dynamic iterative updating; the closed-loop system is formed by integrating feature library construction, intelligent case generation, parallel testing, fault diagnosis and reinforcement learning optimization, bidirectional feedback of test data and strategies is realized, the test efficiency is improved by more than 60%, and new interface technologies can be adapted through iterative optimization.

Description

Technical Field

[0001] This invention belongs to the field of motherboard testing technology, specifically a method for optimizing automated testing of motherboard multi-interface compatibility. Background Technology

[0002] With the rapid development of electronic information technology, the motherboard, as the core hardware carrier of electronic devices, integrates multiple interfaces such as PCIe, USB, HDMI, and SATA. Its compatibility directly determines the operational stability and functional integrity of the device. Interface compatibility testing is a key step in the motherboard R&D and mass production stages. Verifying the protocol adaptation, transmission performance, and collaborative working capabilities of each interface by simulating real-world usage scenarios is a core means of ensuring product quality. Currently, electronic devices are iterating towards thinner and lighter designs and higher performance. The types of motherboard interfaces are constantly being enriched, and protocol versions are continuously upgraded, which places higher demands on the efficiency, accuracy, and adaptability of compatibility testing.

[0003] Motherboard multi-interface compatibility testing plays an irreplaceable role in many fields. In consumer electronics, it is necessary to ensure stable compatibility between motherboard interfaces and various peripherals (such as hard drives, monitors, and USB flash drives) to improve user experience. In industrial control, motherboard interfaces must meet the real-time data transmission requirements under high temperature and high interference environments to ensure continuous operation of industrial systems. In the server field, the stability of multiple interfaces working in parallel directly affects the computing power output and data security of data centers. In automotive electronics, motherboard interfaces must adapt to the special power supply and timing requirements of vehicle equipment to ensure driving safety. The differentiated needs of each field further highlight the importance of accurate compatibility testing.

[0004] The core flaw of existing technologies lies in the lack of an intelligent and integrated testing architecture: First, there is a lack of a unified interface feature library. Each interface test script is developed independently, resulting in chaotic data formats and an inability to adapt to multiple motherboard models, leading to a large amount of repetitive testing work and high maintenance costs. Second, test cases mostly rely on manual writing or simple parameterization generation, resulting in low coverage, high redundancy, and no dynamic optimization mechanism, making it difficult to adapt to new interface protocols.

[0005] Therefore, this invention provides an optimized method for automated testing of motherboard multi-interface compatibility. Summary of the Invention

[0006] In order to overcome the shortcomings of the prior art, at least one technical problem raised in the background art is solved.

[0007] The technical solution adopted by this invention to solve its technical problem is: an automated testing optimization method for motherboard multi-interface compatibility, which includes the following steps: S1. Motherboard interface feature library construction and update: Based on the import of new motherboard models, test standard updates or fault data feedback triggers, interface information and industry test standards are obtained through a combination of automatic collection and manual completion. After data cleaning and index optimization, a standardized feature library is built, which supports cross-motherboard model adaptation and dynamic iterative updates. S2. Intelligent test case generation and optimization: Based on the updated feature library and historical test records, a basic test case set is generated through a decision tree model. Boundary value analysis is combined to expand extreme scenario test cases. Then, a genetic algorithm is used to optimize and eliminate redundant test cases. Finally, the optimal test case set is generated by sorting the test cases according to the importance of the interface and the historical failure rate. S3, Parallel test environment configuration: Based on the loaded test case set, initialize the hardware platform and load the adapter driver. Calculate the interface resource allocation ratio through the resource scheduling module, allocate independent test threads and hardware channels to each interface, and complete the parallel test architecture configuration after resource conflict detection and environment self-check. S4: Multi-threaded parallel test execution, starts the test thread pool and allocates test cases according to priority, each thread executes the test process in parallel, monitors the test progress in real time, pauses the current thread and records the fault snapshot when an exception is triggered, releases thread resources after the fault is handled, and supports breakpoint resume testing. S5. Real-time data acquisition and fault self-diagnosis: Collect test data at a preset frequency and preprocess it. Use a similarity matching algorithm to compare the test results with the standard data in the feature library to determine the test results. If the threshold is not met, trigger fault tree analysis to locate the cause of the fault. After generating a diagnostic report, perform secondary verification. If the verification is successful, feed back the fault data to the feature library update module. S6. Test report generation and closed-loop optimization: Summarize test data to generate a visual report, start the reinforcement learning module to update the test case generation strategy, and synchronously update the feature library to supplement fault information and new interface parameters. After review, save the optimized feature library and test case model to form a closed-loop test system of testing, diagnosis and optimization.

[0008] Preferably, the interface information in S1 includes interface type, protocol version, pin definition, transmission rate range and power supply standard. The feature library adopts a two-level index structure of motherboard model and interface type, which improves the retrieval efficiency by more than 80% compared with traditional linear retrieval. The data cleaning process uses preset regular expressions to unify interface naming and protocol version formats, rejects non-standard expressions, and ensures the consistency of feature library data.

[0009] Preferably, in S2, the population size of the genetic algorithm is set to 100, the crossover probability is 0.6, the mutation probability is 0.1, the maximum number of iterations is 50, and the fitness function weight can be dynamically adjusted according to the test scenario. During mass production testing, the weight of execution time is increased, and during R&D testing, the weight of coverage is increased.

[0010] Preferably, the resource allocation ratio in S3 is calculated using a dynamic resource scheduling algorithm, the complete formula of which is as follows: in, For the first The resource allocation ratio of the first interface represents the proportion of total hardware resources allocated to the first interface. The percentage of each interface; The test host comprehensively represents the hardware capabilities of the host, including CPU computing power, memory bandwidth, and I / O interface bandwidth, based on total hardware resources. For the first The test weight for each interface is set according to its importance level: core interfaces =0.3, important interface =0.2, normal interface =0.1; This represents the total number of interfaces to be tested. The S3 employs a global clock synchronization mechanism, achieving a synchronization accuracy of 1. When resource conflicts occur, a time-slicing reuse mechanism is used to adjust resource allocation to ensure the timing consistency of parallel testing of multiple interfaces.

[0011] Preferably, the test thread pool in S4 adopts a fixed thread pool and cache queue mode, the number of threads is equal to the number of interfaces and does not exceed 32, and the fault snapshot collection content includes interface voltage, signal waveform and instruction log.

[0012] Preferably, in step S5, the data acquisition frequency is 1kHz, a 16-bit ADC module is used to acquire voltage and signal data, with an error ≤ ±0.5%, and high-frequency noise is removed using a digital filtering algorithm; the similarity matching threshold is set to 90%, and the similarity matching algorithm formula is as follows: ,in For similarity, For test data, For standard data, For data dimensions.

[0013] Preferably, the fault tree model in S5 pre-sets 12 common fault nodes, and combines the collected data to reverse reason the cause of the fault, with a diagnostic accuracy of ≥95%. Secondary verification is achieved by adjusting the test conditions and executing special test cases.

[0014] Preferably, in S6, the reinforcement learning module designs a reward function based on improved test coverage and fault detection rate, and adjusts the decision tree splitting threshold and the fitness weight of the genetic algorithm; the visualization report supports PDF / Excel format, includes three levels of details (interface, use cases, and results) and fault diagnosis information, and the feature library update adopts an automatic labeling and manual review mechanism, and high-risk updates must be manually reviewed and approved before they can be saved.

[0015] The beneficial effects of this invention are as follows: 1. The motherboard multi-interface compatibility automated testing optimization method described in this invention integrates feature library construction, intelligent test case generation, parallel testing, fault diagnosis and reinforcement learning optimization into a closed-loop system, realizing bidirectional feedback of test data and strategies, improving testing efficiency by more than 60%, and can adapt to new interface technologies through iterative optimization.

[0016] 2. The motherboard multi-interface compatibility automated testing optimization method described in this invention adapts to the needs of multiple scenarios and models through intelligent dynamic decision-making; it integrates a multi-algorithm collaborative mechanism of decision tree, genetic algorithm and reinforcement learning, and can dynamically adjust parameters according to different test scenarios in R&D / mass production. At the same time, it adapts to multiple motherboard models through an expandable feature library. Compared with the traditional fixed test scheme, the scenario adaptability is improved by 80% and the multi-model test cost is reduced by 50%. Attached Figure Description

[0017] The invention will now be further described with reference to the accompanying drawings.

[0018] Figure 1 This is an overview diagram of the core control flow in this invention; Figure 2 This is a flowchart of the motherboard interface feature library construction and update control process in this invention; Figure 3 This is a flowchart of the intelligent test case generation and optimization control process in this invention; Figure 4 This is a flowchart of the test report generation and feature library optimization control process in this invention. Detailed Implementation

[0019] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0020] like Figures 1 to 4 As shown in the embodiment of the present invention, an automated testing optimization method for motherboard multi-interface compatibility includes the following steps: S1. Motherboard interface feature library construction and update: Based on the import of new motherboard models, test standard updates or fault data feedback triggers, interface information and industry test standards are obtained through a combination of automatic collection and manual completion. After data cleaning and index optimization, a standardized feature library is built, which supports cross-motherboard model adaptation and dynamic iterative updates. S2. Intelligent test case generation and optimization: Based on the updated feature library and historical test records, a basic test case set is generated through a decision tree model. Boundary value analysis is combined to expand extreme scenario test cases. Then, a genetic algorithm is used to optimize and eliminate redundant test cases. Finally, the optimal test case set is generated by sorting the test cases according to the importance of the interface and the historical failure rate. S3, Parallel test environment configuration: Based on the loaded test case set, initialize the hardware platform and load the adapter driver. Calculate the interface resource allocation ratio through the resource scheduling module, allocate independent test threads and hardware channels to each interface, and complete the parallel test architecture configuration after resource conflict detection and environment self-check. S4: Multi-threaded parallel test execution, starts the test thread pool and allocates test cases according to priority, each thread executes the test process in parallel, monitors the test progress in real time, pauses the current thread and records the fault snapshot when an exception is triggered, releases thread resources after the fault is handled, and supports breakpoint resume testing. S5. Real-time data acquisition and fault self-diagnosis: Collect test data at a preset frequency and preprocess it. Use a similarity matching algorithm to compare the test results with the standard data in the feature library to determine the test results. If the threshold is not met, trigger fault tree analysis to locate the cause of the fault. After generating a diagnostic report, perform secondary verification. If the verification is successful, feed back the fault data to the feature library update module. S6. Test report generation and closed-loop optimization: Summarize test data to generate a visual report, start the reinforcement learning module to update the test case generation strategy, and synchronously update the feature library to supplement fault information and new interface parameters. After review, save the optimized feature library and test case model to form a closed-loop test system of testing, diagnosis and optimization.

[0021] like Figures 1 to 4 As shown, the interface information in S1 above includes interface type, protocol version, pin definition, transmission rate range and power supply standard. The feature library adopts a two-level index structure of motherboard model and interface type, which improves the retrieval efficiency by more than 80% compared with traditional linear retrieval. The above data cleaning process uses predefined regular expressions to standardize interface naming and protocol version formats, rejecting non-standard expressions and ensuring the consistency of the feature library data. like Figures 1 to 4 As shown, in the genetic algorithm in S2 above, the population size is set to 100, the crossover probability is 0.6, the mutation probability is 0.1, the maximum number of iterations is 50, and the fitness function weight can be dynamically adjusted according to the test scenario. During mass production testing, the weight of execution time is increased, and during R&D testing, the weight of coverage is increased. The genetic algorithm described above optimizes test cases through a fitness function, which is fully expressed as follows: in, For fitness value, A higher value indicates a better set of use cases; Test coverage (unit: %), which is the proportion of test scenarios covered by the current test case set to all test scenarios in the feature library; Test case redundancy (unit: %) is the proportion of test cases in the current test case set that repeatedly cover the same test scenario to the total number of test cases; The estimated execution time (in minutes) is the estimated time required for the current test case set to complete the test. , , These are the weighting coefficients, and 1; Research and development testing scenarios =0.5、 =0.2、 =0.3, prioritizing test coverage; in mass production testing scenarios =0.3、 =0.2、 =0.5, prioritize shortening the test duration; By using a weighted multi-objective fitness function, a balanced optimization of test coverage, redundancy, and execution time is achieved, adapting to the needs of different test scenarios. At the same time, by setting iterative termination conditions, the optimization efficiency is avoided due to excessive iteration. Compared with traditional single-objective optimization genetic algorithms, the overall performance of test case sets is improved by more than 40%.

[0022] like Figures 1 to 4 As shown, the resource allocation ratio in S3 above is calculated using a dynamic resource scheduling algorithm. The complete formula for the algorithm is as follows: in, For the first The resource allocation ratio (in %) of the first interface represents the proportion of total hardware resources allocated to the first interface. The percentage of each interface; Total hardware resources (unit: resource unit RU) comprehensively characterize the hardware capabilities of the test host, such as CPU computing power, memory bandwidth, and I / O interface bandwidth. For the first The test weights for each interface are set according to the importance level of the interface: core interfaces (such as CPU direct connection PCIe 5.0, USB 4.0) =0.3, important interfaces (such as SATA 3.0, HDMI 2.1) =0.2, common interfaces (such as USB 2.0, audio interfaces) =0.1; This represents the total number of interfaces to be tested. When a resource conflict is detected, a conflict resolution mechanism is activated. The weight of the interface with the lower weight in the conflicting interfaces is reduced by 20%, and the resource allocation ratio is recalculated. If a conflict still exists, a time-slicing reuse strategy is adopted, with a slice duration of 10ms. Resources are dynamically allocated based on the importance of interfaces to ensure that core interfaces receive sufficient hardware resources, avoiding test lag or accuracy degradation caused by resource contention. The introduction of a conflict resolution mechanism reduces the occurrence rate of resource conflicts by more than 85%. Compared with the traditional equal resource allocation method, the stability of core interface testing is improved by more than 60%. The above-mentioned S3 adopts a global clock synchronization mechanism, with a synchronization accuracy of 1. When resource conflicts occur, a time-slicing reuse mechanism is used to adjust resource allocation to ensure the timing consistency of parallel testing of multiple interfaces. High-precision clock synchronization avoids timing deviations during parallel testing of multiple interfaces, reduces test misjudgments caused by timing asynchrony (such as false alarms caused by timing deviations in hot-plug testing), and lowers the misjudgment rate by more than 70%.

[0023] like Figures 1 to 4 As shown, the test thread pool in S4 above adopts a fixed thread pool and cache queue mode. The number of threads is equal to the number of interfaces and does not exceed 32. The thread scheduling adopts a priority preemptive scheduling strategy, and the test thread corresponding to the core interface is set to the highest priority. The fault snapshot collection content includes interface voltage (accuracy ±0.01V), signal waveform (sampling rate 100MHz) and instruction log (including instruction code, response code, execution time). The fixed thread pool mode avoids the performance loss caused by frequent thread creation and destruction, the priority preemptive scheduling ensures that core interface tests are executed first, and the high-precision data collection of fault snapshots provides complete on-site data for subsequent fault diagnosis, increasing the fault reproduction rate to over 98%. Compared with testing methods without a snapshot mechanism, the fault troubleshooting efficiency is improved by 80%.

[0024] like Figures 1 to 4 As shown, the data acquisition frequency in S5 above is 1kHz. A 16-bit ADC module is used to acquire voltage and signal data with an error ≤ ±0.5%. High-frequency noise is removed using a digital filtering algorithm. The complete formula for the filtering algorithm is as follows: in, For the first The optimal estimated value after filtering in the next sampling; For the first Prior estimates of the next sample; For the first Kalman gain for sub-sampling; For the first The original observations from the second sampling; For the observation matrix (here) =1, because the collected data are direct observations); For the first The prior error covariance matrix of the sub-sampling; To observe the noise covariance (set to 0.0001 based on the characteristics of the ADC module); It is the identity matrix; The similarity matching threshold is set to 90%, and the similarity matching algorithm formula is as follows: in, To measure the similarity between the test data and the standard data (within a range of 0-1), the similarity threshold is set to 0.9 (i.e., 90%). The test is considered passed when the value is ≥0.9. The test is considered to have failed if the value is less than 0.9. For the first Preprocessed test data (such as transmission rate, voltage, signal strength, etc.); For the first Standard data in the dimensional feature library; For data dimensions (defined according to interface type, USB interface) =5, including transmission rate, voltage, signal integrity, error code, and response time.

[0025] like Figures 1 to 4As shown, the fault tree model in S5 above presets 12 common fault nodes. By combining the collected data to infer the cause of the fault, the diagnostic accuracy is ≥95%. Secondary verification is achieved by adjusting the test conditions (including driver version replacement and hardware connection check) and executing special test cases. The reasoning logic of the above fault tree adopts the Bayesian probabilistic reasoning algorithm, and the complete formula is as follows: in, In order to observe fault data At that time, the cause of the malfunction was The posterior probability; Cause of the malfunction When it occurred, fault data was observed. The likelihood probability; Cause of the malfunction The prior probability (obtained based on historical fault data statistics); The sequence number of the cause of the fault (1≤ ≤12); The Bayesian probabilistic inference algorithm combines historical fault data with real-time observation data to achieve quantitative inference of fault causes. Compared with traditional qualitative fault tree analysis, the fault location accuracy is improved by more than 30%, and the fault location time is shortened from the traditional 1 hour level to 5 minutes level.

[0026] like Figures 1 to 4 As shown, the reinforcement learning module in S6 above designs a reward function based on improved test coverage and fault detection rate, and adjusts the decision tree splitting threshold and the fitness weight of the genetic algorithm; the above visualization report supports PDF / Excel format, including three levels of details of interfaces, test cases and results, as well as fault diagnosis information; the feature library update adopts an automatic labeling and manual review mechanism, and high-risk updates must be manually reviewed and approved before they can be saved. The reinforcement learning module uses the Q-learning algorithm to update the test case generation strategy. The complete reward function is as follows: in, To enhance the immediate reward value for learning; This represents the improvement in coverage compared to the historical average coverage (in %). This represents the improvement in the fault detection rate during this test compared to the historical average detection rate (unit: %). This represents the increase in test duration compared to the historical average duration (in minutes). , , As a reward weight, =0.4, =0.4, =0.2; The Q-learning algorithm is guided by a reward function to adjust the splitting threshold of the decision tree and the fitness weights of the genetic algorithm. The above visualization report supports PDF / Excel format and includes three levels of details: "interface-use case-result" and fault diagnosis information. Feature library updates adopt an "automatic labeling + manual review" mechanism, and high-risk updates must be manually reviewed and approved before being saved. The reward function designed based on the improvement in test performance can effectively guide the reinforcement learning model to optimize towards "high coverage, high detection rate, and low duration", and realize the adaptive iteration of the test case generation strategy. After 10 rounds of test iterations, the test coverage stabilized at over 98%, and the fault detection rate improved by over 40%. Compared with the solution without reinforcement learning optimization, the testing capability continues to evolve.

[0027] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. An automated testing and optimization method for motherboard multi-interface compatibility, characterized in that: The optimization method includes the following steps: S1. Motherboard interface feature library construction and update: Based on the import of new motherboard models, test standard updates or fault data feedback triggers, interface information and industry test standards are obtained through a combination of automatic collection and manual completion. After data cleaning and index optimization, a standardized feature library is built, which supports cross-motherboard model adaptation and dynamic iterative updates. S2. Intelligent test case generation and optimization: Based on the updated feature library and historical test records, a basic test case set is generated through a decision tree model. Boundary value analysis is combined to expand extreme scenario test cases. Then, a genetic algorithm is used to optimize and eliminate redundant test cases. Finally, the optimal test case set is generated by sorting the test cases according to the importance of the interface and the historical failure rate. S3, Parallel test environment configuration: Based on the loaded test case set, initialize the hardware platform and load the adapter driver. Calculate the interface resource allocation ratio through the resource scheduling module, allocate independent test threads and hardware channels to each interface, and complete the parallel test architecture configuration after resource conflict detection and environment self-check. S4: Multi-threaded parallel test execution, starts the test thread pool and allocates test cases according to priority, each thread executes the test process in parallel, monitors the test progress in real time, pauses the current thread and records the fault snapshot when an exception is triggered, releases thread resources after the fault is handled, and supports breakpoint resume testing. S5. Real-time data acquisition and fault self-diagnosis: Collect test data at a preset frequency and preprocess it. Use a similarity matching algorithm to compare the test results with the standard data in the feature library to determine the test results. If the threshold is not met, trigger fault tree analysis to locate the cause of the fault. After generating a diagnostic report, perform secondary verification. If the verification is successful, feed back the fault data to the feature library update module. S6. Test report generation and closed-loop optimization: Summarize test data to generate a visual report, start the reinforcement learning module to update the test case generation strategy, and synchronously update the feature library to supplement fault information and new interface parameters. After review, save the optimized feature library and test case model to form a closed-loop test system of testing, diagnosis and optimization.

2. The automated testing and optimization method for motherboard multi-interface compatibility according to claim 1, characterized in that: The interface information in S1 includes interface type, protocol version, pin definition, transmission rate range and power supply standard. The feature library adopts a two-level index structure of motherboard model and interface type. The data cleaning process uses preset regular expressions to unify interface naming and protocol version formats, rejects non-standard expressions, and ensures the consistency of feature library data.

3. The automated testing and optimization method for motherboard multi-interface compatibility according to claim 1, characterized in that: In S2, the population size of the genetic algorithm is set to 100, the crossover probability is 0.6, the mutation probability is 0.1, the maximum number of iterations is 50, and the fitness function weight can be dynamically adjusted according to the test scenario. During mass production testing, the weight of execution time is increased, and during R&D testing, the weight of coverage is increased.

4. The automated testing and optimization method for motherboard multi-interface compatibility according to claim 1, characterized in that: The resource allocation ratio in S3 is calculated using a dynamic resource scheduling algorithm, the complete formula of which is as follows: in, For the first The resource allocation ratio of the first interface represents the proportion of total hardware resources allocated to the first interface. The percentage of each interface; The test host comprehensively represents the hardware capabilities of the host, including CPU computing power, memory bandwidth, and I / O interface bandwidth, based on total hardware resources. For the first The test weight for each interface is set according to its importance level: core interfaces =0.3, important interface =0.2, normal interface =0.1; This represents the total number of interfaces to be tested. The S3 employs a global clock synchronization mechanism, achieving a synchronization accuracy of 1. When resource conflicts occur, a time-slicing reuse mechanism is used to adjust resource allocation to ensure the timing consistency of parallel testing of multiple interfaces.

5. The automated testing and optimization method for motherboard multi-interface compatibility according to claim 1, characterized in that: The test thread pool in S4 adopts a fixed thread pool and cache queue mode, and the fault snapshot collection content includes interface voltage, signal waveform and instruction log.

6. The automated testing and optimization method for motherboard multi-interface compatibility according to claim 1, characterized in that: In S5, data acquisition uses a 16-bit ADC module to acquire voltage and signal data with an error ≤ ±0.5%, and high-frequency noise is removed using a digital filtering algorithm. The similarity matching threshold is set to 90%, and the similarity matching algorithm formula is as follows: ,in For similarity, For test data, For standard data, For data dimensions.

7. The automated testing and optimization method for motherboard multi-interface compatibility according to claim 1, characterized in that: The fault tree model in S5 pre-sets fault nodes, combines the collected data to reverse reason the cause of the fault, and the secondary verification is achieved by adjusting the test conditions and executing special test cases.

8. The automated testing and optimization method for motherboard multi-interface compatibility according to claim 1, characterized in that: The reinforcement learning module in S6 designs a reward function based on improved test coverage and fault detection rate, and adjusts the decision tree splitting threshold and the fitness weight of the genetic algorithm. The visualization report supports PDF / Excel format and includes three levels of details: interface, use case and result, as well as fault diagnosis information. The feature library update adopts an automatic labeling and manual review mechanism. High-risk updates must be manually reviewed and approved before they can be saved.

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