A quasi-streaming computation method based on quasi-continuous discrete signal injection

Abstract

The application discloses a quasi-stream computing method based on quasi-continuous discrete signal injection and belongs to the technical field of general computing architecture. A complete computing task is divided into discrete computing units, a scheduling sequence is dynamically generated according to task logical dependency, and the quasi-continuous discrete signal is delivered to the computing units in a streaming mode according to demand to participate in operation. The quasi-continuous discrete signal follows the "immediate triggering and on-demand accessibility" principle: the next unit delivery is directly triggered after the current step is completed, and there is no need to wait for the full amount of data to be in place. Only the units directly required by the task logic have scheduling rights, and the rest do not consume delivery and computing resources. The application overturns the traditional "global loading-random memory access" architecture from the bottom paradigm, gets rid of the dependence on large-capacity high-speed storage, significantly reduces the computing power cost, and is suitable for the fields of artificial intelligence large models and numerical calculation.

Description

Technical Field

[0001] This invention relates to the field of general computing architecture technology, and in particular to a quasi-streaming computing method that reduces the rigid demand for high-speed storage capacity and eliminates random memory access bottlenecks. It can be widely applied to various information processing fields that employ discrete computing units. Background Technology

[0002] Current large-scale computing predominantly employs a "global load-random memory access" architecture, where all data and instructions for a complete computation task are first loaded into high-speed memory, and then the data is retrieved for computation using random addressing. The fundamental flaw of this architecture is that the computing unit must wait for all data to be available before starting computation, while the effective data actually required for a single computation often represents only a tiny fraction of the total data. A large amount of invalid data consumes transmission bandwidth, resulting in a double waste of storage resources and bus bandwidth. While some existing streaming computing technologies achieve batch loading of data, they still rely on traditional random addressing mechanisms for data scheduling and require the retention of numerous reusable global copies in high-speed storage, failing to truly eliminate the dependence on full data preloading. As the scale of computing tasks grows exponentially, these flaws become increasingly pronounced: the demand for large-capacity, high-speed storage surges, leading to persistently high computing costs; simultaneously, random memory access results in extremely low bandwidth utilization, wasting a significant amount of computing power. Existing optimization methods focus on improving memory access efficiency and hardware performance, without fundamentally changing the underlying "full load-random memory access" computing architecture, and thus cannot completely solve the aforementioned problems. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a non-resident streaming computing method based on quasi-continuous discrete signal injection, which completely gets rid of the dependence on large-capacity high-speed storage from the computing paradigm level, eliminates the bottleneck of random memory access, and builds an autonomous, controllable, high-efficiency, and scalable next-generation general-purpose computing architecture.

[0004] This invention is achieved through the following technical solution: 1. Based on the input-based computation task sequence, the scheduling module dynamically derives the discrete computation units required for the current computation step according to the logical dependencies in the evolution of the computation task, and generates the corresponding scheduling sequence; the derivation basis of the scheduling sequence includes, but is not limited to, the logical structure of the computation task, the real-time load of the computation unit, external input, and the dynamic requirements revealed by the intermediate states generated during the computation process; the scheduling sequence can be dynamically adjusted according to changes in any one or more of the above-mentioned basis.

[0005] 2. Divide the complete computing task into several discrete computing units. The discrete computing units are independently schedulable computing segments divided according to the logical structure of the computing task. The granularity of each discrete computing unit can be flexibly determined according to the characteristics of the computing task and the hardware conditions. Assign a unique scheduling identifier to each discrete computing unit. The scheduling identifier is the abstract identity of the unit in the scheduling logic and is decoupled from the physical storage location.

[0006] 3. According to the scheduling sequence, discrete computing units are injected into the computing units on demand in the form of quasi-continuous discrete signals, and computation is performed while the signals are being delivered.

[0007] The scheduling module generates a scheduling sequence based on the logical structure of the computation task, and the injection module delivers the corresponding discrete computing units to the computing core using a signal injection method according to the scheduling sequence. In this process, the scheduling and delivery of discrete computing units follow the logical principle of "instant triggering and on-demand availability." - The "logical structure" refers to the execution dependencies of computing tasks at the abstract level; - The "instant triggering" refers to the direct triggering of the scheduling and delivery of the next required discrete computing unit when the current calculation step is completed, without waiting for all task data to be available; - The term "on-demand accessibility" means that at any given moment, only those discrete computing units that are directly required by the evolution logic of the computing task have the right to be scheduled; the remaining units, regardless of their storage location, do not respond to scheduling and do not consume delivery and computing resources.

[0008] Under the above criteria, this method does not depend on any specific scheduling algorithm, address mapping strategy, or hardware topology; any scheduling and injection mechanism that enables the above logical criteria falls within the protection scope of this invention.

[0009] 4. The use of discrete computing units follows the principle of "on-demand scheduling, termination upon completion": - For discrete computing units that do not need to participate in the current computation step, regardless of whether they are physically located in high-speed storage units, they are not included in the current scheduling sequence and do not consume computing resources. - For discrete computing units that have completed the current step of the operation, their corresponding storage space is no longer forcibly dependent on by subsequent steps, and can be immediately released, overwritten or set to a lazy state, without retaining a reusable global copy; - Dynamic intermediate states generated during the computation process can be temporarily stored in high-speed storage to ensure computational continuity, provided that a global copy that can be reused across tasks is not created.

[0010] The above principles do not change their applicability due to changes in hardware conditions.

[0011] Core operating principles and key technical details I. Foundation of Mathematical Equivalence The correctness of the technical solution disclosed in this invention is based on the following mathematical facts: the layers of the Transformer model have a strict sequential dependency relationship, and the input of each layer depends only on the output of the previous layer and the weights of the current layer, with no cross-layer interleaving dependencies. Therefore, by decomposing the complete model into discrete computational units at the layer level and strictly scheduling them in a sequential streaming manner, the input / output data flow of each layer is completely consistent with a one-time full load execution, and is equivalent in a mathematical computational sense.

[0012] When the granularity of discrete computation units is further refined into attention heads or weight slices within a layer, the parallel independence between attention heads and the decomposability of matrix block multiplication and addition within the feedforward network layer ensure that computation within a slice does not depend on other slices in the same layer. Therefore, slice-based streaming computation is mathematically equivalent to one-time computation of the entire layer. This equivalence does not depend on the specific parameter scale of the model or the task type.

[0013] II. Layer-by-layer serial triggering and on-demand loading mechanism This invention employs a strict layer-by-layer serial computation and layer-by-layer on-demand loading mode, loading only the entire weight slice of a single layer corresponding to the current computation sequence at a time; after completing the attention score calculation and activation unit selection within the layer, only the discrete computation units activated by the current context are retained, and all storage and computation resources that are not activated in the layer are immediately released before loading the weights of the next layer for subsequent computation.

[0014] Under this mechanism, the system only needs to retain the complete weights of at most one layer in memory at any given time, and its resource overhead is only 1 / N of the full model loading (N is the total number of model layers), which fundamentally avoids the resource waste of preloading the full model weights.

[0015] III. Real-time capture method for discrete computing unit hit flags The hit flag capture of discrete computing units is achieved by inserting a lightweight scheduling hook function into the computation graph execution engine. A unique global scheduling flag is pre-bound at the entry point of each discrete computing unit. When the unit is executed by forward propagation logic, the hook function automatically reports the unique scheduling flag of the unit to the global scheduling index module, thus completing the real-time capture and recording of the hit flag.

[0016] This capture method does not require modification of the model's core computational logic; it can be achieved simply through lightweight injection at the computation graph level, and its impact on overall computational performance is negligible.

[0017] IV. Physical transport instruction generation mechanism based on scheduling identifier The global scheduling index module maintains a hardware mapping table, recording the correspondence between each unique scheduling identifier and the physical storage location of the corresponding discrete computing unit in the source storage unit. Once the scheduling sequence is determined, the index module converts the scheduling identifier into the corresponding physical address or bus transmission instruction through a table lookup operation, driving the physical transfer of data from the source storage unit to the computing unit.

[0018] This mechanism decouples the logical-level scheduling identifier from the physical-level address addressing: the upper-level scheduling logic only focuses on "which unit to schedule," while the lower-level hardware mapping is responsible for "where the unit is located." This solution does not eliminate the physical addressing operations necessary for data movement, but rather encapsulates them as a one-way mapping from identifier to address, making it transparent to the upper-level scheduling.

[0019] The source storage unit is the physical location where the discrete computing unit resides before it is scheduled. It can be a low-speed storage unit or a different region of the same high-speed storage unit. This mechanism does not restrict the physical type and speed level of the source storage unit.

[0020] V. Configurability of Attention Activation Threshold This invention supports a dynamically adjustable attention activation threshold mechanism, which only includes discrete computing units in the current computation scheduling sequence when the attention weight corresponding to the discrete computing unit is greater than the preset activation threshold. The activation threshold can be flexibly configured according to hardware resources, computational accuracy requirements and application scenario characteristics to achieve an optimal balance between resource consumption and computational accuracy.

[0021] VI. Scheduling and processing of cross-layer data dependencies For discrete computing units with cross-layer data dependencies, the global scheduling index module automatically maintains a complete dependency chain and prioritizes scheduling preceding dependent units according to the data dependency order. Units that do not meet all preceding dependency conditions are not loaded into the computing core until all their preceding dependent calculations are completed and valid data is output. This mechanism ensures the correctness of the computing logic while avoiding the premature occupation of invalid resources.

[0022] VII. Granularity Definition of Discrete Computational Units The discrete computing unit described in this invention is an independently schedulable computing module of arbitrary granularity, including but not limited to: complete model layers, weight slices within layers, single operator modules, sub-network fragments, etc. Any computing unit of any granularity, as long as it adopts the core mechanism of "unique global scheduling identifier + dynamic attention triggering + on-demand loading scheduling", falls within the protection scope of this invention.

[0023] VIII. Optimization Forms of Quasi-Stream Scheduling The quasi-stream scheduling method described in this invention includes, but is not limited to, engineering optimization forms such as real-time loading, preloading of units required for subsequent time series, and batch scheduling of continuously identified units; as long as the core logic is "only loading units necessary for current and subsequent calculations, without preloading all model weights", it falls within the scope of quasi-stream scheduling defined in this invention.

[0024] IX. Logical Definition of "Quasi-Continuous Discrete Signal" It should be noted that the "quasi-continuous discrete signal" described in this invention is essentially a logical-level abstraction, and is not limited to having independent physical encapsulation or independent time intervals at the physical transmission layer.

[0025] Any delivery mechanism that logically satisfies the following conditions simultaneously constitutes the "delivery of quasi-continuous discrete signals containing effective information of discrete computing units to the computing core for computation as described in this invention": 1. The delivered valid information completely and exclusively describes a discrete computing unit with a unique scheduling identifier; 2. The computing core can extract the valid information of the discrete computing unit from the data stream based on the metadata provided by the delivery mechanism, and independently execute its operation.

[0026] 3. Therefore, implementation methods such as "continuous data stream + in-band instructions" can enable the scheduling and injection mechanism described in this invention and fall within the protection scope of this invention, as long as the in-band instructions logically define the boundaries of each discrete computing unit and the delivered content meets the above conditions.

[0027] Terminology Boundary Definition To clarify the precise boundaries of the core term "non-residential" in this invention, the following definition is provided: The "non-resident" in this invention refers to the fact that the complete original data of the computing task and its reusable global copy do not reside in the high-speed storage of the computing unit after the current computing step is completed.

[0028] The following data does not fall under the category of "stay": 1. Dynamic intermediate states generated during the computation process. These intermediate states are only valid for the current computation task sequence, do not have the ability to be reused across tasks, and do not constitute a reusable global data copy; 2. The metadata such as the scheduling index table and hardware mapping table that reside in order to achieve streaming scheduling is much smaller in size than the original data of the computing task and does not have general computing reuse value. The "non-resident" principle of this invention opposes "global loading," not "dynamic intermediate state temporary storage necessary for computational continuity."

[0029] 3. It should be noted that the implementation methods of the "dynamic derivation" include, but are not limited to, real-time computation graph derivation, as well as static scheduling mapping tables generated based on the pre-analysis of the logical dependencies of computation tasks. Regardless of the implementation method, the scheduling behavior must follow the logical principle of "instant triggering and on-demand reachability," that is, only those discrete computing units that are directly required by the evolution logic of the computation task have the right to be scheduled.

[0030] 4. It should be noted that the "scheduling and delivery" in the above logical principle is a functional abstraction of the scheduling module described in this invention, and does not limit the specific physical implementation location of the "on-demand filtering" function. Regardless of whether the filtering logic is implemented in the scheduling module, the injection module, or the computing core, as long as the entire computing system only activates and delivers discrete computing units directly required by the evolution logic of the computing task at any given time, it constitutes the enabling of the "instant triggering, on-demand reach" logical principle of this invention.

[0031] 5. It should be noted that the "delivery resources" in the "not consuming delivery and computing resources" mentioned in this invention include, but are not limited to, any physical resources used to transmit valid information of discrete computing units, such as system bus bandwidth, direct memory access channels, and network links. Any actively initiated delivery behavior that occupies the above-mentioned physical resources, regardless of whether it utilizes idle time periods, constitutes a consumption of delivery resources.

[0032] 6. Furthermore, the judgment criterion for the "direct requirement of the computation task evolution logic" described in this invention is strictly limited to "whether, at the current computation moment, there is a direct and indispensable dependency on the operation to complete the current computation step." Any relaxation of this judgment criterion, including but not limited to pre-assigning scheduling rights based on predictions of future computation steps, does not constitute compliance with the "on-demand reachability" logic principle of this invention. Beneficial effects

[0033] This invention has the following significant technical and industrial effects: I. Technical Effects 1. Significantly reduces the rigid demand for high-speed storage capacity: Through an on-demand scheduling mechanism, the system only needs to reside the discrete computing units necessary for the current computing step in high-speed storage, reducing the rigid dependence of large-scale computing tasks on high-speed storage capacity from the level of "full task scale" to the level of "current effective computing demand". This fundamentally shifts the core bottleneck of the computing system from "storage density" to "computation density", making it possible to accomplish large tasks with limited resources on resource-constrained hardware, while also allowing for a more efficient release of computing power constrained by ineffective data movement on resource-rich hardware. 2. Significantly improved computational efficiency: By decoupling the data scheduling logic from the physical address addressing, the dependence of the upper-layer scheduling logic on the traditional random memory access mechanism is eliminated, enabling the computing unit to continuously receive the required discrete computing unit data stream, minimizing the idle time of the computing unit caused by data waiting; the bus bandwidth utilization is greatly improved, approaching the theoretical peak of the hardware, and the total computational latency is significantly reduced. 3. Broad hardware and scenario adaptability: This method does not depend on a specific hardware platform, instruction set architecture or computing task type. Its core scheduling logic is decoupled from the physical implementation, and can be widely applied to various information processing devices that use discrete computing units for operation, covering the entire hardware spectrum from low-end edge devices to high-end computing power clusters, as well as various computing scenarios such as artificial intelligence, numerical computing, and signal processing. II. Industry Impact 1. Significantly reduces the rigid dependence of large model applications on high-end hardware: Through an on-demand scheduling mechanism, the high-speed storage capacity required for a single computation is greatly reduced, making it possible to deploy ultra-large-scale models on low-cost hardware; even on high-end hardware, this invention can release computing power constrained by storage bottlenecks by eliminating invalid computations. The decoupling of long context inference capability with large-capacity high-speed random access storage capacity enables ultra-long context inference on low-resource hardware; based on the technical solution of this invention, it also provides the possibility of achieving ultra-large batch training on low-cost hardware, which is expected to significantly improve training convergence speed and overall efficiency.

[0034] 2. Promoting the independent development of the domestic computing ecosystem: The method of this invention decouples from specific hardware architectures at the underlying scheduling logic, effectively adapting to various processors such as domestic CPUs, GPUs, and NPUs. This provides underlying technical support for independent computing software stacks based on domestic chips.

[0035] 3. Provides key technical support for achieving independent and controllable computing power: The method of this invention significantly reduces the rigid dependence threshold of large-scale computing tasks on specific high-end imported hardware, enabling the same computing tasks to run efficiently on a wider range of hardware platforms (including domestically produced chips), providing a key computing paradigm support for building an independent and controllable computing power system. Detailed Implementation

[0036] Example 1: Layer-by-layer release inference scenario under low-resource hardware conditions This embodiment is one of the preferred embodiments of the present invention, demonstrating the technical solution of the present invention for implementing large model inference on hardware with limited storage resources. The specific steps are as follows: 1. Divide the weights of the large model into several discrete computing units (i.e., weight blocks) according to the hierarchical structure, and assign a unique scheduling identifier to each weight block; 2. When the input inference sequence enters the system, the scheduling module dynamically derives the weight block identifiers required for the current step based on the current computing position and the inherent hierarchical structure of the model, and generates a scheduling sequence. At the same time, the scheduling module can dynamically adjust the injection order and rate of weight blocks according to the real-time load of the computing unit to avoid the computing unit being idle or overloaded. 3. The injection module injects the weight blocks into the computing unit in the form of quasi-continuous discrete signals from the low-speed storage unit according to the scheduling sequence. The computing unit directly receives the weight block data stream for calculation, without having to load the complete model weights into the high-speed storage. 4. After the operation is completed, the corresponding weight block is released immediately or set to an inert state. Its corresponding storage space is no longer forcibly depended on by subsequent steps. No reusable copies that can be used for subsequent inference steps are retained. The high-speed storage only retains the streaming buffer necessary for the execution of the current calculation step. At the same time, a small amount of necessary intermediate data can be retained according to the task requirements of large model inference. This intermediate data is only used for the subsequent steps of the current inference sequence, does not form a reusable global copy, and does not affect the core feature of streaming scheduling of this invention. 5. The computation process and the weight block delivery process form a pipeline overlap, and the total inference latency does not depend on the loading latency of the complete model.

[0037] Example 2: High-end hardware full-resident zero-handling inference scenario This embodiment is a preferred implementation of the present invention under high-end hardware conditions, and the specific steps are as follows: 1. The complete large model weights are loaded into the high-speed storage of the high-end computing unit in full-precision format at once, achieving global static resident; this loading process is only a one-time operation in the initialization phase, and the physical location of the weights will not change across devices during subsequent inference processes; 2. When the input inference sequence enters the system, the scheduling module dynamically derives the discrete computing unit identifiers required for the current step based on the current computing position and the inherent hierarchical structure of the model, and generates a scheduling sequence. In this scenario, the attention activation threshold can be flexibly configured according to performance requirements, and only discrete computing units that have a substantial impact on the current context are selected. 3. The computing unit directly initiates computing instructions to the statically resident discrete computing units according to the scheduling sequence, without having to re-transfer weight data from the low-speed storage unit; the discrete computing units excluded by the scheduling sequence are physically located in high-speed storage, but do not participate in any computing in the current step and do not consume computing resources. 4. After each discrete computing unit completes its operation, its calculation result is directly written into the dynamic intermediate state without the need for intermediate data transfer or additional storage copy generation. At the same time, the weight data of the discrete computing unit itself remains in a static resident state and is not removed or released. Only its corresponding activation flag is reset so that it can be re-selected in the next inference step. 5. Repeat the above steps until the complete inference task is completed. Throughout the inference process, the physical location of the model weights remains static, and only the instruction stream and activation flags are dynamically changed, achieving quasi-streaming efficient inference with "zero weight cross-device transfer and zero invalid computation".

[0038] 6. The effect of this embodiment is that by eliminating invalid calculations and releasing the computing power of the computing core, a single high-end graphics card can simultaneously serve far more concurrent inference requests than traditional architectures, resulting in an order-of-magnitude leap in throughput.

[0039] It should be noted that, in this embodiment, although the model weights achieve global static residency, the inference calculation at each step still strictly follows the "instant triggering, on-demand reach" logical principle of this invention. The scheduling module only initiates calculation instructions for discrete computing units directly required by the evolution logic of the computed task; units excluded from the scheduling sequence do not participate in the calculation. Any technical solution that implements the above-mentioned "full residency, on-demand scheduling" on high-end hardware falls within the protection scope of this invention.

[0040] Experiment Example 3: Sparsity Verification of On-Demand Scheduling Mechanism Experimental environment and configuration: The software environment for this experiment was: Python 3.10, PyTorch 2.1.2 + cu118, Transformers 4.41.0; the hardware environment was: Intel i7-12700KF CPU, 16GB DDR5 memory, NVIDIA GeForce GTX 1070 (8GB) GPU. The experimental model was the Qwen2.5-1.5B-Instruct open-source dense Transformer model, with all its weights loaded in FP32 full-precision format for inference.

[0041] With the aforementioned hardware and software configuration, the input text is segmented into words. During the model's forward inference process, the attention weights of each layer's self-attention module are captured by registering forward hooks. Multiple attention activation thresholds are set in the experiment to simulate the "on-demand filtering" process of the scheduling module described in this invention on discrete computing units.

[0042] Under the condition of simulating long context reasoning (context sequence length of 7 tokens), different granularities of filtering were achieved by setting attention activation thresholds. The experimental results are as follows: Activation threshold 0.01 - Overall activation rate 46.36% - Memory transfer reduction rate 53.64% Activation threshold 0.05 - Overall activation rate 31.97% - Memory transfer reduction rate 68.03% Activation threshold 0.10 - Overall activation rate 24.93% - Memory transfer reduction rate 75.07% Activation threshold 0.20 - Overall activation rate 18.45% - Memory transfer reduction rate 81.55% Under the condition of simulating long context reasoning (context sequence length of 174 tokens), different granularities of filtering were achieved by setting attention activation thresholds. The experimental results are as follows: Activation threshold 0.01 - Overall activation rate 10.13% - Memory transfer volume reduction rate 89.87% Activation threshold 0.05 - Overall activation rate 3.41% - Memory transfer volume reduction rate 96.59% Activation threshold 0.10 - Overall activation rate 2.09% - Memory transfer volume reduction rate 97.91% Activation threshold 0.20 - Overall activation rate 1.33% - Memory transfer volume reduction rate 98.67% Experimental data shows that, regardless of whether the sequence is short or long, scheduling only a very small number of activated discrete computing units is sufficient to cover the majority of the computational needs of the inference process. This experimental data strongly supports the core claim of this invention: during the evolution of the computational task, only a very small number of discrete computing units make a substantial contribution to the current output. This directly confirms the universality and effectiveness of the "on-demand reachability" logic principle of this invention, namely, scheduling only the discrete computing units directly required by the evolving logic of the computational task can achieve computational results equivalent to full loading. The quasi-streaming scheduling method described in this invention is based on this ubiquitous objective phenomenon, thereby reducing computational resource overhead by more than an order of magnitude.

[0043] The scope of protection of this invention is not limited to the above embodiments and experimental examples. Any equivalent transformations and substitutions based on the technical solutions of this invention are within the scope of protection of this invention.

Claims

1. A calculation method, characterized in that, include: Based on the logical dependencies in the evolution of computing tasks, the discrete computing units required for the current computing step are dynamically derived, and the corresponding scheduling sequence is generated. According to the scheduling sequence, quasi-continuous discrete signals containing valid information of discrete computing units are delivered to the computing core for computation as needed. The scheduling and delivery of discrete computing units follow the logical principle of "instant triggering and on-demand availability"—the delivery of the next required unit is triggered directly when the current computing step is completed, without waiting for all task data to be available. At any given moment in computation, only the units directly required by the computation task's evolution logic have scheduling rights; the remaining units do not consume delivery and computation resources.

2. The method according to claim 1, characterized in that, The quasi-continuous discrete signal refers to a discrete computing unit that exists as an independent unit and whose delivery process is continuous and orderly, enabling the computing core to continuously receive and execute discrete computing units without substantial idle waiting; the quasi-continuous discrete signal does not limit the specific type of encoding method, modulation method, or transmission medium.

3. The method according to claim 1, characterized in that, The quasi-continuous discrete signal may contain auxiliary information superimposed, interleaved, or encapsulated with the effective information of the discrete computing unit, and the presence of the auxiliary information does not impair the independent extraction of the effective information by the computing core. The computing unit extracts the effective information of the discrete computing unit before or during the calculation.

4. The method according to claim 1, characterized in that, Each discrete computing unit corresponds to a unique scheduling identifier, which is the abstract identity of the unit in the scheduling logic. The scheduling sequence is delivered in an orderly manner through this identifier, and the mapping relationship between the scheduling identifier and the physical storage location is transparent to the upper-level scheduling logic.

5. The method according to claim 1, characterized in that, After a discrete computing unit completes the current step of the operation, its corresponding storage space is no longer forcibly dependent on by subsequent steps, and it does not retain a global copy that can be reused across tasks.

6. The method according to claim 1, characterized in that, The computation process overlaps with the delivery process of discrete computing units in a pipeline, and the total computation latency does not depend on the global loading latency of the complete computation task.

7. The method according to claim 1, characterized in that, The computing unit is any information processing device capable of performing discrete computing unit operations.

8. The method according to claim 7, characterized in that, The computing unit includes a classical computing processor; the classical computing processor includes a CPU, GPU, NPU, FPGA, and application-specific integrated circuits.

9. The method according to claim 1, characterized in that, The computational tasks include artificial intelligence model inference and training, combinatorial optimization calculations, molecular simulations, numerical calculations, and signal processing execution.

10. The method according to claim 1, characterized in that, The discrete computing unit is an independently schedulable computing segment divided according to the logical structure of the computing task. Its granularity can be flexibly determined according to the characteristics of the computing task and the hardware conditions; including but not limited to data blocks, instruction blocks, and weight blocks.

11. The method according to claim 1, characterized in that, The derivation of the scheduling sequence is based on, but is not limited to, the logical structure of the computing task, the real-time load of the computing unit, external input, and the dynamic requirements revealed by the intermediate states generated during the computing process; the scheduling sequence can be dynamically adjusted according to changes in any one or more of the above-mentioned criteria.

12. The method according to claim 1, characterized in that, Dynamic intermediate states generated during computation can be temporarily stored in high-speed storage to ensure computational continuity, provided that a global copy that can be reused across tasks is not created.

13. A computing device, characterized in that, include: The computation task input interface is used to receive the input sequence of computation tasks; The scheduling module is used to dynamically deduce the discrete computing units required for the current computing step based on the logical dependencies in the evolution of the computing task, and generate the corresponding scheduling sequence. The derivation of the scheduling sequence is based on, but is not limited to, the logical structure of the computing task, the real-time load of the computing units, external inputs, and the dynamic requirements revealed by the intermediate states generated during the computing process. The scheduling module is also used to dynamically adjust the scheduling sequence according to changes in any one or more of the above criteria. Discrete computing storage units are used to store the partitioned discrete computing units; the discrete computing storage units include, but are not limited to, volatile storage media and non-volatile storage media. The injection module is used to deliver quasi-continuous discrete signals containing valid information of discrete computing units to the computing core as needed, according to the scheduling sequence. The computing module is used to receive the quasi-continuous discrete signal and perform calculations; wherein, the scheduling and delivery of discrete computing units follow the logical principle of "instant triggering and on-demand availability"—when the current computing step is completed, the delivery of the next required unit is triggered directly, without waiting for all task data to be in place; at any computing moment, only the units directly required by the computing task evolution logic have the right to be scheduled, and the other units do not consume delivery and computing resources. The calculation result output interface is used to output the calculation results.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1-12.

15. A computer program product, characterized in that, When the computer program product is run on a computer, it causes the computer to perform the method according to any one of claims 1-12.