Cache space management method and storage device

Abstract

This application provides a cache space management method and a storage device. The method includes: in response to meeting a reduction condition, performing a traversal from the head of an LRU linked list to select the first cache unit belonging to a cold cache unit set as the cache unit to be reduced; performing a read operation on the cache unit to be reduced to determine whether there exists at least one other cache unit different from the cache unit to be reduced, whose total capacity of free storage slots can accommodate all mapping table entries in the set to be processed; if so, performing a copy write operation to other cache units on the mapping table entries in the set to be processed; if not, performing a write operation to the memory module on the dirty mapping table entries in the set to be processed. The above method, through cold and hot separation and LRU dual screening mechanism, prioritizes the retention of high-value mapping table entries within a limited cache space, reduces write operations to the memory module, thereby reducing write amplification, improving storage device performance, and extending its service life.

Description

Technical Field

[0001] This application relates to the field of memory control, and in particular to a cache space management method and a storage device. Background Technology

[0002] In NAND flash memory modules, the logical address to physical address (L2P) mapping is the core data structure supporting data read and write operations. It not only carries the basic address mapping function but also solves problems such as the inability to overwrite NAND flash, inconsistent erase / write units, and bad block management. Specifically, when the host issues a read / write request, the storage device first queries the L2P table to translate the logical address into a physical address before executing subsequent data access operations. Therefore, the management efficiency of the L2P table directly determines the read and write performance of the storage device.

[0003] To meet the demands of high-speed read and write operations, L2P tables typically need to be cached in volatile memory with fast access speeds, such as SRAM (Static Random-Access Memory). However, due to limitations in cost and chip area, the actual configurable SRAM capacity in a storage device is often limited, making it difficult to accommodate a complete L2P table.

[0004] Furthermore, SRAM, as a cache space, needs to accommodate L2P tables as well as serve multiple functions such as instruction caching and user data caching. For example, given a fixed total cache space, there is an inherent resource contention between the L2P table cache and the data cache: if the L2P table occupies too much cache space, the data cache capacity will be squeezed. In scenarios such as random reads, insufficient data cache will lead to frequent NAND Flash accesses, resulting in a significant decrease in overall performance. Conversely, if data cache is prioritized, the cache hit rate of the L2P table will decrease, and each address translation may trigger an additional read of the NAND Flash, similarly slowing down read and write response speeds.

[0005] Therefore, under the constraint of limited SRAM capacity, how to efficiently manage the mapping table entries in the cache space is a technical problem that researchers in this field are studying. Summary of the Invention

[0006] In view of this, this application provides a cache space management method and storage device to solve or partially solve the above problems.

[0007] In a first aspect, this application provides a cache space management method applied to a storage device. The storage device includes a memory controller and a cache space. The cache space is configured with multiple cache units for temporarily storing mapping table entries. Each cache unit is a contiguous storage area within the cache space, internally divided into multiple slots of equal size. Each slot can accommodate one or more mapping table entries, wherein each mapping table entry is marked as a dirty mapping table entry or a clean mapping table entry based on its data state, and as a hot mapping table entry or a cold mapping table entry based on its access frequency. The method includes: maintaining an LRU linked list and a hot / cold separation data structure to manage the multiple cache units; in response to meeting a reduction condition, performing a traversal starting from the head of the LRU linked list, selecting the first cache unit classified by the hot / cold separation data structure as belonging to a cold cache unit set as the cache unit to be reduced; if the traversal fails to find a cache unit belonging to the cold cache unit set, the current traversal is terminated. The process involves several steps: First, reducing the cache size. This involves performing a read operation on the cache unit to be reduced to obtain all dirty and hot mapping entries stored in the cache unit as a set to be processed. Then, invalidating the clean cold mapping entries stored in the cache unit to be reduced, where the hot mapping entries include both clean and dirty hot mapping entries. Next, it is determined whether one or more other cache units different from the cache unit to be reduced exist, whose total free storage slot capacity can accommodate all mapping entries in the set to be processed. If the determination result is yes, a copy-write operation is performed on the mapping entries in the set to be processed to the other cache units, and the cache unit to be reduced is released after the operation is completed. If the determination result is no, a write operation is performed on the dirty mapping entries in the set to be processed to the memory module, the clean hot mapping entries in the set to be processed are invalidated, and the cache unit to be reduced is released.

[0008] Optionally, the cache space includes static random access memory and a host cache. The hot and cold separation data structure includes a hot cache unit linked list and a cold cache unit linked list, which are used to maintain cache units classified into the hot cache unit set and the cold cache unit set, respectively.

[0009] A second aspect of this application provides a storage device, comprising: a connection interface for electrically connecting to a host; a memory module including multiple planes, each plane including multiple blocks, each block including multiple physical pages; and a memory controller including error checking and correction circuitry, cache memory, and memory control circuitry, electrically connected to the connection interface and the memory module; and a cache space including static random access memory and a host cache; wherein the memory control circuitry is configured to perform the cache space management method as described in the first aspect.

[0010] This application provides a cache space management method and storage device. When managing cache units in a limited cache space, in addition to the eviction criterion of most recent access time in the LRU linked list, a cold and hot separation data structure is introduced to perform secondary classification of cache units. During reduction, it requires that both the end of the LRU linked list and belonging to the cold cache unit set be satisfied simultaneously. This essentially transforms the evaluation of cache units from a single dimension (time) to a two-dimensional (time + popularity) approach. Furthermore, regarding the selective processing of eviction granularity, instead of invalidating all selected cache units, processing is performed at the granularity of the mapping table entries within the cache unit: dirty mapping table entries (regardless of whether they are cold or hot) and hot mapping table entries (regardless of whether they are dirty or clean) are retained, and only clean cold mapping table entries are invalidated. This constructs a three-classification problem: non-discardable (dirty), worth retaining (hot and clean), and directly discardable (cold and clean). Finally, the eviction process for mapping entries within the cache unit is as follows: priority is given to migrating them to other cache units (to avoid write amplification), followed by writing dirty data back to the memory module (to ensure data consistency). On this basis, in conjunction with the parallel execution of host commands (read commands and push operations), high-value mapping entries are prioritized to be retained within the limited cache space, reducing write operations to the memory module, thereby reducing write amplification, improving storage device performance, and extending its lifespan. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of this application; Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application; Figure 3 This is a schematic diagram of a memory management module according to an embodiment of this application; Figure 4 This is a schematic diagram of the cache space shown according to an embodiment of this application; Figure 5 This is a flowchart of a cache space management method proposed in an embodiment of this application; Figure 6 This is a schematic representation of the LRU chain of the management cache unit shown in the embodiments of this application; Figure 7 This is a schematic diagram of a cold and hot data structure management cold and hot cache unit shown in an embodiment of this application; Figure 8 This is a schematic diagram illustrating the set of management cold and hot cache units shown in an embodiment of this application; Figure 9 This is a flowchart illustrating the cache unit lifecycle management process in an embodiment of this application; Figure 10 This is a schematic diagram of the internal structure of the cache unit shown in the embodiments of this application; Figure 11 This is a two-level decision flowchart for determining the target cache unit, as shown in the embodiments of this application; Figure 12 This is a flowchart illustrating the cold and heat separation management and dynamic threshold adjustment method in an embodiment of this application; Figure 13 This is a flowchart illustrating the pre-read push triggering process based on host command prediction, as shown in an embodiment of this application. Figure 14 This is a flowchart illustrating the collaborative processing of reduction and push operations in an embodiment of this application. Figure 15 This application presents a deadlock avoidance mechanism for scenarios with extremely tight cache space. Detailed Implementation

[0013] Reference will now be made in detail to exemplary embodiments of this application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0014] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of this application. Please refer to... Figure 1 The data storage system 10 includes a host 11 and a storage device 12. The storage device 12 can be connected to the host 11 and can be used to store data from the host 11. For example, the host 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, automotive infotainment system, advanced driver assistance system (ADAS), game console, server, or computer system set up in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host 11 is not limited to these.

[0015] The host 11 includes a processor 111 and memory 112. The processor 111 is responsible for all or part of the operation of the host 11. For example, the processor 111 may include a central processing unit (CPU), a graphics processing unit (GPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof.

[0016] Memory 112 is connected to processor 111 and used to cache data. For example, memory 112 may include random access memory (RAM) or a similar volatile storage device. It should be noted that memory 112 is located in host 11 (e.g., on the motherboard of host 11 or directly in processor 111), and not in storage device 12.

[0017] In one embodiment, the processor 111 may configure (e.g., partition) a host cache 1121 in the memory 112, and the storage device 12 may use the host cache 1121 to write and read data in the memory module 122.

[0018] In addition, storage device 12 may include solid-state drives (SSDs), universal flash storage (UFS), embedded multi-media cards (eMMC), USB flash drives, memory cards, or other types of non-volatile storage devices. It is particularly suitable for industrial control, edge computing, and automotive electronics fields with stringent requirements for reliability, data integrity, environmental tolerance, and long-term stability.

[0019] In one embodiment, the storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to a host 11. For example, the connection interface 121 may support embedded multimedia cards, general-purpose flash memory, Peripheral Component Interconnect Express (PCIE), Non-Volatile Memory Express (NVMe), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host 11 (e.g., exchange signals, instructions, and / or data) via the connection interface 121.

[0020] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include single-level cell (SLC) NAND flash memory modules, multi-level cell (MLC) NAND flash memory modules, triple-level cell (TLC) NAND flash memory modules, quadruple-level cell (QLC) NAND flash memory modules, and / or other memory modules with the same or similar characteristics. For multi-level cell (MLC, TLC, QLC, and PLC) flash memory modules, specially selected and tested flash memory modules that meet the requirements of wide operating temperature (e.g., -40°C to 105°C or higher), high durability, and data retention can be used.

[0021] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller. In particular, for automotive functional safety requirements, the architecture of memory controller 123 may include safety islands, dual-core lockstep, or other redundancy and monitoring mechanisms to ensure the reliability of control logic.

[0022] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in this application. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0023] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application. Please refer to... Figure 1 and Figure 2The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to a host 11 via the connection interface 121 for communication with the host 11. The memory interface 22 is used to connect to the memory module 122 for accessing the memory module 122. In one embodiment, the memory interface 22 (such as ONFI, Toggle) includes data lines, command latches, address latches, read / write enable signals, and ready / busy signals.

[0024] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22, serving as the central processing and control hub of the memory controller 123, responsible for executing firmware code / instructions. This firmware runs on the memory control circuit 23 to implement the various functions of the storage device 12. The memory control circuit 23 can be used to control or manage the overall or partial operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host 11 via the host interface 21 and access the memory module 122 via the memory interface 22. The memory control circuit 23 may include control circuits for embedded processors such as the ARM Cortex-M / R series and Andes NDS32. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0025] In one embodiment, the memory controller 123 may further include a cache memory 24. The cache memory 24 is connected to the memory control circuitry 23 and controlled by the memory controller 123 to cache data. For example, the cache memory 24 can be used to cache instructions from the host 11, data from the host 11, and / or data from the memory module 122. Specifically, the logical-to-physical mapping table is typically resident or cached in the cache memory 24 to support high-speed access and updates. To ensure the reliability and consistency of the mapping table data (described in detail below) in the event of sudden events such as abnormal power failures, the cache memory 24 may employ a storage medium with power loss protection (PLP) characteristics, or incorporate a backup capacitor design to ensure that critical metadata has sufficient time to be written into the memory module 122. In one embodiment, the cache memory 24 is a static random-access memory (SRAM).

[0026] In one embodiment, the memory controller 123 may further include an error checking and correction circuit 25. The error checking and correction circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the error checking and correction circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code.

[0027] In one embodiment, the memory controller 123 may further include a power management circuit 26. The power management circuit 26 is connected to the memory control circuit 23 and is used to control the power supply of the storage device 12. The power management circuit 26 not only manages conventional power consumption, but also meets the complex power sequences and low static power consumption requirements of automotive electronics, and can handle voltage fluctuations during vehicle start-stop processes, ensuring that the storage device 12 operates stably in harsh power environments.

[0028] Figure 3 This is a schematic diagram illustrating a memory management module according to an embodiment of this application. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(0)-301(B). Each physical unit includes multiple storage cells for non-volatile data storage.

[0029] In one embodiment, an entity unit may include an entity programming unit. In one embodiment, an entity programming unit is also referred to as an entity programming unit. In one embodiment, an entity programming unit may be considered as an entity page.

[0030] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and this application is not limited thereto. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and this application is not limited thereto.

[0031] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0032] In one embodiment, an entity erasure unit may include multiple entity programmable units. In another embodiment, an entity erasure unit may be considered as an entity block.

[0033] In one embodiment, multiple programmed units in a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to multiple programmed units in this physical erase unit to change the threshold voltage of at least some of the memory cells in these programmed units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased.

[0034] In one embodiment, the memory control circuit 23 can logically associate entity units 301(0)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(0)-301(A) in the data area 31 all store data (also referred to as user data) from the host 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0035] In one embodiment, if a physical unit does not store valid data, this physical unit can be associated with the free area 32. Furthermore, physical units in the free area 32 can be erased to clear the data within them. In one embodiment, physical units in the free area 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as the free pool.

[0036] In one embodiment, in response to the requirements of predictable storage lifetime for industrial and automotive applications, the memory control circuit 23 can implement wear leveling and bad block management strategies, and monitor the number of erase / write cycles, read counts, and data retention time of each physical unit in real time, so as to provide the host 11 with a health status report and remaining lifetime prediction of the storage device 12, thereby meeting the diagnostic coverage requirements of relevant functional safety standards.

[0037] In one embodiment, when data needs to be stored (including new data in response to a write command from host 11 and the removal of old data during garbage collection operations), memory control circuitry 23 may select one or more physical units from idle area 32 and instruct memory module 122 to store data into the selected physical units. After data is stored in this physical unit, this physical unit can be associated with data area 31. In other words, one or more physical units can be used cyclically between data area 31 and idle area 32.

[0038] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(0)-302(C) to map physical units (i.e., physical units 301(0)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0039] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0040] In one embodiment, the memory control circuit 23 may record the mapping relationship between logical units and physical units in at least one management table (also known as a logical-to-physical mapping table, or L2P table, mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform data read, write, or erase operations based on the information in this management table (i.e., logical address to physical address mapping table).

[0041] In one embodiment, the aforementioned logical-to-physical mapping table is stored in the system area of ​​the memory module 122. Each mapping table includes multiple mapping entries, each recording the mapping relationship between a logical address and a physical address. For example, mapping entry LBA0 records which physical address corresponds to logical address 0. Each mapping table contains multiple mapping entries; for example, a 4KB mapping table can contain 1024 mapping entries. Taking a physical page size of 4KB as an example, the L2P entry indexing this page is 4 bytes, and the L2P table memory required to index 1GB of storage space is approximately 1MB, indicating a large memory requirement.

[0042] The cache space resources of storage device 12 are limited. To reduce cache space consumption, related technologies often employ a hierarchical mapping scheme, where the complete mapping table is stored in memory module 122, and only the indexes pointing to the mapping table are cached in the cache space, thereby reducing the memory consumption of mapping 1GB of physical space to approximately 1KB. However, this scheme introduces new performance challenges. For example, the mapping table must be read before each data read. If the mapping table is not cached in the cache space, it must be loaded from memory module 122, severely impacting read performance. Therefore, it is common practice to cache some frequently used mapping tables in the cache space and employ a cache replacement strategy to manage the mapping table cache in the cache space.

[0043] In scenarios where cache space is used to temporarily store mapping table entries, how to efficiently evict and reduce cached mapping table entries, and prioritize the retention of high-value mapping table entries within limited cache space, is also a key issue affecting the overall performance of the storage device.

[0044] To at least address the aforementioned issues, this application provides a cache space management method.

[0045] Figure 4 This is a schematic diagram of a cache space according to an embodiment of this application. The cache space 40 is provided by physical storage media such as the host cache 1121 and cache memory 24. The cache space 40 is logically divided into multiple cache units (Buffers) for temporarily storing mapping table entries. Each cache unit is a contiguous storage area within the cache space, internally divided into multiple slots of equal size, each slot can hold one or more mapping table entries. Furthermore, each mapping table entry is marked as a dirty mapping table entry or a clean mapping table entry based on its data state, and as a hot mapping table entry or a cold mapping table entry based on its access frequency. That is, a mapping table entry can simultaneously have both dirty / clean and hot / cold attributes, for example, it can be marked as a dirty hot mapping table entry, a dirty cold mapping table entry, a clean hot mapping table entry, or a clean cold mapping table entry.

[0046] Figure 5This is a flowchart of a cache space management method proposed in an embodiment of this application. The method is executed by the memory control circuit 23 and includes the following steps: S501: Maintain an LRU linked list and a hot / cold data structure to manage cache units in cache space 40.

[0047] Specifically, an LRU (Least Recently Used) linked list is maintained for all allocated cache units. This LRU linked list sorts all cache units according to their most recently accessed time, with the cache units at the tail of the list being the most recently accessed and the cache units at the head of the list being the least accessed. This linked list provides the selection criteria for the reduction operation. Simultaneously, a hot / cold separation data structure is maintained, including a hot cache unit linked list and a cold cache unit linked list, used to maintain cache units categorized into the hot cache unit set and the cold cache unit set, respectively. At any given time, a cache unit either belongs to the hot cache unit set (attached to the hot cache unit linked list) or the cold cache unit set (attached to the cold cache unit linked list). Initially, all newly allocated cache units are categorized into the cold cache unit set and attached to the cold cache unit linked list. As the storage device 12 begins operation, cache units are migrated from the cold cache unit set to the hot cache unit set based on the popularity ratio of their internal mapping table entries. It should be noted that a cache unit can exist simultaneously in both the LRU list and the hot / cold separation data structure (i.e., it can be removed from the cold cache unit list and added to the hot cache unit list). Furthermore, a cache unit can exist in either the LRU list or one of the cache unit lists in the hot / cold separation data structure. These lists operate independently, and the cache unit is added to its respective list via its pointer field.

[0048] For example, cache space 40 includes 1024 cache units. Figure 6 This is a schematic representation of the LRU chain for managing cache units, as shown in the embodiments of this application. Figure 6 As shown, Buffer17 was last accessed 1 second ago, so it is at the end of the linked list. Buffer5 was last accessed 100 seconds ago, so it is at the head of the linked list. Figure 7 This is a schematic diagram of a cold and hot data structure management cold and hot cache unit as shown in an embodiment of this application. Figure 8 This is a schematic diagram illustrating the set of management cold and hot cache units as shown in an embodiment of this application. Figure 7 and Figure 8 As shown, Buffer3 and Buffer45 belong to cold buffer unit set 802, and Buffer10 and Buffer78 belong to hot buffer unit set 804.

[0049] S502: In response to meeting the reduction conditions, a traversal is performed starting from the head of the LRU list, selecting the first cache unit classified by the hot-cold separation data structure as belonging to the cold cache unit set 802 as the cache unit to be reduced. By limiting the cache unit to be reduced to meet the two conditions of being located at the "head of the LRU list" and "belonging to the cold cache unit set 802", it is ensured that the cache unit containing the hot mapping table entry will not be mistakenly reclaimed even if it has not been accessed for a long time. If the aforementioned traversal fails to find a cache unit belonging to the cold cache unit set, the current reduction is terminated.

[0050] Specifically, the reduction condition can be triggered when the number of free cache units in cache space 40 falls below a preset low-water threshold. The traversal process can be set to a maximum traversal depth N to avoid long-duration scans. Specifically: from... Figure 6 Starting from the head of the LRU linked list shown, each cache unit is checked sequentially within the cold / hot separation data structure. If the currently checked cache unit belongs to the cold cache unit set 802, it is immediately identified as a cache unit to be reduced. If N consecutive cache units are checked and all belong to the hot cache unit set 804, meaning no cache unit belonging to the cold cache unit set 802 is found, the current reduction operation is terminated, and the process is restarted when the reduction conditions are met again.

[0051] S503: Perform a read operation on the aforementioned cache unit to be reduced to obtain all dirty mapping table entries and all hot mapping table entries stored in the aforementioned cache unit to be reduced as a set to be processed, and perform invalidation processing on the clean cold mapping table entries stored in the cache unit to be reduced, wherein the aforementioned hot mapping table entries include clean hot mapping table entries and dirty hot mapping table entries. This step achieves selective retention: dirty mapping table entries must be retained because they contain non-persistent modifications, hot mapping table entries are worth retaining because they may be accessed in the future, and clean cold mapping table entries can be directly discarded because they are consistent with the data in memory module 122 and have a low access probability.

[0052] Specifically, each slot within the cache unit to be reduced is scanned. If a slot stores a clean, cold map entry, the valid bit of that slot is marked as invalid, meaning it is discarded. If a slot stores a dirty map entry (regardless of whether the entry itself is hot or cold) or a hot map entry (regardless of whether it is clean or dirty), it is added to the set to be processed.

[0053] S504: Determine whether there are one or more other cache units different from the above-mentioned cache units to be reduced, and the total capacity of the free storage slots of these other cache units is sufficient to accommodate all the mapping table entries in the above-mentioned set to be processed.

[0054] The purpose of this step is to attempt to find new storage space in other cache units for the mapping table entries in the set to be processed, so as to avoid or reduce write-back operations to memory module 122, thereby reducing write amplification and improving performance. A specific decision-making implementation will be detailed in subsequent embodiments.

[0055] S505: If the judgment result is that it exists, then perform a copy write operation to other cache units on the mapping table entries in the above set to be processed, and proceed to step S507 after the operation is completed.

[0056] S506: If the determination result is that it does not exist, then a write operation is performed to the memory module 122 for the dirty mapping table entries in the above-mentioned set to be processed, and invalidation processing is performed on the clean hot mapping table entries in the above-mentioned set to be processed, and then proceed to step S507. Since the clean hot mapping table entries are consistent with the data in the memory module 122, directly discarding them will not cause data loss, and they can be read from the memory module 122 again when needed later.

[0057] S507: Release the cache unit to be reduced. The release operation includes marking all slots of the cache unit to be reduced as invalid / clearing its internal mapping table entries, removing it from the LRU list and the hot / cold separation data structure, and then returning it to the free cache unit pool.

[0058] This embodiment introduces a cold / hot data structure into the reduction object selection process, prioritizing the discarding of cold cache units with low access frequency, regardless of whether they are the oldest in the LRU order. Simultaneously, when selecting sacrifice cache units, they are not discarded entirely; instead, high-value mapping entries (dirty data, hot data) are salvaged through migration or write-back. This approach strikes a balance between the limited cache space 40 and the write tolerance of the memory module 122: discarding clean cold mapping entries incurs no additional overhead, writing back dirty mapping entries ensures data consistency, and retaining hot mapping entries avoids a sharp drop in future access performance due to cache reclamation.

[0059] To make the technical solution of this application clearer, the following uses a specific numerical example to illustrate the complete execution process of the above cache space management method.

[0060] In this example, it is assumed that cache space 40 is configured with 1024 cache units, numbered Buffer0 to Buffer1023. Each cache unit has a fixed size and is internally divided into 128 equally sized slots, each slot accommodating one mapping table entry and its label. The memory control circuit 23 currently has 1020 cache units allocated and in use, leaving only 4 free cache units in the pool, below the preset low watermark threshold (set to 8), triggering the reduction condition. Cache space 40 caches a total of 2048 mapping table entries, numbered Table0 to Table2047. The heat count threshold is initially set to 8 times, with the preset time period being the most recent 1 second; the first threshold (heating threshold) is 60%, and the second threshold (cooling threshold) is 30%.

[0061] The LRU linked list, from head (longest-unaccessed) to tail (most recently accessed), is currently: Buffer7, Buffer15, Buffer3, Buffer89, Buffer202... (tail omitted). The current classification of the cold / hot separated data structure is as follows: Cold cache unit set 802 includes: Buffer3, Buffer7, Buffer15, Buffer45, Buffer89, etc.; Hot cache unit set 804 includes: Buffer10, Buffer78, Buffer201, etc.

[0062] According to step S502, the memory control circuit 23 traverses from the head of the LRU list to find cache units belonging to the cold cache unit set 802. The maximum traversal depth N is set to 16, meaning the process terminates if 16 consecutive cache units are hot cache units; however, this is not triggered in this example.

[0063] Table 1: First, check Buffer7. Although Buffer7 belongs to the cold buffer unit set 802, it is skipped by the protection mechanism because it is in a state where the migration from the previous reduction operation is not yet completed. Continue traversing to Buffer15, which belongs to the cold buffer unit set 802 and is in a normal state, and is selected as the buffer unit to be reduced in this reduction operation.

[0064] According to step S503, scan the 128 slots inside Buffer15. The current state summary of Buffer15 is shown in Table 2: Table 2: Furthermore, the details of the mapping entries in Table 2 are shown in Table 3: Table 3: The memory control circuit 23 includes 40 dirty mapping table entries and 20 clean hot mapping table entries into the processing set, for a total of 60 mapping table entries. It should be noted that a dirty hot mapping table entry satisfies both "dirty" and "hot" conditions, but is only counted once. Here, 60 = 30 dirty cold entries + 10 dirty hot entries + 20 clean hot entries. For the 36 clean cold mapping table entries, their corresponding slots are directly marked as invalid.

[0065] According to step S504, it is necessary to find whether there are other cache units that can accommodate the 60 mapping table entries. The memory control circuit 23 scans all active cache units (excluding Buffer15 itself), counts the number of free slots, and classifies them into hot and cold sets, maintaining a cache unit index table (partial) sorted in descending order of the number of free slots, as shown in Table 4: Table 4: According to the priority selection strategy, the first step is to examine whether there are any cache units in the hot cache unit set 804 with a total number of free slots greater than or equal to 60. Buffer201 has 80 free slots, which meets the condition, so Buffer201 is determined as the target cache unit, and cache units in the cold cache unit set 802 are no longer considered.

[0066] It should be noted that, as shown in Table 4, if Buffer201 has only 50 (<60) free slots, then Buffer10 (45 slots, insufficient) and Buffer78 (20 slots, insufficient) are checked, and the hot cache unit set does not meet the requirements. In this case, the focus shifts to the cold cache unit set, and Buffer89 (70 slots), which has the most free slots, is selected as the target cache unit. In this example, Buffer201 meets the requirements, so the target cache unit is Buffer201 (which belongs to the hot cache unit set).

[0067] According to step S505, a copy-write operation is performed to move 60 pending mapping entries from Buffer15 to Buffer201. The copying process is performed slot-by-slot, with each copy taking 1 μs. When copying the 35th mapping entry (Table1001, a clean hot mapping entry), host 11 issues a read command through host interface 21, with the target address matching Table1001. At this time, the slot of Table1001 in Buffer15 is marked as "migration in progress". Memory control circuit 23 pauses the migration of the current mapping entry, prioritizes reading Table1001 from the source slot of Buffer15 in response to the host read command, and resumes the copy-write operation from Table1001 to Buffer201 after the response is completed. After the migration is completed, the metadata of Buffer201 is updated (e.g., the valid mapping entry count is increased by 60, the hot mapping entry count is increased by 20, and the dirty mapping entry count is increased by 40), and the valid mapping entry count of Buffer15 is cleared to zero, and all slots are marked as invalid.

[0068] Finally, according to step S507, Buffer15 is released: it is removed from the LRU list and the list corresponding to the cold cache unit set 802, its metadata is cleared, and it is returned to the free cache unit pool. At this time, the free cache unit pool changes from 4 to 5, which is still below the low watermark threshold. The memory control circuit 23 will continue to trigger reduction in the next detection cycle.

[0069] In this example, because Buffer201 received a cold dirty map entry from Buffer15, its hot map entry ratio changed from the original (30 / 48) to (60 / 108), but it is still higher than the second threshold of 30%, and continues to remain in the hot cache unit set 804, reflecting the stability of the hysteresis interval.

[0070] In contrast, in another reduction, if the cache unit to be reduced is Buffer89 (a set of cold cache units), its set of cache units to be processed contains 100 mapping table entries, but 95 of them are dirty mapping table entries, with a dirty data ratio of 95%, exceeding the preset dirty data ratio threshold (set to 80%). In this case, the memory control circuit 23 will skip the target cache unit search and migration steps, directly write the 95 dirty mapping table entries to the memory module 122 in batches, invalidate the 5 clean hot mapping table entries, and release Buffer89. This fast write-back path avoids the high-cost invalid migration.

[0071] As can be seen from the specific numerical scenario examples above, the cache space management method of this application can achieve cold and hot separation and elimination, selective rescue, priority hot set migration, and zero-blocking parallel processing of host commands.

[0072] Figure 9 This is a flowchart illustrating the cache unit lifecycle management process in an embodiment of this application, which fully demonstrates the entire process of cache unit allocation to recycling. Figure 9 As shown, when new cache space is needed, the memory control circuit 23 allocates a cache unit from the free cache unit pool. The newly allocated cache unit initially belongs to the cold cache unit set by default, and is simultaneously attached to the tail of the LRU list (indicating recent use) and the cold set list in the hot-cold separation data structure. As the storage device 12 operates, the cache unit continuously receives new map table writes and responds to read hit requests from the host 11. Each time a map table entry is hit, its access count is incremented, its timestamp is updated, and the cache unit is moved to the tail of the LRU list.

[0073] The memory control circuit 23 periodically performs cold / hot evaluation on each cache unit, based on the ratio of the number of hot cache entries to the total number of valid cache entries. When this ratio rises to a first threshold, the cache unit is migrated from the cold cache unit set to the hot cache unit set; when this ratio falls below a second threshold, it is migrated back from the hot set to the cold set. The first threshold being greater than the second threshold forms a hysteresis interval, effectively preventing ping-pong switching near the critical point.

[0074] When the reduction condition is triggered (e.g., the number of free cache units falls below the low watermark threshold), the memory control circuit 23 traverses the LRU list starting from the head, selecting the first cache unit belonging to the cold cache unit set as the target for reduction. This dual-selection mechanism ensures that even if a hot cache unit is located early in the LRU list, it will not be mistakenly reclaimed. If no cache unit meeting the condition is found within the maximum traversal depth, the current reduction is terminated, and the process waits for the next time the reduction condition is met before triggering it again.

[0075] When dealing with a cache unit to be shrunk, the memory control circuit 23 performs selective salvage: it reads the dirty and hot mapping table entries (including clean and hot mapping table entries and dirty and hot mapping table entries) as the set to be processed, and discards the clean cold mapping table entries directly. It then attempts to find space for the set to be processed in other cache units. If a space is found, a migration operation is performed to avoid writing to the memory module 122; if not, the dirty mapping table entries are written back to the memory module 122, and the clean hot mapping table entries are invalidated. Finally, the cache unit to be shrunk is released, removed from the LRU list and the cold / hot separation data structure, its metadata and all slots are cleared, and it is returned to the free cache unit pool, completing a full lifecycle cycle.

[0076] In one embodiment, it is proposed that each cache unit is not bound to a fixed logical address index range, and each cache unit adopts a set-associative or fully associative structure, locating mapping entries by tags. This structure makes the migration of the set to be processed during the reduction operation more flexible. That is, the target cache unit can accept the migration of mapping entries as long as there are free slots, without needing to care whether the logical address of the mapping entry matches its own bound address range. This avoids the situation where migration is impossible due to address range mismatch, and improves the success rate of the rescue migration of mapping entries during the reduction operation.

[0077] Specifically, a cache unit is divided into multiple slots, each slot storing a mapping table entry and its corresponding tag. The tag is the high-order part of the mapping table entry's logical address, used for fast retrieval of the target mapping table entry within the cache unit. Because cache units are not bound to fixed address ranges, expansion and contraction operations can be flexibly applied to any cache unit, without being constrained by address ranges.

[0078] Figure 10 This is a schematic diagram of the internal structure of the cache unit shown in the embodiments of this application. For example... Figure 10 As shown, each cache unit is divided into a metadata area and multiple slots of equal size. The metadata area stores status information such as the count of valid mapping entries, the count of dirty mapping entries, the count of hot mapping entries, and the count of free slots, which is used to support quick determination of the cache unit's hot / cold status, space capacity, etc. Each slot can hold one mapping entry and its corresponding tag. The tag is the high-order part of the mapping entry's logical address, used to implement set-associative or fully associative retrieval within the cache unit. Since the cache unit is not bound to a fixed logical address range, the migration of mapping entries to be processed during the reduction operation only requires that the target cache unit has enough free slots, without needing to worry about address matching, thus improving migration flexibility.

[0079] In one embodiment, Figure 6 The LRU linked list in the cache moves the cache unit to the tail of the list in response to any access to a cache entry in the LRU list. Specifically, each cache unit's metadata includes an LRU predecessor pointer and an LRU successor pointer, pointing to the preceding and following cache units in the LRU linked list, respectively. When a cache entry is matched, the relevant pointers are modified, the cache unit is removed from the list, and reinserted at the tail. This mechanism ensures that frequently accessed cache units remain at the tail of the LRU linked list, making them less likely to be selected for reduction, thus protecting hot-mapped cache entry data.

[0080] In one embodiment, a fixed cache unit size is proposed, with each cache unit maintaining a count of valid mapping entries and a count of free slots. The free slot count is used to determine whether other cache units can accommodate the aforementioned set to be processed. By querying the free slot count of the target cache unit and comparing it with the total number of the set to be processed, it can be quickly determined whether the target cache unit can accommodate all the mapping entries to be migrated, eliminating the need for slot-by-slot scanning and improving the efficiency of target cache unit selection during the reduction operation.

[0081] For example, if the cache unit size is 4KB and each mapping table entry occupies 32 bytes, then each cache unit can hold 128 mapping table entries. A free slot counter is maintained in the cache unit's metadata, decremented each time a mapping table entry is inserted and incremented each time a mapping table entry is deleted. When performing a shrinkage operation, by querying the free slot count of the target cache unit and comparing it with the total number of entries in the set to be processed, it can be quickly determined whether the target cache unit can accommodate all the mapping table entries to be migrated, without needing to scan slot by slot.

[0082] In the above embodiments, the reduction conditions are illustrated using the example of the number of idle cache units falling below a low watermark threshold. In one embodiment, the reduction conditions include at least one of the following as alternative or supplementary triggering conditions: the total number of cache units exceeds the upper limit, the global cache utilization rate falls below a first utilization rate threshold, a cache unit belonging to the cold cache unit set has not been accessed for K consecutive monitoring cycles, and the storage device 12 enters a low-power mode.

[0083] Each monitoring cycle corresponds to a preset number of input / output operations; for example, one monitoring cycle consists of processing 1000 I / O operations (Input / Output). When the total number of cache units exceeds the upper limit, it must be reduced to free up resources. When the global cache utilization rate is lower than the first utilization threshold, it indicates that the cache space utilization is low, and reduction can save power and resources. If a cold cache unit has not been accessed for K consecutive cycles, it indicates that the data in that cache unit has lost its value and is suitable for reclamation. Reducing the cache space in low-power mode helps reduce power consumption. The combination of multiple triggering conditions allows the reduction operation to be initiated promptly in various scenarios, rather than relying solely on a fixed threshold.

[0084] In one embodiment, the dirty mapping entries in the aforementioned set to be processed include dirty hot mapping entries and dirty cold mapping entries. This means that when obtaining the set to be processed in step S503, any dirty data that has not yet been written to the memory module 122 (i.e., mapping entries with a dirty data flag but low access frequency) is considered as non-lossable critical data and included in the set to be processed, regardless of its access frequency. This is because dirty mapping entries contain modifications that have not yet been persisted, and regardless of their access frequency, they must be retained to avoid data loss. In other words, for dirty data, "dirty" is an absolute condition, while "hot" and "cold" are relative conditions, and the retention priority of dirty mapping entries is higher than the distinction between hot and cold.

[0085] In one embodiment, a specific optimization strategy is provided for the judgment process in step S504 above. This embodiment aims to solve the problem of how to efficiently select target cache units for mapping entries to be processed, so as to balance migration efficiency and subsequent access performance. The method includes: if there exists at least one other cache unit belonging to the hot cache unit set 804 and whose total capacity of its free storage slots can accommodate all mapping entries in the above-mentioned set to be processed, then at least one other cache unit belonging to the hot cache unit set 804 is preferentially determined as the target cache unit; Otherwise, from the other cache units belonging to the cold cache unit set 802, select the cache unit with the most remaining free slots and determine it as the target cache unit.

[0086] In practice, the hot cache unit set 804 is first traversed to check if there is at least one cache unit whose number of free slots is greater than or equal to the total number of mapping table entries in the set to be processed. If so, it is selected first. The consideration for this design is that hot mapping table entries have temporal locality, and aggregating them with other hot mapping table entries in the hot cache unit can improve the cache hit rate. If there is no suitable unit in the hot cache unit set 804, the search is turned to the cold cache unit set 802, and the one with the most remaining free slots is selected to achieve load balancing and avoid some cache units generating too much fragmented space. This strategy ensures that cold cache units are only used as a fallback when hot cache units cannot accommodate the load, because the latter are likely to become the target of reduction again soon, causing mapping table entries to be repeatedly migrated, resulting in a ping-pong effect.

[0087] In one embodiment, such as Figure 11 As shown, Figure 11 This is a two-level judgment flowchart for judging the target cache unit as shown in the embodiment of this application. Figure 11 A detailed embodiment of step S504 is as follows: the first level determines and searches for a single cache unit, and the second level determines and searches for multiple cache units to jointly accommodate the set to be processed, and performs split migration to maintain address continuity.

[0088] Please refer to Figure 11 The process first checks if there exists a single cache unit with a free slot count greater than or equal to the total number of mapping entries in the set to be processed. If so, that cache unit is directly designated as the target cache unit, and the entire set is migrated. If the first-level check fails, the process proceeds to the second-level check to find if there are multiple other cache units whose combined free slot count can accommodate all the mapping entries to be processed. If the second-level check succeeds, the set to be processed is split, ensuring that mapping entries with consecutive logical addresses are completely migrated into the same target cache unit to maintain access locality. Only when both levels of checks fail is a dirty mapping entry in the set to be processed written back to memory module 122. This hierarchical strategy minimizes unnecessary write operations.

[0089] In one embodiment, the process of determining whether other cache units can accommodate the set to be processed is accelerated by maintaining a cache unit index table sorted by the number of free slots. This cache unit index table records the number of free slots for each active cache unit and is sorted in descending order of the number of free slots. When a target cache unit needs to be found, the cache unit index table is queried to directly locate the set of candidate cache units with a number of free slots greater than or equal to the total number of the set to be processed, without traversing all cache units. Then, in the candidate cache unit set, cache units belonging to the hot cache unit set 804 but with insufficient capacity are excluded, and hot cache units are selected first; if none are found, selection is made from the cold cache unit set 802, thus determining the final target cache unit. The maintenance overhead of the index table is very low; each time a mapping table entry is inserted or deleted into a cache unit, only the position of the cache unit in the index table needs to be updated, with a time complexity of O(log H), where H is the total number of active cache units. This index structure supports the real-time requirement of the critical decision point of "determining whether other cache units exist" in the reduction operation, and can still quickly complete the selection of the target cache unit under high IO pressure.

[0090] In one embodiment, the specific implementation of transferring the aforementioned set to be processed includes: copying each mapping table entry in the set to be processed to a free slot in the target cache unit, updating the metadata of the target cache unit (including the count of valid mapping table entries, the count of hot mapping table entries, the count of dirty mapping table entries, the count of free slots, etc.), and deleting the mapping table entry in the cache unit to be reduced, without modifying the main mapping table in the memory module 122. It should be noted that the reason for not modifying the main mapping table is that the migration operation only changes the position of the mapping table entry in the cache space, without changing the mapping relationship between its logical address and physical address. Therefore, the records in the main mapping table regarding the physical addresses corresponding to these mapping table entries do not need to be updated, that is, the memory module 122 does not need to perform write / erase operations, reducing write amplification.

[0091] In one embodiment, a processing mechanism is provided to reduce read / write command latency for the copy-write operation performed on the mapping entries in the set to be processed to other cache units in step S505. Since the storage device 12 typically needs to respond quickly to commands from the host 11, and data migration between cache units can be time-consuming, this embodiment allows host commands to be processed intermittently during the migration process. The method includes: during the copy-write operation performed on a per-mapping mapping entry basis, allowing the host interface 21 to process read commands from the host 11 in parallel; if the target address of these read commands hits a mapping entry in the source cache unit that has not yet been copied, then suspending the migration (copy-write operation) of that mapping entry; preferentially reading the mapping entry from the source cache unit to respond to the aforementioned read command, and resuming the migration (copy-write operation) of the mapping entry after the response is completed. Through the above mechanism, if the mapping table entry requested by the received host read command happens to be a mapping table entry that is currently being migrated but has not yet been copied, the migration operation of that mapping table entry will be paused, and the host read command will be responded to first. This ensures that the data migration is completed while minimizing the response latency of the migration operation to the host read.

[0092] It should be noted that when a mapping table entry in the pending set begins to be copied from the source cache unit to the target cache unit, the slot of that mapping table entry in the source cache unit is marked as "migration in progress". When a host read command is received and the slot is found to be matched, a pause signal is generated. After the currently executing burst transfer is completed, the next transfer is paused, and bus control is released. Subsequently, the mapping table entry is read from the "migration in progress" slot and returned to host 11. After the read operation is completed, the pause signal is removed, and the copying of the remaining mapping table entries continues from the breakpoint. In this way, the response latency of the host read command is not affected by the background data migration operation.

[0093] In one embodiment, a two-level judgment implementation is provided for the judgment process in step S504 above, aiming to solve the problem of how to effectively accommodate the set to be processed when the space of a single cache unit is insufficient but the combined space of multiple cache units is sufficient. The method includes: performing a first-level judgment, traversing and judging whether there is a single other cache unit whose free slot bit bit value is greater than or equal to the total number of mapping table entries in the set to be processed; if the result of the first-level judgment is negative, then performing a second-level judgment, traversing and judging whether there are multiple other cache units whose sum of their free slot bits is greater than or equal to the total number of mapping table entries in the set to be processed; if the result of the second-level judgment is positive, then splitting the set to be processed and performing copy write operations to the multiple other cache units respectively, ensuring that mapping table entries belonging to the same address contiguous range are written to the same target cache unit during splitting; if the result of the second-level judgment is negative, then determining that there are no other cache units that can accommodate the set to be processed.

[0094] Specifically, when splitting the set to be processed, the logical address contiguity of the mapping table entries is analyzed. For example, if consecutive logical block addresses (LBAs) LBA0-7 and LBA100-107 form two consecutive ranges of mapping table entries, then during splitting, the mapping table entries for LBA0-7 will be completely migrated to target cache unit A, while the mapping table entries for LBA100-107 will be completely migrated to target cache unit B, even if there is still space in A to accommodate some data from LBA100. This approach is to maximize the locality of mapping table entry access, facilitating subsequent possible prefetching or batch operations.

[0095] In one embodiment, when writing dirty map entries from the set to be processed to memory module 122, dirty map entries from cache units belonging to cold cache unit set 802 are written preferentially over dirty map entries from cache units belonging to hot cache unit set 804. This writing is performed in batches of dirty map entries. For example, a single write operation writes 32 dirty map entries in batches to a page of memory module 122, rather than writing each entry individually. For write-back tasks generated by multiple different cache units to be reduced, dirty map entries from cache units belonging to the cold cache unit set are written preferentially over those from cache units belonging to the hot cache unit set. This is because cold cache units are more likely to be selected for reduction in the future, and flushing their dirty data in advance avoids reprocessing these dirty map entries during future reduction. This strategy reduces the number of writes to memory module 122, reduces write amplification, and avoids a full scan of the entire cache space.

[0096] In one embodiment, a specific implementation for releasing cache units to be reduced is also proposed: the cache unit to be reduced is removed from the LRU linked list, and the pointers of its preceding and following nodes are modified to close the linked list; simultaneously, the cache unit to be reduced is removed from the hot-cold separation data structure (hot cache unit set or cold cache unit set). All mapping entries and metadata inside the cache unit are cleared, and the cache unit is returned to the idle cache unit pool for use in subsequent expansion operations. The total number of global cache units is decremented by one, completing the release.

[0097] In one embodiment, it is also proposed that clean cold map entries are directly discarded without being included in the set to be processed. In step S503, when obtaining the set to be processed, only dirty map entries and hot map entries are collected. Clean cold map entries are consistent with the data in memory module 122 and have a low access probability. Directly discarding them will not cause data loss or significantly affect the cache hit rate. Discarding clean cold map entries saves migration overhead and flushing overhead, and is the part with the lowest time and resource consumption in the reduction operation.

[0098] In one embodiment, a method is provided to quickly release cache resources in response to a specific host command. In certain scenarios, such as file deletion or full disk formatting, host 11 may issue an unmap command or a format command. These commands will invalidate some or all mapping relationships. If a slow reduction operation is still being performed in the background at this time, it will not only waste time and power consumption, but may also cause unnecessary write-back of invalid data. To solve this problem, the method includes: in response to receiving an unmap command or a format command, determining whether there is a reduction operation currently being executed or waiting to be executed; if so, and the cache unit to be reduced in the reduction operation contains mapping entries affected by the unmap command or the format command, then terminating the reduction operation, directly discarding all mapping entries in the aforementioned cache unit to be reduced, not writing dirty mapping entries to the memory module 122, and returning the cache unit to the free cache unit pool.

[0099] It should be noted that this mechanism is implemented through high-priority interrupts during the command parsing phase. When such a command is parsed, all ongoing shrinking tasks are traversed. By comparing the address information of the cache unit to be shrunk with the scope of the command's impact, if there is overlap, a task termination flag is set. The shrinking operation's state machine checks this flag before executing the next step; if it is already set, it directly jumps to the resource release phase, skipping all data migration and write-back steps. This significantly improves the response speed of storage device 12 when receiving "invalidate" type commands and reduces unnecessary write amplification.

[0100] In one embodiment, a specific management method for the hot-cold separation data structure is also proposed. The hot-cold separation data structure includes a hot cache unit set and a cold cache unit set. Mapping entries are marked as hot or cold mapping entries in the following way: if the access count of a mapping entry reaches a hot count threshold (e.g., 8 times) and it has been hit within a recent preset time period (e.g., within the last second or the last 1000 I / O operations), it is determined to be a hot mapping entry; otherwise, it is determined to be a cold mapping entry. Initially, all cache units are assigned to the cold cache unit set. In response to the proportion of hot mapping entries in a cache unit rising to a first threshold, the cache unit is moved from the cold cache unit set to the hot cache unit set; in response to the proportion of hot mapping entries in a cache unit falling below a second threshold, the cache unit is moved from the hot cache unit set to the cold cache unit set. The first threshold is greater than the second threshold. For example, the first threshold ranges from 50% to 70%, and the second threshold ranges from 30% to 40%, which can be set according to the actual application scenario. This hysteresis interval prevents ping-pong switching of the set attributes of cache units near the critical point, ensuring the stability of classification.

[0101] Furthermore, each mapping entry's metadata includes an access count field and a timestamp field. When a mapping entry is hit by host 11, its access count increments, and the timestamp is updated to the current storage device time. A background scanning task periodically checks all cache units. For each cache unit, it calculates the proportion of its internal hot mapping entries to the total number of valid mapping entries. If it is currently cold and the proportion exceeds a first threshold (e.g., 70%), it is moved to the hot set; if it is currently hot and the proportion is below a second threshold (e.g., 30%), it is moved to the cold set. The design of the first threshold being greater than the second threshold constitutes a hysteresis interval, effectively preventing ping-pong switching of cache unit set attributes near the critical point, ensuring the stability of classification.

[0102] In one embodiment, based on the aforementioned dynamic hot / cold classification, an adaptive mechanism for adjusting the heat determination criteria according to the workload is further introduced to address the adaptability issue of a fixed threshold in different scenarios of sequential or random reads. The method includes: monitoring the input / output load characteristics of the storage device 12 to obtain a randomness index of the current load; dynamically adjusting the heat counting threshold according to the randomness index: when the randomness index is higher than the random threshold, lowering the heat counting threshold so that more mapping entries are determined to be hot mapping entries; when the randomness index is lower than the sequential threshold, raising the heat counting threshold so that fewer mapping entries are determined to be hot mapping entries.

[0103] Furthermore, randomness metrics can be obtained by analyzing the logical address continuity of host commands. For example, within a monitoring window, the average or entropy of the difference between the starting logical addresses of adjacent read commands can be calculated. If address jumps are large (high randomness), it indicates irregular data access. In this case, the hot count threshold should be lowered (e.g., from 8 to 4) so ​​that frequently accessed mapping entries can be quickly identified as hot data and kept in the cache, improving the random read hit rate. Conversely, if address continuity is high (sequential reads), data reuse is low. In this case, the hot count threshold should be increased (e.g., from 8 to 16) to ensure that only frequently accessed mapping entries are considered hot. This prevents sequential reads from mistakenly marking the first accessed data as hot and crowding out the cache space of truly hot data, achieving optimal configuration of cache resources under different load modes.

[0104] Figure 12 This is a flowchart illustrating the cold and heat separation management and dynamic threshold adjustment method shown in an embodiment of this application. Figure 12 As shown, in each monitoring cycle, the memory control circuit 23 traverses all cache units and calculates the ratio of hot cache entries to the total number of valid cache entries in each cache unit. For a unit currently belonging to a cold cache unit, if this ratio reaches a first threshold, it is moved to the hot cache unit set; for a unit currently belonging to a hot cache unit, if this ratio drops below a second threshold, it is moved back to the cold cache unit set. Because the first threshold is greater than the second threshold, a hysteresis interval is formed to prevent ping-pong switching. After this, the randomness index of the current load is obtained. When the randomness is higher than the randomness threshold, the hot count threshold is lowered so that cache entries accessed frequently but occasionally can also be identified as hot data, improving the random read hit rate; when the randomness is lower than the sequential threshold, the hot count threshold is increased to prevent one-time data in the sequential read stream from crowding out the hot cache space. This mechanism ensures that the hot and cold separation is always matched with the current load.

[0105] In one embodiment, a protection mechanism is provided for the process of traversing and searching for cache units to be reduced in step S502 above, to solve the problem that in extreme cases (such as a large influx of hot data in a short period of time), a cold cache unit cannot be found near the head of the LRU list for a long time, causing the traversal to fall into an infinite loop or take too long. The method includes: setting a maximum traversal depth N, starting from the head of the LRU list, and checking whether each cache unit belongs to the cold cache unit set in turn; determining the first cache unit that belongs to the cold cache unit set as the cache unit to be reduced; if no cache unit belonging to the cold cache unit set is found after checking N cache units consecutively, the current reduction operation is terminated, and the operation is restarted when the reduction conditions are met again.

[0106] This design sets clear abandonment boundaries for the scaling-up operation, avoiding unnecessary scanning overhead under transient pressure of 40 cache units. The deferred trigger mechanism allows for retrying in the next scaling-up cycle when the workload or hot / cold state changes, typically by which time cache units have cooled down and met the requirements.

[0107] In one embodiment, a cost-based fast path is provided to address the problem that when there are too many dirty mapping entries in the cache unit to be shrunk, the complexity and overhead of the "migration" strategy are greater than that of the "direct write-back" strategy. The method includes: monitoring the ratio of the number of dirty mapping entries in the cache unit to be shrunk to the total number of entries in the set to be processed; if the ratio exceeds a preset dirty data ratio threshold, skipping the steps of determining whether there are other cache units that can accommodate the set to be processed and copying to other cache units, directly writing the dirty mapping entries in the set to be processed into the memory module 122, invalidating the clean mapping entries in the set to be processed, and releasing the cache unit to be shrunk.

[0108] For example, a dirty data ratio threshold is set to 80%. This dirty data ratio threshold can be set to a fixed value between 70% and 90%, or it can be dynamically adjusted by the memory control circuit 23 based on data from historical write-back and migration operations. For instance, the memory control circuit 23 can calculate the average time of migration and write-back paths in each reduction operation. When the average time of migration paths increases (e.g., due to frequent splitting and migration of multiple cache units caused by cache fragmentation), the dirty data ratio threshold is reduced, allowing more cache units to be reduced to use the fast write-back path. If a cache unit to be reduced has 100 mapping table entries in its processing set, of which 85 are dirty mapping table entries, the combined cost of the search cost, data copying overhead between multiple cache units, and potential subsequent multiple write-backs in determining and migrating these mapping table entries may be higher than directly writing back these 85 dirty mapping table entries to the memory module 122 at once. By using this fast path, the complex decision-making logic is bypassed, and the write-back is performed directly, which can achieve better overall throughput and lower average latency under certain conditions.

[0109] In one embodiment, a mapping entry push operation is provided to work in conjunction with a reduction operation. To further improve read performance, storage device 12 (e.g., UFS or SSD) can utilize the Host Performance Booster (HPB) function to push mapping entries to the host-side HMB (Host Memory Buffer), enabling host 11 to directly initiate read commands carrying physical addresses. This embodiment provides a triggering and execution framework for this push operation. The method includes: in response to meeting push conditions, performing a mapping entry push operation to transfer the mapping entries to be pushed to the host cache 1121. The host cache 1121 is a component of cache space 40 and is located in host-side memory. By actively pushing mapping entries from cache memory 24 to the host cache 1121, host 11 can directly use the mapping entries in the host cache 1121 to complete address translation when initiating a read command, without needing to read from memory module 122, thereby significantly reducing read latency. The mapping table entry push operation works in conjunction with the aforementioned shrink and expand operations to form a complete management system for cache space 40: expanding and shrinking manage the capacity of the cache space, while the push operation manages the output of cache space content to the host.

[0110] Furthermore, the push condition can be the expiration of a periodic timer or the command queue status meeting specific requirements. The core of the push operation is to select mapping table entries that may be beneficial to future read operations of the host 11 from the cache memory 24 of the storage device 12, and actively or passively transmit them to the host 11, thereby shifting the pressure of address translation forward and shortening the processing path of read commands.

[0111] In one embodiment, it is further proposed to aggregate mapping entries with contiguous addresses and similar priorities before transmitting them to the host cache, forming a data range that is an integer multiple of the minimum recommendation unit. For example, the HPB protocol specifies that the minimum recommendation unit is a fixed-size LBA range, and the aggregation operation merges multiple mapping entries with adjacent addresses and the same priority into a recommendation range that is an integer multiple of this minimum unit. This reduces the number of cache read commands initiated to the host, lowers command processing overhead, and avoids fragmented advancements that could reduce the cache management efficiency of host 11.

[0112] In one embodiment, a push triggering and mapping entry selection mechanism based on host command prediction is provided. This method aims to solve the problem of how to accurately predict the mapping entries needed by host 11 to improve the push hit rate. The push condition includes that there are pending input / output commands in the command queue of storage device 12. The method includes: parsing the pending input / output commands to obtain the logical address range they access. If the logical address range hits an existing mapping entry in cache space 40, it indicates that the corresponding address mapping information already exists in cache memory 24. The hit mapping entry is then identified as a mapping entry to be pushed and immediately pushed to host cache area 1121. This ensures that the mapping entry to be accessed already exists in host cache area 1121 before being actually read, allowing subsequent read commands to quickly complete address translation. If the logical address range does not hit cache space 40, but the access mode is detected as sequential read or has regular address jumps, the corresponding mapping entry is pre-read from memory module 122 into an independent pre-read cache area in cache memory 24, and the pre-read mapping entry is identified as a mapping entry to be pushed.

[0113] The aforementioned global historical access popularity information can be obtained by maintaining an access frequency statistics table. This access frequency statistics table records the cumulative number of times the mapping table entries within each logical address range have been accessed in historical operations. The background task periodically scans this access frequency statistics table and selects the mapping table entries with the highest access frequency as candidates for pre-reading and pushing.

[0114] It should be noted that the aforementioned regular address transitions are, for example, traversing a file system table with a fixed step size. The prefetch mechanism allows cache gaps to be filled by reading from the memory module 122 in advance, even if the required mapping table entry does not exist in the current cache space 40, thus achieving proactive push even if a cache miss occurs. The prefetch operation on the storage device 12 and the push operation on the host 11 work together to form a pipeline-like performance optimization.

[0115] In detail, this mechanism allows storage device 12 to not only process the mapping table entries required by the current command, but also to predict the pattern of subsequent commands. For example, if the logical addresses of three consecutive read commands in the command queue are incrementing and consecutive, the firmware determines it to be a sequential read mode. In this case, even if only the mapping table entries of the first three commands are in the cache, it will still proactively pre-read the mapping table entries of subsequent consecutive addresses (e.g., those required by the next 8 commands) from memory module 122 into a dedicated pre-read cache area, and immediately package and push these pre-read mapping table entries to host 11. The above mechanism effectively improves the predictability and hit rate of HPB function.

[0116] Figure 13 This is a flowchart illustrating the pre-read push triggering process based on host command prediction, as shown in an embodiment of this application. Figure 13As shown, when there are pending input / output commands in the command queue, the memory control circuit 23 parses the logical address access requested by these commands. If the address range hits an existing mapping table entry in the cache space, the hit entry is directly identified as the mapping table entry to be pushed and immediately pushed to the host cache 1121, so that subsequent read commands can directly use HMB to complete address translation. If there is a miss, but the current access mode is detected as sequential read or has regular address jumps, the prefetch mechanism is triggered. The mapping table entry corresponding to the subsequent address is read in advance from the memory module 122 into an independent prefetch cache, and the prefetched mapping table entry is identified as the target and actively pushed to the host 11. This proactive push method of "pre-judging even if there is a miss" allows the coverage of the host cache to be ahead of the read pointer, improving the HPB hit rate in sequential read scenarios.

[0117] In one embodiment, in sequential read mode, mapping entries that have been pre-read into cache space 40 are directly pushed.

[0118] Specifically, when the access mode is sequential read mode, and the steps for identifying pre-read mapping entries as mapping entries to be pushed include: identifying mapping entries that have already been pre-read into the cache space when the access mode is detected as mapping entries to be pushed. This means that in a sequential read scenario, subsequent mapping entries can be read into the cache space in advance. When the push condition is triggered, these pre-read mapping entries do not need to wait for a new round of pre-reading and can be directly included in the push scope. The push operation and the pre-read operation work together to enable the data range of the host cache 1121 to "advance" the current read pointer, achieving deeper pipeline optimization.

[0119] In one embodiment, a dynamic capacity adjustment mechanism is provided to match the resource utilization efficiency of the prefetch buffer to the current workload. The method includes: monitoring the depth of the command queue and the hit rate of the prefetch buffer; and dynamically adjusting the capacity of the prefetch buffer based on these two metrics. The command queue depth reflects the intensity of the current I / O load, and the prefetch buffer hit rate reflects the effectiveness of the prefetch operation. The capacity of the prefetch buffer is dynamically adjusted based on these two metrics: when the command queue depth exceeds a first depth threshold (e.g., more than 16 commands to be processed in the queue) and the hit rate is lower than a first hit threshold (e.g., 60%), the capacity of the prefetch buffer is increased to accommodate more prefetch mapping entries and improve the hit rate. When the command queue depth is lower than a second depth threshold (e.g., 4 commands) or the hit rate is higher than a second hit threshold (e.g., 90%), the capacity of the prefetch buffer is reduced, and the released cache resources are returned to multiple cache units for use, because at this point the I / O pressure is low or the hit rate is already high enough that excessive cache resources are not required. This dynamic adjustment mechanism enables the cache space to be allocated on demand between the "prefetch cache" and the "normal cache unit", thereby maximizing the overall resource utilization.

[0120] Specifically, when the command queue is deep (host 11 is very busy) and the prefetch hit rate is low, it means that the prefetching effort is insufficient or the prefetching strategy is inaccurate. In this case, the prefetch cache area is expanded to allow for more aggressive prefetching to capture more future access opportunities. Conversely, when the queue is shallow or the hit rate is already high, it indicates that prefetching resources are excessive or the prediction is highly accurate. In this case, the prefetch area is reduced, and the valuable cache memory 24 resources are returned to the general cache unit pool to store new mapping table entries or dirty data, achieving a dynamic balance between "serving the present" and "predicting the future" of resources.

[0121] In one embodiment, the resource contention problem when shrinking and pushing operations coexist on the same cache unit is resolved. Improper scheduling may lead to pushing dirty data that is about to be written back, or the shrinking operation disrupting the push data source, among other conflicts. A priority and parallelism control method is provided. This method further includes: when both a shrinking operation and a push operation are pending, comparing whether the cache unit to be shrunk corresponding to the shrinking operation and the cache unit containing the mapping entry to be pushed corresponding to the push operation are the same cache unit; if they are the same cache unit, the push operation is executed first, transmitting the mapping entry to be pushed to the host cache 1121, and then the shrinking operation is performed on that cache unit; if they are not the same cache unit, the shrinking and push operations are allowed to be executed in parallel.

[0122] The logic for prioritizing push operations is as follows: the beneficiary of push operations is host 11, which can immediately reduce the host's read latency, and the data in HMB is a read-only copy, which does not disrupt the consistency of storage device 12. Delaying shrink operations, although briefly occupying resources, does not affect correctness. Parallel execution maximizes the use of the multi-channel characteristics of the memory controller 123 and the memory control circuit 23, thereby improving the overall throughput of background tasks.

[0123] Figure 14 This is a flowchart illustrating the collaborative processing of reduction and push operations in an embodiment of this application. Figure 14 As shown, when the memory control circuit 23 has both a shrinking task and a push task to be processed simultaneously, it first compares whether the cache units involved in the two tasks are the same physical cache unit. If they are the same unit, to avoid inconsistent data read during the push operation or loss of push source data due to shrinking release, the push operation is executed first. After the mapping table entry to be pushed is transferred to the host cache 1121, the normal shrinking process is initiated for that cache unit. If they are different cache units, since there is no resource contention, the shrinking operation and the push operation can be executed in parallel, making full use of the multi-channel parallel processing capability inside the memory controller 123 and improving the throughput of background tasks in the storage device.

[0124] In one embodiment, background refresh is also proposed to utilize the idle time of storage device 12. The push conditions include: the command queue of storage device 12 is empty and is about to enter or is already in an idle state. At this time, a background task is started, and based on global historical access popularity information, the mapping table entries with the highest access frequency that are not yet in the host cache 1121 are pre-read from the memory module 122 to the cache space 40, and the pre-read mapping table entries are determined as mapping table entries to be pushed. Unlike the aforementioned command-triggered push, background refresh does not depend on the content of the current command queue, but is based on historical statistics to determine which mapping table entries are most likely to be accessed in the future. This strategy effectively utilizes idle bandwidth, improves the coverage of the host cache without affecting the foreground IO performance, so that after storage device 12 enters an idle state, the host cache is ready for the next active session.

[0125] In one embodiment, a response to formatting or demapping commands is also proposed. Upon receiving a formatting or demapping command, the mapping entries affected by the command are marked as invalid, and the host cache 1121 is notified to immediately invalidate the corresponding mapping entries. The formatting command resets the mapping relationships in the main mapping table of storage device 12, while the demapping command invalidates a specified range of mapping relationships. By actively notifying the host cache 1121 to invalidate these mapping entries, the host 11 avoids using outdated mapping information, ensuring strong consistency between the host 11's cache and the state of storage device 12. This notification can be implemented by the storage device 12 sending an HPB response message carrying the invalidated address range to the host 11. Upon receiving this message, the host 11 marks the corresponding mapping entries in the host cache 1121 as invalid.

[0126] In one embodiment, considering the version evolution of the UFS protocol, a method is provided to mask differences and optimize push operations through a protocol adaptation layer. Storage device 12 supports the Universal Flash Storage Protocol, and transmitting the mapping entries to be pushed to the host cache 1121 includes initiating a cache suggestion command to host 11 via the Host Performance Enhancer Protocol (HPB). The method further includes: dynamically adjusting at least one of the following parameters according to the version of the Universal Flash Storage Protocol through a protocol adaptation layer: the length of a preset time window, the aggressiveness of the pre-read operation, and the submission frequency of the mapping entries to be pushed.

[0127] It should be noted that this protocol adaptation layer can be a functional component in the firmware. This component negotiates the protocol version of storage device 12 with the host during storage device 12 initialization and configures a set of protocol feature registers based on the negotiation result. These protocol feature registers include fields such as the maximum HPB packet length and the recommended time window. The memory control circuit 23 adjusts behavioral parameters such as the length of the preset time window, the aggressiveness of the pre-read operation, and the submission frequency of the mapping table entries to be pushed, based on the values ​​of these protocol feature registers.

[0128] For example, UFS 3.1 and UFS 4.0 may differ in HPB command format, maximum packet length, or recommended interaction timing. The protocol adaptation layer obtains the host-negotiated UFS version number during device initialization. Newer protocol versions may support larger HPB packets, allowing for a larger time window or submission frequency to push more mapping table entries at once. Older versions employ a more conservative push strategy. This enables a single firmware image to flexibly adapt to different generations of host platforms, achieving optimal performance and compatibility.

[0129] In one embodiment, a deadlock avoidance mechanism is provided that, when cache space 40 is extremely tight, temporarily "borrows" cache units that are about to be released to ensure the smooth completion of push operations. The method further includes: During the execution of the mapping table entry push operation, if there is no free cache unit in the cache space 40 to accommodate the new mapping table entry to be pushed, and a shrinking operation is detected that is in progress or waiting to be performed, and the shrinking operation has selected a cache unit to be shrunk and the mapping table entry in the cache unit to be shrunk has been processed into a releaseable state but has not yet been released; then the cache unit to be shrunk is temporarily used as a cache unit to accommodate the new mapping table entry to be pushed, and after the mapping table entry to be pushed is transferred to the host cache area 1121, the release process is then performed on the cache unit to be shrunk.

[0130] Figure 15 This application presents a deadlock avoidance mechanism for scenarios with extremely limited cache space, as proposed in its embodiments. Figure 15 As shown, when a mapping table entry push operation requires a new cache unit to accommodate the mapping table entry to be pushed, but there are no free cache units in the cache space 40, the memory control circuit 23 detects whether there is a shrinking operation being executed or waiting to be executed. If there is, and the shrinking operation has selected a cache unit to be shrunk and the mapping table entry in the cache unit to be shrunk has been processed into a releaseable state (i.e., dirty mapping table entries have been written to the memory module 122, and clean mapping table entries have been invalidated) but has not yet been released, a cache unit is temporarily borrowed as a transit storage for the push data. After the push operation uses the borrowed unit to complete the transfer of the mapping table entry to the host cache area 1121, it immediately returns the unit to the shrinking operation so that it can continue to complete the original release process. This operation is like a micro-operation of "trading space for time". When borrowing, the data on the cache unit to be shrunk has been processed (dirty data has been written back / clean data has been invalidated), and its cache space is about to be returned to the storage device 12, but before being returned, it is temporarily given a new mission - as a transit station for the push operation. Once the push is complete, the cache unit is immediately formatted and returned, allowing for a seamless transition to the subsequent release process of the scaling-down operation. This mechanism prevents the push operation from failing due to a lack of cache space, even in the extreme boundary condition where only one cache unit remains in the cache space of 40, and that unit has already been reserved by the scaling-down process.

[0131] Figures 4 to 15 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figures 4 to 15 Each step can be implemented as multiple program codes or circuits, and this application does not impose any limitations. Furthermore, Figures 4 to 15 The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this application does not impose any restrictions.

[0132] In summary, the cache space management method and storage device provided in the embodiments of this application manage the multiple cache units by maintaining an LRU linked list and a cold / hot separation data structure. In response to meeting the reduction condition, a traversal is performed starting from the head of the LRU linked list, selecting the first cache unit classified as belonging to the cold cache unit set by the cold / hot separation data structure as the cache unit to be reduced. If the traversal fails to find a cache unit belonging to the cold cache unit set, the reduction is terminated. A read operation is performed on the cache unit to be reduced to obtain all dirty mapping entries and all hot mapping entries stored in the cache unit to be reduced as a set to be processed, and the reduction is then performed on the cache unit to be reduced. The process involves invalidating clean, cold map entries stored in the cache unit; determining if one or more other cache units exist that are different from the one to be reduced, and if the total capacity of their free storage slots is sufficient to accommodate all map entries in the set to be reduced; if the determination finds that such cache units exist, a copy-write operation is performed on the map entries in the set to be reduced to other cache units, and the cache unit to be reduced is released after the operation is completed; if the determination finds that such cache units do not exist, a write operation is performed on dirty map entries in the set to be reduced to the memory module, clean, hot map entries in the set to be reduced are invalidated, and the cache unit to be reduced is released. This application improves cache space management efficiency, enhances storage device performance, reduces write amplification, and extends storage device lifespan.

[0133] The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of this application. It should be noted that, for those skilled in the art, several improvements and modifications can be made to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A cache space management method, characterized in that, For a storage device, the storage device includes a memory module and a cache space, the cache space being configured with multiple cache units for temporarily storing mapping table entries, each mapping table entry being marked as a dirty mapping table entry or a clean mapping table entry based on its data state, and marked as a hot mapping table entry or a cold mapping table entry based on its access frequency, the method comprising: Maintain an LRU linked list and a hot / cold data structure to manage multiple cache units; In response to the fulfillment of the reduction condition, a traversal is performed starting from the head of the LRU list, and the first cache unit that is classified as belonging to the cold cache unit set by the cold and hot separation data structure is selected as the cache unit to be reduced. If the traversal fails to find a cache unit belonging to the cold cache unit set, the current reduction is terminated. A read operation is performed on the cache unit to be shrunk to obtain all dirty mapping table entries and all hot mapping table entries stored in the cache unit to be shrunk as a set to be processed, and the clean cold mapping table entries stored in the cache unit to be shrunk are invalidated, wherein the hot mapping table entries include clean hot mapping table entries and dirty hot mapping table entries. Determine whether there are one or more other cache units that are different from the cache unit to be reduced, and whether the total capacity of the free storage slots of the other cache units can accommodate all the mapping table entries in the set to be processed; If the result of the judgment is that it exists, then the mapping table entries in the set to be processed are copied and written to other cache units, and the cache units to be reduced are released after the operation is completed; If the determination result is that it does not exist, then the dirty mapping table entries in the set to be processed are written to the memory module, the clean hot mapping table entries in the set to be processed are invalidated, and the cache units to be reduced are released. The determination of whether there exists at least one other cache unit different from the cache unit to be reduced, whose total free storage slot capacity is sufficient to accommodate all mapping entries in the set to be processed, includes: Perform the first-level judgment, traverse and determine whether there is a single other cache unit whose free slot bit value is greater than or equal to the total number of mapping table entries in the set to be processed; If the result of the first-level judgment is negative, then the second-level judgment is executed, traversing and judging whether there are multiple other cache units whose sum of their free slots is greater than or equal to the total number of mapping table entries in the set to be processed. If the result of the second-level judgment is yes, then the set to be processed is split and copy-write operations to the multiple other cache units are performed respectively. During the split, the mapping table entries to be processed that belong to the same address range are written to the same target cache unit. If the result of the second-level judgment is negative, it is determined that there are no other cache units that can accommodate the set to be processed.

2. The cache space management method according to claim 1, characterized in that, The cache space includes static random access memory and a host cache area; The hot and cold separation data structure includes a hot cache unit linked list and a cold cache unit linked list, which are used to maintain cache units classified into the hot cache unit set and the cold cache unit set, respectively.

3. The cache space management method according to claim 2, characterized in that, The determination of whether there exists at least one other cache unit different from the cache unit to be reduced, whose total free storage slot capacity is sufficient to accommodate all mapping entries in the set to be processed, includes: If there exists at least one other cache unit belonging to the hot cache unit set and whose total capacity of its free storage slots can accommodate all mapping entries in the set to be processed, then at least one other cache unit belonging to the hot cache unit set shall be preferentially identified as the target cache unit. Otherwise, from the other cache units belonging to the cold cache unit set, select the cache unit with the most remaining free slots as the target cache unit.

4. The cache space management method according to claim 2, characterized in that, The step of performing a copy-write operation to other cache units on the mapping entries in the set to be processed includes: During the copy operation performed on a per-mapped-table-entry basis, read commands from the host can be processed in parallel. If the target address of the read command hits a mapping entry in the source cache unit that has not yet been copied, then the migration of that mapping entry is paused. The mapping table entry is preferentially read from the source cache unit in response to the read command, and the migration of the mapping table entry is restored after the response is completed.

5. The cache space management method according to claim 2, characterized in that, The method further includes: In response to receiving a demapping command or a formatting command, determine whether there is a shrinking operation currently being executed or waiting to be executed; If such a cache unit exists and contains a mapping entry affected by the unmapping command or formatting command, the reduction operation is terminated, all mapping entries in the cache unit to be reduced are discarded directly, the dirty mapping entries are not written to the memory module, and the cache unit is returned to the idle cache unit pool.

6. The cache space management method according to claim 2, characterized in that, The hot-cold separation data structure includes a set of hot cache units and a set of cold cache units, and the method further includes: If the access count of a mapping table entry reaches the hot count threshold and is hit within the most recent preset time period, it is determined to be a hot mapping table entry; otherwise, it is determined to be a cold mapping table entry. Initially, all cache units are assigned to the cold cache unit set; When the proportion of hot-mapped entries in a cache unit increases to a first threshold, the cache unit is moved from the cold cache unit set to the hot cache unit set. In response to the proportion of hot-mapped entries in a cache unit falling below a second threshold, the cache unit is moved from the hot cache unit set to the cold cache unit set. The first threshold is greater than the second threshold.

7. The cache space management method according to claim 6, characterized in that, The method further includes: Monitor the input / output load characteristics of the storage device to obtain the randomness index of the current load; The heat count threshold is dynamically adjusted based on the randomness index. When the randomness index is higher than the randomness threshold, the hot count threshold is lowered so that more mapping entries are identified as hot mapping entries. When the randomness index is lower than the order threshold, the hot count threshold is increased so that fewer mapping entries are identified as hot mapping entries.

8. The cache space management method according to claim 2, characterized in that, The step of traversing the LRU list starting from the head and selecting the first cache unit that is classified as belonging to the cold cache unit set by the cold-hot separation data structure as the cache unit to be reduced includes: Set the maximum traversal depth N, starting from the head of the LRU list, and check in turn whether each cache unit belongs to the cold cache unit set; The first cache unit found to belong to the cold cache unit set is identified as the cache unit to be reduced. If no cache unit belonging to the cold cache unit set is found after checking N cache units consecutively, the current reduction operation is terminated, and the operation is restarted when the reduction conditions are met again.

9. The cache space management method according to claim 2, characterized in that, The method further includes: Monitor the ratio of the number of dirty mapping entries in the cache unit to be reduced to the total number of sets to be processed; If the ratio exceeds a preset dirty data ratio threshold, the steps of determining whether there are other cache units that can accommodate the set to be processed and copying and writing to other cache units are skipped. Instead, the dirty mapping entries in the set to be processed are directly written to the memory module, the clean mapping entries in the set to be processed are invalidated, and the cache unit to be reduced is released.

10. The cache space management method according to claim 2, characterized in that, The method further includes: In response to the fulfillment of the push conditions, a push operation is performed to transmit the mapping table entries to be pushed to the host cache.

11. The cache space management method according to claim 10, characterized in that, The push condition includes that there are input / output commands to be processed in the command queue of the storage device, and the method further includes: Parse the input / output commands to be processed to obtain the range of logical addresses they access; If the logical address range matches an existing mapping entry in the cache space, the matched mapping entry is determined as the mapping entry to be pushed. If the logical address range is not hit, but the access mode is detected as sequential read or has regular address jumps, the corresponding mapping table entry is pre-read from the memory module into an independent pre-read cache, and the pre-read mapping table entry is determined as the mapping table entry to be pushed.

12. The cache space management method according to claim 11, characterized in that, The method further includes: Monitor the depth of the command queue and the hit rate of the prefetch buffer; The capacity of the prefetch buffer is dynamically adjusted based on the depth of the command queue and the hit rate of the prefetch buffer. When the command queue depth exceeds a first depth threshold and the hit rate is lower than a first hit threshold, the capacity of the prefetch cache is increased. When the command queue depth is lower than the second depth threshold or the hit rate is higher than the second hit threshold, the capacity of the pre-read cache is reduced, and the released cache resources are returned to the multiple cache units for use.

13. The cache space management method according to claim 10, characterized in that, The method further includes: The storage device supports the general flash storage protocol, and the step of transmitting the mapping table entry to be pushed to the host cache includes initiating a cache suggestion command to the host through the host performance enhancer protocol. Through a protocol adaptation layer, at least one of the following parameters is dynamically adjusted according to the version of the general flash storage protocol, including the length of the preset time window, the aggressiveness of the pre-read operation, and the submission frequency of the mapping table entries to be pushed.

14. The cache space management method according to claim 10, characterized in that, The method further includes: When there are both pending reduction operations and pending push operations, compare whether the cache unit to be reduced corresponding to the reduction operation and the cache unit containing the pending push mapping table entry corresponding to the push operation are the same cache unit. If it is the same cache unit, the push operation is performed first, and the mapping table entry to be pushed is transmitted to the host cache area before the shrink operation is performed on the cache unit. If they are not in the same cache unit, the shrink operation and the push operation are allowed to be executed in parallel.

15. The cache space management method according to claim 10, characterized in that, The method further includes: During the execution of the mapping entry push operation, if there are no free cache units in the cache space to accommodate the new mapping entry to be pushed, and a shrinking operation is detected that is in progress or waiting to be performed, and the shrinking operation has selected a cache unit to be shrunk and the mapping entry in the cache unit to be shrunk has been processed into a releaseable state but has not yet been released; The cache unit to be reduced is temporarily used as a cache unit to accommodate the new mapping table entry to be pushed. After the mapping table entry to be pushed is transferred to the host cache area, the cache unit to be reduced is then released.

16. A storage device, characterized in that, include: A connection interface for electrically connecting to a host computer; The memory module includes multiple planes, each plane includes multiple blocks, and each block includes multiple physical pages; as well as The memory controller, including error checking and correction circuitry, cache memory, and memory control circuitry, is electrically connected to the connection interface and the memory module. The cache space includes static random access memory and a host cache. The memory control circuit is configured to perform the cache space management method as described in any one of claims 1 to 15.

Images