A data processing method and system
By preloading data packets into the cache in the virtualization environment, the problem of frequent CPU cache access failures in the virtio_net driver was solved, improving system performance and throughput.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JD DIGITS HAIYI INFORMATION TECHNOLOGY CO LTD
- Filing Date
- 2026-04-30
- Publication Date
- 2026-07-21
Smart Images
Figure CN122432067A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and more specifically, to a data processing method and system. Background Technology
[0002] The virtio_net driver is a paravirtualization driver in the Linux kernel used for network device communication in virtualized environments, and is part of the Virtio framework. It primarily runs in the guest operating system for efficient communication with the virtual machine monitor. However, due to the irregularities in the front-end and back-end communication protocol of the virtio_net driver, the CPU frequently fails to access cached data. Furthermore, because the CPU's processing speed is much faster than memory access speed, the CPU needs to wait a long time when it needs to read data from memory, which severely impacts system performance. Summary of the Invention
[0003] In view of this, embodiments of the present invention provide at least one data processing method, apparatus, electronic device, and storage medium that can preload data packets into a cache closer to the CPU, reducing the CPU's waiting time for data and improving system performance.
[0004] In a first aspect, embodiments of the present invention provide a data processing method, including: Based on the descriptor index, obtain the first descriptor corresponding to the first data packet, determine the memory address of the second descriptor, and initiate a prefetch request for the second descriptor and the second data packet corresponding to the second descriptor based on the memory address; Based on the data address corresponding to the first descriptor, obtain the data content of the first data packet, and execute the data processing task corresponding to the first data packet based on the data content; In response to the completion of the data processing task, the system retrieves the second descriptor returned in response to the prefetch request and stored in the cache, as well as the second data packet corresponding to the second descriptor, and executes the data processing task corresponding to the second data packet based on the data content of the second data packet.
[0005] Optionally, the data content of the first data packet is obtained according to the data address corresponding to the first descriptor, including: Based on the data address corresponding to the first descriptor, initiate a data access request to the cache for the data content of the first data packet; In response to the fact that the cache does not contain the data content of the first data packet, the cache forwards the data access request for the data content of the first data packet to memory in order to retrieve the data content of the first data packet; In response to the fact that the cache contains the data content of the first data packet, the data content of the first data packet is retrieved from the cache.
[0006] Optionally, the data content includes header data and valid data; based on the data address corresponding to the first descriptor, the data content of the first data packet is obtained, including: Obtain the header data of the first data packet and parse the header data to determine the data processing method for the first data packet; In response to the start of header data parsing, a prefetch request for valid data in the first data packet is initiated. In response to the data processing method indicating that data processing is required on the first data packet, the valid data of the first data packet is retrieved from the cache in response to the prefetch request for valid data of the first data packet and stored therein, so as to process the valid data according to the data processing method.
[0007] Optionally, the method further includes: In response to the completion of the data processing task corresponding to the first data packet, a consumption message for the first descriptor is generated and forwarded to the virtual device so that the virtual device can put the first descriptor back into the descriptor availability queue based on the received consumption message.
[0008] Secondly, embodiments of the present invention provide a data processing system, including a CPU, a cache, and memory; wherein, The CPU is used to obtain the first descriptor corresponding to the first data packet, determine the memory address of the second descriptor, and initiate a prefetch request for the second descriptor and the second data packet corresponding to the second descriptor based on the memory address; according to the data address corresponding to the first descriptor, obtain the data content of the first data packet, and execute the data processing task corresponding to the first data packet based on the data content; in response to the completion of the data processing task, obtain the second descriptor and the second data packet corresponding to the second descriptor returned in response to the prefetch request and stored in the cache, and execute the data processing task corresponding to the second data packet based on the data content of the second data packet; The memory is used to send a first descriptor and the data content of a first data packet corresponding to the first descriptor to the cache; and to send a second descriptor and the data content of a second data packet corresponding to the second descriptor to the cache according to the received prefetch request for the second descriptor. The cache is used to receive prefetch requests sent by the CPU and forward the prefetch requests to memory. It receives and saves the data content of the first descriptor and the first data packet corresponding to the first descriptor, as well as the data content of the second descriptor and the second data packet corresponding to the second descriptor, sent by memory. It then sends the data content of the first descriptor and the first data packet corresponding to the first descriptor, as well as the data content of the second descriptor and the second data packet corresponding to the second descriptor, to the CPU.
[0009] Optionally, after the CPU calculates the memory address of the second descriptor, it generates a prefetch request for the second descriptor and the second data packet corresponding to the second descriptor based on the memory address of the second descriptor, and sends the prefetch request to the cache so that the cache forwards the prefetch request to memory.
[0010] Optionally, the memory sends the second descriptor and the second data packet corresponding to the second descriptor to the cache based on the prefetch request sent by the cache for the second descriptor and the second data packet corresponding to the second descriptor. In response to the completion of the data processing task, the CPU reads the second descriptor and the second data packet corresponding to the second descriptor from the cache, and executes the data processing task corresponding to the second data packet based on the data content of the second data packet.
[0011] Thirdly, embodiments of the present invention also provide an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the computer device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the first aspect or any optional implementation of the first aspect are performed.
[0012] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the first aspect or any optional implementation thereof.
[0013] Fifthly, embodiments of the present invention also provide a computer program product, including a computer program that, when executed by a processor, implements the method of any of the above embodiments.
[0014] In any of the above-described aspects or any implementation thereof, in a packet processing scenario based on a descriptor queue, the CPU typically needs to first locate the memory address of the packet using the descriptor, and then read the corresponding packet content from memory for processing. Due to the significant access latency between memory and the CPU, if the CPU only initiates a data read request when it needs to process data, it often waits for memory to return data due to cache misses, thus reducing overall processing efficiency. Therefore, after obtaining the first descriptor corresponding to the first packet, the memory address of the second descriptor corresponding to the next packet to be processed can be determined in advance based on the descriptor index. Before or during the CPU starts processing the first packet, a prefetch request for the second descriptor and the second packet corresponding to it can be proactively initiated to the cache system. The prefetch request can drive the cache control logic to initiate a read operation from memory in the background, loading the key data of the second descriptor and the second packet from memory into a cache closer to the CPU. When the CPU subsequently retrieves the data content of the first data packet based on the data address in the first descriptor and executes the corresponding data processing task, the CPU mainly spends time on data parsing, protocol judgment, or business logic processing. Meanwhile, the cache system completes the loading process of the second descriptor and the second data packet in parallel within this time window, thus creating an overlap between computation and memory access. After the data processing task of the first data packet is completed, when the CPU needs to process the next data packet, it can directly retrieve the prefetched second descriptor and the corresponding second data packet from the cache without triggering another memory access request, thereby avoiding additional waiting time due to cache misses. In this way, the memory read operation, which originally occurred when the CPU accessed the data, is moved to the previous data packet processing stage. This allows the data to be loaded into the cache closer to the CPU before the CPU actually accesses it, significantly reducing memory access latency and effectively improving cache hit rate. This enables the CPU to continuously and efficiently execute data packet processing tasks, thereby improving the throughput and performance of the entire system in high-concurrency network data processing scenarios.
[0015] The beneficial effects of the aforementioned data processing system, electronic equipment, and storage medium are described in the description of the aforementioned data processing method, and will not be repeated here. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. These drawings are incorporated in and constitute a part of this specification. They illustrate embodiments conforming to the present invention and, together with the specification, serve to explain the technical solutions of the present invention. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.
[0017] Figure 1 A flowchart of a data processing method provided by an embodiment of the present invention is shown; Figure 2 A flowchart illustrating a data processing method provided by an embodiment of the present invention is shown; Figure 3 An exemplary system architecture in which embodiments of the present invention can be applied is shown; Figure 4 A schematic diagram of the structure of a computer system used to implement embodiments of the present invention is shown. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0019] It should be noted that the collection, use, storage, sharing and transfer of user personal information involved in the technical solution of the present invention all comply with the provisions of relevant laws and regulations, and require notification to users and obtaining their consent or authorization. When applicable, user personal information is subjected to de-identification and / or anonymization and / or encryption technical processing.
[0020] The above problems and solutions are the result of the inventor's practice and careful research. The discovery process of the above problems and the solutions proposed for the above problems should be considered as the inventor's contribution to the invention.
[0021] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0022] To facilitate understanding of this embodiment, a data processing method disclosed in this invention will first be described in detail. The execution subject of the data processing method provided in this invention is generally a computer device with certain computing capabilities. This computer device may include, for example, a terminal device, a server, or other processing devices. The terminal device may be a user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc. In some possible implementations, this data processing method can be implemented by a processor calling computer-readable instructions stored in memory.
[0023] See Figure 1 The diagram shows a flowchart of a data processing method provided in an embodiment of the present invention. The method includes steps S101 to S103, wherein: S101: Based on the descriptor index, obtain the first descriptor corresponding to the first data packet, determine the memory address of the second descriptor, and initiate a prefetch request for the second descriptor and the second data packet corresponding to the second descriptor based on the memory address.
[0024] In this embodiment of the invention, the descriptor index can be used to identify a specific position in the descriptor queue. It is an index value pointing to a certain entry in the descriptor table. The descriptor index can be used to quickly locate the descriptor associated with the data packet. A descriptor is a data structure used to describe data buffer information. It typically contains information such as the address of the data buffer in memory, the data length, and related control flags. The descriptor can determine the storage location of the data packet in memory and its corresponding data size, thereby providing a location basis for subsequent data reading and processing by the CPU.
[0025] In specific implementation, such as Figure 2As shown, the process begins by searching the descriptor table for the first descriptor corresponding to the first data packet based on the current descriptor index. Information such as the address and length of the data packet buffer are then retrieved from the first descriptor to determine the storage location of the first data packet in memory. After determining the first descriptor, the position of the second descriptor corresponding to the next data packet to be processed in the descriptor table can be inferred based on the organization of the descriptor queue or the index increment relationship. This allows the specific memory address of the second descriptor to be determined. After obtaining this memory address, a prefetch request can be initiated to the processor's cache level to pre-trigger the data read operation for the second descriptor, enabling the cache to load the structure information of the second descriptor from memory based on the provided memory address. Simultaneously, since the second descriptor records the address information of the second data packet buffer in memory, a prefetch request for the data content of the second data packet can also be initiated based on this address, thereby driving the cache to pre-load the header data or critical data of the second data packet from memory into a cache closer to the CPU. In this way, before the CPU starts processing the second data packet, the relevant descriptor information and data packet data have been preloaded into the cache. This allows the CPU to read the data directly from the cache when it needs to access it later, avoiding the extra latency caused by memory access due to cache misses and improving data access efficiency.
[0026] S102: Obtain the data content of the first data packet according to the data address corresponding to the first descriptor, and perform the data processing task corresponding to the first data packet based on the data content.
[0027] In this embodiment of the invention, obtaining the data content of the first data packet according to the data address corresponding to the first descriptor includes: initiating a data access request for the data content of the first data packet to the cache according to the data address corresponding to the first descriptor; in response to the cache not storing the data content of the first data packet, causing the cache to forward the data access request for the data content of the first data packet to memory to obtain the data content of the first data packet; and in response to the cache storing the data content of the first data packet, obtaining the data content of the first data packet from the cache.
[0028] In practical implementation, the first descriptor records information such as the data address and data length of the first data packet in memory. The starting position of the data content of the first data packet in memory can be determined through the data address. For example... Figure 2As shown, after obtaining the first descriptor, the CPU can generate a data access request for the first data packet based on the data address corresponding to the first descriptor, and send the data access request to the processor's cache level to attempt to read the data content of the first data packet directly from the cache. Upon receiving the data access request, the cache can first search its own stored data to determine if the data content corresponding to the first data packet is already stored. If the cache does not contain the data content of the first data packet, it indicates a cache miss. In this case, the cache control logic can forward the data access request to memory, which will read the corresponding data content based on the data address and return the read data to the cache for temporary storage. Simultaneously, the cache will provide this data content to the CPU for subsequent data processing tasks. In another scenario, if the cache already contains the data content of the first data packet, it means that the data has been pre-loaded or previously accessed, resulting in a cache hit. In this case, the cache can directly read the corresponding data content from its own stored data according to the data access request and return the data content of the first data packet to the CPU without initiating a data read operation from memory again. This allows the cached copy of data to be used preferentially when accessing data, reducing the number of memory accesses, thereby reducing data access latency and improving the efficiency of CPU data retrieval.
[0029] In this embodiment of the invention, the data content of the first data packet may include header data and valid data. The header data can be used to record control information related to data packet transmission and processing, such as protocol type, source address, destination address, data length, or port information. The valid data is the actual business data carried in the data packet, which can be read and processed after a specific processing strategy is determined. That is, the header data mainly describes the attributes of the data packet and indicates the subsequent processing method, while the valid data is the actual data content that, based on the header parsing result, determines whether further processing is needed. Specifically, the data content includes header data and valid data. Obtaining the data content of the first data packet according to the data address corresponding to the first descriptor includes: obtaining the header data of the first data packet and parsing the header data to determine the data processing method for the first data packet; in response to the start of header data parsing, initiating a prefetch request for the valid data of the first data packet; in response to the data processing method of the first data packet indicating that data processing is required, retrieving the valid data of the first data packet returned and saved in response to the prefetch request for the valid data of the first data packet from the cache, and processing the valid data according to the data processing method.
[0030] In practical implementation, the storage location of the first data packet in memory can be located first based on the data address recorded in the first descriptor. The header data of the first data packet is retrieved first, as it is usually located at the beginning of the data packet and is relatively small, allowing for fast reading. After retrieving the header data, the CPU can parse it to determine the data processing method corresponding to the first data packet, such as whether protocol parsing, data forwarding, or business calculation is required. Simultaneously, a prefetch request for the valid data of the first data packet can be initiated to drive the cache to load the valid data of the first data packet from memory in advance, ensuring that the valid data is stored closer to the CPU before subsequent access. When the header data parsing is complete and it is determined that data processing of the first data packet is required, the CPU can directly retrieve the valid data returned and saved in response to the prefetch request from the cache and execute the corresponding data processing task according to the determined data processing method, thus avoiding the access delay caused by triggering memory reads when actually accessing the valid data. Compared to directly obtaining the data content of the first data packet, obtaining the header data and valid data of the first data packet separately allows the CPU to complete the data packet attribute judgment with a smaller amount of data first, and trigger the loading of valid data in advance during the parsing process, thereby achieving parallel execution of the calculation process and memory access process. Even when the amount of valid data is large, it can also reduce unnecessary data readings while ensuring the correctness of the processing logic.
[0031] S103: In response to the completion of the data processing task, obtain the second descriptor returned in response to the prefetch request and stored in the cache, as well as the second data packet corresponding to the second descriptor, and execute the data processing task corresponding to the second data packet based on the data content of the second data packet.
[0032] In this embodiment of the invention, after completing the data processing task for the first data packet, the CPU can continue to process subsequent data packets. Since the memory address of the second descriptor has been determined based on the descriptor index before or during the processing of the first data packet, and a prefetch request for the second descriptor and the second data packet corresponding to it has been initiated in advance, the cache has already loaded the corresponding data from memory in the background according to the prefetch request during the execution of the first data packet's data processing task. Specifically, the cache can read the structure data of the second descriptor from memory based on the memory address information carried in the prefetch request, and temporarily store this descriptor information in the cache. Simultaneously, it can trigger the reading operation of the second data packet's data content based on the data address recorded in the second descriptor, ensuring that the relevant data of the second data packet is loaded into the cache before the CPU actually accesses it. When the data processing task for the first data packet is completed, the CPU can begin processing the next data packet. At this time, the CPU can directly retrieve the second descriptor returned and saved in response to the prefetch request from the cache, thereby obtaining information such as the data address and data length of the second data packet in memory, and further read the data content of the second data packet corresponding to the second descriptor from the cache accordingly. Because the relevant data has already been pre-loaded into the cache during the previous prefetching phase, the CPU can achieve a cache hit when accessing the second descriptor and the second data packet, thus avoiding triggering another memory access request. Then, based on the content of the second data packet, the CPU can execute the corresponding data processing task, such as parsing the packet header information, determining the processing logic based on the protocol type, or performing corresponding business processing operations on valid data. This allows the CPU to prepare the data needed for the next data packet while processing the current one, creating a temporal overlap between the data loading and processing processes. This effectively reduces the CPU's idle time while waiting for data to return from memory, improves the cache hit rate, and lowers the overall memory access latency. This enables the processor to execute data packet processing tasks more continuously and efficiently, thereby improving the overall system performance in high-throughput data processing scenarios.
[0033] In this embodiment of the invention, after completing the data processing task corresponding to the first data packet, the status of the currently used descriptors can be updated so that subsequent data packet processing can continue to use the descriptor resource. Specifically, the method further includes: in response to the completion of the data processing task corresponding to the first data packet, generating a consumption message for the first descriptor, and forwarding the consumption message to the virtual device, so that the virtual device can return the first descriptor to the descriptor availability queue according to the received consumption message.
[0034] In specific implementation, such as Figure 2As shown, after the CPU obtains the data content of the first data packet based on the first descriptor and completes the corresponding data processing task, it indicates that the buffer associated with the data packet has been successfully consumed. Therefore, a consumption message can be generated for the first descriptor to indicate that the descriptor has been processed and is no longer occupied by the current processing flow. The consumption message may contain the descriptor index corresponding to the first descriptor, a processing completion identifier, or related status information, used to indicate to the virtual device that the data buffer described by the descriptor has been used. After generating the consumption message, it can be forwarded to the virtual device, enabling the virtual device to be aware of the change in the usage status of the corresponding descriptor. Upon receiving the consumption message, the virtual device can locate the corresponding first descriptor based on the descriptor identifier information carried in the message, update the status in the descriptor queue, and put the processed first descriptor back into the descriptor availability queue for reuse in subsequent new data packet reception or transmission processes. This allows for the timely release of occupied descriptor resources after data packet processing, achieving continuous descriptor reuse and avoiding the problem of long-term descriptor resource occupation or exhaustion.
[0035] According to a second aspect of the present invention, a data processing system is provided, including a CPU, a cache, and memory; wherein, The CPU is used to obtain the first descriptor corresponding to the first data packet, determine the memory address of the second descriptor, and initiate a prefetch request for the second descriptor and the second data packet corresponding to the second descriptor based on the memory address; according to the data address corresponding to the first descriptor, obtain the data content of the first data packet, and execute the data processing task corresponding to the first data packet based on the data content; in response to the completion of the data processing task, obtain the second descriptor and the second data packet corresponding to the second descriptor returned in response to the prefetch request and stored in the cache, and execute the data processing task corresponding to the second data packet based on the data content of the second data packet; The memory is used to send a first descriptor and the data content of a first data packet corresponding to the first descriptor to the cache; and to send a second descriptor and the data content of a second data packet corresponding to the second descriptor to the cache according to the received prefetch request for the second descriptor. The cache is used to receive prefetch requests sent by the CPU and forward the prefetch requests to memory. It receives and saves the data content of the first descriptor and the first data packet corresponding to the first descriptor, as well as the data content of the second descriptor and the second data packet corresponding to the second descriptor, sent by memory. It then sends the data content of the first descriptor and the first data packet corresponding to the first descriptor, as well as the data content of the second descriptor and the second data packet corresponding to the second descriptor, to the CPU.
[0036] As described above, after the CPU determines the location of the second descriptor corresponding to the next data packet to be processed based on the descriptor index or the organization of the descriptor queue, it can further calculate the specific address of the second descriptor in memory. Since descriptors are usually stored in a descriptor table or descriptor queue, the CPU can calculate the memory address of the second descriptor based on the base address of the descriptor table and the index value corresponding to the second descriptor. After obtaining this memory address, the CPU can generate a prefetch request for the second descriptor based on this address, and simultaneously generate a data prefetch request for the second data packet corresponding to the second descriptor based on the data buffer address information recorded in the second descriptor, thus forming a prefetch operation for preloading relevant data. The CPU can then send the generated prefetch request to the cache, which receives and processes the prefetch request. When the cache receives a prefetch request, it can determine whether the corresponding data already exists in the cache based on the memory address information carried in the request. If the relevant data is not stored in the cache, the cache will forward the prefetch request to the memory, which will read the second descriptor and the relevant data of the second data packet based on the provided memory address, and return the read data to the cache for storage, so that the relevant data is loaded into the cache closer to the CPU in advance before subsequent CPU access.
[0037] Once the CPU completes its current data processing task, it can directly read the prefetched second descriptor and its corresponding second data packet from the cache without accessing memory again, thus avoiding access latency. The CPU can then execute corresponding data processing tasks based on the content of the second data packet, such as parsing the packet header information, determining processing logic, or performing business operations on valid data, thereby achieving continuous and efficient data packet processing. This allows memory access and CPU computation tasks to overlap, enabling the CPU to quickly obtain the data needed for the next data packet, improving cache hit rate, significantly reducing processing latency, and enhancing overall system performance.
[0038] According to a third aspect of the present invention, an electronic device for data processing is provided, comprising: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method provided in the first aspect of the present invention.
[0039] According to a fourth aspect of the present invention, a computer-readable medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method provided in the first aspect of the present invention.
[0040] According to a fifth aspect of the present invention, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the method of any of the above embodiments.
[0041] Figure 3 An exemplary system architecture 300 is shown that can be applied to the data processing method or data processing apparatus implemented in this invention.
[0042] like Figure 3 As shown, system architecture 300 may include terminal devices 301, 302, and 303, a network 304, and a server 305. Network 304 serves as the medium for providing communication links between terminal devices 301, 302, and 303 and server 305. Network 304 may include various connection types, such as wired or wireless communication links, or fiber optic cables, etc.
[0043] Users can use terminal devices 301, 302, and 303 to interact with server 305 via network 304 to receive or send messages, etc. Various communication client applications can be installed on terminal devices 301, 302, and 303, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, social media platform software, etc. (for example only).
[0044] Terminal devices 301, 302, and 303 can be various electronic devices with displays and web browsing capabilities, including but not limited to smartphones, tablets, laptops, and desktop computers.
[0045] Server 305 can be a server that provides various services, such as a backend management server that supports shopping websites browsed by users using terminal devices 301, 302, and 303 (for example only). The backend management server can process received data processing requests and return the processing results (for example only) to the terminal devices.
[0046] It should be noted that the data processing method provided in the embodiments of the present invention is generally executed by server 305, and correspondingly, the data processing device is generally disposed in server 305. The data processing method provided in the embodiments of the present invention can also be executed by terminal devices 301, 302, and 303, and correspondingly, the data processing device can be disposed in terminal devices 301, 302, and 303.
[0047] It should be understood that Figure 3 The number of terminal devices, networks, and servers shown is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, and servers can be included.
[0048] The following is for reference. Figure 4 It shows a schematic diagram of the structure of a computer system 400 suitable for implementing a terminal device of the present invention. Figure 4The terminal device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.
[0049] like Figure 4 As shown, the computer system 400 includes a central processing unit (CPU) 401, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 402 or programs loaded from storage section 408 into random access memory (RAM) 403. The RAM 403 also stores various programs and data required for the operation of the system 400. The CPU 401, ROM 402, and RAM 403 are interconnected via a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.
[0050] The following components are connected to I / O interface 405: an input section 406 including a keyboard, mouse, etc.; an output section 407 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 408 including a hard disk, etc.; and a communication section 409 including a network interface card such as a LAN card, modem, etc. The communication section 409 performs communication processing via a network such as the Internet. Drive 410 is also connected to I / O interface 405 as needed. Removable media 411, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 410 as needed so that computer programs read from them can be installed into storage section 408 as needed.
[0051] In particular, according to the embodiments disclosed in this invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this invention include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 409, and / or installed from removable medium 411. When the computer program is executed by central processing unit (CPU) 401, it performs the functions defined above in the system of this invention.
[0052] It should be noted that the computer-readable medium shown in this invention can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this invention, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.
[0053] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.
[0054] The modules described in the embodiments of the present invention can be implemented in software or in hardware. The described modules can also be located in a processor. For example, a processor includes a first prefetch module, a processing module, and a second prefetch module. The names of these modules do not necessarily limit the module itself. For example, the first prefetch module can also be described as "a module that initiates a prefetch request for a second descriptor and a second data packet corresponding to the second descriptor based on a memory address".
[0055] In another aspect, the present invention also provides a computer-readable medium, which may be included in the device described in the above embodiments; or it may exist independently and not assembled into the device. The computer-readable medium carries one or more programs, and when the one or more programs are executed by the device, the device implements the following method: obtaining a first descriptor corresponding to a first data packet based on a descriptor index, and determining the memory address of a second descriptor; initiating a prefetch request for the second descriptor and the second data packet corresponding to the second descriptor based on the memory address; obtaining the data content of the first data packet based on the data address corresponding to the first descriptor, and executing a data processing task corresponding to the first data packet based on the data content; in response to the completion of the data processing task, obtaining the second descriptor returned in response to the prefetch request and stored in a cache, and the second data packet corresponding to the second descriptor; and executing a data processing task corresponding to the second data packet based on the data content of the second data packet.
[0056] Finally, it should be noted that the above embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A data processing method applied to a CPU, characterized in that, include: Based on the descriptor index, obtain the first descriptor corresponding to the first data packet, determine the memory address of the second descriptor, and initiate a prefetch request for the second descriptor and the second data packet corresponding to the second descriptor based on the memory address; Based on the data address corresponding to the first descriptor, the data content of the first data packet is obtained, and a data processing task corresponding to the first data packet is executed based on the data content; In response to the completion of the data processing task, the system obtains the second descriptor returned in response to the prefetch request and stored in the cache, as well as the second data packet corresponding to the second descriptor, and executes the data processing task corresponding to the second data packet based on the data content of the second data packet.
2. The method according to claim 1, characterized in that, Based on the data address corresponding to the first descriptor, the data content of the first data packet is obtained, including: Based on the data address corresponding to the first descriptor, a data access request for the data content of the first data packet is initiated to the cache; In response to the fact that the cache does not contain the data content of the first data packet, the cache forwards the data access request for the data content of the first data packet to memory in order to obtain the data content of the first data packet; In response to the fact that the cache contains the data content of the first data packet, the data content of the first data packet is retrieved from the cache.
3. The method according to claim 2, characterized in that, The data content includes header data and valid data; based on the data address corresponding to the first descriptor, the data content of the first data packet is obtained, including: Obtain the header data of the first data packet and parse the header data to determine the data processing method for the first data packet; In response to the start of header data parsing, a prefetch request for valid data of the first data packet is initiated. In response to the data processing method indicating that the first data packet needs to be processed, the valid data of the first data packet is retrieved from the cache in response to the prefetch request for valid data of the first data packet and stored therein, so as to process the valid data according to the data processing method.
4. The method according to claim 1, characterized in that, The method further includes: In response to the completion of the data processing task corresponding to the first data packet, a consumption message for the first descriptor is generated and the consumption message is forwarded to the virtual device so that the virtual device can put the first descriptor back into the descriptor availability queue according to the received consumption message.
5. A data processing system, characterized in that, This includes CPU, cache, and memory; among which, The CPU is configured to acquire a first descriptor corresponding to a first data packet, determine the memory address of a second descriptor, and initiate a prefetch request for the second descriptor and the second data packet corresponding to the second descriptor based on the memory address; acquire the data content of the first data packet according to the data address corresponding to the first descriptor, and execute a data processing task corresponding to the first data packet based on the data content; in response to the completion of the data processing task, acquire the second descriptor and the second data packet corresponding to the second descriptor that were returned in response to the prefetch request and stored in the cache, and execute a data processing task corresponding to the second data packet based on the data content of the second data packet; The memory is used to send a first descriptor and the data content of a first data packet corresponding to the first descriptor to the cache; and to send a second descriptor and the data content of a second data packet corresponding to the second descriptor to the cache according to the received prefetch request for the second descriptor. The cache is used to receive a prefetch request sent by the CPU, forward the prefetch request to the memory, receive and save the data content of a first descriptor and a first data packet corresponding to the first descriptor, as well as the data content of a second descriptor and a second data packet corresponding to the second descriptor sent by the memory, and send the first descriptor and the data content of the first data packet corresponding to the first descriptor, as well as the data content of the second descriptor and the second data packet corresponding to the second descriptor, to the CPU.
6. The system according to claim 5, characterized in that, After the CPU calculates the memory address of the second descriptor, it generates a prefetch request for the second descriptor and the second data packet corresponding to the second descriptor based on the memory address of the second descriptor, and sends the prefetch request to the cache so that the cache forwards the prefetch request to the memory.
7. The system according to claim 6, characterized in that, The memory sends the second descriptor and the second data packet corresponding to the second descriptor to the cache according to the prefetch request sent by the cache for the second descriptor and the second data packet corresponding to the second descriptor; In response to the completion of the data processing task, the CPU reads the second descriptor and the second data packet corresponding to the second descriptor from the cache, and executes the data processing task corresponding to the second data packet based on the data content of the second data packet.
8. An electronic device, characterized in that, include: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1-4.
9. A computer-readable medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1-4.
10. A computer program product comprising a computer program that, when executed by a processor, implements the method as described in any one of claims 1-4.