A method for a CPU and a scatter DMA to share a cache
By acquiring cache management information and redirecting data through hardware, the cache consistency problem between the CPU and DMA is solved, reducing CPU consumption and waiting time, achieving consistency transparency, and improving system performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHUHAI HUGE IC CO LTD
- Filing Date
- 2026-05-08
- Publication Date
- 2026-07-21
AI Technical Summary
In existing technologies, the cache coherence problem between CPU and DMA leads to high CPU consumption and long waiting times. Software maintenance methods are inefficient, while hardware solutions suffer from data loss and read inconsistency.
The system obtains cache management information through hardware, restricts CPU access, determines cache line hits, redirects data to an intermediate transfer area, performs data operations using Scatter DMA, and releases access control.
Reduce CPU utilization, decrease waiting time, achieve transparent cache consistency, and improve system throughput and application smoothness.
Smart Images
Figure CN122432068A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design technology, and more specifically to a method for CPU and Scatter DMA to share a cache. Background Technology
[0002] With advancements in chip design, most chips today employ cache to bridge the significant speed differences between the CPU and external memory. However, DMA (Direct Memory Access) devices are typically designed to read and write data directly to memory without notifying the cache. This separate access path creates cache coherence issues between the CPU and DMA when processing shared data.
[0003] Currently, there are two main approaches to resolving cache coherency issues between the CPU and DMA: The first is hardware maintenance, typically achieved through automatic replacement mechanisms and TTL expiration management. However, this approach has significant limitations, failing to handle critical situations and usually requiring manual software maintenance. The second approach is manual software maintenance. While flexible, this method suffers from drawbacks because hardware interfaces are typically managed line-by-line. When processing large amounts of data (hundreds of KB or more) such as video caches, the software must traverse the entire data space line-by-line to perform invalidation or write-back operations, resulting in substantial CPU consumption and waiting time. External cache designs, with their increased register operations, consume even more time than embedded CPU caches.
[0004] Therefore, a method for sharing the cache between the CPU and Scatter DMA needs to be proposed to solve the problems of high CPU usage and long waiting time caused by handling cache coherency issues through software maintenance in the existing technology, as well as the data loss and read inconsistency problems in the existing hardware solutions. This would improve system operating efficiency while reducing the workload of developers in complex consistency maintenance. Summary of the Invention
[0005] This invention provides a method and system for CPU and Scatter DMA to share a cache, thereby solving the technical problem of existing cache coherency processing methods requiring large CPU consumption and waiting time.
[0006] To address the above problems, this invention provides a method for CPU and Scatter DMA to share a cache, comprising:
[0007] Before Scatter DMA performs data access to main memory, cache management information is obtained through hardware using the main memory access bus. During the acquisition process, concurrent access of the CPU to the cache management information is limited to ensure the stability of the cache management information during the acquisition.
[0008] Based on the cache management information, determine whether the cache line corresponding to the accessed main memory target address is in a hit state;
[0009] When a cache line is hit, access control is performed on the hit cache line to restrict CPU access to the data in the cache line;
[0010] The data of the hit cache line is stored in the intermediate transfer area, and the Scatter DMA access to the target address is redirected to the intermediate transfer area through the address translation mechanism, so that the Scatter DMA can use the intermediate transfer area to complete the data read and write operations.
[0011] After the Scatter DMA data access operation is completed, access control on the cache line is released.
[0012] Secondly, the present invention also provides a cache consistency management module, which is connected to the CPU, ScatterDMA and cache. The module includes a monitoring unit, a hard acquisition unit, a decision unit, a remapping unit and an access control unit connected in sequence, and also includes an intermediate transfer unit connected to the remapping unit.
[0013] The monitoring unit is used to monitor the main memory access request signals initiated by Scatter DMA in real time.
[0014] The hardware acquisition circuit is used to automatically read and latch the cache management information in the external cache module when the access request signal is detected;
[0015] The determination unit is used to determine whether the target address of the access request hits a cache line based on the cache management information;
[0016] The remapping unit is used to redirect the access request of the target address to the intermediate transfer module when a hit is determined, so that the Scatter DMA can complete the data read and write operations through the intermediate transfer module;
[0017] An access control unit is used to perform a locking operation on the cache line that has been hit after a hit is determined, and to release the lock after the access request is completed;
[0018] The intermediate transfer module is used to mirror and cache the hit cache lines.
[0019] Thirdly, the present invention also provides a system for CPU and Scatter DMA to share a cache, including CPU, cache, Scatter DMA and cache consistency management module, wherein the cache consistency management module is connected to CPU, Scatter DMA and cache;
[0020] The CPU initiates storage access requests to the Cache; the Cache stores data lines and associated management information; the Scatter DMA initiates access requests to main memory addresses; and the Cache consistency management module, as described in the above technical solution, maintains data consistency between the Cache module and the Scatter DMA through hardware.
[0021] Compared with the prior art, the beneficial effects of the present invention include:
[0022] (1) Through the underlying hardware-level automatic query and redirection logic, the traditional inefficient software traversal cache maintenance method is completely replaced. During the operation of Scatter DMA, the cache management information is automatically latched by hardware and a hit determination is performed to accurately redirect DMA access traffic to the intermediate transfer area, freeing the CPU from the heavy consistency maintenance logic, eliminating the computational overhead caused by software traversal, and significantly reducing the CPU utilization rate.
[0023] (2) For software developers, complete transparency of cache consistency is achieved. When writing DMA drivers or big data transfer logic, programmers no longer need to manually call complex cache write-back or invalidation instructions, which greatly reduces programming difficulty and avoids potential human logic errors. The hardware-level managed design not only makes consistency maintenance more deterministic, but also directly improves the system throughput and the smoothness of application response by reducing the waiting time of cache processing.
[0024] This invention replaces the software-based cache line traversal maintenance method by directly querying cache management information and cache data areas through hardware. This eliminates the need for programmers to worry about cache consistency issues, significantly reduces CPU usage, improves application smoothness, and has a huge economic effect. Attached Figure Description
[0025] Figure 1 A schematic diagram of the method for CPU and Scatter DMA sharing cache provided by the present invention;
[0026] Figure 2 A schematic diagram illustrating the cache management information format for this invention;
[0027] Figure 3 This is a schematic diagram of the connection structure of the cache consistency management module provided by the present invention;
[0028] Figure 4 This is a schematic diagram illustrating the application implementation process of the Cache consistency management module provided by the present invention;
[0029] Figure 5 This is a schematic diagram of the system structure of the CPU and Scatter DMA shared cache provided by the present invention. Detailed Implementation
[0030] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.
[0031] Before introducing the embodiments of the present invention, the inventive concept will be explained first.
[0032] The current software methods for cache maintenance are as follows:
[0033] Before performing a DMA (Direct Memory Access) operation to write data to memory, the CPU first invalidates the cache line corresponding to the target address, and then initiates DMA to begin the write. After the DMA write is complete, the CPU may need to invalidate the corresponding cache line again to prevent software / hardware prefetching operations from occurring between the previous invalidation and the completion of the DMA write. Through these two invalidation operations, the CPU can ensure the reliability of data reads. While the above method solves the hardware overhead problem, to ensure the correctness of reads and writes, the CPU needs to perform two invalidation operations on the cache corresponding to the DMA address range for both DMA reads and fetches. However, these two invalidation operations significantly reduce processor efficiency, and not all cache lines need to be invalidated.
[0034] Before performing data read operations on memory using DMA, the CPU first performs a write-back (Clean) or write-back and invalidation (Clean & invalid) on the hit cache lines, and then initiates DMA to read the data and completes the data read. This is because: if the CPU has just modified the data, the latest data may still be in the cache, while the data in main memory is still the old data. If DMA reads directly from main memory, it will read the old data. By performing a Clean operation, the CPU can be forced to flush the latest value from the cache back to main memory. However, when performing a Clean operation, it is usually unknown which data lines actually exist in the cache, and it is necessary to blindly traverse the entire memory address range involved in the DMA and scan line by line.
[0035] Since the data that the CPU and DMA need to access at the same time is usually only the beginning and end, especially in audio and video applications, a large amount of audio and video data streams often only require the CPU to add a few layers of protocol header information at the beginning; the number of lines entering the cache from the DMA area is usually small, but it still has to be processed. Therefore, there are often situations where thousands of missed lines are traversed and processed just for a few hit cache lines, which greatly wastes CPU resources.
[0036] Taking a 32KB cache, a line size of 16 bytes, and a data length of 512KB as an example, software maintenance of the cache requires traversing the entire data space, and the total number of cache lines that need to be processed is: 512*1024 / 16 = 32768 (lines). Assuming that each line takes 10 CPU clock cycles to process, it takes 32768*10 CPU clock cycles. For a 100MHz CPU, it takes 32768*10 / 10 (us) = 32.768ms, which is a huge cost.
[0037] To reduce CPU usage (Cache processing time), improve application smoothness, and allow programmers to focus on cache consistency, this invention proposes a new solution that replaces the existing method of maintaining cache lines by traversing them in software by directly querying cache management information and cache data areas through hardware.
[0038] Example 1
[0039] This invention provides a method for CPU and Scatter DMA to share a cache, such as... Figure 1 As shown, Figure 1 This is a flowchart illustrating the method for sharing a cache between the CPU and Scatter DMA, including:
[0040] Step S101: Before the Scatter DMA performs data access to the main memory, the main memory access bus is used by the hardware to obtain cache management information. During the acquisition process, the concurrent access of the CPU to the cache management information is limited to ensure the stability of the cache management information during the acquisition.
[0041] Step S102: Determine whether the cache line corresponding to the accessed main memory target address is in a hit state based on the cache management information;
[0042] Step S103: When a cache line is hit, access control is performed on the hit cache line to restrict CPU access to the cache line.
[0043] Step S104: Store the data of the hit cache line in the intermediate transfer area, and redirect the Scatter DMA's access to the target address to the intermediate transfer area through the address translation mechanism, so that the Scatter DMA can use the intermediate transfer area to complete the data read and write operations;
[0044] Step S105: After the Scatter DMA data access operation is completed, release the access control on the cache line.
[0045] The method for sharing cache between the CPU and Scatter DMA provided in this embodiment firstly obtains cache management information and determines the hit status by directly monitoring the bus in hardware, while restricting CPU access. Secondly, it implements hardware-level locking for the hit cache line and diverts DMA access to a dedicated intermediate transfer area for data reading and writing through an address redirection mechanism. Finally, it automatically releases access control after the DMA transfer is completed, achieving consistency maintenance. This method uses hardware automation to complete latching-determination-redirection, replacing the traditional inefficient software loop traversal. It not only eliminates the redundant double invalidation overhead in write operation scenarios, but also ensures that DMA can directly read the latest image data modified by the CPU from the transfer area in read operation scenarios. This avoids the huge bus latency and invalid main memory I / O caused by writing back to main memory and then reading, greatly reducing CPU load and processing latency, and achieving cache consistency between the CPU and Scatter DMA in all scenarios.
[0046] In a preferred embodiment, when the Scatter DMA performs a write request on the main memory, if a cache line is hit, the data to be written sent by the Scatter DMA is stored in the row space corresponding to the intermediate transfer area, and the hit cache line is updated synchronously. After the synchronous update is completed, the status bit of the hit cache line is marked as modified.
[0047] If no cache line is hit, the Scatter DMA directly exchanges data with main memory without triggering cache replacement or write-back logic.
[0048] The following specific example illustrates the cache coherency handling process in a scenario where DMA performs write operations on main memory.
[0049] Before the DMA performs a write operation on the target address, the cache management information is first obtained through the hardware access path. During the acquisition process, the CPU access requests for the cache management information are controlled to keep the acquired cache management information stable, thereby forming valid cache state information for hit determination.
[0050] Based on the cache management information, a cache line hit determination is performed on the cache line corresponding to the DMA target address. When a cache line hit is determined, access control is executed on the hit cache line to restrict CPU access to the data in the cache line. Next, the data of the hit cache line is read into the intermediate transfer area via hardware, and an address mapping relationship between the DMA access address and the intermediate transfer area is established, so that DMA write operations to the target address are redirected to the intermediate transfer area.
[0051] If the target address does not hit the cache line, the DMA will directly perform a write operation on the main memory.
[0052] Using the above method, during DMA execution, the data interaction between the intermediate storage area and the corresponding cache line is controlled by hardware. The data in the intermediate storage area is updated to the corresponding cache line in parallel, and the cache line is marked as modified to indicate that the cache data has been updated relative to the main memory data.
[0053] After the DMA write operation is completed, access control to the cache line is released, allowing the CPU to resume access to the cache line.
[0054] This scheme eliminates the need to traverse the DMA address range and perform two invalid cache operations as required by traditional DMA write operations, greatly improving processing efficiency. Even if the CPU accesses this cache area during DMA data writing, the old data loaded into the cache by the CPU will be updated to the new data by DMA, ensuring the consistency between the CPU and Scatter DMA sharing the cache.
[0055] In a preferred embodiment, after the address redirection takes effect, when the Scatter DMA performs a read request on the main memory, if a cache line is hit, the data extracted from the hit cache line to the intermediate transfer area is provided to the Scatter DMA as the target data.
[0056] If a cache line is not hit, the Scatter DMA directly exchanges data with the main memory.
[0057] As a specific implementation, when the DMA reads main memory, if a hit occurs, the cache line data is read into the intermediate transfer area via hardware, and scatter DMA redirection is set so that the scatter DMA reads data from the intermediate transfer area. In this way, the read is completed using hardware by preloading data.
[0058] If no row is hit, the DMA reads the required data directly from main memory.
[0059] The above method reduces main memory I / O, eliminating the need for CPU and cache data to constantly interact through main memory.
[0060] In some embodiments, to prevent DMA from causing additional hits and misses to the cache, DMA read and write data only accesses cache lines that have already been hit, thus unifying the interaction between DMA and main memory for the hit cache lines.
[0061] In a preferred embodiment, the restriction on concurrent CPU access to cache management information during the acquisition process is implemented using a cache lock register or bus blocking.
[0062] In some embodiments, a portion of the cache has a locking function, in which case the cache lock register can be configured directly. If there is no locking function, cache access requests to that region of memory can only be temporarily held (requiring a comparator).
[0063] Specifically, for hardware environments that support native locking, a control word is written to the lock register of the external cache controller via the bus interface. This control word contains the set index and line index corresponding to the hit cache line. Once the register is configured, the CPU will automatically be prohibited from replacing or modifying that specific cache line. This approach achieves minimal power consumption for consistency maintenance by reusing existing hardware resources.
[0064] For hardware environments that do not support native locking, access control is implemented through an internally integrated hardware intercept comparator. Specifically, this intercept comparator is deployed on the address bus between the external CPU and the cache. When a hit indication signal is generated, the hit main memory target address is loaded into the reference register of the intercept comparator. Subsequently, the intercept comparator monitors memory access requests issued by the CPU in real time. If it detects that the address requested by the CPU matches the address in the reference register, the intercept comparator forcibly suspends the CPU's memory request for that specific address segment by setting a pending signal or pulling a ready signal low, until the Scatter DMA operation is completed and the request is released.
[0065] The above method achieves adaptability in chip architectures with different performance levels. It can reduce power consumption by utilizing the register characteristics of high-level chips, and can also achieve strong consistency guarantee in low-level chips through simple comparator logic, ensuring the absolute security of data during DMA transfer.
[0066] In a preferred embodiment, the cache management information includes at least Tag, Set, and Offset information; wherein, the Tag information is used for hardware parallel comparison with the high-order bits of the main memory target address to generate hit indication information; the Set information is used to quickly locate the group index of the target cache line during the hardware acquisition phase; and the Offset information is used to determine the specific starting position of the data within the line when redirected to the intermediate transfer area.
[0067] As a specific example, such as Figure 2 As shown, Figure 2 This demonstrates common cache management information formats. The offset represents the inline offset, occupying 0 bits; the cache set identifies the cache path, occupying 6 bits; the tag identifies the high address, occupying 10 bits; T + 6 + 0 = 32.
[0068] Taking a 32KB 4-way set-associative cache with line 16 as an example: O=4 (2^4=16); S=2 (2^2=4); T=32-SO=26; (high address).
[0069] By using the tag and set in the cache management information, we can quickly locate whether the corresponding row is valid and follow up with DMA requirements to write new data or read the corresponding row data.
[0070] In a preferred embodiment, the direct hardware query for cache management information includes:
[0071] Using a multi-way parallel comparator, the validity of the corresponding cache line is determined by the Tag and Set information in the cache management information.
[0072] Furthermore, the step of using a multi-way parallel comparator to locate the validity of the corresponding cache line through the Tag and Set information in the cache management information includes:
[0073] Iteratively query all cache lines, searching multiple paths in parallel during each iteration. Each path compares one cache group, traversing from the first path to the last path to match the target address.
[0074] As a specific implementation, each iteration compares one cache way; multiple sets in the cache are searched in parallel (multi-way); traversal starts from the first way of the cache and continues until the last way of the cache. For example: a 32KB cache with 4 sets (ways) associative LineSize=16Byte; each way has 32*1024 / 4 / 16=512 lines, each time comparing the 4 sets in one way to see if they match the target address range; a total of 512 traversals are required.
[0075] Furthermore, the intermediate transfer area (hereinafter referred to as remap memory) is a memory used to temporarily cache CPU and DMA data; it is managed by line, and the line size is consistent with the cache line size.
[0076] The initial data for remap memory is always retrieved from the cache line. Then, by modifying the remap address on the memory bus, the DMA behavior of reading and writing main memory space is changed to reading and writing remap memory space. Hardware modifications are needed to maintain remap memory management information for easy recording and debugging. The format of remap memory management information is shown in Table 1 (one per line):
[0077] Table 1. Format of Intermediate Transfer Area Management Information
[0078]
[0079] This method replaces the software-based cache line maintenance by directly querying cache management information and the cache data area through hardware. This eliminates the need for programmers to worry about cache consistency issues and significantly reduces CPU usage (cache processing time), improving application smoothness and user experience, resulting in a huge economic benefit.
[0080] Example 2
[0081] This invention also provides a cache consistency management module, which is connected to the CPU, Scatter DMA and cache. The module includes a monitoring unit, a hard acquisition unit, a decision unit, a remapping unit and an access control unit connected in sequence, and also includes an intermediate transfer unit connected to the remapping unit.
[0082] The monitoring unit is used to monitor the main memory access request signals initiated by Scatter DMA in real time.
[0083] The hardware acquisition circuit is used to automatically read and latch the cache management information in the external cache module when the access request signal is detected;
[0084] The determination unit is used to determine whether the target address of the access request hits a cache line based on the cache management information;
[0085] The remapping unit is used to redirect the access request of the target address to the intermediate transfer module when a hit is determined, so that the Scatter DMA can complete the data read and write operations through the intermediate transfer module;
[0086] An access control unit is used to perform a locking operation on the cache line that has been hit after a hit is determined, and to release the lock after the access request is completed;
[0087] The intermediate transfer module is used to mirror and cache the hit cache lines.
[0088] like Figure 3 As shown, Figure 3 This embodiment illustrates the connection structure of the cache consistency management module.
[0089] For a clearer explanation of the system's operating logic, please refer to [link / reference]. Figure 4 , Figure 4 The flowchart illustrating the actual application of this module is shown.
[0090] In a preferred embodiment, the determination unit employs a multi-channel parallel determination array;
[0091] The multi-path parallel decision array contains multiple independent address comparators, which are used to simultaneously match the management information of multiple latched cache lines with the target address in parallel.
[0092] Example 3
[0093] This invention also provides a system for CPU and Scatter DMA to share a cache, including CPU, cache, Scatter DMA and cache consistency management module, wherein the cache consistency management module is connected to CPU, Scatter DMA and cache;
[0094] The CPU initiates storage access requests to the Cache; the Cache stores data lines and associated management information; the Scatter DMA initiates access requests to main memory addresses; the Cache consistency management module adopts the Cache consistency management module in Embodiment 2, and is used to maintain data consistency between the Cache module and the Scatter DMA through hardware.
[0095] like Figure 5 As shown, Figure 5 A schematic diagram of the architecture of a system with a shared cache for CPU and Scatter DMA provided in the embodiment is shown.
[0096] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for CPU and Scatter DMA to share a cache, characterized in that, include: Before Scatter DMA performs data access to main memory, cache management information is obtained through hardware using the main memory access bus. During the acquisition process, concurrent access of the CPU to the cache management information is limited to ensure the stability of the cache management information during the acquisition. Based on the cache management information, determine whether the cache line corresponding to the accessed main memory target address is in a hit state; When a cache line is hit, access control is performed on the hit cache line to restrict CPU access to the data in the cache line; The data of the hit cache line is stored in the intermediate transfer area, and the ScatterDMA access to the target address is redirected to the intermediate transfer area through the address translation mechanism, so that the ScatterDMA can use the intermediate transfer area to complete the data read and write operations. After the Scatter DMA data access operation is completed, access control on the cache line is released.
2. The method for CPU and Scatter DMA sharing cache according to claim 1, characterized in that, When the Scatter DMA performs a write request on the main memory, if a cache line is hit, the data to be written sent by the Scatter DMA is stored in the row space corresponding to the intermediate transfer area, and the hit cache line is updated synchronously. After the synchronous update is completed, the status bit of the hit cache line is marked as modified. If no cache line is hit, the Scatter DMA directly exchanges data with main memory without triggering cache replacement or write-back logic.
3. The method for CPU and Scatter DMA sharing cache according to claim 1, characterized in that, After the address redirection takes effect, when the Scatter DMA performs a read request on the main memory, if a cache line is hit, the data extracted from the hit cache line to the intermediate transfer area will be provided to the Scatter DMA as the target data. If a cache line is not hit, the Scatter DMA directly exchanges data with the main memory.
4. The method for CPU and Scatter DMA sharing cache according to claim 1, characterized in that, The process of obtaining information restricts concurrent CPU access to cache management information by using cache lock registers or bus blocking.
5. The method for CPU and Scatter DMA sharing cache according to claim 1, characterized in that, The cache management information includes at least Tag, Set, and Offset information; wherein, Tag information is used for hardware parallel comparison with the high bits of the main memory target address to generate hit indication information; Set information is used to quickly locate the group index of the target cache line during the hardware acquisition phase; Offset information is used to determine the specific starting position of the data within the line when redirected to the intermediate transfer area.
6. The method for CPU and Scatter DMA sharing cache according to claim 5, characterized in that, The method of directly querying cache management information via hardware includes: Using a multi-way parallel comparator, the validity of the corresponding cache line is determined by the Tag and Set information in the cache management information.
7. The method for CPU and Scatter DMA to share cache according to claim 6, characterized in that, The step of using a multi-way parallel comparator to locate the validity of the corresponding cache line through the Tag and Set information in the cache management information includes: Iteratively query all cache lines, searching multiple paths in parallel during each iteration. Each path compares one cache group, traversing from the first path to the last path to match the target address.
8. A cache consistency management module, characterized in that, The module is connected to the CPU, Scatter DMA and Cache. The module includes a monitoring unit, a hard acquisition unit, a decision unit, a remapping unit and an access control unit connected in sequence, and also includes an intermediate transfer unit connected to the remapping unit. The monitoring unit is used to monitor the main memory access request signals initiated by Scatter DMA in real time. The hardware acquisition circuit is used to automatically read and latch the cache management information in the external cache module when the access request signal is detected; The determination unit is used to determine whether the target address of the access request hits a cache line based on the cache management information; The remapping unit is used to redirect the access request of the target address to the intermediate transfer module when a hit is determined, so that the Scatter DMA can complete the data read and write operations through the intermediate transfer module; An access control unit is used to perform a locking operation on the cache line that has been hit after a hit is determined, and to release the lock after the access request is completed; The intermediate transfer module is used to mirror and cache the hit cache lines.
9. The cache consistency management module according to claim 9, characterized in that, The determination unit employs a multi-channel parallel determination array; The multi-path parallel decision array contains multiple independent address comparators, which are used to simultaneously match the management information of multiple latched cache lines with the target address in parallel.
10. A system in which the CPU and Scatter DMA share a cache, characterized in that, It includes a CPU, a cache, a ScatterDMA, and a cache consistency management module, wherein the cache consistency management module is connected to the CPU, the ScatterDMA, and the cache; The CPU initiates storage access requests to the Cache; the Cache stores data lines and associated management information; the Scatter DMA initiates access requests to main memory addresses; and the Cache consistency management module, as described in claim 8 or 9, maintains data consistency between the Cache module and the Scatter DMA via hardware.