A mapping table caching method and device

Abstract

A cache method and device of a mapping table, the exemplary embodiment includes two or more granularity logical address range, based on the access data including access frequency, access time and access mode to calculate the heat score of logical address range, according to the calculated heat score to distinguish the heat of the L2P mapping table corresponding to the query logical address; based on the available DRAM size and workload to dynamically divide the full DRAM area and the DRAM less area, in the determined full DRAM area, cache the L2P mapping table corresponding to the preset number of logical address range with the highest heat score, cache the L2P mapping table corresponding to the remaining logical address range in the DRAM less area, so as to cache the L2P mapping table corresponding to the logical address range with high heat score such as high frequency access, recent access and random access in the full DRAM area, cache the L2P mapping table corresponding to the remaining logical address range in the DRAM less area, to provide support for improving the search efficiency of L2P mapping table.

Description

Technical Field

[0001] This article relates to solid-state drive (SSD) storage technology, and more particularly to a method and apparatus for caching a mapping table. Background Technology

[0002] With the development of solid-state drive (SSD) technology, the management of logical address to physical address (L2P) mapping tables has become a key factor affecting SSD performance.

[0003] L2P mapping table management methods in related technologies include: Host Memory Buffer (HMB) scheme, Dynamic Random Access Memory (DRAM) scheme, DRAM-less scheme, and Partial DRAM scheme. Among them, the HMB scheme relies on host memory resources, and its performance is affected when the host system load is high. It requires host support, has compatibility issues, and its performance is affected when the host system load is high. Accessing host memory via PCIe will consume PCIe bandwidth. In addition, it requires host operating system support, and some older systems may not support it. HMB technology originates from the NVMe protocol specification and is defined by the NVM Express organization. When the host initializes the SSD, the SSD controller requests HMB memory from the host as the L2P table storage area. The all-DRAM solution uses a large-capacity DRAM as a complete cache for the L2P mapping table. During SSD initialization, the L2P table is loaded from NAND to DRAM, and read / write requests are handled directly in DRAM for lookup and modification. However, the large DRAM capacity increases SSD cost and power consumption, limiting further capacity increases. In the all-DRAM scenario, there is a lack of hardware-level L2P table access acceleration mechanisms, and the need for significant DRAM resources results in high costs. The DRAM-less solution is a low-cost SSD design with no dedicated DRAM, using only a small amount of SRAM. The L2P table is stored in NAND flash memory. When handling read / write requests, the SRAM cache is checked; if a cache miss occurs, the L2P table entry is read from NAND to SRAM. When updating the L2P table, the SRAM cache is updated first, and then the data is written back to NAND. The DRAM-less solution requires complex cache management strategies, resulting in a complex L2P table management mechanism, less optimized swap-in / swap-out strategies, high random read / write latency, and unstable performance. Especially during intensive random access, frequent L2P table reads increase NAND wear. While low-cost, performance is limited. Partial DRAM solutions balance cost and performance by caching some L2P table entries in limited DRAM, but still have the following problems: 1) In full DRAM scenarios, there is a lack of hardware-level L2P table access acceleration mechanisms; 2) In DRAM-less scenarios, the L2P table management mechanism is complex, the swap-in / swap-out strategy is not optimized, random read / write latency is high, and performance is unstable, especially during intensive random access; 3) The logical address region partitioning strategy is fixed and cannot be dynamically adjusted according to the actual workload, nor can it intelligently adjust the region partitioning according to the access frequency and access mode; 4) It depends on host memory resources, performance is affected when the host system load is high, it requires host support, has compatibility issues, and consumes PCIe bandwidth.

[0004] In summary, L2P mapping table management in related technologies struggles to achieve a balance between performance and cost. Summary of the Invention

[0005] This application provides a method for caching a mapping table, including: The access data for each logical address range is determined according to a preset period. The logical address range has two or more granularities. The access data includes: access frequency, access time and access mode. The access mode includes random access and sequential access. Calculate a heat score for each logical address range based on the determined access data; The calculated popularity scores are sorted, and the L2P mapping tables corresponding to the logical address ranges with the highest popularity scores are cached in the full DRAM region. The L2P mapping tables corresponding to the remaining logical address ranges are cached in the DRAMless region. The size of the full DRAM region is determined based on the available DRAM size and workload, and the preset number is determined based on the storage size of the full DRAM region.

[0006] On the other hand, embodiments of this application also provide a caching device for a mapping table, including: an access monitoring module, a heat analysis module, and a region management module; wherein, The access monitoring module is set to determine the access data for each logical address range according to a preset period. The logical address range has two or more granularities. The access data includes: access frequency, access time and access mode. The access mode includes random access and sequential access. The popularity analysis module is set to calculate a popularity score for each logical address range based on the determined access data; The region management module is configured to: sort the calculated popularity scores, cache the L2P mapping tables corresponding to the logical address ranges with the highest popularity scores in the full DRAM region, and cache the L2P mapping tables corresponding to the remaining logical address ranges in the DRAM less region. The size of the full DRAM region is determined based on the available DRAM size and workload, and the preset number is determined based on the storage size of the full DRAM region.

[0007] This exemplary embodiment calculates a heat score for logical address ranges containing two or more granularities based on access data including access frequency, access time, and access pattern. The calculated heat score is used to differentiate the heat of querying the L2P mapping table corresponding to the logical address. Based on available DRAM size and workload, a full DRAM region and a DRAM less region are dynamically divided. A preset number of L2P mapping tables corresponding to the logical address ranges with the highest heat scores are cached in the determined full DRAM region. The remaining L2P mapping tables corresponding to logical address ranges are cached in the DRAM less region. This provides support for improving the lookup efficiency of L2P mapping tables by caching L2P mapping tables corresponding to logical address ranges with high heat scores (such as high-frequency access, recent access, and random access) in the full DRAM region and caching L2P mapping tables corresponding to the remaining logical address ranges in the DRAM less region.

[0008] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0009] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0010] Figure 1 This is a flowchart of a caching method for a mapping table according to an embodiment of this disclosure; Figure 2 This is a structural block diagram of the caching device for the mapping table in an embodiment of this disclosure; Figure 3 This is a schematic diagram of the hardware architecture of an embodiment of this disclosure; Figure 4 This is a schematic diagram showing the composition and connection of the L2P mapping acceleration module according to an embodiment of this disclosure; Figure 5 This is a schematic diagram showing the composition and connection of the multi-level mapping table management module in an embodiment of this disclosure; Figure 6 This is a schematic diagram illustrating the relationship between the multi-level mapping tables in an embodiment of this disclosure; Figure 7 This is a schematic diagram of the swap-in and swap-out process of the L2P mapping table in an embodiment of this disclosure; Figure 8 This is a schematic diagram of the L2P lookup process according to an embodiment of this disclosure; Figure 9 This is a schematic diagram of the L2P update process according to an embodiment of this disclosure. Detailed Implementation

[0011] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0012] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0013] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0014] Figure 1 This is a flowchart of the caching method for the mapping table in an embodiment of this disclosure, as follows: Figure 1 As shown, it includes: Step 101: Determine the access data for each logical address range according to a preset period. The logical address range has two or more granularities. The access data includes: access frequency, access time and access mode. The access mode includes random access and sequential access. Step 102: Calculate the heat score for each logical address range based on the determined access data; Step 103: Sort the calculated popularity scores, cache the L2P mapping table corresponding to the logical address range with the highest popularity score in the full DRAM region, and cache the L2P mapping table corresponding to the remaining logical address range in the DRAM less region. The size of the full DRAM region is determined according to the available DRAM size and workload, and the value of the preset number is determined according to the storage size of the full DRAM region.

[0015] This exemplary embodiment calculates a heat score for logical address ranges containing two or more granularities based on access data including access frequency, access time, and access pattern. The calculated heat score is used to differentiate the heat of querying the L2P mapping table corresponding to the logical address. Based on available DRAM size and workload, a full DRAM region and a DRAM less region are dynamically divided. A preset number of L2P mapping tables corresponding to the logical address ranges with the highest heat scores are cached in the determined full DRAM region. The remaining L2P mapping tables corresponding to logical address ranges are cached in the DRAM less region. This provides support for improving the lookup efficiency of L2P mapping tables by caching L2P mapping tables corresponding to logical address ranges with high heat scores (such as high-frequency access, recent access, and random access) in the full DRAM region and caching L2P mapping tables corresponding to the remaining logical address ranges in the DRAM less region.

[0016] In one exemplary embodiment, the calculated popularity scores are sorted, and the L2P mapping tables corresponding to the logical address ranges with the highest popularity scores are cached in the full DRAM region. The remaining L2P mapping tables corresponding to the logical address ranges are then cached in the DRAM less region. The caching method further includes: Generate region boundary information based on the cache location of the L2P mapping table; The L2P mapping table is accessed based on the generated region boundary information, and the access process includes lookup and update.

[0017] In one exemplary embodiment, the popularity score consists of two or more scoring items. Each scoring item is calculated from one or more access data. When the access data used to calculate the scoring item includes access frequency, the higher the access frequency, the larger the scoring item. When the access data used to calculate the scoring item includes access time, the closer the access time is to the time when the popularity score is calculated, the larger the scoring item. When the access data used to calculate the scoring item includes access pattern, the value of the scoring item for random access is greater than the value of the scoring item for sequential access.

[0018] In one exemplary embodiment, random access is defined as the offset between consecutive logical addresses being greater than a preset offset threshold; a high heat score is equivalent to a high priority, and this exemplary embodiment preferentially retains the L2P mapping table of the high-priority logical address range in the entire DRAM region.

[0019] In one exemplary embodiment, the popularity score is calculated based on the following formula: Popularity rating = ×(Access Frequency × Time Decay Factor) + × Access mode factor; in: Weighting coefficients for access frequency The weighting coefficient for the access mode. and satisfy The time decay factor is , It is the attenuation constant. The time difference since the last access (in seconds); the access mode factor is a pre-set access weight, with random access having a greater access weight than sequential access.

[0020] In one exemplary embodiment, , , The access weights for random access and sequential access can be set and adjusted through the CPU configuration registers. For example, the access weights can be set to: It is 0.8. It is 0.2. The value range is 0.001-0.01, and can be set to 0.01. The access frequency is the number of accesses within the most recent preset unit of time. The sequential access weight is 1.0, and the random access weight is 0.

[0021] In one exemplary embodiment, the caching method further includes: Before accessing the L2P mapping table based on the generated region boundary information, configure the DRAM interface bus of the full DRAM region and the SRAM interface bus of the DRAM less region to use burst transmission mode for data transmission, and set the amount of data the host can read at one time according to the bus bandwidth of the DRAM interface bus and the amount of data the host can read at one time according to the bus bandwidth of the SRAM interface bus. When accessing the L2P mapping table based on the generated region boundary information, the I / O read / write commands from the host and the L2P mapping table lookup are stored in predetermined registers.

[0022] This exemplary embodiment employs burst transmission mode for both the DRAM and SRAM interface buses, allowing for the reading of 256 bits of data from DRAM at a time and 128 bits of data from the DRAM less area (SRAM) at a time. This effectively reduces the command overhead and latency of memory access. In this exemplary embodiment, when the host inputs I / O read / write commands to query the L2P mapping table, the I / O read / write commands and the retrieved L2P mapping table are stored in registers. Register access latency is significantly lower than memory access latency, resulting in more pipelined I / O command processing.

[0023] In this exemplary embodiment, the registers are accessed through the DTCM (Data Tightly-Coupled Memory) interface, which has extremely low access latency compared to traditional memory interfaces in related technologies.

[0024] In one exemplary embodiment, the caching method further includes: Modify the L2P mapping table in DRAM or SRAM through registers; The L2P mapping tables corresponding to logical address ranges with popularity scores exceeding a pre-set score threshold are preloaded and cached.

[0025] In one exemplary embodiment, the caching method further includes processing the L2P mapping table of the DRAM less region as follows: Determine the available cache area in SRAM, and write the L2P mapping table of the most recently accessed and written preset amount (set by technical personnel, for example 32K) into the cache table CT that is pre-established in the available cache area. Each CT entry stores the physical address information and corresponding logical address information of an L2P mapping table, as well as the CT index of the L2P mapping table. The logical address information in the written CT entry is hashed to generate the LT index (LT idx) of the linked table of the CT entry. The LT index and CT index of the CT entry are stored in the pre-established linked table LT. The LT index and CT index of the CT entry are in a corresponding relationship. Based on the logical address information in the I / O read / write command when the host accesses the L2P mapping table, the LT index corresponding to the I / O read / write command is determined. After determining the corresponding CT index in the LT based on the LT index, the CT entry in the CT is accessed based on the determined CT index, and the physical address information corresponding to the logical address information is obtained based on the accessed CT entry. The SRAM contains a pre-created flush list, and the CT index is stored in the flush list.

[0026] In this exemplary embodiment, the CT index is requested on demand from a natural sequence pool (e.g., 32K natural sequences). Each L2P mapping table contains a unique CT index. The flush list can be created when the host writes the L2P mapping table to the DRAM less area. After writing each CT entry, the ST index is determined based on the logical address information in the CT entry. Then, this CT index is simultaneously updated to the CT table sequence number in the ST and the flush list. Similarly, the CT table sequence number in the ST serves as the head of the flush list. The flush list can be traversed using this CT table sequence number to obtain all L2P mapping table information to be written to the NAND. This exemplary embodiment records the least recently used CT entries using the LRU algorithm. Specifically, after writing CT entries to the CT in the available cache area, the least recently used CT entries are recorded by updating the information in the LRU list.

[0027] In one exemplary embodiment, when performing a hash calculation on the logical address information in the written CT entry to generate the CT entry linked table LT index, the caching method further includes: Determine whether the calculated LT index has a hash collision with an existing (previously generated) LT index in LT; When the calculated LT index has a hash collision with an existing LT index in LT, the CT index corresponding to the existing LT index that has the collision is stored in the pre-created hash collision list in sequence, and the CT index corresponding to the calculated LT index is stored in the refresh list.

[0028] In this exemplary embodiment, when hash calculations are performed using different logical address information, hash collisions may occur due to the randomness of the hash algorithm itself. Therefore, in the event of a hash collision, the CT indices corresponding to the previously stored conflicting LT indices are sequentially stored in a hash collision list. The CT indices corresponding to the calculated LT indices are stored in a refresh list. During host access, the newly stored CT indices in the refresh list can be prioritized for matching, satisfying the scenario characteristic that L2P lookup generally searches the most recently accessed L2P mapping table first. In this exemplary embodiment, the hash collision list is stored in SRAM. The CT index stored in the LT corresponds to the head of the hash collision list when a hash collision occurs at that LT index. With the list head information, all collision information can be obtained by traversing the list.

[0029] In one exemplary embodiment, when the host accesses the L2P mapping table but misses, the corresponding L2P mapping table is read from the NAND according to the I / O read / write command, and the read L2P mapping table is written into the available cache area as the most recently accessed L2P mapping table. At the same time, the L2P mapping table with the least recently used CT entry is swapped out using the LRU algorithm and written to the flash memory.

[0030] In one exemplary embodiment, the aforementioned I / O read / write command can be generated based on the access request issued by the host. The NAND can be read based on the ST PCA in the ST to obtain the complete L2P mapping table within the logical address range corresponding to the LCA of the I / O read / write command. The least recently used CT entry is recorded using the LRU algorithm; specifically, after writing a CT entry into the available cache area's CT, the information in the LRU list is updated to record the least recently used CT entry. In one exemplary embodiment, the order in which CT entries are used can also be determined using methods including a stack; this exemplary embodiment does not limit this approach.

[0031] In one exemplary embodiment, before determining an available cache region in SRAM and writing the recently accessed and written L2P mapping table into the available cache region, the caching method further includes: Determine whether the CT index of the L2P mapping table storing the DRAM less area in the refresh list has reached the preset processing threshold; When the CT index of the L2P mapping table storing the DRAM less region in the flush list reaches the preset processing threshold, the L2P mapping table corresponding to the CT index is written to the NAND flash memory. The status information of the L2P mapping table of the DRAM less region is recorded by the pre-established slice table ST. The status information includes the following for each logical address range: ST index, CT index of the last L2P mapping table written in the logical address range (recording the head information of the flush list), physical address information of all L2P mapping tables written in the NAND flash memory in the logical address range, and ST index is the logical address range information.

[0032] In one exemplary embodiment, the caching method further includes: When the proportion of cached areas occupied exceeds a preset threshold, the least used CT entries of a preset percentage are swapped out of the cache to flash memory. The most recently accessed and written L2P mapping table is then rewritten into the available cache area using the LRU algorithm based on ST.

[0033] The preset percentage in this exemplary embodiment can be a value between 70% and 100%, which can be configured and adjusted by technicians according to data processing efficiency and resource usage; the amount of data swapped out to flash memory is theoretically equal to the amount of data swapped into the available cache area.

[0034] This disclosure also provides a computer storage medium storing a computer program, which, when executed by a processor, implements the above-described caching method for the mapping table.

[0035] This disclosure also provides a terminal, including: a memory and a processor, wherein the memory stores a computer program; wherein, The processor is configured to execute computer programs in memory; When a computer program is executed by a processor, a caching method for a mapping table as described above is implemented.

[0036] Figure 2 The following is a structural block diagram of the caching device for the mapping table in an embodiment of this disclosure, as shown below. Figure 2 As shown, it includes: an access monitoring module, a popularity analysis module, and a region management module; among which, The access monitoring module is set to determine the access data for each logical address range according to a preset period. The logical address range has two or more granularities. The access data includes: access frequency, access time and access mode. The access mode includes random access and sequential access. The popularity analysis module is set to calculate a popularity score for each logical address range based on the determined access data; The region management module is configured to: sort the calculated popularity scores, cache the L2P mapping tables corresponding to the logical address ranges with the highest popularity scores in the full DRAM region, and cache the L2P mapping tables corresponding to the remaining logical address ranges in the DRAM less region. The size of the full DRAM region is determined based on the available DRAM size and workload, and the preset number is determined based on the storage size of the full DRAM region.

[0037] In one exemplary embodiment, the popularity score is calculated based on the following formula: Popularity rating = ×(Access Frequency × Time Decay Factor) + × Access mode factor; in: Weighting coefficients for access frequency The weighting coefficient for the access mode. and satisfy The time decay factor is , It is the attenuation constant. The access mode factor is the time difference between the accessed logical address range and the last access, in seconds; the access mode factor is the access weight of the pre-set access mode, with random access having a greater access weight than sequential access.

[0038] In one exemplary example, the caching device further includes an access module, which includes access units configured as follows: Generate region boundary information based on the cache location of the L2P mapping table; The L2P mapping table is accessed based on the generated region boundary information, and the access process includes lookup and update.

[0039] In one exemplary example, the access module also includes an acceleration unit configured as follows: Before accessing the L2P mapping table based on the generated region boundary information, configure the DRAM interface bus of the full DRAM region and the SRAM interface bus of the DRAM less region to use burst transmission mode for data transmission, and set the amount of data the host can read at one time according to the bus bandwidth of the DRAM interface bus and the amount of data the host can read at one time according to the bus bandwidth of the SRAM interface bus. When accessing the L2P mapping table based on the generated region boundary information, the I / O read / write commands from the host and the L2P mapping table lookup are stored in predetermined registers.

[0040] In one exemplary example, the acceleration unit is further configured as follows: Modifying the L2P mapping table in DRAM or SRAM via registers; and / or, The L2P mapping tables corresponding to logical address ranges with popularity scores exceeding a pre-set score threshold are preloaded and cached.

[0041] In one exemplary example, the cache device further includes a multi-level mapping table management module configured to perform the following processing on the L2P mapping table of the DRAM less region: Determine the available cache area in SRAM, and write the preset amount of L2P mapping table that has been recently accessed and written to the cache table CT that has been pre-established in the available cache area. Each CT entry stores the physical address information and corresponding logical address information of an L2P mapping table, as well as the CT index of the L2P mapping table. The logical address information in the written CT entry is hashed to generate the LT index of the CT entry linked table. The LT index and CT index of the CT entry are stored in the pre-established linked table LT. The LT index and CT index of the CT entry are in a corresponding relationship. Based on the logical address information in the I / O read / write command when the host accesses the L2P mapping table, the LT index corresponding to the I / O read / write command is determined. After determining the corresponding CT index in the LT based on the LT index, the CT entry in the CT is accessed based on the determined CT index, and the physical address information corresponding to the logical address information is obtained based on the accessed CT entry. The SRAM contains a pre-created refresh list, and the CT index is stored in the refresh list.

[0042] This exemplary embodiment can request space from SRAM in advance to store CT entries before writing the preset amount of recently accessed and written L2P mapping table into the pre-established cache table CT in the available cache area using the LRU algorithm.

[0043] In one exemplary example, the multi-level mapping table management module is also configured as follows: Determine whether the calculated LT index has a hash collision with the LT index already stored in LT; When the calculated LT index has a hash collision with an existing LT index in LT, the CT index corresponding to the existing LT index that has the collision is stored in the pre-created hash collision chain list in sequence, and the CT index corresponding to the calculated LT index is stored in the refresh chain list.

[0044] In one exemplary example, the multi-level mapping table management module is also configured as follows: When the host accesses the L2P mapping table but misses, the corresponding L2P mapping table is read from the NAND according to the host's I / O read / write command for accessing the L2P mapping table. The read L2P mapping table is then written into the cache as the most recently accessed L2P mapping table. At the same time, the LRU algorithm is used to determine the least recently used CT entry, and the L2P mapping table in the determined CT entry is written to the flash memory.

[0045] In one exemplary example, the multi-level mapping table management module is also configured as follows: Determine whether the number of CT indexes stored in the refresh list has reached a preset processing threshold; When the CT index stored in the refresh list reaches the preset processing threshold, the L2P mapping table corresponding to the CT index is written to the NAND flash memory, and the status information of the L2P mapping table of the DRAM less area is recorded through the pre-established slice table ST. The status information includes the following for each logical address range: ST index, CT index of the last L2P mapping table written within the logical address range, and physical address information of all L2P mapping tables written to the NAND flash memory within the logical address range. The ST index is the logical address range information.

[0046] In one exemplary example, the multi-level mapping table management module is also configured as follows: When the proportion of available cache area occupied exceeds a preset threshold, the preset percentage of the least used CT entries are swapped out of the cache to flash memory, and the most recently accessed and written L2P mapping table is rewritten to the available cache area according to ST.

[0047] The following application examples briefly illustrate the embodiments of this disclosure. These application examples are only used to illustrate the embodiments of this disclosure and are not intended to limit the scope of protection of the embodiments of this disclosure.

[0048] Application Examples This exemplary embodiment of the caching method can be implemented based on a certain hardware architecture. Figure 3 This is a schematic diagram of the hardware architecture of an embodiment of this disclosure, as shown below. Figure 3 As shown, the hardware architecture may include: The host (CPU in the diagram) outputs an access request to the L2P mapping acceleration module, having accessed the L2P mapping table from both the full DRAM region and the DRAM less region. The L2P mapping acceleration module receives host access requests and is responsible for looking up and updating the L2P table, as well as dynamic region partitioning and adjustment, i.e., dynamically adjusting the size and range of the full DRAM region and the DRAM less region; see also Figure 4 The L2P mapping acceleration module includes an access module containing an access unit and an acceleration unit, and the access module is connected to the access monitoring module. Multi-level mapping table management module: responsible for swapping in and out of the LT, ST, CT cache tables in the DRAM less area and the L2P table in the DRAM less area, as well as the pre-allocation of CT entries; SRAM cache controller: manages SRAM access; DRAM controller: Manages DRAM access; NAND controller: Manages NAND flash memory access.

[0049] The registers include control and status registers. The L2P mapping table obtained by the L2P mapping acceleration module can be queried through the registers, or the L2P mapping acceleration module can update the L2P mapping table by configuring the registers.

[0050] The logical address range of this exemplary embodiment can be configured to be 64KB, 512KB, 1MB, etc.; in addition, this exemplary embodiment can use a sliding window statistics method to determine whether the current access mode is random access (the offset between consecutive access logical addresses is large, such as ≥64KB) or sequential access (the offset between consecutive access logical addresses is small, such as <64KB). Table 1 is a schematic table of access data of this exemplary embodiment. As shown in Table 1, the access frequency is recorded by the number of accesses, and the access time is recorded based on the last access timestamp.

[0051] Table 1 This exemplary embodiment can configure a data storage module in SRAM to store: access data, popularity scores, and region boundary information; after calculating the popularity score, this exemplary embodiment stores the popularity score in the data storage module inside the SRAM, and the popularity scores are shown in Table 2.

[0052] Table 2 Suppose there are two logical address ranges A and B. Address A had 100 sequential accesses 5 minutes ago and no recent accesses. Address B had 50 random accesses 1 minute ago. It is 0.8. It is 0.2. The weight is 0.01, the sequential access weight is 1.0, and the random access weight is 0. After time decay and access pattern weighting: The heat score for logical address range A can be calculated as: 0.8 * 100 * e^(-0.01×300) + 0.2 * 1.0 ≈ 80 × 0.05 + 0.2 = 4.2; the heat score for logical address range B is: 0.8 * 50 * e^(-0.01×60) + 0.2 * 2.0 ≈ 40 × 0.55 + 0.4 = 22.4. Based on the above calculations, although logical address range A has a higher total number of accesses, its heat score is lower than that of logical address range B, which has recent random accesses, due to the longer time frame and the sequential nature of the accesses. This aligns with the caching requirements in practical applications, as recent random accesses require more caching support.

[0053] After calculating the popularity score, the region management module sorts the calculated popularity scores, caches the L2P mapping table corresponding to the logical address range with the highest popularity score in the full DRAM region, and caches the L2P mapping table corresponding to the remaining logical address range in the DRAM less region. After the adjustment is completed, the region boundary information is recorded in the data storage module. The region boundary information is shown in Table 3.

[0054] Table 3 In this exemplary embodiment, the region management module transmits region boundary information to the access unit, acceleration unit, and multi-level mapping table management module, enabling these units or modules to determine which logical address ranges are in the full DRAM region and which are in the DRAM less region.

[0055] This exemplary embodiment of the multi-level mapping table module achieves efficient L2P management in the DRAM less area through multi-level mapping tables such as LT, ST, and CT, pre-allocation, and Least Recently Used (LRU) mechanisms. This exemplary embodiment of the multi-level mapping table module sets up several units to respectively implement LT, ST, CT, Flush list, LRU, hash calculation, and processing of pre-allocating space to store CT entries in SRAM. The composition and connection of the multi-level mapping table management module are as follows: Figure 5 As shown.

[0056] Figure 6 This is a schematic diagram illustrating the relationship between the multi-level mapping tables in an embodiment of this disclosure, such as... Figure 6 As shown, the relationship between LT, ST, and CT is as follows: the CT table sequence number in LT and ST is the CT index; ST PCA represents the physical address information of the L2P mapping table written in flash memory within the logical address range corresponding to the ST index; LCA and PCA in CT are the logical address information and physical address information in L2P; the hash collision list is formed based on the hash collision ptr (pointer) in the figure; and the flush list is formed based on the flush ptr in the figure.

[0057] Figure 7 This is a schematic diagram of the swap-in and swap-out process of the L2P mapping table in this embodiment of the present disclosure. When the L2P mapping table is not accessed, the L2P mapping table is read from NAND to CT, and the most recently accessed L2P mapping table is swapped in first. The LRU algorithm is used to select the L2P table entries to be swapped out. When the CT reaches the capacity threshold, the table entries of the L2P mapping table that have not been used for the longest time are swapped out in batches. This exemplary embodiment sets a preset ratio threshold. When the preset ratio threshold is exceeded, batch swap-in and swap-out are performed.

[0058] Figure 8 This is a schematic diagram of the L2P lookup process according to an embodiment of the present disclosure, such as... Figure 8As shown, the L2P mapping acceleration module receives host access requests from the host, i.e., logical address access requests. It determines whether the logical address range to which the logical address information belongs is located in the entire DRAM region. If the logical address range to which the logical address information belongs is located in the entire DRAM region, it directly looks up the physical address information from the L2P mapping table in the entire DRAM. If the logical address range to which the logical address information belongs is not located in the entire DRAM region, it queries in the DRAM less region: the hash calculation unit calculates the LT index based on the LCA, queries the LT to obtain the CT index, and at the same time, the LRU management unit sets the CT entry as the Most Recently Used (MRU) entry. It accesses the CT and Hash collision list through the CT index to obtain the PCA that matches the LCA. If the CT does not match, it queries the mapping information stored in the NAND through the ST slice table where the LCA is located and loads the query result into the CT.

[0059] Figure 9 This is a schematic diagram of the L2P update process according to an embodiment of this disclosure, such as... Figure 9 As shown, the L2P mapping acceleration module receives write requests from the host and determines whether the logical address in the logical address information is located in the full DRAM region. If the logical address in the logical address information is located in the full DRAM region, the L2P mapping table in the full DRAM is directly updated. If the logical address in the logical address information is not located in the full DRAM region, it is updated in the DRAM less region: the hash calculation unit calculates the LT index based on the LCA, queries the LT to obtain the CT index, and accesses the CT through the CT index; if there is an old CT entry in the CT, the new LCA and PCA are written to the CT table; if there is no old entry, a new CT entry is taken from the pre-allocation module, and then the LCA and PCA are written to the CT; the LRU management unit sets the CT entry as an MRU entry; the Flush list is updated, and if there is a hash collision, the Hashcollision list also needs to be updated; the CT index in the LT table is updated; when the CT entries reach the threshold, the LCA-PCA information in the CT entry is written to the NAND flash memory according to the Flush list, and the ST PCA information of the corresponding entry in the ST table is updated.

[0060] This exemplary embodiment combines the high performance of full DRAM with the low cost of DRAM-less. It employs a dynamic region partitioning strategy, automatically adjusting the size and range of the full DRAM and DRAM-less regions based on actual workload. Simultaneously, in full DRAM scenarios, it provides hardware acceleration for L2P mapping table access. By predicting future L2P entry demands based on access patterns and prefetching them, it improves the access speed of the L2P mapping table. Efficient L2P management is achieved through multi-level mapping tables such as LT (Link Table), ST (Slice Table), and CT (Cache Table), improving SSD performance while avoiding the host dependency issues of HMB solutions. Entry swapping management based on access frequency and access patterns optimizes cache hit rate.

[0061] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A method for caching a mapping table, characterized in that, include: The access data for each logical address range is determined according to a preset period. The logical address range has two or more granularities. The access data includes: access frequency, access time and access mode. The access mode includes random access and sequential access. Calculate a heat score for each logical address range based on the determined access data; The calculated popularity scores are sorted, and the L2P mapping tables corresponding to the logical address ranges with the highest popularity scores are cached in the full DRAM region. The L2P mapping tables corresponding to the remaining logical address ranges are cached in the DRAM less region. The size of the full DRAM region is determined based on the available DRAM size and workload, and the preset number is determined based on the storage size of the full DRAM region.

2. The caching method according to claim 1, characterized in that, The method of sorting the calculated popularity scores, caching the L2P mapping tables corresponding to the logical address ranges with the highest popularity scores in the full DRAM region, and caching the L2P mapping tables corresponding to the remaining logical address ranges in the DRAM less region, further includes: Generate region boundary information based on the cache location of the L2P mapping table; The L2P mapping table is accessed based on the generated region boundary information, wherein the access process includes lookup and update.

3. The caching method according to claim 1, characterized in that, The popularity score is calculated based on the following formula: Popularity rating = ×(Access Frequency × Time Decay Factor) + × Access mode factor; in: The weighting coefficient for the access frequency, The weighting coefficient for the access mode. and satisfy The time decay factor is , The attenuation constant is The access time factor is the time difference between the access logical address range determined based on the access time information and the last access, in seconds; the access mode factor is the access weight of the pre-set access mode, where the access weight of random access is greater than the access weight of sequential access.

4. The caching method according to claim 1, characterized in that, The caching method further includes: Before performing L2P mapping table access processing based on the generated region boundary information, the DRAM interface bus of the full DRAM region and the SRAM interface bus of the DRAM less region are configured to use burst transmission mode for data transmission, and the amount of data read by the host at one time is set according to the bus bandwidth of the DRAM interface bus and the amount of data read by the host at one time is set according to the bus bandwidth of the SRAM interface bus. When accessing the L2P mapping table based on the generated region boundary information, the I / O read / write commands from the host and the looked-up L2P mapping table are stored in a predetermined register, which is accessed through the DTCM interface.

5. The caching method according to claim 4, characterized in that, The caching method further includes: The L2P mapping table is modified through the register; The L2P mapping tables corresponding to the logical address ranges whose popularity scores are greater than a preset score threshold are preloaded and cached.

6. The caching method according to any one of claims 1 to 5, characterized in that, The DRAM less region includes NAND flash memory and SRAM, and the caching method further includes performing the following processing on the L2P mapping table of the DRAM less region: Determine the available cache area in the SRAM, and write the preset amount of L2P mapping table that has been recently accessed and written to the cache table CT that has been pre-established in the available cache area. Each CT entry stores the physical address information and corresponding logical address information of an L2P mapping table, as well as the CT index of the L2P mapping table. The logical address information in the written CT entry is hashed to generate the linked table LT index of the CT entry, and the LT index and CT index of the CT entry are stored in the pre-established linked table LT. The LT index and CT index of the CT entry are in a corresponding relationship. Based on the logical address information in the I / O read / write command when the host accesses the L2P mapping table, the LT index corresponding to the I / O read / write command is determined. After determining the corresponding CT index in the LT based on the LT index, the CT entry in the CT is accessed based on the determined CT index, and the physical address information corresponding to the logical address information is obtained based on the accessed CT entry. The SRAM contains a pre-created refresh list, and the CT index is stored in the refresh list.

7. The caching method according to claim 6, characterized in that, When performing hash calculation on the logical address information in the written CT entry to generate the linked table LT index of the CT entry, the caching method further includes: Determine whether the calculated LT index has a hash collision with the LT index already stored in LT; When the calculated LT index has a hash collision with an existing LT index in LT, the CT index corresponding to the existing LT index that has the collision is stored sequentially in a pre-created hash collision chain list, and the CT index corresponding to the calculated LT index is stored in a refresh chain list.

8. The caching method according to claim 6, characterized in that, The caching method further includes: When the host accesses the L2P mapping table but misses, the corresponding L2P mapping table is read from the NAND according to the host's I / O read / write command for accessing the L2P mapping table. The read L2P mapping table is then written into the available cache area as the most recently accessed L2P mapping table. At the same time, the LRU algorithm is used to determine the least recently used CT entry, and the L2P mapping table in the determined CT entry is written to the flash memory.

9. The caching method according to claim 6, characterized in that, Before determining the available cache area in SRAM and writing the L2P mapping table of the most recently accessed and written data to the pre-established cache table CT in the available cache area, the caching method further includes: Determine whether the number of CT indexes stored in the refresh list has reached a preset processing threshold; When the number of CT indexes stored in the refresh list reaches the processing threshold, the L2P mapping table corresponding to the CT index is written into the NAND, and the status information of the L2P mapping table of the DRAM less region is recorded through the pre-established slice table ST. The status information includes the following for each logical address range: ST index, CT index of the last L2P mapping table written within the logical address range, and physical address information of all L2P mapping tables written in the NAND flash memory within the logical address range. The ST index is logical address range information.

10. The caching method according to claim 6, characterized in that, The caching method further includes: When the proportion of the available cache area occupied is greater than a preset threshold, the preset percentage of the least used CT entries are swapped out of the available cache area to flash memory, and the recently accessed and written L2P mapping table is rewritten into the available cache area according to ST.

11. A caching device for a mapping table, characterized in that, include: Access monitoring module, popularity analysis module, and area management module; among them, The access monitoring module is set to determine the access data for each logical address range according to a preset period. The logical address range has two or more granularities. The access data includes: access frequency, access time and access mode. The access mode includes random access and sequential access. The popularity analysis module is set to calculate a popularity score for each logical address range based on the determined access data; The region management module is configured to: sort the calculated popularity scores, cache the L2P mapping tables corresponding to the logical address ranges with the highest popularity scores in the full DRAM region, and cache the L2P mapping tables corresponding to the remaining logical address ranges in the DRAM less region. The size of the full DRAM region is determined based on the available DRAM size and workload, and the preset number is determined based on the storage size of the full DRAM region.

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