Notebook cache management device, system and general processor

Abstract

The application provides a note cache management device, system and general processor. The device comprises: an address mapping table configured to store a mapping relationship between a virtual address of a process and a physical address of a note cache; an address access table configured to record address range information accessed by a process currently using the note cache; an allocation logic unit configured to: in response to executing a note cache allocation instruction, establish a table entry in the address mapping table; and in response to executing a note cache release instruction, invalidate a corresponding table entry in the address mapping table and invalidate a record associated with the corresponding table entry in the address access table; and an access logic unit configured to: in response to executing a note cache access instruction, perform a legality check on an access address according to a mapping relationship stored in the address mapping table, perform a read / write operation of the note cache after passing, and mark an address range corresponding to the present access in the address access table.

Description

Technical Field

[0001] This application relates to the field of general-purpose processor technology, and in particular to a note-style cache management device, system and general-purpose processor. Background Technology

[0002] With the widespread adoption of neural network artificial intelligence applications such as deep learning and neuromorphic computing, increasingly higher demands are being placed on the intelligent computing acceleration capabilities of processors. Generally speaking, Graphics Processing Units (GPUs) and dedicated Neural Processing Units (NPUs) are more suitable for accelerating various neural network calculations compared to general-purpose processors (CPUs). In the hardware architecture design of GPUs and NPUs, on-chip scratchpad memory (SPM), which is directly addressed by software instructions, is typically used to store frequently used data or intermediate calculation results during the computation process. Specifically, software loads data from slower off-chip memory (such as DRAM) into the faster SPM for computation via instructions, or writes data from the SPM back to DRAM via software instructions.

[0003] In contrast, general-purpose processors typically use a fast cache that is automatically controlled by hardware and transparent to software to store frequently accessed data. That is, when software accesses data on slow storage components (such as DRAM), the cache can automatically cache the accessed data and perform functions such as lookup and replacement, without requiring dedicated software instructions to manage the data in the cache.

[0004] For intelligent computing tasks such as neural networks, SPM has the following advantages over Cache: (1) It can eliminate the hardware circuitry for automatic lookup and replacement in Cache, thereby saving chip area; (2) Software can precisely control which data resides in the cache and which should be replaced, thereby maximizing the utilization efficiency of on-chip cache, reducing the number of accesses to slow storage (such as DRAM), improving computing performance and reducing power consumption; (3) In some GPU and NPU designs, SPM can realize free data exchange between different computing units or processing units, avoiding the introduction of additional data exchange instructions and simplifying instruction set design. Therefore, SPM is widely used in GPU and NPU designs to maximize the computing performance of the chip.

[0005] The widespread application of artificial intelligence computing is also constantly driving the improvement and enhancement of intelligent computing capabilities in general-purpose processors. Current mainstream high-performance CPUs are continuously incorporating and enhancing vector and matrix computing capabilities to adapt to this trend. For example, Intel has designed the AVX512 vector instruction set and the AMX matrix computing instruction set in its x86 CPUs used in servers; ARM has designed the SVE, SVE2 vector instruction sets and the SME matrix computing instruction set; and RISC-V has designed the RVV vector instruction set and is actively discussing the development of a matrix computing instruction extension standard.

[0006] However, despite these CPUs' enhancements at the instruction set level for intelligent computing, they did not employ SPM (Skill Process Management) design to further improve computing performance. The main reason for this is that introducing SPM into the CPU would increase the overhead and complexity of process scheduling and switching.

[0007] Specifically, unlike GPUs and NPUs, CPUs are responsible for running the operating system and a large number of user-mode processes, far exceeding the number of physical CPU cores. Therefore, frequent scheduling and switching between the operating system kernel and various user-mode processes (hereinafter referred to as "processes") are necessary. During process switching, the CPU needs to save the context of the current process so that execution can continue when switching back to that process. Saving the process context mainly refers to saving the contents of the CPU architecture registers into memory.

[0008] Modern CPUs typically have a dozen to several dozen architecture registers, each corresponding to a process context typically ranging from tens to hundreds of bytes. As the number of architecture registers increases, the overhead of process switching (i.e., the overhead of saving and loading architecture register contents into memory) also increases. In GPUs and NPUs, the SPM (System Context) size of a single processor core is generally between tens and hundreds of kilobytes (KB). An excessively small SPM makes it difficult to store large amounts of frequently used data, impacting computational performance. However, if the CPU also uses an SPM of tens of kilobytes or more, then during process switching, the contents of the SPM must be saved to memory along with the architecture register contents, or the same amount of data must be loaded from memory. This obviously incurs significant process switching overhead, severely impacting the overall system performance and responsiveness.

[0009] Therefore, how to effectively reduce the overhead of process switching while integrating a note-style cache into the CPU has become an urgent technical problem to be solved in improving the intelligent computing capabilities of current general-purpose processors. Summary of the Invention

[0010] In view of this, this application provides a note-style cache management device, system, and general-purpose processor to solve at least one of the aforementioned problems.

[0011] To achieve the above objectives, this application adopts the following approach: According to a first aspect of this application, a note-based cache management device is provided, comprising: an address mapping table configured to store the mapping relationship between the virtual addresses of a process and the physical addresses of a note-based cache; an address access table configured to record address range information accessed by a process currently using the note-based cache; an allocation logic unit coupled to the address mapping table and the address access table, configured to: in response to executing a note-based cache allocation instruction, create an entry in the address mapping table; and in response to executing a note-based cache release instruction, invalidate the corresponding entry in the address mapping table and invalidate the record associated with the corresponding entry in the address access table; and an access logic unit coupled to the address mapping table and the address access table, configured to: in response to executing a note-based cache access instruction, perform a validity check on the accessed address according to the mapping relationship stored in the address mapping table, and perform a read / write operation on the note-based cache after the check passes; and mark the address range corresponding to the current access in the address access table.

[0012] In some embodiments of this application, each entry of the address access table includes: an allocation table number, a starting address, an offset, and a valid bit, used to record the address range accessed by the process.

[0013] In some embodiments of this application, each entry of the address access table includes: an allocation table number, an access mask, and a valid bit, used to record the address range accessed by the process.

[0014] In some embodiments of this application, when the above-mentioned access logic unit executes the note-style cache access instruction, the marking of the address access table is decoupled from the read and write operations of the note-style cache.

[0015] In some embodiments of this application, the access logic unit is further configured to, in response to an execution query instruction, return all entries of the corresponding process in the address access table based on the process information given by the query instruction.

[0016] In some embodiments of this application, when the above-mentioned allocation logic unit executes the note-style cache allocation instruction, it searches for a free entry in the address mapping table, fills the process number, starting virtual address, starting physical address and allocation size information carried by the allocation instruction into the free entry, and sets the valid bit of the free entry to true.

[0017] In some embodiments of this application, when the above-mentioned allocation logic unit executes the note-style cache release instruction, it finds the corresponding entry in the address mapping table based on the process number carried by the release instruction, invalidates all records belonging to the entry in the address access table according to the process number of the entry, and then invalidates the corresponding entry in the address mapping table.

[0018] In some embodiments of this application, the access logic unit performs a validity check on the access address by: checking whether the valid bit of the corresponding entry in the address mapping table is true, and checking whether the access address is within the range defined by the allocated starting virtual address and the allocated size.

[0019] According to a second aspect of this application, a note-based cache management system for a general-purpose processor is provided, including the note-based cache management device as described above, and: a driver unit configured to, in response to a process requesting note-based cache space, query a software space allocation table to confirm whether there is sufficient free space; if so, allocate virtual and physical addresses to the process, send a note-based cache allocation instruction to an allocation logic unit, so that the allocation logic unit establishes a corresponding entry in the address mapping table, and updates the software space allocation table after allocation; and in response to a process releasing note-based cache space or the operating system reclaiming process resources, send a note-based cache allocation instruction to the allocation logic unit. The system includes: a release instruction and a synchronized update of the software space allocation table; a scheduling unit configured to manage processes using a note-based cache, wherein the note-based cache usage status of a process includes three states: unoccupied, occupied, and suspended; and a switching unit configured to perform swap-out and loading operations. The swap-out operation includes: when the scheduling unit schedules a suspended process, obtaining the range of note-based cache addresses already accessed by the process to be swapped out from the address access table recorded by the access logic unit, and saving the corresponding content to the memory image based on the address range; the loading operation includes: loading the note-based cache content of the suspended process to be scheduled from the memory image to the note-based cache.

[0020] In some embodiments of this application, the scheduling unit is configured to: prioritize scheduling processes in an occupied state; when there are no schedulable processes in an occupied state, select the process to be scheduled from the processes in a suspended state.

[0021] In some embodiments of this application, when selecting a scheduled process from processes in a suspended state, if the remaining space of the note cache cannot meet the needs of the scheduled process, the scheduling unit first selects a process in an occupied state, calls the switching unit to perform a swap-out operation, and then loads the scheduled process.

[0022] In some embodiments of this application, when it is necessary to select a scheduled process from suspended processes, the scheduling unit preferentially selects suspended processes with small note-style cache space requirements to avoid triggering a swap-out operation.

[0023] In some embodiments of this application, when the switching unit performs the swap-out operation, it first executes the query instruction of the access logic unit to obtain the range of accessed note cache addresses recorded in the address access table of the process to be swapped out. Then, based on the address range, it saves the note cache content of the corresponding range to the memory image through the note cache read instruction, and saves the relevant information in the address access table together.

[0024] In some embodiments of this application, when the switching unit performs a loading operation, it copies the contents of the note cache in the memory image to the note cache of the processor core by sending a note cache write instruction to the processor, based on the address range information stored in the memory image.

[0025] In some embodiments of this application, the driver unit returns failure information to the process when allocation fails, and returns a success flag and the allocated virtual address to the process when allocation succeeds.

[0026] In some embodiments of this application, the software space allocation table is maintained by the driver unit and is used to record the allocation status of each address space of the note-style cache. The driver unit determines the location and size of the free space by querying the software space allocation table.

[0027] According to a third aspect of this application, a general-purpose processor is provided, including the note-style cache management device as described above.

[0028] The note-based cache management device, system, and general-purpose processor proposed in this application achieve precise hardware-based management of the note-based cache by setting up an address mapping table to store the mapping relationship between virtual addresses and physical addresses, and setting up an address access table to record the range of SPM addresses actually accessed by a process. Simultaneously, the allocation logic unit creates or invalidates entries in the address mapping table in response to allocation or release instructions, and synchronously invalidates the associated records in the address access table during release. The access logic unit performs validity checks based on the address mapping table, performs read and write operations, and marks the address range corresponding to the current access in the address access table in response to access instructions. In particular, the address access table records the address range actually accessed by a process, eliminating the need to save or load the entire SPM content during subsequent process switching. Instead, it only requires selective processing of the accessed portion based on the records in the address access table, significantly reducing the amount of data exchange required for process switching. Furthermore, the collaborative maintenance of the address mapping table and address access table by the allocation and access logic ensures the consistency between the mapping relationship and the access records, providing a hardware foundation for reducing the process switching overhead introduced by SPM. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic diagram of the structure of a note-type cache management device provided in an embodiment of this application; Figure 2 This is a schematic diagram of a CPU executing an SPM access instruction according to an embodiment of this application; Figure 3 This is a schematic diagram of the CPU executing SPM allocation and release instructions according to an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a note-based cache management system provided in an embodiment of this application. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and descriptions of this application are used to explain this application, but are not intended to limit this application.

[0031] like Figure 1The diagram shown is a structural schematic of a note-type cache management device provided in an embodiment of this application. The note-type cache management device includes: an address mapping table 110, an address access table 120, an allocation logic unit 130, and an access logic unit 140, which will be described below.

[0032] Address mapping table 110 is configured to map the virtual addresses of stored processes to the physical addresses of note-based caches.

[0033] In general-purpose processors, processes use virtual addresses for addressing, while the SPM (Sticky Notepad Cache), as an on-chip physical storage resource, uses physical addresses for access. Address mapping table 110 is used to translate the virtual addresses used by processes to access the SPM into the physical addresses of the SPM.

[0034] Address mapping table 110 can be implemented using a register array or static random access memory (SRAM). In this embodiment, each entry in address mapping table 110 may include, but is not limited to, the following fields: process number (or process identifier), starting virtual address, SPM starting physical address, allocation size, and valid bit. The valid bit indicates whether the entry is valid; for example, a valid bit of "1" indicates that the entry has been allocated and is valid, and a valid bit of "0" indicates that the entry is idle or invalid. Other components in the processor (e.g., memory access units) can index address mapping table 110 using process information to find the SPM mapping relationship corresponding to the current process.

[0035] Address access table 120 is configured to record the address range information accessed by the process currently using the note cache.

[0036] Specifically, when a process performs a read or write operation on the SPM, the SPM address range involved in the operation is recorded in the address access table 120. The address access table 120 is used to record which SPM address ranges have been actually accessed by the current process, thus providing a basis for subsequent process switching and SPM content swapping.

[0037] Address access table 120 can be implemented using a register array or SRAM. In this embodiment, each entry in address access table 120 includes at least: index information associated with the entry in address mapping table 110 (e.g., the entry number or process number of the address mapping table), and information describing the range of accessed addresses. The information recorded in address access table 120 can be used by subsequent process scheduling and switching operations. For example, when it is necessary to swap out the SPM content of a process to memory, the content of the corresponding range can be swapped out based only on the accessed address range recorded in address access table 120, without swapping out the entire SPM.

[0038] The allocation logic unit 130, coupled to the address mapping table 110 and the address access table 120, is configured to: in response to executing a note-based cache allocation instruction, create an entry in the address mapping table; and in response to executing a note-based cache release instruction, invalidate the corresponding entry in the address mapping table and invalidate the record associated with the corresponding entry in the address access table.

[0039] Specifically, when software (such as a driver) needs to allocate SPM space for a process, it sends an SPM allocation instruction to the processor. This instruction is pipelined and decoded by the processor before being sent to the allocation logic unit 130. Upon receiving the SPM allocation instruction, the allocation logic unit 130 searches for a free entry in the address mapping table 110, then fills the free entry with the process ID, starting virtual address, starting physical address, allocation size, and other information carried in the SPM allocation instruction, and sets the valid bit of the entry to "1," thus completing the entry creation.

[0040] When a process releases SPM space or the operating system reclaims process resources, the software sends an SPM release instruction to the processor. Upon receiving the SPM release instruction, the allocation logic unit 130 locates the corresponding entry in the address mapping table 110 based on the process ID information carried in the instruction. Then, according to the index of that entry, the allocation logic unit 130 invalidates all records associated with that entry in the address access table 120. After completing the above operations, the allocation logic unit 130 invalidates the corresponding entry in the address mapping table 110.

[0041] In the above manner, the allocation logic unit 130 can realize the allocation and release of SPM space and ensure the consistency of data between the address mapping table 110 and the address access table 120. That is, when a process releases the SPM space, its related records in the address access table 120 are also cleared synchronously, avoiding interference of residual data to subsequent processes.

[0042] Access logic unit 140, coupled to address mapping table 110 and address access table 120, is configured to: in response to executing a note-based cache access instruction, perform a validity check on the access address according to the mapping relationship stored in the address mapping table, and perform a read / write operation on the note-based cache after the check passes; and mark the address range corresponding to this access in the address access table.

[0043] Specifically, when a process needs to read or write data in the SPM, it executes SPM access instructions (including SPM write instructions and SPM read instructions). SPM access instructions typically contain the starting virtual address to be accessed and the access range information. This instruction is pipelined and decoded by the processor before being sent to the access logic unit 140.

[0044] The access logic unit 140 first queries the address mapping table 110 based on the process information of the current process (e.g., the process ID obtained from the processor execution context) to convert the starting virtual address in the instruction into the physical address of the SPM. Simultaneously, the access logic unit 140 performs validity checks, including but not limited to: checking whether the valid bit of the corresponding entry in the address mapping table 110 is "1" (i.e., whether the process has been allocated SPM space), and checking whether the access address is within the range defined by the allocated starting virtual address and the allocated size (i.e., whether it is out of bounds). If the validity check fails, the access logic unit 140 can trigger exception or error handling; if the check passes, it continues with subsequent operations.

[0045] After the validity check passes, the access logic unit 140 performs read and write operations on the SPM. For SPM write operations, the access logic unit 140 copies data from other storage components of the processor (such as registers) to the SPM; for SPM read operations, the access logic unit 140 copies data from the SPM to other storage components of the processor.

[0046] While or concurrently with the SPM read / write operations performed by the access logic unit 140, the access logic unit 140 also marks the address access table 120. Specifically, the access logic unit 140 records the SPM address range corresponding to this access in the address access table 120 according to the starting address and access range accessed by this SPM access instruction. This marking operation is used to update the SPM address range information already accessed by the process, so that it can know which SPM contents need to be swapped out during subsequent process switching.

[0047] In this way, the access logic unit 140 can not only perform normal read and write access to the SPM, but also automatically record the access history of the process, providing hardware support for reducing process switching overhead.

[0048] As described above, the note-based cache management device proposed in this application achieves precise hardware-based management of the note-based cache by setting up an address mapping table to store the mapping relationship between virtual addresses and physical addresses, and setting up an address access table to record the SPM address range actually accessed by the process. Simultaneously, the allocation logic unit creates or invalidates entries in the address mapping table in response to allocation or release instructions, and synchronously invalidates the associated records in the address access table during release. The access logic unit performs a validity check based on the address mapping table, performs read / write operations, and marks the address range corresponding to the current access in the address access table in response to access instructions. In particular, the address access table records the address range actually accessed by the process, eliminating the need to save or load the entire SPM content during subsequent process switching. Instead, it only requires selective processing of the accessed portion based on the records in the address access table, significantly reducing the amount of data exchange required for process switching. Furthermore, the collaborative maintenance of the address mapping table and address access table by the allocation and access logic ensures the consistency between the mapping relationship and the access records, providing a hardware foundation for reducing the process switching overhead introduced by SPM.

[0049] In some embodiments of this application, each entry of the address access table 120 includes: an allocation table number, a starting address, an offset, and a valid bit, used to record the address range accessed by the process. Wherein: The allocation table number is used to associate the corresponding entry in address mapping table 110. Since each entry in address mapping table 110 is identified by a process number or entry index, the allocation table number field in address access table 120 records the address mapping table entry to which the access record belongs. This allocation table number determines which process's SPM allocation space the current access record belongs to.

[0050] The starting address is used to record the starting physical address of the SPM address range accessed by the process. When the process executes an SPM access instruction, the access logic unit 140 fills this field with the SPM physical starting address corresponding to this access.

[0051] The offset, used in conjunction with the starting address, defines the range of addresses accessed by a process. The offset field can represent the length of a continuous address sequence starting from the starting address. For example, if the starting address is Addr_start and the offset is Offset, then the address range recorded in this entry is [Addr_start, Addr_start + Offset]. The offset can be in units of bytes, words, or cache lines; this embodiment does not impose any restrictions on this.

[0052] The valid bit is used to indicate whether the entry is valid. A valid bit of "1" indicates that the entry records a valid address range; a valid bit of "0" indicates that the entry is free or has expired. When a process releases the SPM space, the allocation logic unit 130 sets the valid bits of each entry associated with the address access table 120 to "0" to invalidate the record.

[0053] Using the above tabular structure, address access table 120 can record the contiguous address ranges accessed by a process in a compact manner. When the address ranges corresponding to multiple access operations are consecutive or partially overlap, the number of entries can be further reduced through a merging mechanism, saving storage resources.

[0054] In some embodiments of this application, each entry in the address access table includes: an allocation table number, an access mask, and a valid bit, used to record the address range accessed by the process. Unlike the previous embodiments, this embodiment replaces the starting address and offset entries with an access mask.

[0055] An access mask is a bit vector consisting of multiple bits, where each bit corresponds to a fixed-size address range (i.e., an address block). When a bit is set to "1", it indicates that the address range corresponding to that bit has been accessed by the process; when a bit is "0", it indicates that the corresponding address range has not been accessed.

[0056] Specifically, assuming each address block is B bytes in size (e.g., B can be 64 bytes, 128 bytes, or 256 bytes; this embodiment does not impose any restrictions), and the total size of the SPM is S bytes, then the access mask requires at least (S / B) bits. If the division is not exact, it can be rounded up. Each bit corresponds sequentially to a fixed address block within the SPM. For example, if the SPM size is 64KB and each address block size is 1KB, then the access mask requires 64 bits, where bit 0 corresponds to SPM physical address bytes 0-1023, bit 1 corresponds to SPM physical address bytes 1024-2047, and so on.

[0057] The advantages of a masked structure are that the marking operation is simple and efficient; that is, only a bitwise OR operation needs to be performed on the corresponding bits in the mask, without the need for address range comparisons and entry merging. In addition, each bit in the masked structure corresponds to a fixed-size address block, and the number of entries is fixed (one entry per process), which facilitates hardware implementation and management.

[0058] Compared to the aforementioned embodiments, the masked structure is more suitable for application scenarios with a large SPM space but relatively regular access granularity. Those skilled in the art can choose either a table-based structure or a masked structure to implement the address access table 120 according to specific application requirements; this embodiment does not impose any restrictions on this.

[0059] Based on the construction of the above two address access tables 120, as follows: Figure 2 The diagram shown is a schematic of a CPU executing an SPM access instruction according to an embodiment of this application. The following is in conjunction with... Figure 2 The working process of access logic unit 140 will be explained further.

[0060] like Figure 2 As shown, the access logic unit 140 is connected to the address mapping table (i.e., Figure 2 The address allocation table, address access table, note cache (SPM), and other storage components of the processor (such as registers, cache, etc.) are coupled together. The access logic unit 140 can receive SPM read instructions, SPM write instructions, and poll instructions.

[0061] When a process needs to read or write data in the SPM (Server Module), it executes SPM access instructions (including SPM write and read instructions). SPM access instructions typically contain the starting virtual address to be accessed and the access range information. This instruction is pipelined and decoded by the processor before being sent to the access logic unit 140.

[0062] The access logic unit 140 first queries the address mapping table 110 based on the process information of the current process (e.g., the process ID obtained from the processor execution context) to convert the starting virtual address in the instruction into the physical address of the SPM. Simultaneously, the access logic unit 140 performs validity checks, including but not limited to: checking whether the valid bit of the corresponding entry in the address mapping table 110 is "1", and checking whether the access address is within the range defined by the allocated starting virtual address and the allocated size. If the validity check fails, the access logic unit 140 can trigger exception or error handling; if the check passes, it continues with subsequent operations.

[0063] After the validity check is passed, the access logic unit 140 performs read and write operations on the SPM. For SPM write operations, the access logic unit 140 copies data from other storage components of the processor to the SPM; for SPM read operations, the access logic unit 140 copies data from the SPM to other storage components of the processor.

[0064] While or concurrently with the SPM read / write operations performed by the access logic unit 140, the access logic unit 140 also marks the address access table 120. Specifically, the access logic unit 140 records the SPM address range corresponding to this access in the address access table 120 according to the starting address and access range accessed by this SPM access instruction. For a table-type address access table, the access logic unit 140 completes the marking by searching, merging, or creating new entries; for a mask-type address access table, the access logic unit 140 completes the marking by setting the mask bit of the corresponding address block to "1". This marking operation is used to update the SPM address range information already accessed by the process, so that subsequent process switching can know which SPM contents need to be swapped out.

[0065] In this way, the access logic unit 140 can not only perform normal read and write access to the SPM, but also automatically record the access history of the process, providing hardware support for reducing process switching overhead.

[0066] In some embodiments of this application, when the access logic unit 140 executes the note cache access instruction, it decouples the marking of the address access table 120 from the read and write operations of the note cache.

[0067] like Figure 2 As shown, when the access logic unit 140 executes an SPM read instruction or an SPM write instruction, it interacts with the SPM for data read / write operations on one hand, and performs a marking operation with the address access table on the other. These two operations are independent of each other and do not require waiting for each other.

[0068] Decoupled execution here means that the marking operation on the address access table 120 and the read / write operation on the SPM are independent of each other and do not need to wait for each other. Specifically, the access logic unit 140 can independently update the address access table 120 while completing the read / write operation on the SPM or in parallel with it. There is no data dependency or control dependency between the two, and they can be completed in parallel in different pipeline stages or different execution units.

[0069] In one specific implementation of this embodiment, when the access logic unit 140 executes the SPM access instruction, it may contain two parallel processing paths: the first path is responsible for the SPM read and write operations, and the second path is responsible for the marking operations of the address access table 120. The first path reads data from the SPM or writes data to the SPM based on the SPM physical address converted by the address mapping table 110; the second path calculates the address range to be marked based on the starting address and access range of this access, and updates the corresponding entries or masks in the address access table 120. The two paths can start and execute simultaneously, and the first path does not need to wait for the second path to complete, nor does the second path need to wait for the first path to complete.

[0070] Since the marking operation on address access table 120 does not affect the result of SPM read and write operations (i.e., the marking operation does not change the data content stored in SPM), the two can be executed decoupled. Even if the marking operation is delayed due to write conflicts or resource contention in address access table 120, it will not block SPM read and write operations; similarly, the delay in SPM read and write operations will not affect the execution of the marking operation.

[0071] This embodiment decouples the marking operation of the address access table 120 from the read / write operation of the SPM in time, allowing the two operations to be executed in parallel, thereby reducing the overall execution latency of the SPM access instruction. Taking a typical SPM access instruction as an example, if the SPM read / write operation requires T1 clock cycles and the address access table marking operation requires T2 clock cycles, the total latency would be T1 + T2 if they were executed serially. However, by decoupling the execution, the total latency can be reduced to max(T1, T2), which is the larger of T1 and T2. When neither T1 nor T2 is zero, decoupling the execution can bring a significant performance improvement.

[0072] In another specific implementation of this embodiment, decoupled execution can be further extended to different instruction granularities. For example, the access logic unit 140 can first submit the SPM read / write operation to the memory subsystem for execution, while simultaneously placing the marking operation of the address access table 120 into a separate marking queue, which is then asynchronously completed by the background hardware logic. Subsequent instructions can continue execution without waiting for the marking operation to complete, thereby further improving the throughput of the instruction pipeline.

[0073] It's important to note that decoupled execution doesn't mean the marking operation never needs to be completed. When subsequent operations (such as querying address access table 120 during process switching) depend on the marking result of address access table 120, a synchronization mechanism is needed to ensure the marking operation has been completed. However, in most cases, SPM access instructions themselves do not depend on the marking result, so decoupled execution is safe and efficient.

[0074] In some embodiments of this application, the access logic unit 140 is further configured to, in response to an execution query instruction, return all entries of the corresponding process in the address access table based on the process information given by the query instruction.

[0075] like Figure 2 As shown, the access logic unit 140 can receive a query instruction. A query instruction is a newly added processor instruction used by software to obtain information about the SPM address range already accessed by a specified process. This instruction can be explicitly sent to the processor by the software; after the processor pipeline's decoding stage recognizes the instruction, it sends it to the access logic unit 140 for execution.

[0076] In one specific implementation of this embodiment, the query instruction carries at least the following information: the process ID of the process to be queried. After receiving the query instruction, the access logic unit 140 searches for all entries in the address access table 120 associated with that process ID, based on the process ID carried in the instruction. As mentioned earlier, each entry in the address access table 120 contains an allocation table number field, which is used to associate with the corresponding entry in the address mapping table 110. By matching the allocation table number with the process ID, the access logic unit 140 can filter out all address access table entries belonging to that process.

[0077] After finding all entries belonging to the process, the access logic unit 140 returns the contents of these entries to the processor. For example... Figure 2 As shown, the access logic unit 140 can return the query results to the software through coupling with storage components such as registers and cache.

[0078] A typical application scenario for the query instruction in this embodiment is in the swap-out operation during process switching. When the operating system needs to swap out the SPM content of a suspended process into memory, it first needs to know which SPM address ranges the process has actually accessed. At this time, the operating system can execute a query instruction, passing the process ID of the process to be swapped out as a parameter to the access logic unit 140, to obtain all entries of the process in the address access table 120 (i.e., the SPM address range information that the process has accessed). After obtaining this address range information, the operating system can save only the SPM content of the corresponding range into memory, without having to save the entire SPM, thereby significantly reducing the amount of data in the swap-out operation.

[0079] In another implementation of this embodiment, the query instruction can also support more flexible query conditions. For example, the query instruction can carry a starting entry number and a query quantity to retrieve entries in the address access table 120 in batches; or the query instruction can carry an address range parameter to query which parts within a specified address range have been accessed by a process. These variant implementations are all within the scope of this embodiment.

[0080] It should be noted that the query command returns information about the accessed address ranges recorded in address access table 120, not all the data stored in the current SPM. Because address access table 120 accurately records the address ranges actually accessed by the process, the query command can provide more concise information than the entire SPM, thus providing a foundation for efficient selective swapping.

[0081] In some embodiments of this application, when the allocation logic unit 130 executes the SPM allocation instruction, it searches for a free entry in the address mapping table and fills the free entry with the process number, starting virtual address, starting physical address, and allocation size information carried by the allocation instruction, and sets the valid bit of the free entry to true. Simultaneously, when the allocation logic unit 130 executes the SPM release instruction, it finds the corresponding entry in the address mapping table based on the process number carried by the release instruction, invalidates all records belonging to that entry in the address access table according to the process number of the entry, and then invalidates the corresponding entry in the address mapping table.

[0082] Figure 3 This is a schematic diagram illustrating the CPU executing SPM allocation and release instructions according to an embodiment of this application. The following is in conjunction with... Figure 3 The working process of the allocation logic unit 130 will be further explained.

[0083] like Figure 3 As shown, the allocation logic unit 130 is associated with the address mapping table (i.e., Figure 3 The address allocation table and the address access table are coupled. Figure 3 The left side shows one tabular implementation of an address access table, while the right side shows another masked implementation.

[0084] (a) The execution process of SPM allocation instructions.

[0085] When software (such as a driver) needs to allocate SPM space for a process, it sends an SPM allocation instruction to the processor. Depending on the specific implementation, the SPM allocation instruction can consist of one or more instructions; this embodiment does not impose any limitations on this. Figure 3 As indicated by the arrow for "SPM allocation instruction / SPM release instruction", this instruction is recognized by the decoding stage of the processor pipeline and sent to the allocation logic unit 130 during the issue stage.

[0086] After receiving the SPM allocation instruction, the allocation logic unit 130 first checks the address mapping table to see if there is a free entry. As mentioned earlier, each entry in the address mapping table contains a valid bit, which indicates whether the entry is occupied. The allocation logic unit 130 traverses each entry in the address mapping table and finds the first entry with a valid bit of "0" as the free entry.

[0087] If a free entry exists in the address mapping table, the allocation logic unit 130 extracts allocation information from the SPM allocation instruction, including but not limited to: process ID, starting virtual address, starting physical address, and allocation size. The process ID identifies the process requesting SPM space; the starting virtual address is the starting address of the virtual address space the process will use; the starting physical address is the starting address of the physical space allocated in the SPM; and the allocation size is the size of the space requested by the process. The allocation logic unit 130 fills this information into the corresponding fields of the found free entry. After filling in the information, the allocation logic unit 130 sets the valid bit of the entry to true, indicating that the entry has been occupied and the process has successfully allocated SPM space.

[0088] If no free entry exists in the address mapping table, the allocation fails. In this case, the allocation logic unit 130 can send an allocation failure message to the write-back stage of the processor pipeline, and the software can return a failure flag to the process after receiving the failure message.

[0089] In one specific implementation, after the allocation logic unit 130 completes the table entry creation, it can also send instruction completion information to the write-back stage of the processor pipeline, such as... Figure 3 As indicated by the "Completed" arrow. Depending on the specific implementation, this completion information may include the entry number of the newly allocated entry in address mapping table 110, so that subsequent SPM access or release instructions can quickly index the entry.

[0090] Through the above operations, the allocation logic unit 130 realizes hardware-based allocation management of the SPM space. Compared with software-maintained allocation tables, hardware allocation logic can complete table entry creation and address mapping at a faster speed, reducing the overhead of allocation operations.

[0091] In one extended implementation of this embodiment, the allocation logic unit 130 can also perform additional checks when allocating SPM space. For example, before filling in the allocation information, the allocation logic unit 130 can check whether the parameters carried by the allocation instruction are valid (such as whether the allocation size exceeds the total SPM capacity, whether the starting physical address is aligned, etc.). If the parameters are invalid, the allocation fails and no entry is created. These additional checks can be selectively implemented according to actual design requirements, and this embodiment does not impose any restrictions on them.

[0092] (ii) The execution process of the SPM release command.

[0093] When a process actively releases SPM space or the operating system reclaims process resources, the software sends an SPM release instruction to the processor. Depending on the specific implementation, the SPM release instruction can consist of one or more instructions; this embodiment does not impose any restrictions. Figure 3 As shown, the instruction is also sent to the allocation logic unit 130 after being decoded.

[0094] After receiving the SPM release instruction, the allocation logic unit 130 first extracts the process ID of the process to be released from the instruction. Then, the allocation logic unit 130 searches for the corresponding entry in the address mapping table based on the process ID. Specifically, the allocation logic unit 130 traverses each entry in the address mapping table, matches the process ID stored in each entry with the process ID carried in the release instruction, and selects the successfully matching entry as the entry to be released.

[0095] After finding the corresponding entry in the address mapping table, the allocation logic unit 130 obtains the entry number of that entry. This entry number is used to associate with related records in the address access table. As mentioned earlier, each entry in the address access table contains an allocation table number field, which records the entry number of the address mapping table to which the access record belongs. Based on this entry number, the allocation logic unit 130 searches the address access table for all records whose allocation table numbers match this entry number.

[0096] After finding all address access table records belonging to this entry, the allocation logic unit 130 invalidates these records. For example... Figure 3 As shown, the allocation logic unit 130 is coupled to the address access table, and can index the corresponding record in the address access table based on the entry number of the address mapping table. In specific implementations, disabling can be accomplished in several ways: for example, for Figure 3 The table-based address access table on the left sets the valid bits of each entry that matches the allocation table number to "0"; for Figure 3 The masked address access table on the right sets the valid bit of the corresponding entry to "0". This embodiment does not limit the specific failure implementation method, as long as these records are no longer considered valid by subsequent operations.

[0097] After invalidating the relevant records in the address access table, the allocation logic unit 130 then invalidates the corresponding entry in the address mapping table. Specifically, the allocation logic unit 130 sets the valid bit of the entry to "0", indicating that the entry has been released and can be reused by subsequent SPM allocation instructions. In one implementation, the allocation logic unit 130 can also clear or invalidate other fields in the entry (such as process number, starting virtual address, starting physical address, allocation size, etc.) to avoid interference from residual data. Finally, the allocation logic unit 130 sends completion information to the write-back stage of the processor pipeline, such as... Figure 4 As indicated by the "Completed" arrow in the middle.

[0098] It is worth emphasizing that the order of clearing the associated records in the address access table first, and then invalidating the entries in the address mapping table, is of great significance in this embodiment. This is because the records in the address access table are associated with the entry numbers in the address mapping table. If the address access table is cleared after the entries in the address mapping table are invalidated, the following problem may occur: when the entry number is reassigned to another process, the clearing operation may mistakenly delete the address access table record of the new process. Therefore, this embodiment adopts the order of clearing the address access table first, and then invalidating the address mapping table, to ensure the correctness of the release operation and data isolation.

[0099] Through the above operations, the allocation logic unit 130 implements hardware-based release management of the SPM space and ensures data consistency between the address mapping table and the address access table. When a process releases the SPM space, all its historical access records in the address access table are synchronously cleared, avoiding interference from residual data to subsequent processes, and also preparing for the reallocation of entries in the address mapping table.

[0100] In some embodiments of this application, the access logic unit 140 performs a validity check on the access address by checking whether the valid bit of the corresponding entry in the address mapping table is true, and checking whether the access address is within the range defined by the allocated starting virtual address and the allocated size.

[0101] When a process executes an SPM access instruction, the access logic unit 140 needs to ensure that the process's access to the SPM is legal and safe, preventing errors such as accessing SPM space without allocating it or accessing it out of bounds. The legality check mainly includes the following two aspects: (a) Check the valid bits.

[0102] The access logic unit 140 first searches for the corresponding entry in the address mapping table 110 based on the process ID of the current process. After finding the corresponding entry, the access logic unit 140 reads the valid bit field of that entry.

[0103] The valid bit indicates whether the entry has been allocated and is valid. When the valid bit is true, it means that the process has been allocated SPM space and the mapping relationship stored in address mapping table 110 is valid, allowing the process to continue accessing SPM. When the valid bit is false, it means that the process has not been allocated SPM space, or the allocated SPM space has been released. In this case, the access logic unit 140 determines that the validity check fails, rejects the SPM access instruction, and may trigger the corresponding exception or error handling mechanism, such as reporting a page fault or illegal access exception to the processor.

[0104] (ii) Check the range of access addresses.

[0105] After the valid bit check passes, the access logic unit 140 further checks whether the address being accessed is within the allocated SPM space range. Specifically, the access logic unit 140 reads two key pieces of information from the corresponding entry in the address mapping table 110: the starting virtual address (denoted as VA_start) and the allocation size (denoted as Size). The range of valid virtual addresses defined by this entry is [VA_start, VA_start + Size].

[0106] Access logic unit 140 extracts the starting virtual address (denoted as VA) and access range (denoted as AccessSize) to be accessed from the SPM access instruction. Since the SPM access instruction may access a continuous range of addresses (e.g., reading or writing multiple bytes continuously starting from the starting address), the virtual address range covered by this access is [VA, VA + AccessSize].

[0107] Access logic unit 140 determines whether the address range of this access is completely contained within the allocated SPM space, that is, whether the following two conditions are met simultaneously: Condition 1: VA ≥ VA_start (the access start address is not less than the allocation start address); Condition 2: VA + AccessSize ≤ VA_start + Size (the access end address does not exceed the allocation end address).

[0108] If both of the above conditions are met, the address range of this access is entirely within the allocated SPM space, and the legality check passes; if either condition is not met, this access is out of bounds, and the legality check fails.

[0109] In one specific implementation, the access logic unit 140 can also perform finer-grained checks. For example, when the SPM allocation granularity is inconsistent with the access granularity, the access logic unit 140 can also check whether the starting address meets the alignment requirements (such as word alignment or cache line alignment), or check whether the access size is within the allowed range. These additional checks can be selectively implemented according to specific design requirements, and this embodiment does not impose any restrictions on them.

[0110] Once the validity check passes, the access logic unit 140 continues to perform subsequent operations: converting the starting virtual address into the physical address of the SPM through the address mapping table 110, then performing read and write operations on the SPM, and marking the address range corresponding to this access in the address access table 120.

[0111] When the validity check fails, the access logic unit 140 does not perform SPM read / write operations, nor does it mark the address access table 120. Simultaneously, the access logic unit 140 reports the exception to the processor, which is then handled appropriately by the operating system's exception handler (e.g., terminating the process that is illegally accessing the SPM, or allocating SPM space for the process and retrying execution). This validity check mechanism prevents processes from accessing the SPM space out of bounds or illegally accessing other processes, thus ensuring system security.

[0112] In one specific implementation of this embodiment, to accelerate the validity check process, a comparator circuit can be set inside the access logic unit 140 to compare the VA and AccessSize provided by the access instruction with the VA_start and Size read from the address mapping table 110. When both conditions are met simultaneously, a pass signal is output. This comparison operation can be completed within one clock cycle and will not have a significant impact on the overall latency of SPM access.

[0113] like Figure 4 The diagram shows a structural schematic of a note-based cache management system provided in an embodiment of this application. It includes a note-based cache management device 410, a note-based cache 420, a driver unit 430, a scheduling unit 440, and a switching unit 450, as described above. The note-based cache management device 410 includes an address mapping table 110, an address access table 120, an allocation logic unit 130, and an access logic unit 140, as described above. These are the hardware components of the system, and their details can be found in the description of the foregoing embodiments, which will not be repeated here. The software components of this system, namely the driver unit 430, the scheduling unit 440, and the switching unit 450, will be further described below.

[0114] The driver unit 430 is configured to, in response to a process requesting note-style cache space, query the software space allocation table to confirm whether there is sufficient free space; if so, allocate virtual and physical addresses to the process, send a note-style cache allocation instruction to the allocation logic unit so that the allocation logic unit establishes a corresponding entry in the address mapping table, and updates the software space allocation table after allocation; and in response to a process releasing note-style cache space or the operating system reclaiming process resources, send a note-style cache release instruction to the allocation logic unit and synchronously update the software space allocation table.

[0115] In this embodiment, the driving unit 430 is generally implemented in the device driver of SPM, and is responsible for allocating SPM space to the process and reclaiming the SPM space allocated to the process after the process has finished using the SPM.

[0116] When a process needs to request SPM space, it sends an SPM space request to the driver unit 430 via an interface call. Upon receiving the request, the driver unit 430 first queries the software space allocation table. The software space allocation table is a software data structure maintained by the driver unit 430 to record the allocation status of each address space in the SPM, such as which address ranges have been allocated to which processes and which address ranges are still free. By querying the software space allocation table, the driver unit 430 confirms whether there is enough free SPM space to meet the process's request.

[0117] If there is sufficient free space in the software space allocation table, the driver unit 430 allocates virtual and physical addresses for the process. After allocating the addresses, the driver unit 430 sends an SPM allocation instruction to the hardware allocation logic unit. This instruction carries information such as the process number, the starting virtual address to be allocated, the starting physical address to be allocated, and the requested space size. After receiving the instruction, the allocation logic unit 130 establishes a corresponding entry in the address mapping table in the manner described in the aforementioned hardware embodiment. After the driver unit 430 waits for the allocation instruction to be executed, it performs subsequent processing based on the instruction execution result: if the allocation is successful, it updates the software space allocation table, marks the space as allocated, and returns a success flag and the allocated virtual address to the process; if the allocation fails, it returns failure information to the process.

[0118] When a process actively releases SPM space, it sends a release request to the driver unit 430 via an interface call. Upon receiving the release request, the driver unit 430 sends an SPM release instruction to the allocation logic unit 130, carrying the process ID of the process to be released. Upon receiving this instruction, the allocation logic unit 130 invalidates the corresponding entry in the address mapping table 110 as described in the aforementioned hardware embodiment, and simultaneously invalidates the associated record in the address access table. After the instruction is executed, the driver unit 430 synchronously updates the software space allocation table, marking this portion of space as free for subsequent allocation to other processes.

[0119] In addition, when the operating system reclaims process resources (e.g., when a process terminates abnormally or is forcibly terminated), the operating system calls the reclamation interface of the driver unit 430. The driver unit 430 also sends an SPM release instruction to the allocation logic unit 130 and updates the software space allocation table synchronously to ensure that the SPM space is correctly reclaimed.

[0120] In this way, the drive unit 430 realizes software-level management of the SPM space, works in conjunction with the allocation logic unit 130, and jointly maintains the correctness and consistency of the address mapping table 110.

[0121] The scheduling unit 440 is configured to schedule and manage processes that use note-style caching, wherein the note-style caching usage status of a process includes three states: unoccupied, occupied, and suspended.

[0122] The scheduling unit 440 is configured to schedule and manage processes that use a note-style cache, wherein the note-style cache usage status of a process includes three states: unoccupied, occupied, and suspended.

[0123] The scheduling unit 440 is typically embedded as a submodule within the operating system's process scheduling module code, responsible for scheduling and managing processes using SPM. To ensure precise SPM management, the operating system adds an SPM usage status field to the maintained process information. This status includes the following three types: Unoccupied state: This indicates that the process is not using SPM, or although it used it, it has released the SPM space. Such processes do not occupy any processor core's SPM resources.

[0124] Occupied Status: This indicates that a process is currently occupying the SPM of a processor core. At this time, the SPM content of the process resides in the SPM of the processor core, and the process can execute SPM access instructions normally.

[0125] Suspended state: This indicates that a process is using SPM, but is not actually occupying any processor core's SPM. In this state, the process's SPM content is stored in a temporarily allocated memory area called the SPM memory image. When the process is suspended, its SPM content is swapped out to the memory image to free up SPM space for other processes.

[0126] Scheduling unit 440 is invoked when the operating system performs process scheduling. Before switching processes, the operating system checks whether a process using SPM exists. If it does, scheduling unit 440 is invoked to execute the SPM-related scheduling logic.

[0127] The switching unit 450 is configured to perform a swap-out operation and a loading operation; wherein, the swap-out operation includes: when the scheduling unit schedules a process in a suspended state, obtaining the range of note-style cache addresses that the process to be swapped out has accessed recorded in the address access table through the access logic unit, and saving the corresponding content to the memory image according to the address range; the loading operation includes: loading the note-style cache content of the suspended process to be scheduled from the memory image to the note-style cache.

[0128] Switching unit 450 is typically embedded as a submodule into the process switching module code of the operating system, and is responsible for the actual data transfer work.

[0129] When scheduling unit 440 decides to swap out a process currently occupying SPM, it calls switching unit 450 to perform the swapping function. Switching unit 450 first obtains the address access table information of the process to be swapped out through access logic unit 140. Specifically, switching unit 450 can execute a query instruction, which is responded to by access logic unit 140 and returns all entries in the address access table for that process, i.e., the SPM address range information actually accessed by the process. After obtaining this address range information, switching unit 450 saves the corresponding SPM content within these address ranges to a pre-allocated memory image. Because only the address range actually accessed by the process is saved, rather than the entire SPM, the data volume of the swapping operation is significantly reduced, and the swapping overhead is significantly lowered. Furthermore, switching unit 450 also saves relevant information from address access table 120 so that it can be correctly restored during subsequent loading operations.

[0130] When scheduling unit 440 decides to schedule a suspended process to execute on the processor core, it calls switching unit 450 to perform the loading function. Switching unit 450 copies the SPM content from the memory image to the processor core's SPM based on the address range information stored in the process's memory image. During loading, since access logic unit 140 automatically modifies address access table 120 (i.e., records the access range of the newly loaded content) according to SPM write instructions, switching unit 450 does not need to perform additional operations to modify address access table 120. After loading is complete, the SPM content of the scheduled process is ready, and the process can continue execution.

[0131] Through the aforementioned swap-out and loading operations, the switching unit 450 achieves selective swapping out and on-demand loading of SPM content during process switching. Together with the scheduling strategy of the scheduling unit 440, it minimizes the process switching overhead in the SPM scenario.

[0132] As described above, the note-based cache management system provided in this application, based on a hardware device including an address mapping table, an address access table, an allocation logic unit, and an access logic unit, further integrates a driver unit, a scheduling unit, and a switching unit. The driver unit, through the collaboration of the software space allocation table and the hardware allocation logic unit, realizes on-demand allocation and synchronous reclamation of SPM space; the scheduling unit manages processes using the note-based cache by introducing three process states: unoccupied, occupied, and suspended; when performing a swap-out operation, the switching unit obtains the accessed address range recorded in the address access table through the access logic unit, saving only the SPM content actually accessed by the process to the memory image, rather than saving the entire SPM. When performing a load operation, it restores the content in the memory image to the SPM as needed. Therefore, based on the accurate recording of the process access range by the address access table provided by the hardware device, this system, through the combination of software scheduling strategies and selective swap-out mechanisms, significantly reduces the amount of data movement during process switching, avoids unnecessary swap-out and load operations, and thus effectively reduces the overhead of process switching while introducing a note-based cache into a general-purpose processor, improving the overall performance and response speed of the system.

[0133] In some embodiments of this application, the scheduling unit 440 is further configured to: prioritize scheduling processes in an occupied state; and when there are no schedulable processes in an occupied state, select a process to be scheduled from processes in a suspended state.

[0134] Since swapping out and loading operations involve moving data between the SPM and the memory image, which incurs significant time overhead, reducing the frequency of these operations is key to reducing process switching overhead.

[0135] Based on the above principles, in this embodiment, the scheduling unit 440 first checks whether there is a process in an occupied state in the set of schedulable processes. An occupied state means that the process is currently occupying the SPM (Server Page Memory) of a processor core, and its SPM content is already resident in the SPM. If the scheduling unit 440 selects such a process for execution, the process can continue running directly without any swapping out or loading of SPM content. This is because the process's SPM content is already in the SPM, and the entries in its address mapping table and the records in its address access table remain valid. Therefore, scheduling a process in an occupied state is the least costly option.

[0136] When scheduling unit 440 finds that there are no currently schedulable processes in an occupied state—for example, all processes using SPM are in a suspended state, or there are no occupied SPM processes on the current processor core—scheduling unit 440 selects a process to be scheduled from the suspended processes. The SPM content of the suspended process is not currently in the SPM but is stored in the memory image. Selecting a suspended process requires a load operation (and possibly a swap-out operation), which has a higher overhead than scheduling an occupied process, but it is a necessary choice when there are no occupied processes available for scheduling.

[0137] In one specific implementation, when making scheduling decisions, the scheduling unit 440 first scans the process scheduling queue to check if there are any processes with an SPM usage status of "occupied". If so, it selects one of these occupied processes for scheduling, and the entire scheduling process ends, no longer considering suspended processes. If there are no occupied processes, the scheduling unit 440 further filters the process scheduling queue for processes with an SPM usage status of "suspended", and selects one of them as the scheduled process.

[0138] Through the aforementioned priority scheduling strategy, scheduling unit 440 can avoid unnecessary SPM content swapping and loading operations in most cases. When there are runnable processes in a preoccupied state in the system, scheduling unit 440 prioritizes them, allowing SPM content to be reused and keeping process switching overhead at a low level. Only when no preoccupied processes are available is the scheduling of suspended processes triggered, at which point SPM content loading (and possible swapping) is necessary. This strategy minimizes the frequency of SPM content swapping and loading, thereby effectively reducing the process switching overhead introduced by SPM.

[0139] In some embodiments of this application, when selecting a scheduled process from processes in a suspended state, if the remaining space of the note cache cannot meet the needs of the scheduled process, the scheduling unit 440 first selects a process in an occupied state, calls the switching unit 450 to perform a swap-out operation, and then loads the scheduled process.

[0140] Specifically, when the scheduling unit 440 determines that there are no schedulable processes in an occupied state and it needs to select a process to be scheduled from the processes in a suspended state, it also needs to further consider whether the remaining space of the SPM is sufficient to accommodate the SPM content of the scheduled process.

[0141] As mentioned earlier, the SPM (Service Memory Management) content of each suspended process is stored in a memory image, and its SPM space requirement is known and can be obtained from the process information. However, the SPM of the current processor core may already contain the SPM content of other processes, which occupy part or all of the SPM space.

[0142] Before deciding to load a suspended process, scheduling unit 440 first calculates the remaining space of the current SPM. The remaining SPM space is equal to the total SPM capacity minus the sum of the SPM space occupied by all currently occupied processes. If the remaining space is greater than or equal to the SPM space requirement of the scheduled suspended process, scheduling unit 440 can directly call switching unit 450 to perform a loading operation, loading the SPM content of the scheduled process from the memory image into the free area of ​​the SPM without needing to perform a swapping operation.

[0143] However, if the remaining space in the SPM is less than the SPM space requirement of the scheduled suspended process, the scheduled process cannot be loaded directly. In this case, the scheduling unit 440 needs to free up sufficient SPM space first. Specifically, the scheduling unit 440 selects one or more processes currently in an occupied state, calls the switching unit 450 to perform a swap-out operation on them, saves the SPM content of these processes to their respective memory images, and changes their SPM usage status from "occupied" to "suspended". After the swap-out operation is completed, the corresponding space in the SPM is released, and the remaining space increases. When the remaining space meets the needs of the scheduled process, the scheduling unit 440 calls the switching unit 450 to perform a loading operation, loading the SPM content of the scheduled process from the memory image into the SPM.

[0144] In one specific implementation, when it is necessary to swap out a process in an occupied state to free up space, the scheduling unit 440 can select one process to swap out. If the space freed up after swapping out one process is still insufficient to meet the needs of the scheduled process, the scheduling unit 440 can continue to swap out a second and a third process until the remaining space meets the requirements. Of course, multiple processes can also be swapped out at once, and this embodiment does not impose any restrictions on this.

[0145] In another specific implementation, when selecting processes in an occupied state to be swapped out, the scheduling unit 440 may prioritize processes with smaller SPM space usage, or prioritize processes with lower priority and least recent usage, in order to minimize the impact of the swapping operation on the overall system performance. These specific selection strategies can be configured according to actual application requirements, and this embodiment does not impose any restrictions on them.

[0146] It should be noted that in this embodiment, both the swapping out and loading operations are actually executed by the switching unit 450, while the scheduling unit 440 is responsible for decision-making and invocation. Through the above mechanism, even if the SPM space is insufficient, the scheduling unit 440 can free up enough space for the scheduled suspended process by swapping out the currently occupied process, ensuring that it can be successfully loaded and executed.

[0147] The scheduling strategy in this embodiment complements the aforementioned strategy of prioritizing the scheduling of processes in an occupied state: when possible, processes in an occupied state are scheduled first to avoid swapping out and loading; if no processes in an occupied state are available for scheduling, suspended processes are loaded directly if there is sufficient SPM space; if there is insufficient SPM space, some processes in an occupied state are swapped out before the scheduled processes are loaded. This complete scheduling strategy system ensures that the system can correctly perform SPM process scheduling under any circumstances, while minimizing the overhead of swapping out and loading operations.

[0148] In some embodiments of this application, when it is necessary to select a scheduled process from suspended processes, the scheduling unit 440 preferentially selects suspended processes with small note-style cache space requirements to avoid triggering a swap-out operation.

[0149] The purpose of this embodiment is to minimize the triggering of swap-out operations. As mentioned earlier, when the scheduling unit 440 needs to load a suspended process, it needs to check whether the remaining space in the current SPM is sufficient to meet the SPM space requirements of the process. Let the remaining space in the current SPM be R, and the SPM requirement of the scheduled process be D. If R ≥ D, the scheduled process can be loaded directly without a swap-out operation; if R < D, some processes in the occupied state need to be swapped out first to free up enough space, which will trigger additional swap-out operations and increase the overhead of process switching.

[0150] Therefore, under otherwise identical or similar conditions, selecting a suspended process with a smaller SPM space requirement can increase the probability of R ≥ D, i.e., increase the likelihood of direct loading without swapping out. Even if the remaining SPM space is insufficient to satisfy the process with the smaller demand, the amount of data that needs to be swapped out may be less than the amount of data that needs to be swapped out when selecting a process with a larger demand.

[0151] In one specific implementation, when scanning the queue of suspended processes, the scheduling unit 440 can sort the suspended processes according to their SPM space requirements from smallest to largest, prioritizing the process with the smallest space requirement for scheduling. For example, assuming the current remaining SPM space is 32KB, and there are three processes in the queue: process A requires 16KB, process B requires 32KB, and process C requires 64KB. The scheduling unit 440 prioritizes process A (smallest requirement), because 16KB ≤ 32KB, it can be loaded directly without swapping out. If process B is selected, although 32KB ≤ 32KB, it can also be loaded directly, but if process C is selected, 64KB > 32KB, requiring the process occupying the space to be swapped out first, triggering additional overhead. Prioritizing processes with smaller requirements can avoid swapping out operations with a higher probability.

[0152] In another specific implementation, if the SPM (Scheduling Process Requirement) space requirements of multiple suspended processes are the same or similar, the scheduling unit 440 can combine other factors for selection, such as process priority, process last running time (least recently used), etc. These auxiliary selection strategies can be configured according to actual application requirements, and this embodiment does not impose any restrictions on them.

[0153] It should be noted that prioritizing suspended processes with smaller demands is a biased strategy, not a mandatory rule. In certain special cases, such as when a process with a large demand has extremely high priority, the scheduling unit 440 may prioritize it even if its demand space is large, even if this triggers a swap-out operation. Therefore, the preferred selection described in this embodiment refers to the scheduling unit 440's tendency to select suspended processes with smaller SPM demand spaces under normal circumstances, when other factors are equal.

[0154] By employing the aforementioned selection strategy, the scheduling unit 440 can minimize or avoid triggering swap-out operations when making scheduling decisions from suspended processes, thereby reducing the overall overhead of process switching and improving system response performance. This embodiment, together with the aforementioned strategies of prioritizing scheduling occupied processes and swapping out processes before loading them when space is insufficient, constitutes a complete SPM process scheduling optimization system.

[0155] In some embodiments of this application, when the switching unit 450 performs the swap-out operation, it first executes the query instruction of the access logic unit 140 to obtain the range of accessed note cache addresses recorded in the address access table 120 of the process to be swapped out. Then, based on the address range, the note cache content of the corresponding range is saved to the memory image through the note cache read instruction, and the relevant information in the address access table 120 is also saved.

[0156] When scheduling unit 440 decides to swap out a process currently occupying SPM, it calls switching unit 450 to perform the swap operation. The goal of the swap operation is to save the process's contents in SPM to a memory image so that its SPM state can be restored when the process is rescheduled. However, as mentioned earlier, simply saving the entire SPM space (which may be tens to hundreds of KB) into memory would incur huge data migration overhead. This application utilizes the process access history recorded in address access table 120 to achieve selective swapping, saving only the contents within the SPM address range actually accessed by the process.

[0157] The specific procedure for the swapping out operation in this embodiment is as follows: Step 1: Execute the query command to obtain the range of accessed addresses.

[0158] The switching unit 450 first executes a query instruction via the processor, which is sent to the access logic unit 140. The query instruction carries the process ID of the process to be swapped out. Upon receiving the query instruction, the access logic unit 140 searches the address access table 120 for all entries belonging to that process based on the process ID, and returns the contents of these entries to the switching unit 450. As mentioned earlier, each entry in the address access table 120 records a SPM address range that the process has previously accessed. Therefore, the query instruction returns information on all SPM address ranges that the process has actually accessed.

[0159] Step 2: Based on the address range, save the corresponding content to the memory image.

[0160] After obtaining the accessed address range of the process to be swapped out, the switching unit 450, based on these address ranges, executes SPM read instructions to read the SPM content within the corresponding range one by one and save it to the pre-allocated memory image. Specifically, for each address range, the switching unit 450 can execute one or more SPM batch read instructions to copy the data in that area from the SPM to the corresponding location in the memory image. Since only the address range actually accessed by the process is saved, rather than the entire SPM, the amount of data that needs to be saved is usually much smaller than the total capacity of the SPM, thereby significantly reducing the data movement and time overhead of the swapping out operation.

[0161] Step 3: Save the relevant information in the address access table.

[0162] In addition to saving the data in the SPM, the switching unit 450 also saves the information related to the process in the address access table 120 to the memory image. This information includes, but is not limited to, the address access table entries for the process, and other metadata that may be associated. The purpose of saving the address access table information is that when the process is subsequently reloaded, the switching unit 450 can restore the address access table 120 based on this information, so that after the process resumes execution, the address access table 120 can correctly reflect the historical access records of the process, thereby ensuring that subsequent swapping operations can still perform selective swapping based on the complete access history.

[0163] In one specific implementation, the switching unit 450 may first save the address access table information and then save the SPM data content; or it may save the SPM data content first and then save the address access table information; or it may save both as a whole at once. Regardless of the order, as long as it can be correctly restored during loading, this embodiment does not impose any restrictions.

[0164] Through the aforementioned swap-out operation, the switching unit 450 utilizes the process access history precisely recorded in the address access table 120 to save only the SPM content actually accessed by the process to the memory image, while retaining the address access table information for subsequent recovery. This selective swap-out mechanism is one of the key technical means to reduce the SPM process switching overhead. Together with the priority scheduling strategy of the scheduling unit 440, it minimizes the process switching overhead in the SPM scenario.

[0165] In an extended implementation of this embodiment, the switching unit 450 can also merge or optimize address ranges during the swap-out operation. For example, if multiple address ranges are very close together, they can be merged into a single contiguous address range for storage, thereby reducing the number of SPM read instructions executed and data fragmentation during data movement. These optimizations can be selectively implemented according to actual design requirements, and this embodiment does not impose any limitations on them.

[0166] In some embodiments of this application, when the switching unit 450 performs the loading operation, it copies the note cache content in the memory image to the note cache of the processor core by sending a note cache write instruction to the processor based on the address range information stored in the memory image.

[0167] When scheduling unit 440 decides to schedule a suspended process to execute on the processor core, it calls switching unit 450 to perform a load operation. The goal of the load operation is to restore the SPM content saved in the memory image when the process was previously swapped out to the SPM of the processor core so that the process can continue execution.

[0168] The specific process of the loading operation in this embodiment is as follows: Step 1: Obtain the address range information stored in the memory image.

[0169] As mentioned earlier, when the process was previously swapped out, the switching unit 450 not only saved the SPM content to the memory image but also saved the process's address access table information. Therefore, at the start of the load operation, the switching unit 450 first reads the previously saved address range information from the process's memory image. This information records the SPM address ranges actually accessed by the process before swapping out, corresponding to the data content saved at the time of swapping out.

[0170] Step 2: Copy the contents of the memory image to SPM based on the address range information.

[0171] After obtaining the address range information, the switching unit 450 copies the contents of the corresponding range in the memory image to the SPM of the processor core by sending SPM write instructions to the processor. Specifically, for each address range, the switching unit 450 can execute one or more SPM batch write instructions to copy the data at the corresponding position in the memory image to the same address range in the SPM.

[0172] In one specific implementation, the SPM write instruction includes the target physical address, source data location, and data length information. When the processor executes these instructions, the access logic unit 140 is responsible for writing the data into the SPM. Since the access logic unit 140 automatically marks the address access table 120 when executing the SPM write instruction, the switching unit 450 does not need to perform any additional operations to update the address access table 120. This feature simplifies the implementation of the loading operation and ensures that the address access table 120 correctly reflects the data distribution in the loaded SPM.

[0173] Step 3: Restore the address access table information.

[0174] Although the access logic unit 140 automatically marks the address access table 120 when the SPM write instruction is executed, since the write operation is performed region by region according to the address range saved in the memory image, these write operations themselves trigger the marking update of the address access table 120, so that the address access table 120 naturally contains the address access records of the process after loading. Therefore, in most implementations, the switching unit 450 does not need to perform an additional address access table information recovery operation. However, in some special cases (such as saving additional metadata during swapping out, or needing to restore other states related to the address access table), the switching unit 450 may also explicitly write the address access table information saved in the memory image back to the address access table 120, and this embodiment does not limit this.

[0175] Through the loading operation described above, the switching unit 450 can restore the SPM content of the suspended process from the memory image to the SPM of the processor core. Simultaneously, utilizing the automatic marking feature of the access logic unit 140, the records in the address access table 120 can be restored without additional operation. After loading is complete, the SPM content of the scheduled process is ready, and the process can continue to execute its subsequent SPM access instructions.

[0176] In some embodiments of this application, the driving unit 430 returns failure information to the process when allocation fails, and returns a success flag and the allocated virtual address to the process when allocation succeeds.

[0177] Specifically, in this embodiment, when a process requests SPM space from the driver unit 430 via an interface call, the driver unit 430 executes the aforementioned allocation process (querying the software space allocation table, allocation address, sending SPM allocation instructions, etc.). Based on the allocation result, the driver unit 430 returns the corresponding response information to the process.

[0178] If the allocation is successful (i.e., there is sufficient free space in the software space allocation table, and the hardware allocation logic unit successfully establishes the corresponding entry in the address mapping table), the driver unit 430 returns a success flag and the virtual address allocated to the process. After receiving the success flag and the virtual address, the process can use the virtual address to execute subsequent SPM access instructions.

[0179] If allocation fails (e.g., there is not enough free space in the software space allocation table, or the hardware allocation logic unit returns allocation failure information), the driver unit 430 returns a failure message to the process. After receiving the failure message, the process can handle it according to the specific situation, such as waiting for a period of time to retry the request, or using other alternative solutions.

[0180] Through the aforementioned return mechanism, the driver unit 430 provides the process with clear feedback on the SPM space allocation results, facilitating the process to perform corresponding flow control based on the allocation results.

[0181] In some embodiments of this application, the software space allocation table is maintained by the driver unit 430 to record the allocation status of each address space of the note-style cache. The driver unit 430 determines the location and size of the free space by querying the software space allocation table.

[0182] As mentioned above, the software space allocation table is a software data structure maintained in memory by the driver unit 430, such as a bitmap, a free list, or a free block list. This table records the allocation status of each address range in the overall SPM address space, including which address ranges have been allocated to which processes and which address ranges are currently in a free state.

[0183] When the driver unit 430 receives an SPM space allocation request from a process, it first queries the software space allocation table, traversing the allocation status of each address space to find if there is a contiguous free address range whose size meets the request requirements. If it exists, the location (starting physical address) and size of the free space are determined for subsequent allocation; if it does not exist, the allocation fails. After the driver unit 430 completes the SPM space allocation or release operation, it synchronously updates the software space allocation table, marking the corresponding address range as allocated or free, ensuring that the software space allocation table always reflects the latest SPM space allocation status.

[0184] In this embodiment, by maintaining the software space allocation table, the driver unit 430 can quickly learn about the overall usage of SPM space without relying on hardware, providing a basis for decision-making regarding the SPM space allocation of processes.

[0185] This application also provides a general-purpose processor, such as ​ As shown, it includes the note-type cache management device 410 and note-type cache 420 as described above, which will not be described in detail further.

[0186] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A note-style cache management device, characterized in that, include: The address mapping table is configured to represent the mapping relationship between the virtual addresses of stored processes and the physical addresses of note-based caches. The address access table is configured to record the address range information accessed by the process currently using the note cache; The allocation logic unit, coupled to the address mapping table and the address access table, is configured to: create an entry in the address mapping table in response to the execution of a note-style cache allocation instruction; In response to executing a note-style cache release instruction, the corresponding entry in the address mapping table is invalidated, and the record associated with the corresponding entry in the address access table is invalidated. The access logic unit, coupled to the address mapping table and the address access table, is configured to: in response to executing a note-based cache access instruction, perform a validity check on the access address according to the mapping relationship stored in the address mapping table, and perform a read / write operation on the note-based cache after the check passes; and mark the address range corresponding to this access in the address access table.

2. The note-style cache management device as described in claim 1, characterized in that, Each entry in the address access table includes: allocation table number, starting address, offset, and valid bits, used to record the address range accessed by the process.

3. The note-style cache management device as described in claim 1, characterized in that, Each entry in the address access table includes: an allocation table number, an access mask, and a valid bit, used to record the address range accessed by the process.

4. The note-style cache management device as described in claim 1, characterized in that, When executing the note-based cache access instruction, the access logic unit decouples the marking of the address access table from the read and write operations of the note-based cache.

5. The note-style cache management device as described in claim 1, characterized in that, The access logic unit is further configured to respond to a query instruction and, based on the process information given by the query instruction, return all entries of the corresponding process in the address access table.

6. The note-style cache management device as described in claim 1, characterized in that, When executing a note-based cache allocation instruction, the allocation logic unit searches for a free entry in the address mapping table, fills the process number, starting virtual address, starting physical address, and allocation size information carried by the allocation instruction into the free entry, and sets the valid bit of the free entry to true.

7. The note-style cache management device as described in claim 6, characterized in that, When the allocation logic unit executes the note-style cache release instruction, it finds the corresponding entry in the address mapping table based on the process number carried by the release instruction, invalidates all records belonging to the entry in the address access table according to the process number of the entry, and then invalidates the corresponding entry in the address mapping table.

8. The note-style cache management device as described in claim 1, characterized in that, The access logic unit performs a validity check on the access address by checking whether the valid bit of the corresponding entry in the address mapping table is true, and whether the access address is within the range defined by the allocated starting virtual address and the allocated size.

9. A note-style cache management system, characterized in that, Includes a note-type cache management device as described in any one of claims 1 to 8, and: The driving unit is configured to, in response to a process requesting note-style cache space, query the software space allocation table to confirm whether there is sufficient free space; if so, allocate virtual and physical addresses to the process, send a note-style cache allocation instruction to the allocation logic unit so that the allocation logic unit establishes a corresponding entry in the address mapping table, and updates the software space allocation table after allocation; and in response to a process releasing note-style cache space or the operating system reclaiming process resources, send a note-style cache release instruction to the allocation logic unit and synchronously update the software space allocation table. The scheduling unit is configured to schedule and manage processes that use note-style caching, where the note-style caching usage status of a process includes three states: unoccupied, occupied, and suspended. The switching unit is configured to perform a swap-out operation and a loading operation; wherein, the swap-out operation includes: when the scheduling unit schedules a process in a suspended state, obtaining the range of note-style cache addresses that the process to be swapped out has accessed recorded in the address access table through the access logic unit, and saving the corresponding content to the memory image according to the address range; the loading operation includes: loading the note-style cache content of the suspended process to be scheduled from the memory image to the note-style cache.

10. The note-style cache management system as described in claim 9, characterized in that, The scheduling unit is configured to: prioritize scheduling processes that are in an occupied state; when there are no schedulable processes in an occupied state, select the process to be scheduled from the processes in a suspended state.

11. The note-based cache management system as described in claim 10, characterized in that, When selecting a process to be scheduled from processes in a suspended state, if the remaining space in the note cache cannot meet the needs of the scheduled process, the scheduling unit first selects a process in an occupied state, calls the switching unit to perform a swap-out operation, and then loads the scheduled process.

12. The note-style cache management system as described in claim 11, characterized in that, When it is necessary to select a process to be scheduled from suspended processes, the scheduling unit prioritizes suspended processes with small note-style cache space requirements to avoid triggering a swap-out operation.

13. The note-style cache management system as described in claim 9, characterized in that, When the switching unit performs the swap-out operation, it first executes the query instruction of the access logic unit to obtain the range of accessed note cache addresses recorded in the address access table of the process to be swapped out. Then, based on the address range, it saves the note cache content of the corresponding range to the memory image through the note cache read instruction, and saves the relevant information in the address access table together.

14. The note-style cache management system as described in claim 9, characterized in that, When the switching unit performs the loading operation, it copies the contents of the note cache in the memory image to the note cache of the processor core by sending a note cache write instruction to the processor, based on the address range information stored in the memory image.

15. The note-style cache management system as described in claim 9, characterized in that, The driver unit returns a failure message to the process when allocation fails, and returns a success flag and the allocated virtual address to the process when allocation succeeds.

16. The note-style cache management system as described in claim 9, characterized in that, The software space allocation table is maintained by the driver unit and is used to record the allocation status of each address space of the note-style cache. The driver unit determines the location and size of the free space by querying the software space allocation table.

17. A general-purpose processor, characterized in that, Includes a note-type cache management device as described in any one of claims 1 to 8.

Images