A PCM-based DDR memory controller IP core

Abstract

The application discloses a PCM-based DDR memory controller IP core, and belongs to the technical field of semiconductor memory and integrated circuit design. The IP core comprises a UART interface and a group unpacking module, an AXI interface and an address mapping module, a PCM core control module, a DDR training and physical layer module, an ECC check and error correction module, and a clock and power supply control module. The UART interface and the group unpacking module are connected to an upper computer, the AXI interface and the address mapping module and the ECC check and error correction module are connected to a PS end, and the DDR training and physical layer module is connected to a PCM particle chip. The application solves the problem of insufficient high-frequency timing margin through a multi-dimensional adaptive training and VTC voltage temperature compensation mechanism, realizes efficient error correction function through a 16*16 polar code ECC scheme, solves the up and down power supply timing requirements through an intelligent power management scheme, and ensures the signal integrity and data reliability of the memory controller.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory and integrated circuit design technology, and specifically to a PCM-based DDR memory controller IP core. Background Technology

[0002] With the explosive growth in storage capacity demands from fields such as deep neural networks, big data, and high-performance computing, the need for research and development of non-volatile new storage technologies is expanding rapidly, driven by the "memory wall" problem. PCM, with its low access latency, high storage density, and extremely low static leakage power consumption, fully demonstrates its enormous potential to replace DRAM as the main memory medium. Meanwhile, the DDR memory controller, as a crucial bridge for data interaction between the CPU and memory, not only determines core parameters such as the supported storage type, storage capacity, and clock frequency, but also ensures a stable overall data access process. However, existing general-purpose DDR controllers are primarily designed for DRAM and cannot directly adapt to the physical layer timing characteristics of PCM. In addition, PCM suffers from thermal crosstalk and heat accumulation effects, read / write asymmetry, and write endurance issues. Traditional DDR memory controllers lack timing calibration and data preprocessing mechanisms tailored to the physical characteristics of PCM, resulting in narrow read / write windows and high data error rates, severely limiting the performance and reliability of PCM memory modules.

[0003] PCM (Polydimethylformamide) stores data based on the thermal phase transition characteristics of chalcogenide materials between crystalline (low resistance) and amorphous (high resistance) states. Its read / write process combines the Joule heating effect with a resistance difference detection mechanism. In the PCM phase transition programming write operation, a high-amplitude, short-duration current pulse (reset pulse) is applied externally to rapidly raise the temperature of the phase transition material above the amorphous melting point, followed by rapid annealing to achieve a high-resistance RESET operation (writing "0"). Alternatively, a medium-amplitude, long-duration current pulse (set pulse) is applied to heat the material above its crystallization temperature but below its melting point to achieve a low-resistance SET operation (writing "1"). In the PCM resistance detection read operation, a weak voltage, significantly lower than the phase transition threshold, is applied externally to the storage cell to detect the current flowing through it, thus determining its resistance state. A large current corresponds to a low-resistance state (crystalline, data "1"); a small current corresponds to a high-resistance state (amorphous, data "0"). However, since the phase transition process of PCM relies on physical heat accumulation and atomic rearrangement, it has inherent thermal crosstalk and heat accumulation effects, a read-write asymmetry problem caused by the write speed being significantly slower than the read speed, and a write endurance challenge caused by the large drive current during the write process.

[0004] Therefore, in order to reduce the high bit error rate caused by the thermal reliability problem of PCM and to adapt to the timing characteristics of the DDR physical layer of PCM chips, this invention proposes an innovative DDR memory controller IP core, which aims to solve the timing convergence and data reliability problems of PCM under the DDR protocol. Summary of the Invention

[0005] The purpose of this invention is to provide a PCM-based DDR memory controller IP core. It solves the problem of insufficient timing margin under high-frequency DDR interface through multi-dimensional adaptive training and VTC voltage and temperature compensation mechanism. Furthermore, it adopts a 16×16 polar code ECC scheme to achieve efficient error correction function. Combined with intelligent power management scheme, it ensures the signal integrity, data reliability and data throughput improvement of PCM memory controller.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A PCM-based DDR memory controller IP core includes: a UART interface and unpacking module, an AXI interface and address mapping module, a PCM core control module, a DDR training and physical layer module, an ECC check and error correction module, and a clock and power control module. The UART interface and unpacking module is connected to a host computer, the AXI interface and address mapping module and the ECC check and error correction module are connected to the PS terminal, and the DDR training and physical layer module is connected to the PCM chip. The modules are interconnected through internal hierarchical interconnection. The UART interface and group unpacking module are used to realize serial data transmission and protocol parsing with the host computer; The AXI interface and address mapping module are used to realize high-performance bus data transmission and protocol conversion between the PS end and the memory controller; The PCM core control module is used to manage the entire lifecycle control of the PCM chip from power-on initialization to normal read and write operations. The DDR training and physical layer module is used to realize signal training and calibration and physical layer data transmission and reception after the PCM particle chip is powered on. The ECC check and error correction module is used to add ECC redundancy check bits to the written data and to detect and correct errors in the read data. The clock and power control module is used to generate multiple clock signals required by each functional domain and to control the power-on, power-off and reset timing of multiple power rails of the PCM memory chip.

[0007] Furthermore, the UART interface and unpacking module includes a UART interface submodule, an unpacking and command parsing submodule, and a packet assembly and response submodule. The host computer is connected to the UART interface submodule, the UART interface submodule is connected to the unpacking and command parsing submodule, the unpacking and command parsing submodule is connected to the packet assembly and response submodule, and the unpacking and command parsing submodule and the packet assembly and response submodule are connected to the PCM core control module. The UART interface submodule is used to obtain serial write instruction data frames or read / write request instruction frames from the host computer, and return the corresponding response frames or read instruction data frames to the host computer. The unpacking and instruction parsing submodule is used to unpack and parse serial write instruction data frames or read / write request instruction frames. The packet assembly and response submodules are used to generate response frames or read instruction data frames.

[0008] Furthermore, the AXI interface and address mapping module adopts the standard AXI4 bus protocol, including the AXI-Full data path and the AXI-Lite data path. The AXI-Full data path is the data path between the PS end and the PCM core control module, and the AXI-Lite data path is the data path between the PS end and other functional modules.

[0009] Furthermore, the PCM core control module includes an initialization state machine and a working state machine. The initialization state machine is used to manage the power-on training sequence of the PCM chip, and the working state machine is used to schedule the execution of read and write commands during the normal working phase.

[0010] Furthermore, the DDR training and physical layer module includes a training control submodule, a command transmission submodule, a data processing submodule, and a DDR physical layer submodule. The training control submodule adopts a state machine architecture to manage the entire signal training and calibration process after the PCM chip is powered on. The command transmission submodule is used to convert high-level command requests issued by the PCM core control module into CA bus command sequences that conform to the DDR protocol timing specifications. The data processing submodule is used to implement data format conversion and buffer management between the internal data path of the PCM core control module and the data interface of the DDR physical layer submodule.

[0011] Furthermore, the ECC check and error correction module adopts an ECC encoding and decoding scheme based on 16×16 two-dimensional row and column polar codes, including an ECC encoder and an ECC decoder. The ECC encoder is used to add ECC redundancy check bits to the original data in the write operation data path, and the ECC decoder is used to perform error detection and correction on the PCM read data containing check bits in the read operation data path.

[0012] In summary, the present invention has at least one of the following beneficial technical effects: 1. Adopting a multi-dimensional adaptive training method: To address the unavoidable timing stability issues during high-speed DDR data stream transmission, this controller supports multi-dimensional training modes at the physical layer, including CS signal training, CA signal training, write equalization training, and DQ read / write training. It also innovatively introduces a VTC voltage and temperature compensation mechanism, which can sense changes in process, voltage, and temperature in real time and dynamically adjust signal delay. This enables comprehensive calibration of the PCM memory DDR interface, ensuring signal integrity of data stream and control stream in high-speed data transmission scenarios.

[0013] 2. Equipped with ECC polarity code encoding and decoding error correction technology: To address reliability issues such as thermal crosstalk and data flipping in PCM memory, this controller innovatively adopts a 16×16 matrix polarity code ECC error correction scheme to achieve single-bit error correction and double-bit error detection (SEC-DED) functions. Through two-dimensional cross protection of row and column checks, it effectively improves the data reliability of the controller and reduces hardware overhead with only an additional 16-bit check overhead. Its redundancy is reduced by 46.6% compared to the traditional Hamming code scheme.

[0014] 3. Intelligent Multi-Level Power Management Scheme: PCM memory requires complex multi-power domain support, including forward programming voltage (VPH), negative erase voltage (VNH), peripheral voltage (VPSH), and core voltage (VDD). The power-on sequence of different voltages directly affects chip lifespan and data reliability. Therefore, this controller implements four independently controllable intelligent power management units through a state machine, and achieves microsecond-level power ramp adjustment through a precisely programmable timing controller, ensuring that each power domain is powered on sequentially in a strict order.

[0015] 4. Ultra-high-speed serial-to-parallel conversion mechanism: To meet the ever-increasing interface speed requirements of DDR, this controller employs dedicated high-speed serial-to-parallel converters based on the Xilinx UltraScale+ architecture (ISERDES and OSERDES) at the physical layer to achieve an 8:1 data stream serial-to-parallel conversion, increasing its interface speed to four times that of traditional solutions. Furthermore, the controller fully utilizes the FPGA's IDELAY and ODELAY programmable delay units, allowing the delay of each data pin to be independently adjustable. Combined with the adaptive calibration mechanism of the training system, this achieves precise compensation for PCB trace differences and inter-chip deviations. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of the PCM-based DDR memory controller IP core of the present invention; Figure 2 A schematic diagram of the UART interface and group unpacking module structure; Figure 3 This is a schematic diagram of the AXI interface and address mapping module structure; Figure 4 This is a schematic diagram of the PCM core control module structure; Figure 5 To initialize the state machine's state transition timing diagram; Figure 6 This is a schematic diagram of the specific jump process of the working state machine; Figure 7 A schematic diagram of the training control submodule structure; Figure 8 This is a schematic diagram of the command transmission submodule structure; Figure 9 This is a schematic diagram of the data processing submodule structure; Figure 10 This is a schematic diagram of the DDR physical layer submodule structure; Figure 11 This is a schematic diagram of the ECC verification and error correction module structure; Figure 12 A schematic diagram of the clock and power control module; Figure 13 This is a schematic diagram of power supply control. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0018] like Figure 1 As shown, this invention provides a PCM-based DDR memory controller IP core, comprising: The system comprises a UART interface and unpacking module, an AXI interface and address mapping module, a PCM core control module, a DDR training and physical layer module, an ECC check and error correction module, and a clock and power control module. The UART interface and unpacking module is connected to the host computer, the AXI interface and address mapping module and the ECC check and error correction module are connected to the PS terminal, and the DDR training and physical layer module is connected to the PCM chip. The modules are interconnected through internal hierarchical interconnection. The UART interface and group unpacking module are used to realize serial data transmission and protocol parsing with the host computer; The AXI interface and address mapping module are used to realize high-performance bus data transmission and protocol conversion between the PS end and the memory controller; The PCM core control module is used to manage the entire lifecycle control of the PCM chip from power-on initialization to normal read and write operations. The DDR training and physical layer module is used to realize signal training and calibration and physical layer data transmission and reception after the PCM particle chip is powered on. The ECC check and error correction module is used to add ECC redundancy check bits to the written data and to perform error detection and correction on the read data; The clock and power control module is used to generate multiple clock signals required by each functional domain and to control the power-on, power-off and reset timing of multiple power rails of the PCM memory chip.

[0019] The present invention provides the top-level module global parameter definition of the PCM-based DDR memory controller IP core as shown in Table 1. Table 1 Global Parameter Definitions for Top-Level Modules

[0020] The top-level module digital interface definition of the PCM-based DDR memory controller IP core is shown in Table 2. Table 2 Top-level module digital interface definition

[0021] The following is a detailed introduction to each module: 1. UART interface and group unpacking module like Figure 2 As shown, the UART interface and packet / unpacking module are responsible for implementing serial data transmission and protocol parsing between the UART interface and the host computer on a pure FPGA development platform. This module uses the standard UART communication protocol, and through the packet / unpacking of serial data, it completes the reception and parsing of host computer commands and the encapsulation and transmission of PCM controller response data.

[0022] For UART write operations, the UART interface and the UART_RX module of the group unpacking module first receive the serial write command data frame from the host computer. Then, the write data frame undergoes serial-to-parallel data frame conversion via the CMD_PROC submodule. The unpacking module then performs CRC verification on the received data frame and identifies the frame header, opcode, write address field, data length, and payload data according to the communication protocol format. The write address is latched and a write request signal is generated and transmitted to the PCM core control module, while the write data is temporarily stored in an internal buffer. Once the PCM core control module is ready, the write data is read from the buffer and written to the PCM granular chip through the internal data path. After the write operation is completed, the group packet submodule generates an acknowledgment frame or a read command data frame, which contains the operation status code and write confirmation information. This frame is serialized by the UART_TX module and returned to the host computer, thus completing the closed-loop control of the entire write operation.

[0023] For UART read operations, the read operation process of the UART interface and the group / unpacking module is triggered by the host computer initiating a read / write request command frame. After the UART_RX module captures the read / write request command frame, the unpacking module performs a CRC check on the read request frame, identifies the read operation command type, and extracts the target read address and read data length information from the data frame. After ensuring that there are no errors, a read request signal and read address are generated and transmitted to the PCM core control module to initiate the read operation. After the PCM core control module completes the data reading from the storage particle, the read data is first sent back to the internal buffer of the grouping module. The grouping logic constructs a read response data frame according to the communication protocol format, including a frame header identifier, operation type, read address echo, data length field, and the actual effective data payload read. The grouping module calculates and adds a CRC check field to form a complete response frame structure. The data frame after grouping is sent to the UART_TX module and is serialized and sent byte by byte to the host computer at the set baud rate. In addition, the UART interface and group unpacking module also implement a timeout detection and retransmission mechanism. When the UART receives an incomplete data frame or a check error, it automatically generates an error response frame to notify the host computer to retransmit, thereby preventing erroneous data from entering the control flow.

[0024] 2. AXI interface and address mapping module like Figure 3As shown, the AXI interface and address mapping module is responsible for implementing high-performance bus data transmission and protocol conversion between the PS (Power Switch) and the PCM (PCM) core control module on the SoC development platform. This module adopts the standard AXI4 bus protocol, including the AXI-Full and AXI-Lite interfaces. AXI-Full supports efficient concurrency and burst operations and serves as the main data path between the CPU and memory controller. AXI-Lite, as a simplified version of AXI, is used for accessing control signals and mode registers. The AXI interface enables the reception of PS read / write requests, address resolution, data buffering, and response signal generation, bridging the transition from PS access instructions to internal operations within the PCM core control module.

[0025] For AXI-Full read / write operations, the AXI interface module's read / write channel first receives read / write address requests initiated by the PS end through the read / write address channel. After the read / write address handshake is completed, the corresponding address and burst parameters are latched into internal registers. For write operations, the write data channel sequentially receives burst data and byte strobe signals sent by the PS end. The write data is processed across clock domains and temporarily stored in the internal write data FIFO buffer. This module generates a write request signal based on the pre-configured command field in the AXI-Lite register and finally transmits it to the PCM core control module to initiate the write operation. When the WLAST signal for writing data is detected to be valid and the data in the write FIFO is ready, the PCM core control module reads the data from the write FIFO and writes it to the PCM memory chip through the internal data path. For read operations, after generating a read request signal, this module transmits it to the PCM core control module to initiate the read operation. After the PCM core control module completes the data reading from the memory chip, the read data is returned to the read data FIFO buffer through the internal data path, completing the cross-clock domain data transfer from the system clock domain to the AXI clock domain. After the read / write operation is completed, the AXI interface module returns a completion response status to the PS terminal through the read / write response channel, thereby realizing the closed-loop control of the entire AXI-Full burst read / write operation.

[0026] The AXI-Lite submodule is responsible for the configuration management and status monitoring of the controller IP core. The configuration register and status register maintained by this module are shown in Table 3. The configuration register supports functions such as runtime parameter adjustment, transmission control, and user soft reset, while the status register supports functions such as runtime status query.

[0027] Table 3. Schematic diagram of configuration registers and status registers

[0028] The AXI interface and address mapping module internally implement two levels of address mapping and decoding logic. At the AXI-Lite register level, this module maps the 32-bit aligned AXI byte address space to access addresses of eight internal registers, thus covering the register space from offset address 0x00 to 0x1C. For AXI-Lite write operations, the address decoding logic selects a branch based on the low-order field of the latched write address when write enable is valid, determining the target register to be written to. For AXI-Lite read operations, address decoding uses combinational logic to decode the read address in real time, sending the current value of the corresponding register to the read data output. At the AXI-Full data path level, the PS end pre-configures parameters such as command type, transmission length, and channel address through the AXI-Lite registers. Subsequently, burst read / write addresses initiated through the AXI-Full interface are transmitted to the PCM core control module. The core control module further converts the AXI linear address to the PCM memory particle physical address based on the configured channel address and command field, realizing a complete mapping link from PS-side byte addressing to PCM particle row and column addresses. For write operations that miss a valid register address space, the address decoding logic keeps all register values ​​unchanged, ensuring that illegal address writing will not interfere with the normal operation of the controller.

[0029] 3. PCM core control module like Figure 4 As shown, the PCM core control module is the core scheduling unit of the entire DDR memory controller IP core, responsible for managing the entire lifecycle control of the PCM storage chip from power-on initialization to normal read / write operations. This module adopts a two-layer state machine architecture, where the initialization state machine manages the power-on training sequence of the PCM chip, and the working state machine schedules the execution of read / write commands during the normal operation phase. The two work together to achieve complete operational control of the PCM chip.

[0030] After the reset release and controller ready signal are valid, the initialization state machine goes through the following stages in sequence: (1) Power-on phase (PWRUP): The module first sends a power-on request signal, and then enters the mode register configuration phase after waiting for the clock and power control modules to return a power-on response.

[0031] (2) Mode Register Configuration Stage (CFG_MRX): This module configures the seven mode registers (MR0~MR6) of the PCM chip sequentially according to a preset order, generating MRS write requests and corresponding register addresses and configuration data one by one through an internal counter. Among them, MR0 is used to configure read delay parameters, MR1 is used to configure address receive delay parameters, MR2 is used to configure burst length, MR3 is used to configure DLL reset, MR4 is used to configure DLL lock parameters, MR5 is used to configure termination resistor parameters, and MR6 is used to configure DQ check function. After completing the configuration of each mode register and waiting for a fixed timing interval, it automatically progresses to the configuration of the next register until all seven registers are configured.

[0032] (3) ZQ calibration phase (ZQCL): After the mode register is configured, the module sends a ZQ calibration request, waits for the calibration command to be transmitted and enters the ZQ calibration waiting phase. After the ZQ timing requirements are met by the internal timer counter, it enters the device identifier selection phase.

[0033] (4) Device ID Selection Phase (SELID): This module sends a device ID selection request and enters the working phase after the transmission is completed.

[0034] The state transition timing diagram for initializing the state machine is as follows: Figure 5 As shown.

[0035] In addition, the initialization state machine supports optional training processes such as Write Equalization Training (WLTM), DQ Read Training (DQRTM), DQ Write Training (DQWTM), and DQ Reference Voltage Training (DQVFTM). After entering the working phase, the initialization state machine can still respond to custom CS timing measurement requests and CA timing measurement requests from the AXI-Lite configuration register, temporarily jumping to the CSTM or CATM state to perform measurement operations, and returning to the WORK_PHASE state upon completion.

[0036] The working state machine only becomes active during the initialization state machine's WORK_PHASE phase. It is responsible for receiving read and write command requests from the AXI interface module or UART interface module and scheduling their execution. The working process of this state machine is as follows: After receiving a command while in the idle state WRRD_IDLE, the state machine first determines the command type and then jumps to the RD_CMD, WR_DATA, MRR_CMD, and MRS_CMD states respectively, based on the four types: read PCM, write PCM, read PCM register, and write PCM register. The RD_CMD state controls the CA and CS signals to send PCM read instructions. After sending, it enters the RD_DATA state, waits for data return, and then jumps to RD_CMD_END to determine whether to continue reading the next address or return to the WRRD_IDLE state. The WR_DATA state controls the writing of data into the FIFO of the read / write control module. After writing, it enters the WR_CMD state to control the CA and CS signals to send PCM write instructions. After all operations are completed, it enters the WR_CMD_END state. For read operations, it needs to determine whether to continue writing the next address or return to the WRRD_IDLE state. For write operations, which are different from read operations, it needs to enter the WR_WAIT state and wait for a period of time before returning to the WR_DATA state to operate on the next write address and data. MRR_CMD and MRS_CMD are similar, controlling the CA and CS signals to send the corresponding MRR and MRS instructions. After MRS is completed, it will directly return to the WRRD_IDLE state, while MRR will wait until the register is read before returning to the WRRD_IDLE state. Furthermore, because burst writes are supported, the state machine can transition from the WRRD_IDLE state to the WR_DATA state and then return to WRRD_IDLE, thus only sending data to the read / write control module without performing other operations. The specific transition process of the working state machine is as follows: Figure 6 As shown.

[0037] 4. DDR Training and Physical Layer Module The DDR training and physical layer module is the core module in the controller IP core responsible for DDR signal training and calibration, as well as physical layer data transmission and reception. This module handles the complete training sequence after the PCM memory chip powers on, including CS signal training (CSTM), CA address signal training (CATM), write equalization training (WLTM), DQ read training (DQRTM), and DQ write training (DQWTM), as well as DDR physical layer command transmission and data read / write functions during normal operation. This module integrates the training control submodule, command transmission submodule, data processing submodule, and DDR physical layer submodule through top-level encapsulation, realizing a complete conversion link from parallel data within the controller to the PCM chip's DDR physical interface signals.

[0038] In addition, the DDR training and physical layer module is responsible for distributing various training requests and read / write command requests issued by the PCM core control module to internal functional sub-modules, and aggregating the output signals of each sub-module to drive the physical interface pins of the PCM chip. This module receives training request signals and read / write command request signals from the core control module, selects the corresponding functional sub-module through internal enable logic, and outputs the corresponding physical layer interface signals. At the physical interface level, this module manages all DDR pin signals of the PCM chip, including differential clock (CK_P / CK_N), clock enable (CKE), chip select (CS), command address bus (CA), bidirectional data bus (DQ), differential data strobe (DQS_P / DQS_N), termination resistor control (ODT), wake-up signal (WAKE), and reset signal (RESET). This module uses multiplexing logic to route the CA, DQ, DQS, and other signals generated by the corresponding sub-modules to the physical pin output ports according to the current training or normal operation phase.

[0039] The following sections will explain each sub-module in detail: (1) Training control submodule like Figure 7 As shown, the training control submodule is responsible for managing the entire signal training and calibration process after the PCM storage chip is powered on. This module uses a state machine architecture to sequentially complete the following training stages: ① CS Chip Select Signal Training (CSTM): The CS signal training phase is used to calibrate the phase relationship between the output CS signal of the PCM controller and the CS signal received by the chip chip. When the PCM core control module issues a training request, this submodule enters the CSTM state and, by sending a specific CS training mode sequence to the PCM chip, collects the CS feedback signal returned from the chip and gradually adjusts the delay tap value of the output delay primitive until the CS signal meets specific requirements within the sampling window at the chip. A response signal is returned upon completion of training; if training fails, a failure request signal is issued. This training phase also supports manual configuration of the output mode via the CSTM register in the AXI-Lite register, facilitating manual CS signal calibration during the debugging phase.

[0040] ②CA Command / Address Signal Training (CATM): The CA address signal training phase is used to calibrate the signal integrity and timing alignment of the CA address bus. This module enters CATM state after a training request is triggered, sending a predefined training pattern to the CA bus of the PCM chip. It reads back the training feedback results from the chip via the data bus, compares the sent pattern with the read-back pattern, and adjusts the delay parameters of the CA signal path accordingly. This training process supports configuring the CA output value and data bus output value through the CATM register in the AXI-Lite register, enabling flexible control of the CA training mode.

[0041] ③ Write Equalization Training (WLTM): The write equalization phase is used to determine the optimal sampling delay of the write data relative to the clock signal. When the core control module issues a write equalization request during the WLTM_WAIT phase of the initialization state machine, the training module first initiates the PCM chip into write equalization training mode through a mode register write operation. Then, it sends a training pulse sequence to the DQS and acquires write equalization feedback from the chip end via the DQ bus. The training module gradually adjusts the phase offset between the DQS and DQ until the write equalization feedback indicates that the data is correctly sampled at the chip end. Upon completion of training, an acknowledgment signal is sent to the PCM core control module. If an abnormal feedback is detected during training, a training failure signal is generated. After receiving the write equalization training completion acknowledgment, the PCM core control module enters the WLTM_EXIT phase and exits the training mode.

[0042] ④ DQ Read / Write Training (DQRTM / DQWTM): DQ read training first generates a preamble detection timing sequence for calibrating the read DQS signal. Then, it sends a read training command to the PCM particle, progressively scanning the delay tap values ​​of the DQ and DQS input signals using the IDELAY primitive. It collects read data at each delay point, analyzes and determines the center position of the valid data window, and writes the optimal delay value into the IDELAY primitive to complete the timing calibration of the read path. The DQ write training submodule executes a similar process after the training request signal becomes valid, calibrating the timing relationship between the write data and the write strobe signal by adjusting the output delay tap value of the IDELAY primitive.

[0043] (2) Command transmission submodule like Figure 8As shown, the command transmission submodule is responsible for converting high-level command requests issued by the PCM core control module into CA bus command sequences conforming to the DDR protocol timing specifications. This module receives various command request signals from the PCM core control module, including normal write, normal read, non-volatile write, non-volatile read, burst write, burst read, forced write, mode register read / mode register write, ZQ calibration, and device identifier selection. Internally, this submodule employs a state machine architecture to generate corresponding DDR command frame sequences for different command types. For read / write commands, the module splits the 29-bit PCM address into row and column addresses according to the DDR protocol, and outputs them to the CA bus in a two-step command sequence of activation → read / write. The first step transmits the row address and bank address, and the second step transmits the column address and burst length parameters. For mode register write commands, the module encodes the mode register address and configuration data into a DDR MRS command format for output. For ZQ calibration commands, the module generates a ZQCL command frame. During command transmission, this submodule strictly adheres to the timing requirements of the chip select signal and clock enable signal specified by the DDR protocol. This submodule is also responsible for managing the power control timing of the PCM chip. When it receives an up / CS signal request, the module controls the timing of signals such as RESET, CKE, and CS to flip sequentially according to the DDR up / CS signal timing specification. When it receives a power-down request, it executes the power-down sequence according to the specification.

[0044] (3) Data processing submodule like Figure 9 As shown, the data processing submodule is responsible for data format conversion and buffer management between the internal data path of the PCM controller and the data interface of the DDR physical layer. In the write data path, the data processing submodule receives 64-bit parallel write DQ data and 8-bit DQS signals from the PCM core control module and the training control submodule, respectively, and selects the write data path output through the training valid signal. In addition, the write data path also includes DQS waveform generation logic for write preamble and write suffix to ensure that the write strobe signal meets the timing reception window requirements of the PCM chip. In the read data path, the data processing submodule converts the read DQ data returned by the DDR physical layer submodule into 64-bit parallel read data and outputs it to the PCM core control module. The read data path uses the DQS input strobe signal as the sampling clock for the DQ data to achieve source-synchronous data reception.

[0045] like Figure 10As shown, the DDR physical layer submodule is the lowest-level hardware abstraction of the PCM chip's read / write data path. It directly interfaces with Xilinx FPGA primitives such as IOSERDES, IODELAY, ODELAY, IDELAY, and IOBUF / IOBUFDS to achieve high-speed serial-to-parallel conversion of the DDR physical interface. Specifically, OSERDES converts parallel write data in the controller's internal SDR clock domain into serial output data at the DDR rate, driving the DQ pin; ISERDES captures the DDR-rate serial read data returned by the PCM chip and converts it into parallel data in the SDR clock domain for internal controller processing. ODELAY applies programmable fine-tuning to the DQ and DQS output signals, with the delay tap values ​​automatically calibrated and determined by training logic during write equalization training and DQ write training phases; IDELAY applies programmable fine-tuning to the DQ and DQS input signals, with the delay tap values ​​automatically calibrated and determined by training logic during the DQ read training phase. IOBUF / IOBUFDS implements bidirectional tri-state control of the DQ signal and bidirectional tri-state control of the DQS differential signal. It enables output drive during write operation and switches to high-impedance input mode during read operation.

[0046] 5. ECC verification and error correction module like Figure 11 As shown, the ECC check and error correction module is a key module in the PCM memory controller IP core responsible for ensuring data reliability. Since PCM storage chips may experience bit flip errors due to thermal reliability issues during repeated read and write operations, this module employs an ECC encoding and decoding scheme based on 16×16 two-dimensional row and column polarity codes to achieve single-bit error correction and double-bit error detection (SEC-DED) capabilities, thereby ensuring the integrity and reliability of stored data.

[0047] The ECC encoder is responsible for adding ECC redundancy check bits to the raw data in the write operation data path. This encoder uses a 16×16 row-column matrix encoding architecture. After receiving 240 bits (15 rows × 16 columns) of raw data, it first calculates the row parity value (15-bit row parity vector) and the column parity value (16-bit column parity vector) for each row of 16-bit data. Then, it performs grouped XOR compression operations on the row and column parity vectors respectively. Specifically, according to specific grouping rules (alternating parity, pairwise grouping, 4x4 grouping, 8x8 grouping), the 15-bit row parity vector is compressed into an 8-bit row parity bit (RP), and the 16-bit column parity vector is compressed into an 8-bit column parity bit (CP). After encoding, the encoder concatenates 240 bits of raw data, 8 bits of row checksums, and 8 bits of column checksums into a 256-bit encoded codeword in the format {CP[7:0], RP[7:0], Data[239:0]}. The lower 240 bits are the valid data payload, and the higher 16 bits are ECC redundancy check bits. In addition, the encoder integrates state machine control logic and supports a backpressure mechanism. When the downstream module is not ready, the encoder pauses output and holds the encoded data until the downstream module is ready.

[0048] The ECC decoder is responsible for error detection and correction of the PCM read data containing parity bits in the read operation data path. After receiving the 256-bit encoded codeword, the decoder uses a six-level state machine to perform the following processing sequentially: First, in the data loading stage, 240 bits of data payload, 8 bits of receive row parity (RP_rx), and 8 bits of receive column parity (CP_rx) are separated from the codeword, and the data payload is reassembled into a 15-row × 16-column matrix; then, in the first calculation stage, row and column parity check operations are re-performed on the data matrix to generate local row parity vectors and column parity vectors; in the second calculation stage, the local parity vectors are subjected to the same block XOR compression as the encoder to obtain local row parity (RP_calc) and column parity (CP_calc); in the comprehensive check stage, the receive parity is XORed bit by bit with the local parity to generate row parity composites (s_rp) and column parity composites (s_cp); in the error location stage, the decoder performs mode discrimination on the composites. Error address parsing—by detecting whether each two bits of the synastry satisfy the complementary pattern (01 or 10), it is determined whether it is a correctable single-bit data error. At the same time, the number of 1s in the synastry is counted to distinguish the error type. A 4-bit row error address and a 4-bit column error address are extracted from the odd-numbered bits of the synastry and concatenated into an 8-bit error bit index. Finally, in the output stage, three error states are output based on the synastry analysis results: when both the row and column synastry are all zeros, it is determined to be an error-free error, and the original data is directly output; when both the row and column synastry satisfy the complementary pattern, it is determined to be a single-bit data error, and the data bit pointed to by the error bit index is flipped to correct it before outputting the error-corrected data; when only a single bit of the synastry is 1, it is determined to be an error in the parity bit itself, and the original data is output without modification; in other cases, it is determined to be a double-bit or higher uncorrectable error, and the original data is output and the error state is marked to notify the upper-layer module.

[0049] 6. Clock and power control module like Figure 12 As shown, the clock and power control module is the infrastructure module in the PCM memory controller IP core responsible for global clock generation and distribution, as well as power timing control of the PCM memory chips. This module is mainly responsible for generating multiple clock signals required by each functional domain of the controller from an external differential reference clock, and for controlling the power-on, power-off, and reset timing of multiple power rails of the PCM memory chips.

[0050] In terms of clock management, this module first sends the external input clock (clkin) to the Mixed Mode Clock Manager (MMCM) for frequency synthesis. Internally, the MMCM generates four different frequency clock outputs through parameterizable multiplication factors and four independent division factors: a delay calibration reference clock (dcl_ref_clk), a PCM physical layer operating clock (pcm_clk), a system clock (sys_clk), and a PCM chip clock (CK_out). These are then distributed to various functional modules after passing through a global clock buffer (BUFG). Specifically, dcl_ref_clk provides a precise delay calibration reference for the IDELAY and ODELAY delay primitives in the physical layer module; pcm_clk, as the core operating clock for the DDR physical layer serial-to-parallel conversion module and command transmission module, supports multiple frequency configurations ranging from 5MHz to 100MHz; sys_clk serves as the master clock for each functional module of the controller, used for the data transmission and reception logic; and CK_out is used for the electrical connection of the CK port of the PCM chip and is the internal reference clock of the chip.

[0051] like Figure 13 As shown, in terms of power control, this module uses an 8-state finite state machine to manage the power-on and power-off sequences of the four power rails of the PCM memory chip. Upon receiving the rising edge of the power-on request signal (pwr_up_req) from the PCM core control module, it sequentially enables each power rail and controls the initialization pin signals of the PCM chip according to the following strict timing sequence: core voltage VDD → peripheral voltage VPSH → positive programming voltage VPH → negative erase voltage VNH. The delays between each stage are implemented using an internal 24-bit general-purpose timer / counter and a variable target value register. When the PCM controller is in the READY state, the module can respond to both power-off requests (pwr_down_req) and reset requests (rst_req). For a power-off request, the state machine first transitions from the READY state to the VNH state, and then sequentially shuts down each power rail in the strict reverse order of the power-on sequence, with a safety interval of 100μs to 200μs between each stage. This symmetrical power-down timing design avoids the risk of latch-up or floating voltage damage caused by improper power rail turn-off sequence within the PCM chip. For reset requests during normal operation, the state machine transitions from the READY state to the VNH state, pulling down the RESET_n and CKE signals to perform a software reset on the PCM chip. It then reverts to the READY state through the RESET→CKE→READY initialization sequence, without needing to re-execute the power rail power-on / off operations. The reset request signal is reliably captured in the READY state through a latching mechanism and is automatically cleared after the reset process is complete.

[0052] Embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0053] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0054] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0055] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0056] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A PCM-based DDR memory controller IP core, characterized in that, include: The system comprises a UART interface and unpacking module, an AXI interface and address mapping module, a PCM core control module, a DDR training and physical layer module, an ECC check and error correction module, and a clock and power control module. The UART interface and unpacking module is connected to the host computer, the AXI interface and address mapping module and the ECC check and error correction module are connected to the PS terminal, and the DDR training and physical layer module is connected to the PCM chip. The modules are interconnected through internal hierarchical interconnection. The UART interface and group unpacking module are used to realize serial data transmission and protocol parsing with the host computer; The AXI interface and address mapping module are used to realize high-performance bus data transmission and protocol conversion between the PS end and the memory controller; The PCM core control module is used to manage the entire lifecycle control of the PCM chip from power-on initialization to normal read and write operations. The DDR training and physical layer module is used to realize signal training and calibration and physical layer data transmission and reception after the PCM particle chip is powered on. The ECC check and error correction module is used to add ECC redundancy check bits to the written data and to detect and correct errors in the read data. The clock and power control module is used to generate multiple clock signals required by each functional domain and to control the power-on, power-off and reset timing of multiple power rails of the PCM memory chip.

2. The PCM-based DDR memory controller IP core according to claim 1, characterized in that, The UART interface and unpacking module includes a UART interface submodule, an unpacking and command parsing submodule, and a packet assembly and response submodule. The host computer is connected to the UART interface submodule, the UART interface submodule is connected to the unpacking and command parsing submodule, the unpacking and command parsing submodule is connected to the packet assembly and response submodule, and the unpacking and command parsing submodule and the packet assembly and response submodule are connected to the PCM core control module. The UART interface submodule is used to obtain serial write instruction data frames or read / write request instruction frames from the host computer, and return the corresponding response frames or read instruction data frames to the host computer. The unpacking and instruction parsing submodule is used to unpack and parse serial write instruction data frames or read / write request instruction frames. The packet assembly and response submodules are used to generate response frames or read instruction data frames.

3. The PCM-based DDR memory controller IP core according to claim 2, characterized in that, The AXI interface and address mapping module adopts the standard AXI4 bus protocol, including the AXI-Full data path and the AXI-Lite data path. The AXI-Full data path is the data path between the PS end and the PCM core control module, and the AXI-Lite data path is the data path between the PS end and other functional modules.

4. The PCM-based DDR memory controller IP core according to claim 3, characterized in that, The PCM core control module includes an initialization state machine and a working state machine. The initialization state machine is used to manage the power-on training sequence of the PCM chip, and the working state machine is used to schedule the execution of read and write commands during the normal working phase.

5. A PCM-based DDR memory controller IP core according to claim 4, characterized in that, The DDR training and physical layer module includes a training control submodule, a command transmission submodule, a data processing submodule, and a DDR physical layer submodule. The training control submodule adopts a state machine architecture to manage the entire signal training and calibration process after the PCM chip is powered on. The command transmission submodule is used to convert high-level command requests issued by the PCM core control module into CA bus command sequences that conform to the DDR protocol timing specifications. The data processing submodule is used to implement data format conversion and buffer management between the internal data path of the PCM core control module and the data interface of the DDR physical layer submodule.

6. The PCM-based DDR memory controller IP core according to claim 5, characterized in that, The ECC check and error correction module adopts an ECC encoding and decoding scheme based on 16×16 two-dimensional row and column polar codes, including an ECC encoder and an ECC decoder. The ECC encoder is used to add ECC redundancy check bits to the original data in the write operation data path, and the ECC decoder is used to perform error detection and correction on the PCM read data containing check bits in the read operation data path.

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