Memory control method and storage device

Abstract

The application belongs to the field of memory control, and provides a memory control method and a memory device. The method comprises the following steps: in response to the number of idle blocks being less than a first number threshold and not less than a second number threshold, selecting at least one block with a valid page ratio lower than a first ratio threshold as a first target block; calculating a first execution rate according to the difference ratio of the number of idle blocks, the first number threshold and the second number threshold, and performing a data moving operation on the first target block at the first execution rate; if the current number of idle blocks is less than the second number threshold and not less than a third number threshold, selecting at least one block as a second target block; performing a data moving operation on the second target block at a second execution rate; if the number of idle blocks is less than the third number threshold, selecting at least one block as a third target block; and performing a data moving operation on the third target block at a maximum execution rate. The host performance and the efficiency of garbage collection are balanced, and the performance of the memory device is stabilized.

Description

Technical Field

[0001] This application relates to the field of memory control, and more particularly to a memory control method and a memory device. Background Technology

[0002] In flash memory storage devices, due to the inherent characteristics of the flash media, existing data must be erased before it can be written. Therefore, storage controllers typically employ garbage collection mechanisms to reclaim flash blocks containing invalid data, ensuring that there are enough free blocks available for host writing.

[0003] In traditional solutions, the storage controller sets a fixed threshold for the number of free blocks. When the number of free blocks falls below this threshold, the controller triggers a garbage collection process, selecting some blocks from the used blocks for data migration and erasure. During this process, data migration and erasure compete with host write requests for system bandwidth, leading to a noticeable decrease in write performance. If the host continues to write, the number of free blocks may further decrease, forcing the system to perform garbage collection at a higher intensity. In this process, write performance often declines in a step-like manner, and in severe cases, may even experience a precipitous drop, significantly impacting the user experience. Summary of the Invention

[0004] In view of this, this application provides a memory control method and a storage device to solve the technical problem in the prior art where garbage collection operations and host write requests compete for system resources, resulting in a significant decrease in write performance.

[0005] Embodiments of this application provide a memory control method applied to a storage device including a memory module and a memory controller. The method includes: responding to a current number of free blocks in the memory module being less than a first number threshold and not less than a preset second number threshold, selecting at least one block from the memory module with an effective page ratio lower than a preset first ratio threshold as a first target block; calculating a first execution rate based on the ratio of the difference between the current number of free blocks, the first number threshold, and the second number threshold, wherein the first execution rate is negatively correlated with the ratio of the difference; performing a data migration operation on the first target block at a rate not exceeding a first bandwidth upper limit, according to the first execution rate, to generate free blocks, wherein the first bandwidth upper limit is lower than the peak bandwidth of the storage device; if the current number of free blocks is less than the second number threshold... If the number of free blocks is less than the third quantity threshold, then at least one block is selected from the memory module as the second target block; a data migration operation is performed on the second target block at a second execution rate to generate a free block, wherein the second execution rate is greater than the first execution rate and is limited by a second bandwidth limit, the second bandwidth limit being higher than the first bandwidth limit and lower than the peak bandwidth of the storage device; if the current number of free blocks is less than the third quantity threshold, then at least one block is selected from the memory module as the third target block; a data migration operation is performed on the third target block at a maximum execution rate to generate a free block, wherein the maximum execution rate is greater than the second execution rate and is limited by the peak bandwidth of the storage device, and the first quantity threshold, the second quantity threshold, and the third quantity threshold are preset values ​​that decrease sequentially.

[0006] An embodiment of this application further provides a storage device including a connection interface for electrically connecting to a host system; a memory module including multiple planes, each plane including multiple blocks, each block including multiple pages; and a memory controller including error checking and correction circuitry, a buffer memory, and memory control circuitry, electrically connected to the connection interface and the memory module; wherein the memory controller is configured to perform the memory control method described above.

[0007] Based on the above, the memory control method and storage device proposed in the embodiments of this application select target blocks in stages and dynamically set the garbage collection execution rate according to the relationship between the current number of free blocks and the first, second, and third quantity thresholds. When there are many free blocks, blocks with a low effective page ratio are moved at a low rate; when free blocks are scarce, they are moved at a medium-to-high rate; and when free blocks are extremely scarce, they are moved at the peak rate with full force. It further includes: using buffer memory to serve host read requests and forcibly clearing them in emergencies; a write request bypass mechanism; partial moving and temporary storage areas; consumption rate prediction closed-loop control; time-slice round-robin scheduling; variable-granularity batch processing; dynamic parallel granularity; merge-and-move optimization; temperature-sensing speed adjustment; and batch erase delayed release. This application achieves a balance between host performance and garbage collection efficiency through three-level rate control and multiple auxiliary mechanisms, effectively improving the performance of the storage device, write amplification control, and high-temperature reliability.

[0008] To make the above-mentioned objectives, technical solutions and beneficial effects of this application more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, and these are all within the protection scope of this application.

[0010] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of this application; Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application; Figure 3 This is a schematic diagram of a memory management module according to an embodiment of this application; Figure 4 This is a schematic diagram illustrating the division of a buffer memory into multiple cache areas according to an embodiment of this application; Figure 5 This is a general flowchart of a memory control method according to an embodiment of this application; Figure 6 This is a flowchart illustrating a memory control method according to an embodiment of this application. Detailed Implementation

[0011] Reference will now be made in detail to exemplary embodiments of this application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0012] Figure 1This is a schematic diagram of a data storage system according to an embodiment of this application. Please refer to... Figure 1 The data storage system 10 includes a host system 11 (which may be simply referred to as the host) and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, automotive infotainment system, advanced driver assistance system (ADAS), game console, server, or computer system located in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. Furthermore, the storage device 12 may include a solid-state drive (SSD), universal flash storage (UFS), embedded multi-media card (eMMC), USB flash drive, memory card, or other types of non-volatile storage devices. It is particularly suitable for fields with stringent requirements for reliability, data integrity, environmental tolerance, and long-term stability, such as industrial control, edge computing, and automotive electronics.

[0013] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multimedia cards, general-purpose flash memory, Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0014] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include single-level cell (SLC) NAND flash memory modules, multi-level cell (MLC) NAND flash memory modules, triple-level cell (TLC) NAND flash memory modules, quadruple-level cell (QLC) NAND flash memory modules, and / or other memory modules with the same or similar characteristics. For multi-level cell (MLC, TLC, QLC, and PLC) flash memory modules, specially selected and tested flash memory modules that meet the requirements of wide operating temperature (e.g., -40°C to 105°C or higher), high durability, and data retention can be used.

[0015] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller. In particular, for automotive functional safety requirements, the architecture of memory controller 123 may include safety islands, dual-core lockstep, or other redundancy and monitoring mechanisms to ensure the reliability of control logic.

[0016] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in this application. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0017] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host system interface 21, a memory interface 22, and a memory control circuit 23. The host system interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0018] Memory control circuitry 23 is connected to host system interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host system interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0019] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and controlled by the memory controller 123 to cache data. For example, the buffer memory 24 can be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. Specifically, the logical-to-physical mapping table and its higher-level address management unit are typically resident or cached in the buffer memory 24 to support high-speed access and updates. To ensure the reliability and consistency of the mapping table data (described in detail below) in the event of sudden events such as abnormal power failures, the buffer memory 24 may employ a storage medium with power loss protection (PLP) characteristics or incorporate a backup capacitor design to ensure that critical metadata has sufficient time to be written into the memory module 122.

[0020] In one embodiment, the memory controller 123 may further include an error checking and correction circuit 25. The error checking and correction circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the error checking and correction circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code.

[0021] In one embodiment, the memory controller 123 may also include other types of various circuit modules (e.g., power management circuits, etc.), which are not limited in this application.

[0022] In one embodiment, the memory controller 123 may further include a power management circuit 26. The power management circuit 26 is connected to the memory control circuit 23 and is used to control the power supply of the storage device 12. The power management circuit 26 not only manages conventional power consumption, but also meets the complex power sequences and low static power consumption requirements of automotive electronics, and can handle voltage fluctuations during vehicle start-stop processes, ensuring that the storage device 12 operates stably in harsh power environments.

[0023] Figure 3 This is a schematic diagram illustrating a memory management module according to an embodiment of this application. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1)-301(B). Each physical unit includes multiple storage units for non-volatile data storage.

[0024] In one embodiment, an entity unit may include an entity programming unit. In one embodiment, an entity programming unit is also referred to as an entity programming unit. In one embodiment, an entity programming unit may be considered as an entity page.

[0025] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and this application is not limited thereto. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and this application is not limited thereto.

[0026] In one embodiment, a physical programming unit is the smallest unit of data to be synchronously written in the memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0027] In one embodiment, an entity erasure unit may include multiple entity programmable units. In another embodiment, an entity erasure unit may be considered as an entity block.

[0028] In one embodiment, multiple programmed units in a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to multiple programmed units in this physical erase unit to change the threshold voltage of at least some of the memory cells in these programmed units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased.

[0029] In one embodiment, the memory control circuit 23 can logically associate entity units 301(0)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(0)-301(A) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0030] In one embodiment, if a physical unit does not store valid data, this physical unit can be associated with the free area 32. Furthermore, physical units in the free area 32 can be erased to clear the data within them. In one embodiment, physical units in the free area 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as the free pool.

[0031] In one embodiment, in response to the requirements of predictable storage lifetime for industrial and automotive applications, the memory control circuit 23 can implement wear leveling and bad block management strategies, and monitor the number of erase / write cycles, read counts, and data retention time of each physical unit in real time, so as to provide the host system 11 with a health status report and remaining lifetime prediction of the storage device 12, thereby meeting the diagnostic coverage requirements of relevant functional safety standards.

[0032] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used cyclically between the data area 31 and the idle area 32.

[0033] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(0)-302(C) to map physical units (i.e., physical units 301(0)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0034] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0035] In one embodiment, the memory control circuit 23 may record the mapping relationship between logical units and physical units in at least one management table (also known as a logic-to-physical mapping table, or L2P table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logical address to physical address mapping table).

[0036] Figure 4 This is a schematic diagram of a buffer memory 24 shown in one embodiment of this application.

[0037] Please refer to Figure 4 The buffer memory 24 has buffer units 510-51D, each with a capacity of, for example, 4KB, which is aligned with the typical small block I / O size of the host system 11. Specifically, the capacity of the four buffer units corresponds to the capacity of one physical programmable unit of the memory module 122 (i.e., a page size of 16KB). However, it must be understood that this embodiment does not limit the number of buffer units configured in the buffer memory 24, the capacity of the buffer units, or the size of the data transmitted by the host system 11. Furthermore, the host system 11 transmits or accesses data, for example, in units of 4KB. Alternatively, in another embodiment, the capacity of the data transmitted or accessed by the host system 11 each time may be greater than or less than 4KB.

[0038] Figure 5 This is a general flowchart of a memory control method according to an embodiment of the present invention. The method is applied to a storage device 12 including a memory module 122. A memory control circuit 23 or a memory controller 123 is configured to execute this method, which first divides the storage into multiple garbage collection (GC) levels based on the number of free blocks and dynamically adjusts the moving rate during the garbage collection operation. Garbage collection refers to the operation of moving valid data from one or more source blocks to free blocks, and then erasing the source blocks to obtain new free blocks. The method begins at step S501.

[0039] S501: The memory controller 123 detects the number of currently free blocks (blocks that have been erased and do not contain any valid data) in the memory module 122. When the number of free blocks is less than a first threshold (e.g., 100) and not less than a preset second threshold (e.g., 50), at least one block with an effective page ratio lower than a preset first ratio threshold (e.g., 30%) is selected from the memory module 122 as the first target block. The selection strategy can be based on sorting the blocks from low to high based on their effective page ratio, prioritizing the block with the lowest effective page ratio to minimize relocation overhead. Here, the effective page ratio refers to the percentage of pages in a block that currently store valid data out of the total number of pages in that block.

[0040] S502: Calculate the first execution rate based on the ratio of the difference between the current number of free blocks, the first quantity threshold, and the second quantity threshold.

[0041] Specifically, the difference ratio is defined as (first quantity threshold - current number of free blocks) / first quantity threshold - second quantity threshold), with a value range of [0, 1]. The first execution rate is negatively correlated with this difference ratio; for example, the first execution rate = base rate × (1 - difference ratio), where the base rate can be set to 50 MB / s. When the number of free blocks approaches the second quantity threshold (difference ratio approaches 1), the first execution rate approaches 0; when the number of free blocks approaches the first quantity threshold (difference ratio approaches 0), the first execution rate reaches the base rate.

[0042] S503: The memory controller 123 performs a data transfer operation (i.e., garbage collection) on the first target block at a rate not exceeding a first bandwidth limit (e.g., 200 MB / s) and according to a calculated first execution rate, thereby generating new free blocks. The first bandwidth limit is lower than the peak bandwidth of the storage device 12 (e.g., 800 MB / s) to ensure the read / write performance of the host system 11. The bandwidth limit refers to the maximum data transfer bandwidth (in MB / s) set by the memory controller 123 for the garbage collection operation, which is lower than the peak bandwidth of the storage device 12.

[0043] S504: If the current number of free blocks is less than the second quantity threshold (50) and not less than the preset third quantity threshold (10), then at least one block is selected from the memory module 122 as the second target block. When selecting the second target block, blocks with a higher effective page ratio (e.g., >50%) can be considered because the pressure on free blocks increases at this time, and more space needs to be reclaimed as soon as possible.

[0044] S505: Perform a data shift operation on the second target block at a second execution rate to generate a free block. The second execution rate is greater than the first execution rate and is limited by a second bandwidth limit (e.g., 500 MB / s), which is higher than the first bandwidth limit but lower than the peak bandwidth of the storage device 12. In one example, the second execution rate is fixed at 300 MB / s.

[0045] S506: If the current number of free blocks is lower than the third quantity threshold (10), then at least one block is selected from memory module 122 as the third target block. At this time, free blocks are extremely scarce, and garbage collection needs to be carried out with maximum effort.

[0046] S507: Perform a data shift operation on the third target block at the maximum execution rate to create a free block. The maximum execution rate is greater than the second execution rate and is limited by the peak bandwidth of storage device 12 (e.g., 800 MB / s). This rate can be set to the highest garbage collection rate that the memory controller can support (e.g., 600 MB / s), while allowing full bandwidth preemption during periods of idle read / write activity on the host system.

[0047] It should be emphasized that the first quantity threshold, the second quantity threshold, and the third quantity threshold mentioned above are preset values ​​and decrease sequentially.

[0048] Through the above three-level rate control, this embodiment performs slight garbage collection when there are enough free blocks, gradually increases the garbage collection intensity when there are few free blocks, and finally fully collects free blocks in an emergency, thereby achieving a balance between the performance of the host system 11 and the efficiency of garbage collection.

[0049] In one embodiment, to further optimize read performance during garbage collection and reduce interference with the host system 11, the present invention also introduces a buffer memory management mechanism. Figure 5 In addition to the method, the following operations are also included, such as Figure 6 As shown. Figure 6 This is a flowchart illustrating a memory control method according to an embodiment of the present invention. The method is applied to a storage device 12 including a memory module 122. A memory control circuit 23 or a memory controller 123 is configured to execute this method.

[0050] S601: During the data transfer operation to the first target block, the second target block, or the third target block, the transferred valid data is cached in buffer memory 24 (its capacity is, for example, 256KB). This buffer memory is divided into multiple page-sized cache units (Buffers) such as... Figure 4 As shown. When moving valid pages of each source block, the page data is first read into buffer memory 24, and then written to the target free block.

[0051] S602: Upon receiving a read request from host system 11, the buffer memory 24 is searched first. If the logical address of the requested data happens to match a cache unit in buffer memory 24 (i.e., the data has just been moved but not yet written to memory module 122, or resides there due to a previous pre-read operation), the data is returned directly from buffer memory 24 without accessing memory module 122. This reduces read latency. Furthermore, after a hit occurs, the original data page in the source block corresponding to the hit data is marked as no longer needing to be moved (e.g., the corresponding bit is cleared in the block's valid page bitmap), thereby reducing the urgency of moving the block to which it belongs. Thus, when subsequent garbage collection scans the block, it will skip the page, avoiding repeated moving.

[0052] S603: If the current number of free blocks is lower than the third threshold (i.e., at the most urgent garbage collection level), then the buffer memory 24 is prohibited from being used to serve cache hits for read requests (i.e., all read requests directly skip the buffer memory 24 and read from the memory module 122), and the data in the buffer memory 24 is forced to be written to the target block first, and the buffer memory 24 is cleared as soon as possible for subsequent garbage collection relocation operations. This mechanism ensures that when free blocks are extremely scarce, the garbage collection relocation operation will not be halted due to read requests occupying the cache, thereby prioritizing the generation rate of free blocks.

[0053] Through the above-described buffer memory management, this embodiment improves the read hit rate in the normal garbage collection mode and ensures the real-time performance of garbage collection in the emergency mode.

[0054] In one embodiment, to address host write blocking in extreme cases, this embodiment provides a write request bypass mechanism.

[0055] Specifically, when the number of free blocks is lower than the third quantity threshold and the data transfer operation is performed on the third target block at the maximum execution rate, it continuously detects whether any host write requests are continuously blocked for more than a preset blocking time threshold (e.g., 50 milliseconds).

[0056] If it exists, it indicates that garbage collection has severely impacted the host system's write response. Therefore, a high-priority write reserved block is temporarily created, meaning at least one free block is reserved from the free block list specifically for responding to host write requests, and this reserved block is excluded from the garbage collection relocation target block pool. In other words, garbage collection relocation operations cannot use this reserved block as a target block, thus ensuring that host writes always have available free blocks.

[0057] Then, after the reserved blocks are allocated, if the current number of free blocks (including reserved blocks) is still lower than the third quantity threshold (for example, the total number is still less than 10 after reserving 2 blocks), the write request bypass mechanism in the emergency garbage collection mode is triggered.

[0058] The write request bypass mechanism involves directly writing host write data to a pre-allocated emergency free block, instead of the third target block currently being garbage collected and moved. Simultaneously, this emergency free block is logically swapped with the current garbage collection target block, and the mapping table is updated, allowing subsequent moving operations to skip overwritten logical addresses. The emergency free blocks are dynamically obtained from a reservation pool, and their number does not exceed a preset emergency block limit.

[0059] For example, suppose the current garbage collection is moving a third target block A (logical address range LBA_X~LBA_Y), and the host needs to write LBA_Z (which belongs to the range of A). An urgent free block B is taken from the reservation pool, the host data is written to B, and then the physical address of LBA_Z in the mapping table is changed from a page in A to a page in B, and the corresponding page in A is marked as invalid. Subsequently, when the garbage collection scans that page in A, it finds that the mapping has been redirected and skips the move. The number of urgent free blocks does not exceed a preset urgent block limit (e.g., 2 blocks) to avoid excessive consumption of reservation resources.

[0060] The aforementioned bypass mechanism is only enabled when there is at least one third target block with a valid page ratio higher than a preset emergency threshold (e.g., 80%), to prevent valid data from being accidentally overwritten, resulting in the loss of a large amount of valid data. When there is no qualified third target block, bypass is not enabled even if the host write request is blocked, and the system continues to wait for garbage collection to generate free blocks.

[0061] Through the write request bypass mechanism described above, this embodiment can still ensure the continuity of host writes under extreme garbage collection pressure, thereby improving the service quality of storage device 12.

[0062] In one embodiment, to improve the efficiency of free block generation under moderate waste collection pressure, this embodiment proposes a partial relocation mode.

[0063] Specifically, when the number of free blocks is less than the second threshold and not less than the third threshold (i.e., at an intermediate garbage collection level), when performing a data migration operation on the second target block, all valid pages in the block are not migrated, and a partial migration mode is adopted.

[0064] Specifically, only the top P pages with the highest percentage of valid pages in the second target block are moved.

[0065] The calculation method for P is: P = Total number of pages in the second target block × Relocation scaling factor. The relocation scaling factor is less than 1 and is positively correlated with the pressure factor. The pressure factor is defined as: (Second quantity threshold - Current number of free blocks) / (Second quantity threshold - Third quantity threshold), with a value range of [0, 1]. For example, when the pressure factor is 0.2, the relocation scaling factor can be set to 0.3; when the pressure factor is 0.8, the relocation scaling factor can be set to 0.7.

[0066] When choosing which pages to move, first sort all valid pages of the block by their offset addresses, but it is preferable to sort by the page with the highest proportion of valid pages.

[0067] In detail, move the page combinations that minimize the number of remaining valid pages. For example, count whether each page in the block is valid, then scan in page order and move the valid pages on both sides of consecutive invalid page regions. However, to reduce complexity, a strategy can be adopted to move the first P pages with the highest concentration of valid pages in the block, that is, select the sub-region with the highest density of valid pages for moving, so that the number of remaining valid pages is minimized after erasing the block.

[0068] When performing an erase operation on the second target block after partial relocation, the remaining valid page data is remapped into the mapping table, pointing to a new temporary storage area. This temporary storage area is a small number of high-endurance flash memory blocks (e.g., blocks using SLC mode) reserved for storage device 12, with a fixed capacity limit (e.g., 1% of the total capacity). Each remaining valid page is individually mapped to a free page in the temporary storage area.

[0069] When the staging area is full or the number of current free blocks rises back above the second threshold, a merge operation is initiated: the valid page data in the staging area is read out, merged and moved back to normal blocks (i.e., written back to normal TLC / QLC blocks), and then the blocks in the staging area are erased for future use.

[0070] It is important to emphasize that the positive correlation between the migration ratio factor and the stress factor means that fewer free blocks result in more valid pages being migrated and faster block erasure, but at the cost of more legacy pages needing to be temporarily stored. To ensure data reliability, changes to the mapping table in the temporary storage area are only considered complete after power outage protection capabilities (such as tantalum capacitors or supercapacitors) take effect, in order to avoid the loss of temporary data due to unexpected power outages.

[0071] By employing a partial migration mode, this embodiment provides a flexible trade-off between garbage collection efficiency and write amplification, making it particularly suitable for storage devices 12 that are write-intensive UFS / SSDs.

[0072] In one embodiment, a scheme based on free block consumption rate prediction and dynamic adjustment is further provided.

[0073] Specifically, when the current number of free blocks is less than a first threshold and not less than a second threshold (i.e., a light garbage collection level), the consumption rate of the free block count is predicted. The consumption rate is calculated as follows: Consumption rate = Amount of data written by host write requests (number of bytes written by the host per unit time) / Average capacity of each free block - Free block generation rate (number of free blocks generated by garbage collection per unit time). Free block generation rate = First execution rate × Average effective page move efficiency per block (i.e., the percentage of effective capacity released by moving one block).

[0074] For example, if the host write speed is 200MB / s and each block size is 4MB, then the host consumes free blocks at a rate of 50 blocks / second. If the current first execution rate is 100MB / s and the average effective page ratio of the moved blocks is 50%, then every 2MB of data moved can release one block (because after moving 2MB of effective data, a 4MB block can be erased, where 2MB is effective data and 2MB is invalid data), so the free block generation rate is 50 blocks / second. At this time, the consumption rate equals the generation rate, and the storage device 12 is stable.

[0075] If the garbage collection rate is detected to exceed the free block generation rate (e.g., a sudden increase in host write speed to 400MB / s while the garbage collection rate remains unchanged), the first execution rate is dynamically increased (e.g., increasing the base rate from 50MB / s to 100MB / s) and / or the first proportion threshold is decreased (e.g., decreasing from 30% to 20%). This allows garbage collection to reclaim blocks with a lower proportion of valid pages more quickly, increasing the free block generation rate. This adjustment continues until the number of free blocks stops decreasing or the current number of free blocks enters the next garbage collection range (i.e., below the second quantity threshold). If the number of free blocks increases instead, parameters are appropriately adjusted to avoid excessive garbage collection impacting host performance. This allows the garbage collection rate to adapt to changes in host load, preventing large fluctuations in the number of free blocks.

[0076] In this embodiment, in order to finely control the time allocation of garbage collection and host commands, when performing data transfer operations on the first target block, the second target block or the third target block, a time-slice round-robin method is used to schedule the host read and write commands. Within each scheduling cycle, a first time slot is allocated for background garbage collection and a second time slot is allocated for host read / write commands. The two time slots are executed sequentially within each scheduling cycle (e.g., 1 millisecond).

[0077] Specifically, the length of the first time slot is dynamically adjusted based on the currently executing garbage collection level: In the first level (light garbage collection, corresponding to the first execution rate), the first time slot length is set to the base time slot length (e.g., 200 microseconds) multiplied by (current first execution rate / base rate). If the current first execution rate is 30MB / s and the base rate is 50MB / s, then the first time slot length is 200 × 0.6 = 120 microseconds.

[0078] At the second level (medium garbage collection, corresponding to the second execution rate), the length of the first time slot is fixed at twice the base time slot length (i.e., 400 microseconds).

[0079] In the third level (emergency garbage collection, corresponding to the maximum execution rate), the length of the first time slot accounts for more than 50% of the entire scheduling cycle, for example, it can be set to 600 microseconds, and the second time slot is 400 microseconds.

[0080] If the valid data migration of the current target block is completed within the first time slot (e.g., all valid pages of the block have been migrated), the time slot ends early and the process moves to the second time slot, allowing the remaining time to be allocated to host commands. This dynamic time slot allocation strategy ensures that the garbage collection load and storage device 12 are matched, while also enabling rapid host response when the garbage collection task is completed ahead of schedule.

[0081] In one embodiment, in order to improve the efficiency of data transfer, a variable-granularity batch processing method is proposed to be used according to different execution rates, that is, the data transfer operations corresponding to the first execution rate, the second execution rate and the maximum execution rate adopt a variable-granularity batch processing method.

[0082] Specifically, at the initial execution rate (light garbage collection), data is moved in units of single pages (e.g., 16KB). After each move, the host system is checked for pending commands (by checking the command queue flag). If any are found, garbage collection is immediately suspended, and the host commands are processed to minimize the impact on host responsiveness.

[0083] At the second execution rate (medium garbage collection), batch migration is performed in multiples of pages. Each batch contains L pages, which is dynamically determined based on the average distribution of currently active pages. For example, if the average proportion of active pages in the current block to be migrated is high (e.g., 70%), L can be set to 8; if the average is low (e.g., 30%), L can be set to 4 to avoid prolonged bus occupancy. During batch migration, host commands are not checked after each page, but only once after the entire batch is completed, thereby reducing the scheduling overhead of the memory controller 123.

[0084] At maximum execution rate (emergency garbage collection), data is moved in whole blocks. All valid pages in a block are moved at once (potentially hundreds of pages), and host commands are processed only after the entire block has been moved. While this briefly blocks the host, it produces free blocks the fastest.

[0085] Furthermore, at the first execution rate, if the continuous idle time of the host system exceeds a preset idle threshold (e.g., 5 milliseconds), the transfer granularity is automatically increased from single page to batch processing (e.g., transferring 4 pages at a time). Also, during batch processing, if a host system command is detected (via an interrupt or polling flag), the current batch is allowed to exit immediately after completing the current page, rather than interrupting the ongoing page programming operation, because the programming operation of memory module 122 cannot be interrupted once it begins. This improves background efficiency during idle periods while ensuring low-latency response to host commands.

[0086] In one embodiment, for the memory module 122 that supports multiple planes or multiple channels, the parallel granularity is also dynamically configured according to the garbage collection level. In one embodiment, the memory module 122 includes four planes (Plane 0 to 3), each of which can independently perform read, write, and erase operations.

[0087] At the initial execution rate (light garbage collection), data movement is performed using only a single plane (e.g., Plane0) or a single channel (Channel0), and each target block is processed serially. This is done to reduce power consumption and interference with host access.

[0088] At the second execution rate (medium garbage collection), parallel movement is enabled on a portion of all planes or channels in memory module 122. The degree of parallelism is positively correlated with the pressure factor. The pressure factor = (second threshold - current number of free blocks) / (second threshold - third threshold). Its value ranges from [0, 1]. For example, when the pressure factor is 0.2, two planes are enabled; when the pressure factor is 0.8, three out of four planes are enabled. This gradual increase in parallelism allows garbage collection efficiency to rise smoothly with pressure.

[0089] At maximum execution rate (emergency garbage collection), all planes and channels are enabled for fully parallel moving, and moving operations are performed simultaneously on multiple third target blocks (e.g., each plane processes a different target block). This maximizes the internal parallelism of memory module 122, generating free blocks in the shortest possible time. Thus, garbage collection is accelerated while maintaining host performance.

[0090] In one embodiment, to further reduce write amplification and improve space reclamation efficiency, a merge-and-move mechanism is proposed. That is, when performing data migration at a first execution rate, a second execution rate, or a maximum execution rate, it is detected whether there are mergeable block pairs in the memory module 122 that meet the following conditions.

[0091] Specifically, this condition is as follows: the effective page ratio of the first block is lower than a first ratio threshold (e.g., 20%), the effective page ratio of the second block is also lower than the first ratio threshold, and the logical addresses corresponding to the effective pages in the first and second blocks are consecutive in the logical address space or belong to the same logical address range (e.g., the logical range of the same erase block group, such as an LBA range of 0-1023). This condition means that the effective data in the two blocks are logically close and suitable for merging into one block.

[0092] If a mergeable block pair exists, the valid pages from the first and second blocks are merged and moved to the same free block. Specifically, a new free block is allocated as the target block. The valid pages from the first block are written to the target block in logical address order. Then, the valid pages from the second block are written to subsequent pages in the target block, and the mapping table is updated. After the move is complete, the first and second blocks are erased simultaneously, resulting in two free blocks (the target block is occupied, but the source block releases two free blocks, resulting in a net increase of one free block).

[0093] Merge moves have a higher priority than regular moves; that is, when both regular garbage collection candidate blocks and mergeable block pairs exist, merge moves are performed first. Furthermore, the execution rate of merge moves is the same as the execution rate corresponding to the current garbage collection level (i.e., it is executed at the first, second, or maximum execution rate).

[0094] However, when the number of free blocks falls below the third threshold (emergency garbage collection), merge migration is prohibited, and only normal migration is performed. This is because in an emergency, the priority is to quickly generate free blocks, while merge migration requires processing pages from two blocks, which may take longer. This reduces write amplification in non-emergency situations, thus improving the lifespan of the storage device 12.

[0095] Considering that the data retention capability and write endurance of the memory module 122 will decrease under high-temperature environments, in one embodiment, a temperature-sensing garbage collection speed adjustment mechanism is also provided. In one embodiment, the memory controller 123 uses a built-in temperature sensor ( Figure 2 (Not shown) Obtain the current operating temperature.

[0096] Specifically, the current operating temperature of the memory controller 123 is obtained. When the current operating temperature exceeds a preset first temperature threshold (e.g., 70°C), the first bandwidth limit is forcibly reduced to a first predetermined percentage (e.g., 50%) of its original value, i.e., from 200MB / s to 100MB / s; and the second bandwidth limit is reduced to a second predetermined percentage (e.g., 70%) of its original value, i.e., from 500MB / s to 350MB / s. Simultaneously, the transfer granularity corresponding to the maximum execution rate is downgraded from a block-level operation to a batch operation, where each batch does not exceed a predetermined number of pages (e.g., 4 pages). This reduces the heat generated by the memory module 122.

[0097] When the current operating temperature exceeds a preset second temperature threshold (e.g., 85°C), all background garbage collection operations are suspended, and only the immediate release mechanism for blocks with a valid page ratio of 0 is maintained (i.e., immediate erasure and addition to the free block list). The second temperature threshold is higher than the first temperature threshold. Because high temperatures significantly impact the lifespan of the memory module 122, some automotive-grade storage devices can reach a second temperature of 120°C. This temperature is close to the operating limit of the memory module 122, and any additional erase / write operations could cause data errors or damage to the electronic components in the storage device 12.

[0098] Once the current operating temperature drops below the first temperature threshold and remains below the preset cooling time (e.g., 30 seconds), the original bandwidth limit and transfer granularity are restored step by step. For example, the first bandwidth limit is restored first, then the second bandwidth limit is restored, and finally the entire transfer granularity is restored.

[0099] The aforementioned temperature threshold values ​​are related to the casing material and heat dissipation design of the storage device 12. For example, for an SSD with a metal casing, the first temperature threshold can be set to 75°C; for a UFS with a plastic casing, it can be set to 65°C. This embodiment does not impose any limitations on this. By adjusting the garbage collection speed based on temperature sensing, this embodiment improves the reliability of the storage device 12 in high-temperature environments.

[0100] In one embodiment, to reduce the number of erase commands and lower the overhead of the memory controller 123, a batch erase delayed release mechanism is proposed. Specifically, at the first execution rate, when there is at least one used block (i.e., a completely invalid block) with an effective page ratio of 0 in the memory module 122, the block is not immediately released (i.e., erasure is not performed immediately), but is marked as pending delayed release and placed in a delayed release queue.

[0101] In detail, the number of blocks to be delayed for release is counted. If this number exceeds a preset batch release threshold (e.g., 8 blocks), a batch release operation is triggered to continuously erase multiple blocks to be delayed for release in a single erase command. For example, if the memory module 122 supports multi-plane erasure, 8 blocks can be erased simultaneously through a multi-block erase command.

[0102] Batch release operations are executed at a rate not exceeding the first bandwidth limit and are only allowed when the current number of free blocks is below the second quantity threshold. That is, when the number of free blocks is relatively sufficient (above the second quantity threshold), batch erasure is not performed even if there are multiple blocks to be delayed for release, in order to save power; batch erasure is only triggered when the number of free blocks drops below the second quantity threshold, indicating that more free blocks are needed.

[0103] If the current number of free blocks falls below the third threshold (emergency situation), the delayed release mechanism is canceled, and all blocks with a valid page ratio of 0 are immediately released one by one (i.e., erase is performed) to increase the number of free blocks as quickly as possible. This reduces the number of erase commands, lowers the load on the memory controller 123, and avoids unnecessary erase operations when not in an emergency.

[0104] Figures 5 to 6 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figures 5 to 6 Each step can be implemented as multiple program codes or circuits, and this application does not impose any limitations. Furthermore, Figures 5 to 6 The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this application does not impose any restrictions.

[0105] In summary, the memory control method proposed in the embodiments of this application is applied to a storage device, which includes a connection interface for electrically connecting to a host system; a memory module including multiple planes, each plane including multiple blocks, each block including multiple pages; and a memory controller including error checking and correction circuitry, buffer memory, and memory control circuitry, electrically connected to the connection interface and the memory module. The method includes: responding to a current number of free blocks in the memory module being less than a first number threshold and not less than a preset second number threshold, selecting at least one block from the memory module with an effective page ratio lower than a preset first ratio threshold as a first target block; calculating a first execution rate based on the ratio of the difference between the current number of free blocks, the first number threshold, and the second number threshold, wherein the first execution rate is negatively correlated with the ratio of the difference; and executing data on the first target block at a rate not exceeding a first bandwidth upper limit, according to the first execution rate. A data migration operation is performed to generate free blocks, wherein the first bandwidth limit is lower than the peak bandwidth of the storage device; if the current number of free blocks is less than the second quantity threshold and not less than the preset third quantity threshold, at least one block is selected from the memory module as a second target block; a data migration operation is performed on the second target block at a second execution rate to generate free blocks, wherein the second execution rate is greater than the first execution rate and is limited by the second bandwidth limit, the second bandwidth limit being higher than the first bandwidth limit and lower than the peak bandwidth of the storage device; if the current number of free blocks is lower than the third quantity threshold, at least one block is selected from the memory module as a third target block; a data migration operation is performed on the third target block at a maximum execution rate to generate free blocks, wherein the maximum execution rate is greater than the second execution rate and is limited by the peak bandwidth of the storage device, and the first quantity threshold, the second quantity threshold, and the third quantity threshold are preset values ​​that decrease sequentially. Through three-level rate control, a balance is achieved between host system performance and background garbage collection efficiency, improving the performance of the storage device.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A memory control method, characterized in that, Applied to a storage device including a memory module and a memory controller, the method includes: In response to the current number of free blocks in the memory module being less than a first number threshold and not less than a preset second number threshold, at least one block with an effective page ratio lower than a preset first ratio threshold is selected from the memory module as the first target block. A first execution rate is calculated based on the ratio of the difference between the current number of free blocks, the first quantity threshold, and the second quantity threshold, wherein the first execution rate is negatively correlated with the ratio of the difference. At a rate not exceeding a first bandwidth limit, a data shifting operation is performed on the first target block according to the first execution rate to generate a free block, wherein the first bandwidth limit is lower than the peak bandwidth of the storage device; If the current number of free blocks is less than the second number threshold and not less than the preset third number threshold, then at least one block is selected from the memory module as the second target block; A data shifting operation is performed on the second target block at a second execution rate to generate a free block, wherein the second execution rate is greater than the first execution rate and is limited by a second bandwidth limit, which is higher than the first bandwidth limit and lower than the peak bandwidth of the storage device. If the current number of free blocks is lower than the third quantity threshold, then at least one block is selected from the memory module as the third target block; A data migration operation is performed on the third target block at the maximum execution rate to generate a free block, wherein the maximum execution rate is greater than the second execution rate and is limited by the peak bandwidth of the storage device, and the first quantity threshold, the second quantity threshold and the third quantity threshold are preset values ​​and decrease sequentially.

2. The memory control method according to claim 1, characterized in that, Also includes: During the data transfer operation on the first target block, the second target block, or the third target block, the valid data transferred is cached in the buffer memory of the memory controller; When a read request is received from the host system, the buffer memory is searched first. If the requested data hits the buffer memory, the data is returned directly from the buffer memory, and the original data page in the source block corresponding to the hit data is marked as no longer needing to be moved, thereby reducing the urgency of moving the block to which it belongs. If the current number of free blocks is lower than the third quantity threshold, the buffer memory is prohibited from being used to serve read request cache hits, and the data in the buffer memory is forced to be written to the target block first, and the buffer memory is cleared for subsequent garbage collection operations.

3. The memory control method according to claim 1, characterized in that, Also includes: When the number of current free blocks is lower than the third quantity threshold and data migration operation is performed on the third target block at the maximum execution rate, it is detected whether a host write request is continuously blocked for more than a preset blocking time threshold. If it exists, a high-priority write reserved block is temporarily created, at least one free block is reserved from the free block list to respond to host write requests, and the reserved block is excluded from the target block pool for garbage collection and relocation. After the reserved blocks are allocated, if the current number of free blocks is still lower than the third threshold, the write request bypass mechanism in the emergency garbage collection mode is triggered: Write host data directly to a pre-allocated emergency free block instead of the third target block that is being moved by garbage collection. At the same time, logically swap the emergency free block with the current garbage collection target block and update the mapping table so that subsequent moving operations skip over the logical address that has been overwritten. The emergency idle blocks are dynamically obtained from the reserved pool, and the number does not exceed the preset emergency block limit; The bypass mechanism is activated only when there is at least one third target block with a valid page ratio higher than a preset emergency threshold, in order to prevent valid data from being accidentally overwritten.

4. The memory control method according to claim 1, characterized in that, Also includes: When the number of currently free blocks is less than the second threshold and not less than the third threshold, a partial migration mode is adopted when performing data migration operation on the second target block: Only move the top P pages with the highest proportion of valid pages in the second target block, where P is the total number of pages in the second target block multiplied by a move ratio factor less than 1, and do not move the remaining valid pages in the block; When the second target block is erased after the partial relocation is completed, the remaining valid page data is remapped into the mapping table maintained by the memory controller, pointing to a new temporary storage area; The temporary storage area consists of a small number of high-durability blocks reserved in the storage device, with a fixed upper limit on their capacity; When the temporary storage area is full or the number of current free blocks rises back to above the second number threshold, the valid page data in the temporary storage area will be merged back into the normal blocks. The relocation ratio factor is positively correlated with the pressure factor, which is defined as (second quantity threshold - current number of free blocks) / (second quantity threshold - third quantity threshold), and its value range is [0, 1].

5. The memory control method according to claim 1, characterized in that, Also includes: When the current number of free blocks is less than the first quantity threshold and not less than the second quantity threshold, predict the consumption rate of the number of free blocks; The consumption rate is calculated based on the amount of data written by the host write request and the rate at which free blocks are generated under the first execution rate. If the consumption rate is greater than the free block generation rate, the first execution rate is dynamically increased and / or the first ratio threshold is decreased until the number of free blocks stops decreasing or enters the next level of garbage collection.

6. The memory control method according to claim 1, characterized in that, Also includes: When performing data transfer operations on the first target block, the second target block, or the third target block, a time-slice rotation method is used to schedule the host read and write commands. Within each scheduling cycle, the first time slot is allocated for background garbage collection, and the second time slot is allocated for host read and write commands; The length of the first time slot is dynamically adjusted based on the currently executing garbage collection level: At the first level, the first time slot length is set to the base time slot length multiplied by (current first execution rate / base rate). In the second level, the length of the first time slot is fixed at twice the length of the reference time slot; At the third level, the length of the first time slot accounts for more than 50% of the entire scheduling cycle; If the effective data transfer of the current target block is completed within the first time slot, the time slot is ended early and the process moves to the second time slot.

7. The memory control method according to claim 1, characterized in that, Also includes: At the first execution rate, data is moved in units of single pages, and after each move, the host system is checked for any pending commands. At the second execution rate, batch processing is performed in multiples of pages, with each batch containing L pages, where L is dynamically determined based on the average of the current effective page ratio distribution. At maximum execution rate, data is moved in units of entire blocks. At the first execution rate, if the continuous idle time of the host system exceeds the preset idle threshold, the migration granularity is automatically increased from single page to batch processing. When a host system command is detected, the current batch is allowed to exit immediately after completing the current page, rather than interrupting the ongoing page programming operation.

8. The memory control method according to claim 1, characterized in that, Also includes: The memory module contains multiple planes or channels that can operate in parallel; When performing data migration operations on the first target block, the second target block, or the third target block, the parallel granularity is dynamically configured according to the current garbage collection level: At the first execution rate, data transfer is performed using only a single plane or single channel, and each target block is processed sequentially. At the second execution rate, a portion of all planes or channels in the memory module are enabled for parallel movement. The degree of parallelism is positively correlated with the pressure factor, which is defined as (second quantity threshold - current number of free blocks) / (second quantity threshold - third quantity threshold), and its value range is [0, 1]. At the maximum execution rate, all planes and channels are enabled for fully parallel transfer, and transfer operations are performed on multiple third target blocks simultaneously.

9. The memory control method according to claim 1, characterized in that, Also includes: When performing data migration at the first execution rate, the second execution rate, or the maximum execution rate, it is detected whether there are mergeable block pairs in the memory module that meet the following conditions: The effective page ratio of the first block is lower than the first ratio threshold, the effective page ratio of the second block is also lower than the first ratio threshold, and the logical addresses corresponding to the effective pages in the first block and the second block are consecutive in the logical address space or belong to the same logical address range. If the mergeable block pair exists, the valid pages in the first block and the second block are merged and moved to the same free block, and the first block and the second block are erased at the same time after the move is completed; Merged moves have a higher priority than regular moves, and the execution rate of merged moves is the same as the execution rate corresponding to the current garbage collection level. When the number of currently free blocks is lower than the third quantity threshold, merging and moving are prohibited, and only normal moving is performed.

10. The memory control method according to claim 1, characterized in that, Also includes: Obtain the current operating temperature of the memory controller; When the current operating temperature exceeds a preset first temperature threshold, the first bandwidth limit is forcibly reduced to a first predetermined percentage of the original value, and the second bandwidth limit is reduced to a second predetermined percentage of the original value. At the same time, the transfer granularity corresponding to the maximum execution rate is downgraded from a block to batch processing, and the batch processing is no more than a predetermined number of pages per batch. When the current operating temperature exceeds the preset second temperature threshold, all background garbage collection operations are suspended, and only the immediate release mechanism of blocks with an effective page ratio of 0 is retained, wherein the second temperature threshold is higher than the first temperature threshold. When the current operating temperature drops below the first temperature threshold and continues for more than the preset cooling time, the original bandwidth limit and transfer granularity are restored step by step. The temperature threshold value is related to the casing material and heat dissipation design of the storage device.

11. The memory control method according to claim 1, characterized in that, Also includes: At the first execution rate, when there is at least one used block in the memory module with an effective page ratio of 0, the block is not released immediately, but is marked as to be released with a delay. The number of blocks to be released is counted. If the number exceeds the preset batch release threshold, a batch release operation is triggered to continuously erase multiple blocks to be released in a single erase command. The batch release operation is executed at a rate not exceeding the first bandwidth limit, and is only allowed to be executed when the current number of free blocks is lower than the second number threshold. If the current number of free blocks is lower than the third quantity threshold, the delayed release mechanism is canceled, and all blocks with a valid page ratio of 0 are released immediately one by one.

12. A storage device, characterized in that, include: A connection interface for electrically connecting to a host system; The memory module includes multiple planes, each plane includes multiple blocks, and each block includes multiple pages; as well as The memory controller includes an error checking and correction circuit, a buffer memory, and a memory control circuit, and is electrically connected to the connection interface and the memory module; The memory controller is configured to perform the memory control method as described in any one of claims 1 to 11.

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