A multi-channel data acquisition device and acquisition method
By using dynamic configuration and cache module structure of multi-channel data acquisition devices, the problem of wasted transmission bandwidth in multi-channel data acquisition is solved, and high-speed real-time data recovery is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUHAN LINGJIU MICROELECTRONICS CO LTD
- Filing Date
- 2026-06-24
- Publication Date
- 2026-07-21
AI Technical Summary
Existing multi-channel data acquisition technologies cannot dynamically adjust the transmitted data when the number of channels is fixed, resulting in wasted transmission bandwidth and an inability to achieve high-speed real-time data recovery.
A multi-channel data acquisition device is adopted, including multiple data acquisition channels, a first-level buffer module, a channel arbitration module, a second-level buffer module, and an interrupt control module. It is dynamically configured through a channel enable status register and a read priority register to realize the merging and splicing of data streams for transmission.
It enables dynamic switching and high-speed real-time transmission of multi-channel data acquisition, avoids wasting transmission bandwidth, and ensures that the host computer can accurately recover the acquired data streams of each channel.
Smart Images
Figure CN122432077A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of multi-channel signal acquisition technology, and more specifically, to a multi-channel data acquisition device and acquisition method. Background Technology
[0002] Multi-channel data acquisition requires high speed and high real-time performance, and the host computer can accurately recover the data from each channel.
[0003] The conventional design approach is to merge the data collected from multiple channels and transmit it to the host computer, and then split and recover the data.
[0004] Existing multi-channel acquisition methods rely on a fixed number of channels, merging and transmitting data from all channels, resulting in a large bus data width. When different channels have different acquisition rates or when some channels pause acquisition, the transmission data cannot be dynamically adjusted, leading to wasted bandwidth. Summary of the Invention
[0005] To address the challenges of multi-channel dynamic acquisition switching and high-speed real-time transmission, and to enable the host computer to adaptively restore and reconstruct the acquired data streams from each channel, this invention provides a multi-channel data acquisition device and method.
[0006] According to a first aspect of the present invention, a multi-channel data acquisition device is provided, comprising multiple data acquisition channels, multiple first-level buffer modules equal to the number of data acquisition channels, a channel arbitration module, a second-level buffer module, an interrupt control module, and a host computer. The channel arbitration module includes a channel enable status register and a channel read priority register, and the channel enable status register includes a channel write enable status register and a channel read enable status register.
[0007] The host computer configures the channel write enable status register and the channel read priority register respectively. The channel write enable status register is used to configure the write enable status of each data acquisition channel, and the channel read priority register is used to configure the read priority of each first-level cache module. The host computer also configures the channel read enable status register according to the read priority of each first-level cache module. The channel read enable status register is used to configure the read enable status of each first-level cache module.
[0008] Each data acquisition channel is used to acquire data streams based on the write enable state;
[0009] Each of the first-level cache modules is used to cache the sampled data stream output by the corresponding data acquisition channel;
[0010] The channel arbitration module merges and splices a portion of the sampled data streams cached by the first-level cache module and transmits them to the second-level cache module according to the read enable state of each first-level cache module.
[0011] The interrupt control module generates an interrupt based on the empty / full state of the second-level cache module. The host computer enters the interrupt service routine, reads back the sampled data stream of the specified length, and clears the interrupt.
[0012] The host computer parses the read-back sampled data stream and restores the acquired data stream of each acquisition channel based on the read enable state of each first-level cache module.
[0013] Based on the above technical solution, the present invention can also be improved as follows.
[0014] Optionally, the channel write enable status register includes n bits, each bit corresponding to the write enable status of a data acquisition channel, used to control the opening or closing of each data acquisition channel.
[0015] The channel read priority register includes n m bits, each m bit corresponding to the read priority of a first-level cache module. The read priority of each first-level cache module can be directly configured by the host computer or adaptively adjusted according to the empty or full state of each first-level cache module.
[0016] Where n is the number of data acquisition channels, and m is log2 n Round up.
[0017] Optionally, configuring the channel read enable status register according to the read priority of each first-level cache module includes:
[0018] When the read priority of the first-level cache module is greater than the preset threshold, the read enable status bit of the first-level cache module is 1, indicating that it will be read subsequently; otherwise, the read enable status bit of the first-level cache module is 0, indicating that it will not be read subsequently.
[0019] Optionally, the channel arbitration module, based on the read enable state of each first-level cache module, merges and splices a portion of the sampled data streams cached by the first-level cache modules and transmits them to the second-level cache module, including:
[0020] The channel arbitration module reads the sampled data stream from the first-level cache module where the read enable bit is 1, merges and splices them, and transmits them to the second-level cache module.
[0021] Optionally, the channel arbitration module dynamically updates the read priority of the first-level cache module, including:
[0022] If the accumulated unread data count of the current first-level cache module i is greater than the first set data volume threshold, then the read priority value of the first-level cache module that is greater than the read priority value of the current first-level cache module i is reduced by 1, and the read priority value of the current first-level cache module i is assigned to n-1, where n is the number of first-level cache modules, 1≤i≤n;
[0023] If the read enable status bit of the current first-level cache module j is 1 and the cumulative count of unread data is 0, then the read priority value of the first-level cache module that is less than the read priority value of the current first-level cache module j is incremented by 1, and the priority value of the current first-level cache module j is assigned to 0, where 1≤j≤n.
[0024] Optionally, when the read priority values of the n first-level cache modules have not changed, the highest bit of the status flag of the channel arbitration module is set to 0, {1'b0, the acquisition data stream with channel read enable status 1} is written to the second-level cache module, the sampled data stream in the first-level cache module with read enable status 1 is read, merged and spliced, and transmitted to the second-level cache module.
[0025] When the read priority values of n first-level cache modules change, the channel arbitration module sets the highest-order status flag to 1. At this time, it obtains the channel read enable status register value and writes a {1'b1, channel read enable status register} to the second-level cache module. Then, it sets the highest-order status flag of the channel arbitration module to 0, reads the sampled data stream in the first-level cache module with the read enable status bit set to 1, merges and splices it, and transmits it to the second-level cache module.
[0026] The high-order bits of the channel read enable status register are padded with 0s, so that the bit width of {1'b1, channel read enable status register} is the same as that of {1'b0, acquired data with channel read enable status 1}.
[0027] Optionally, the interrupt control module generates an interrupt based on the empty / full state of the second-level cache module. The host computer enters the interrupt service routine, reads back the sampled data of a specified length, and clears the interrupt, including:
[0028] When the accumulated unread data count of the second-level cache module exceeds the second set data volume threshold, the interrupt control module sends an interrupt request to the host computer.
[0029] After receiving an interrupt request, the host computer responds to the interrupt request and enters the interrupt service routine. It reads a sampled data stream of a specified length from the second-level buffer module, performs operations on the sampled data stream of the specified length, and recovers the sampled data stream of each signal sampling channel. After the interrupt service routine completes its processing, it clears the interrupt flag.
[0030] According to a second aspect of the present invention, a multi-channel data acquisition method is provided, applied in a multi-channel data acquisition device, the method comprising:
[0031] The channel write enable status register and the channel read priority register are configured by the host computer. The channel write enable status register is used to configure the write enable status of each data acquisition channel, and the channel read priority register is used to configure the read priority of each first-level cache module.
[0032] The channel read enable status register is configured according to the read priority of each first-level cache module. The channel read enable status register is used to configure the read enable status of each first-level cache module.
[0033] Each data acquisition channel acquires a data stream based on the write enable state and caches the sampled data stream to the corresponding first-level cache module;
[0034] The channel arbitration module merges and splices the sampled data streams cached by some of the first-level cache modules and transmits them to the second-level cache module according to the read enable state of each first-level cache module.
[0035] The interrupt control module generates an interrupt based on the empty or full state of the second-level buffer module. The host computer enters the interrupt service routine, reads back the sampled data stream of the specified length, and clears the interrupt.
[0036] The host computer parses the read-back sampled data stream and restores the acquired data stream of each acquisition channel based on the read enable state of each first-level cache module.
[0037] Optionally, configuring the channel read enable status register according to the read priority of each first-level cache module includes:
[0038] When the read priority of the first-level cache module is greater than the preset threshold, the read enable status bit of the first-level cache module is 1, indicating that it will be read subsequently; otherwise, the read enable status bit of the first-level cache module is 0, indicating that it will not be read subsequently.
[0039] Optionally, the channel arbitration module may also dynamically update the read priority of the first-level cache module, specifically including:
[0040] If the accumulated unread data count of the current first-level cache module i is greater than the first set data volume threshold, then the read priority value of the first-level cache module that is greater than the read priority value of the current first-level cache module i is reduced by 1, and the read priority value of the current first-level cache module i is assigned to n-1, where n is the number of first-level cache modules, 1≤i≤n;
[0041] If the read enable status bit of the current first-level cache module j is 1 and the cumulative count of unread data is 0, then the read priority value of the first-level cache module that is less than the read priority value of the current first-level cache module j is incremented by 1, and the priority value of the current first-level cache module j is assigned to 0, where 1≤j≤n.
[0042] This invention provides a multi-channel data acquisition device and method. The multi-channel data acquisition device includes multiple data acquisition channels, multiple first-level buffer modules (the same number as the data acquisition channels), a channel arbitration module, a second-level buffer module, an interrupt control module, and a host computer. This invention employs a two-level buffer and channel arbitration structure, and uses a dynamic channel configuration read / write method, inserting channel status flags into the acquired data stream transmission. This effectively solves the problems of dynamic multi-channel acquisition switching and high-speed real-time transmission. The host computer can recover and restore the data streams acquired from each channel. Attached Figure Description
[0043] Figure 1 This is a structural block diagram of a multi-channel data acquisition device provided in one embodiment of the present invention;
[0044] Figure 2 This is a flowchart illustrating the read / write process of the first-level cache module according to an embodiment of the present invention.
[0045] Figure 3 This is a flowchart illustrating the read / write process of the second-level cache module according to an embodiment of the present invention.
[0046] Figure 4 This is a data flow structure diagram of the second-level cache module in one embodiment of the present invention. Detailed Implementation
[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In addition, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined with each other to form feasible technical solutions. Such combinations are not constrained by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.
[0048] To address the shortcomings of existing multi-channel data acquisition methods, this invention employs a two-level buffering approach and a configurable channel read / write method. Channel states are inserted into the transmitted data stream, allowing the host computer to accurately reconstruct the data streams for each channel based on these states. This enables dynamic switching of acquisition channels and avoids wasting transmission bandwidth.
[0049] This invention is applicable to the field of multi-channel data acquisition. Figure 1 The diagram illustrates the structure of a multi-channel data acquisition device provided by this invention. The multi-channel data acquisition device includes multiple data acquisition channels, multiple first-level buffer modules equal to the number of data acquisition channels, a channel arbitration module, a second-level buffer module, an interrupt control module, an AXI conversion bridge module, a PCIe bus module, and a host computer. The channel arbitration module includes a channel enable status register and a channel read priority register. The channel enable status register includes a channel write enable status register and a channel read enable status register.
[0050] The working principle of the multi-channel data acquisition device is as follows:
[0051] The host computer configures the channel write enable status register and the channel read priority register respectively. The channel write enable status register is used to configure the write enable status of each data acquisition channel, and the channel read priority register is used to configure the read priority of each first-level cache module. The host computer also configures the channel read enable status register according to the read priority of each first-level cache module. The channel read enable status register is used to configure the read enable status of each first-level cache module.
[0052] Each data acquisition channel is used to acquire data streams based on the write enable state;
[0053] Each of the first-level cache modules is used to cache the sampled data stream output by the corresponding data acquisition channel;
[0054] The channel arbitration module merges and splices the sampled data streams cached by some of the first-level cache modules and transmits them to the second-level cache module according to the read enable state of each first-level cache module.
[0055] The interrupt control module generates an interrupt based on the empty or full state of the second-level buffer module. The host computer enters the interrupt service routine, reads back the sampled data stream of the specified length, and clears the interrupt.
[0056] The host computer parses the read-back sampled data stream and restores the acquired data stream of each acquisition channel based on the read enable state of each first-level cache module.
[0057] The host computer reads and writes the channel enable status register and channel read priority register of the channel arbitration module through the PCIE bus module.
[0058] Specifically, the host computer configures the channel write enable status register of the channel arbitration module. The initial value of the channel write enable status register is {1'b0,……,1'b0}, which means that all data acquisition channels are initially turned off. The least significant bit of the channel write enable status register corresponds to data acquisition channel 1, and the most significant bit corresponds to data acquisition channel n. The n data acquisition channels correspond one-to-one with the n bits of the channel write enable status register.
[0059] Similarly, the host computer configures the channel read enable status register of the channel arbitration module to enable the read status of each first-level cache module. The initial value of the channel read enable status register is {1'b0,……,1'b0}, which means that initially all first-level cache modules are not read. The least significant bit of the channel read enable status register corresponds to first-level cache module 1, and the most significant bit corresponds to first-level cache module n. The n first-level cache modules correspond one-to-one with the n bits of the channel read enable status register.
[0060] The channel read priority register is initially set to {m'h0, ..., m'h0}, representing the read priority of each L1 cache module. The lowest m bits correspond to L1 cache module 1, and the highest m bits correspond to L1 cache module n. There is a one-to-one correspondence between the n L1 cache modules and the n m bits of the channel read priority register, where m is log2. n Round up.
[0061] See Figure 2 When the entire multi-channel data acquisition device is powered on, it opens the data acquisition channel with write enable status 1 according to the channel write enable status register value, acquires the data stream, and caches the data stream acquired by each data acquisition channel into the corresponding first-level cache module.
[0062] Based on the value of the channel read enable status register, the sampled data stream in the first-level cache module with the read enable status set to 1 is read, merged, and transmitted to the second-level cache module.
[0063] Specifically, the channel read enable status register is configured according to the read priority of each first-level cache module. When the read priority of the first-level cache module is greater than the preset threshold, the read enable status bit of the first-level cache module is 1, indicating that it will be read later; otherwise, the read enable status bit of the first-level cache module is 0, indicating that it will not be read later.
[0064] The initial read priority values of n Level 1 cache modules are configured from 0 to n-1. When the accumulated unread data count of Level 1 cache module i (1≤i≤n) exceeds a set data volume threshold (e.g., half full), the read priority values of other Level 1 cache modules with a higher read priority value than Level 1 cache module i are decremented by 1, and the read priority value of Level 1 cache module i is assigned to n-1. When the read enable status register bit of Level 1 cache module j (1≤j≤n) is 1 and the accumulated unread data count is 0, the read priority values of other Level 1 cache modules with a lower read priority value than Level 1 cache module j are incremented by 1, and the read priority value of Level 1 cache module j is assigned to 0.
[0065] When the channel arbitration module reads and merges the sampled data stream from the first-level buffer module (where the read enable state is 1) and transmits it to the second-level buffer module, it adds a 1-bit status flag to the highest bit of the channel arbitration module. The default value of the status flag is 0, representing the data transmission cycle, i.e., merging and transmitting the sampled data streams of the valid channels to the second-level buffer module. During the cycle in which the read priority values of 1 to n in the first-level buffer module change, the 1-bit status flag of the channel arbitration module is set to 1. At this time, the channel read enable status register value is obtained to know which channels the merged data stream received by the second-level buffer module belongs to. After obtaining the channel read enable status register value, the 1-bit status flag of the channel arbitration module is restored to 0, returning to the data transmission cycle.
[0066] Specifically, when the read priority of the first-level cache modules 1 to n changes, the channel arbitration module first writes a {1'b1, channel read enable status register} to the second-level cache module, and then writes the data stream acquired according to the current channel read enable status. The highest-order status flag bit is 1'b0 when transmitting the acquired data stream. Figure 3 The second-level cache data flow structure is shown.
[0067] See Figure 4 After the sampled data stream from the effective first-level buffer module is transmitted to the second-level buffer module, when the accumulated unread data count in the second-level buffer module exceeds a preset data volume threshold, the interrupt control module sends an interrupt to the host computer. Upon receiving the interrupt request, the host computer, if conditions permit, responds to the interrupt and enters the interrupt service routine. It reads a sampled data stream of a specified length from the second-level buffer module, performs calculations, and restores the acquired data stream for each data acquisition channel. After the interrupt service routine completes its processing, it clears the interrupt flag.
[0068] The host computer can configure the enabling status of the second-level cache module. When the enabling status bit of the second-level cache module is 1, it continues to wait for the interrupt request; when the enabling status bit of the second-level cache module is 0, the data acquisition ends.
[0069] Based on the multi-channel data acquisition device provided in the above embodiments, the present invention also provides a multi-channel data acquisition method, which includes the following steps:
[0070] The channel write enable status register and the channel read priority register are configured by the host computer. The channel write enable status register is used to configure the write enable status of each data acquisition channel, and the channel read priority register is used to configure the read priority of each first-level cache module.
[0071] The channel read enable status register is configured according to the read priority of each first-level cache module. The channel read enable status register is used to configure the read enable status of each first-level cache module.
[0072] Each data acquisition channel acquires a data stream based on the write enable state and caches the sampled data stream to the corresponding first-level cache module;
[0073] The channel arbitration module merges and splices the sampled data streams cached by some of the first-level cache modules and transmits them to the second-level cache module according to the read enable state of each first-level cache module.
[0074] The interrupt control module generates an interrupt based on the empty or full state of the second-level buffer module. The host computer enters the interrupt service routine, reads back the sampled data stream of the specified length, and clears the interrupt.
[0075] The host computer parses the read-back sampled data stream and restores the acquired data stream of each acquisition channel based on the read enable state of each first-level cache module.
[0076] The channel write enable status register consists of n bits, each corresponding to the write enable status of a data acquisition channel, used to control the enabling or disabling of each data acquisition channel. The channel read priority register consists of n m bits, each m bit corresponding to the read priority of a first-level cache module. The read priority of each first-level cache module is configured directly by the host computer or adaptively adjusted based on the empty / full status of each first-level cache module. Here, n is the number of data acquisition channels, and m is log2. n Round up.
[0077] The channel read enable status register is configured according to the read priority of each first-level cache module, including:
[0078] When the read priority of the first-level cache module is greater than the preset threshold, the read enable status bit of the first-level cache module is 1, indicating that it will be read subsequently; otherwise, the read enable status bit of the first-level cache module is 0, indicating that it will not be read subsequently.
[0079] Specifically, the channel arbitration module, based on the read enable state of each first-level cache module, merges and splices a portion of the sampled data streams cached by the first-level cache modules and transmits them to the second-level cache module, including:
[0080] The channel arbitration module reads the sampled data stream from the first-level cache module where the read enable bit is 1, merges and splices them, and transmits them to the second-level cache module.
[0081] The channel arbitration module dynamically updates the read priority of the first-level cache module, including:
[0082] If the accumulated unread data count of the current first-level cache module i is greater than the first set data volume threshold, then the read priority value of the first-level cache module that is greater than the read priority value of the current first-level cache module i is reduced by 1, and the read priority value of the current first-level cache module i is assigned to n-1, where n is the number of first-level cache modules, 1≤i≤n;
[0083] If the read enable status bit of the current first-level cache module j is 1 and the cumulative count of unread data is 0, then the read priority value of the first-level cache module that is less than the read priority value of the current first-level cache module j is incremented by 1, and the priority value of the current first-level cache module j is assigned to 0, where 1≤j≤n.
[0084] Specifically, when the read priority values of the n first-level cache modules do not change, the highest bit of the channel arbitration module is set to 0, {1'b0, the acquisition data stream with channel read enable status 1} is written to the second-level cache module, the sampled data stream in the first-level cache module with read enable status 1 is read, merged and spliced, and transmitted to the second-level cache module.
[0085] When the read priority values of the n first-level cache modules change, the channel arbitration module sets the highest-order status flag to 1. At this time, it obtains the channel read enable status register value and writes a {1'b1, channel read enable status register} to the second-level cache module. Then, it sets the highest-order status flag of the channel arbitration module to 0, reads the sampled data stream from the first-level cache module with the read enable status bit set to 1, merges and splices them, and transmits them to the second-level cache module.
[0086] The high-order bits of the channel read enable status register are padded with 0, so that the bit width of {1'b1, channel read enable status register} is the same as that of {1'b0, acquired data with channel read enable status of 1}.
[0087] The interrupt control module generates an interrupt based on the empty / full state of the second-level buffer module. The host computer enters the interrupt service routine, reads back the sampled data of a specified length, and clears the interrupt, including:
[0088] When the accumulated unread data count of the second-level cache module exceeds the second set data volume threshold, the interrupt control module sends an interrupt request to the host computer.
[0089] After receiving an interrupt request, the host computer responds to the interrupt request and enters the interrupt service routine. It reads a sampled data stream of a specified length from the second-level buffer module, performs operations on the sampled data stream of the specified length, and recovers the sampled data stream of each signal sampling channel. After the interrupt service routine completes its processing, it clears the interrupt flag.
[0090] It is understood that the multi-channel data acquisition method provided by the present invention corresponds to the multi-channel data acquisition device provided in the foregoing embodiments. The relevant technical features of the multi-channel data acquisition device can be referred to the relevant technical features of the multi-channel data acquisition device, and will not be repeated here.
[0091] The multi-channel data acquisition device and method provided in this invention have the following advantages compared to the prior art:
[0092] (1) A two-level cache and channel arbitration structure is adopted. The channel dynamic configuration read and write method is used to insert the channel status flag into the data stream transmission, which effectively solves the problem of multi-channel dynamic acquisition switching and high-speed real-time transmission. The host computer can restore and reconstruct the data streams acquired by each channel.
[0093] (2) Each channel's analog-to-digital conversion module can be enabled or disabled in real time via the host computer. The channel arbitration module adaptively and dynamically adjusts the read priority of each channel based on the data collected from the first-level cache of each channel, thereby adaptively and dynamically adjusting the read enable status of each channel to maximize the effective use of transmission bandwidth. Under the condition that bandwidth allows, it ensures that the first-level cache module will not lose analog-to-digital conversion data due to being full. When the first-level cache module is empty, it automatically switches to other channels for reading to avoid wasting transmission bandwidth.
[0094] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0095] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0096] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0097] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0098] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0099] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.
[0100] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A multi-channel data acquisition device, characterized in that, It includes multiple data acquisition channels, multiple first-level cache modules equal to the number of data acquisition channels, a channel arbitration module, a second-level cache module, an interrupt control module, and a host computer. The channel arbitration module includes a channel enable status register and a channel read priority register. The channel enable status register includes a channel write enable status register and a channel read enable status register. The host computer configures the channel write enable status register and the channel read priority register respectively. The channel write enable status register is used to configure the write enable status of each data acquisition channel, and the channel read priority register is used to configure the read priority of each first-level cache module. And configure the channel read enable status register according to the read priority of each first-level cache module. The channel read enable status register is used to configure the read enable status of each first-level cache module. Each data acquisition channel is used to acquire data streams based on the write enable state; Each of the first-level cache modules is used to cache the sampled data stream output by the corresponding data acquisition channel; The channel arbitration module merges and splices a portion of the sampled data streams cached by the first-level cache module and transmits them to the second-level cache module according to the read enable state of each first-level cache module. The interrupt control module generates an interrupt based on the empty / full state of the second-level cache module. The host computer enters the interrupt service routine, reads back the sampled data stream of the specified length, and clears the interrupt. The host computer parses the read-back sampled data stream and restores the acquired data stream of each acquisition channel based on the read enable state of each first-level cache module.
2. The multi-channel data acquisition device according to claim 1, characterized in that, The channel write enable status register includes n bits, each bit corresponding to the write enable status of a data acquisition channel, used to control the opening or closing of each data acquisition channel. The channel read priority register includes n m bits, each m bit corresponding to the read priority of a first-level cache module. The read priority of each first-level cache module can be directly configured by the host computer or adaptively adjusted according to the empty or full state of each first-level cache module. Where n is the number of data acquisition channels, and m is log2 n Round up.
3. The multi-channel data acquisition device according to claim 1 or 2, characterized in that, The step of configuring the channel read enable status register according to the read priority of each first-level cache module includes: When the read priority of the first-level cache module is greater than the preset threshold, the read enable status bit of the first-level cache module is 1, indicating that it will be read subsequently; otherwise, the read enable status bit of the first-level cache module is 0, indicating that it will not be read subsequently.
4. The multi-channel data acquisition device according to claim 3, characterized in that, The channel arbitration module, based on the read enable state of each first-level cache module, merges and splices a portion of the sampled data streams cached by the first-level cache modules and transmits them to the second-level cache module, including: The channel arbitration module reads the sampled data stream from the first-level cache module where the read enable bit is 1, merges and splices them, and transmits them to the second-level cache module.
5. The multi-channel data acquisition device according to claim 3, characterized in that, The channel arbitration module dynamically updates the read priority of the first-level cache module, including: If the accumulated unread data count of the current first-level cache module i is greater than the first set data volume threshold, then the read priority value of the first-level cache module that is greater than the read priority value of the current first-level cache module i is reduced by 1, and the read priority value of the current first-level cache module i is assigned to n-1, where n is the number of first-level cache modules, 1≤i≤n; If the read enable status bit of the current first-level cache module j is 1 and the cumulative count of unread data is 0, then the read priority value of the first-level cache module that is less than the read priority value of the current first-level cache module j is incremented by 1, and the priority value of the current first-level cache module j is assigned to 0, where 1≤j≤n.
6. The multi-channel data acquisition device according to claim 5, characterized in that, When the read priority values of the n first-level cache modules have not changed, the highest bit of the status flag of the channel arbitration module is set to 0, {1'b0, the acquisition data stream with channel read enable status 1} is written to the second-level cache module, the sampled data stream in the first-level cache module with read enable status 1 is read, merged and spliced, and transmitted to the second-level cache module. When the read priority values of n first-level cache modules change, the channel arbitration module sets the highest-order status flag to 1. At this time, it obtains the channel read enable status register value and writes a {1'b1, channel read enable status register} to the second-level cache module. Then, it sets the highest-order status flag of the channel arbitration module to 0, reads the sampled data stream in the first-level cache module with the read enable status bit set to 1, merges and splices it, and transmits it to the second-level cache module. The high-order bits of the channel read enable status register are padded with 0s, so that the bit width of {1'b1, channel read enable status register} is the same as that of {1'b0, acquired data with channel read enable status 1}.
7. The multi-channel data acquisition device according to claim 1, characterized in that, The interrupt control module generates an interrupt based on the empty / full state of the second-level cache module. The host computer enters the interrupt service routine, reads back the sampled data of a specified length, and clears the interrupt, including: When the accumulated unread data count of the second-level cache module exceeds the second set data volume threshold, the interrupt control module sends an interrupt request to the host computer. After receiving an interrupt request, the host computer responds to the interrupt request and enters the interrupt service routine. It reads a sampled data stream of a specified length from the second-level buffer module, performs operations on the sampled data stream of the specified length, and recovers the sampled data stream of each signal sampling channel. After the interrupt service routine completes its processing, it clears the interrupt flag.
8. A multi-channel data acquisition method, applied in the multi-channel data acquisition device of claim 1, characterized in that, The method includes: The channel write enable status register and the channel read priority register are configured by the host computer. The channel write enable status register is used to configure the write enable status of each data acquisition channel, and the channel read priority register is used to configure the read priority of each first-level cache module. The channel read enable status register is configured according to the read priority of each first-level cache module. The channel read enable status register is used to configure the read enable status of each first-level cache module. Each data acquisition channel acquires a data stream based on the write enable state and caches the sampled data stream to the corresponding first-level cache module; The channel arbitration module merges and splices the sampled data streams cached by some of the first-level cache modules and transmits them to the second-level cache module according to the read enable state of each first-level cache module. The interrupt control module generates an interrupt based on the empty or full state of the second-level buffer module. The host computer enters the interrupt service routine, reads back the sampled data stream of the specified length, and clears the interrupt. The host computer parses the read-back sampled data stream and restores the acquired data stream of each acquisition channel based on the read enable state of each first-level cache module.
9. The multi-channel data acquisition method according to claim 8, characterized in that, The step of configuring the channel read enable status register according to the read priority of each first-level cache module includes: When the read priority of the first-level cache module is greater than the preset threshold, the read enable status bit of the first-level cache module is 1, indicating that it will be read subsequently; otherwise, the read enable status bit of the first-level cache module is 0, indicating that it will not be read subsequently.
10. The multi-channel data acquisition method according to claim 9, characterized in that, It also includes a channel arbitration module that dynamically updates the read priority of the first-level cache module, specifically including: If the accumulated unread data count of the current first-level cache module i is greater than the first set data volume threshold, then the read priority value of the first-level cache module that is greater than the read priority value of the current first-level cache module i is reduced by 1, and the read priority value of the current first-level cache module i is assigned to n-1, where n is the number of first-level cache modules, 1≤i≤n; If the read enable status bit of the current first-level cache module j is 1 and the cumulative count of unread data is 0, then the read priority value of the first-level cache module that is less than the read priority value of the current first-level cache module j is incremented by 1, and the priority value of the current first-level cache module j is assigned to 0, where 1≤j≤n.