Method and device for optimizing data transmission performance of FPGA heterogeneous accelerator based on hybrid backhaul mechanism

Abstract

The application discloses a kind of FPGA heterogeneous accelerator data transmission performance optimization method and device based on hybrid back mechanism, method includes: host end before executing DMA write operation, whether the data to be returned quantity exceeds preset threshold value is judged by data return judgment module;According to the selection result of DMA or BAR transmission mode, and simultaneously configure DMA write operation and read operation descriptor;Device end directly enters data processing after completing data writing according to write operation descriptor, and does not need to report write completion interrupt;After data processing is completed, device end returns data according to preset mode and only reports once processing completion interrupt.The data transmission method provided in the application can fully exert the advantages of high bandwidth of DMA large packet transmission and low delay of BAR small packet transmission, reduce the number of interrupt reporting, significantly improve the data transmission efficiency and real-time performance of FPGA heterogeneous acceleration system.

Description

Technical Field

[0001] This invention belongs to the technical field of machine learning, specifically relating to a method and apparatus for optimizing data transmission performance of FPGA heterogeneous accelerators based on a hybrid backhaul mechanism. Background Technology

[0002] With the rapid development of artificial intelligence technology, heterogeneous computing architecture has become the core paradigm for high-performance computing power output of AI servers. Based on the PCIe bus, heterogeneous computing systems built with central processing units (CPUs) and graphics processing units (GPUs), general-purpose graphics processing units (GPGPUs), or field-programmable gate arrays (FPGAs) accelerators have achieved continuous breakthroughs in computing performance by leveraging the complementary functions of various computing units—CPUs excel at complex control logic, GPUs are adapted for large-scale parallel computing, and FPGAs provide customized and efficient acceleration. This has enabled them to widely support high-density computing scenarios such as deep learning training, real-time inference, big data analysis, and cryptographic operations.

[0003] In PCIe-based heterogeneous computing systems, the efficiency of data interaction between the CPU and acceleration units directly determines the overall computing power release. Currently, the mainstream data transfer mechanisms are mainly divided into two categories: Direct Memory Access (DMA) transfer and Base Address Register (BAR) read / write transfer. BAR read / write transfer relies on the memory mapping mechanism of the PCIe device configuration space, allowing the CPU to directly access the mapped address to complete data interaction. This mechanism requires no additional transfer configuration process, has a simple data path, and the latency of a single transfer can be controlled at the microsecond or even nanosecond level, making it suitable for high-frequency interaction scenarios involving small amounts of data such as control instructions and status parameters. DMA transfer, as a core technology for large-volume data interaction in heterogeneous systems, uses a dedicated DMA controller to take over data transfer tasks, enabling direct data transfer between peripherals and memory. This significantly reduces CPU intervention overhead and greatly increases the bandwidth for large data transfers. Its main mode is descriptor-based data transfer.

[0004] However, existing descriptor-based DMA transfers have inherent process constraints: during the data write phase, the CPU must first configure the source address, destination address, and transfer parameters of the descriptor, and the DMA controller initiates data transfer; after the acceleration unit completes data processing, the host must wait for the device to report a write completion interrupt before reconfiguring the read operation descriptor to achieve the return of the processing result. This "two configurations + two interrupts" transfer logic introduces a large amount of additional overhead, including configuration register writing, status flag lookup, linked list node updates, and interrupt response latency. Regarding PCIe end-to-end latency, under a PCIe 4.0 x16 link, the end-to-end latency of traditional descriptor-based DMA bidirectional transfers is typically 40-120 microseconds, with interrupt response latency accounting for 30%-50%, descriptor configuration overhead accounting for approximately 20%-30%, and actual data transfer time accounting for only 20%-40% of the total latency. Regarding small data packet transmission performance, when the data packet size is less than 4KB, the effective bandwidth of DMA transmission is less than 10% of the theoretical bandwidth; when the data packet size is 64 bytes, the effective bandwidth is only 1%-2% of the theoretical bandwidth. At this point, the process overhead of "two configurations + two interrupts" becomes the main bottleneck for performance. Therefore, optimizing the data transmission method of PCIe heterogeneous accelerators to improve their data transmission performance has become a hot research topic in academia and industry. Pan Weitao et al. from Xi'an University of Electronic Science and Technology proposed an efficient interrupt operation method for the PCIe controller of the TTE end system adapter card (CN110990309A). By dividing the DMA read buffer into a non-guaranteed area and a guaranteed area, the interrupt triggering timing is optimized. When the DMA executes the write process, the DMA write buffer is divided into two parts: A_Buffer and B_Buffer. When the driver processes the data in part A, the hardware can write the data to part B. After the driver finishes processing part A, it continues to process the data in part B. By adopting a more efficient DMA read interaction mode, unnecessary interrupts are reduced, and the DMA read transmission rate is significantly improved. Hangzhou Yixin Technology has proposed a low-latency PCIe DMA data transfer method and controller (CN111221757B), which further improves descriptor processing efficiency by optimizing the descriptor prefetching and caching mechanism.

[0005] In summary, although considerable research has been conducted on optimizing data transmission in PCIe heterogeneous accelerators and some progress has been made, the aforementioned technologies still have significant shortcomings: (1) After the acceleration unit completes data processing, the host still needs to wait for an interrupt notification and then reconfigure the read operation descriptor before returning the result, which cannot achieve "one-time configuration, bidirectional transmission"; (2) No scenario-oriented data transmission system has been designed to take into account the specific application scenarios and combine the advantages of the two transmission paths, DMA and BAR, so as to fully utilize the performance of the PCIe interface. Therefore, this invention designs a method for optimizing the data transmission performance of FPGA heterogeneous accelerators based on a hybrid return mechanism, which leverages the performance advantages of DMA and BAR when transmitting different amounts of data, thereby improving the data transmission performance of the FPGA heterogeneous acceleration system. Summary of the Invention

[0006] The main objective of this invention is to overcome the shortcomings and deficiencies of the prior art and provide a method and apparatus for optimizing the data transmission performance of FPGA heterogeneous accelerators based on a hybrid backhaul mechanism. This addresses the problems of frequent interruptions, low efficiency of small data packet transmission, and high end-to-end latency in current descriptor-based DMA transmission, fully leveraging the advantages of different transmission mechanisms to improve the data transmission efficiency and real-time performance of FPGA heterogeneous acceleration systems.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a method for optimizing data transmission performance of FPGA heterogeneous accelerators based on a hybrid backhaul mechanism, comprising the following steps:

[0009] Before performing a DMA write operation, the host determines whether the amount of data to be returned exceeds a preset threshold through the data return judgment module. Based on the judgment result of the data return judgment module, the corresponding data return method is selected, and the descriptor configuration module simultaneously completes the configuration of the DMA write operation descriptor and the read operation descriptor, and sends the complete descriptor to the device.

[0010] The device performs a data write operation based on the write operation descriptor. After completion, it directly enters the user logic module for data processing without reporting a write completion interrupt to the host. After the device completes the data processing, it sends the processing result back to the host according to the configuration information in the descriptor. The device reports a data processing completion interrupt to the host once through the interrupt module.

[0011] The data return judgment module runs on the host kernel; if the sending data cache is write-cleared and the cache space is larger than the return data, then the read data cache address is the same as the sending data cache address.

[0012] As a preferred technical solution, the process of selecting the corresponding transmission mode and configuring the descriptor based on the judgment result includes:

[0013] If the amount of data to be returned does not exceed the preset threshold, the BAR transmission mode is selected. The descriptor configuration module sets the transmission mode flag in the descriptor and writes the preset BAR return address into the destination address field of the read operation descriptor.

[0014] If the amount of data to be returned exceeds the preset threshold, the DMA transfer mode is selected. The data return data storage processing module determines the storage address of the returned data based on the length of the returned data and the overwriteability of the original data. The descriptor configuration module writes the storage address into the destination address field of the read operation descriptor and resets the transfer mode flag.

[0015] As a preferred technical solution, the backhaul data storage processing module determines the storage address of the backhaul data based on the length of the backhaul data and the overwriteability of the original data, including:

[0016] If the length of the returned data is not greater than the length of the original data and the original data can be overwritten, then the storage address of the original data will be used as the destination address of the returned data.

[0017] Otherwise, the data storage and processing module will request new memory space as the destination address for the returned data.

[0018] As a preferred technical solution, the step of sending the processing result back to the host according to the configuration information in the descriptor in a corresponding manner includes:

[0019] If the transmission mode flag is set, the device will write the processing result to the host's preset BAR mapping address through the PCIe BAR read / write interface.

[0020] If the transmission mode flag is reset, the device will write the processing result to the memory address specified by the host through the DMA read interface.

[0021] As a preferred technical solution, the preset threshold is customized by the user according to the actual application scenario.

[0022] As a preferred technical solution, the BAR transmission method is suitable for scenarios with small data volume and fixed length, including SM3 hash operation, SHA256 hash operation and control command interaction scenarios.

[0023] As a preferred technical solution, the host and device are connected via a PCIe bus, and PCIe supports DMA transfer function.

[0024] Secondly, the present invention provides a data transmission performance optimization system for FPGA heterogeneous accelerators based on a hybrid backhaul mechanism, applied to the aforementioned data transmission performance optimization method for FPGA heterogeneous accelerators based on a hybrid backhaul mechanism, comprising a host end and a device end connected via a PCIe bus:

[0025] The host includes a data return judgment module, used to determine whether the amount of data to be returned exceeds a preset threshold, and whether the returned data can overwrite the original data; a return data storage processing module, used to request memory space for the returned data when needed, and send the storage address information to the descriptor configuration module; and a descriptor configuration module, used to configure DMA write operation descriptors and read operation descriptors at the same time, including setting the transmission mode flag and the destination address of the returned data.

[0026] The device includes: a transmission module for performing DMA write, DMA read, and BAR read / write data transmission operations according to the descriptor configuration information; a DDR memory for storing the data to be processed and intermediate processing results received by the device; a user logic module for executing user-defined accelerated computing tasks; and an interrupt module for reporting a single processing completion interrupt to the host after data processing and transmission are completed.

[0027] Thirdly, the present invention provides an electronic device, the electronic device comprising:

[0028] At least one processor; and,

[0029] A memory communicatively connected to the at least one processor; wherein,

[0030] The memory stores computer program instructions that can be executed by the at least one processor, which enables the at least one processor to execute the FPGA heterogeneous accelerator data transmission performance optimization method based on a hybrid backhaul mechanism.

[0031] Fourthly, the present invention provides a computer-readable storage medium storing a program, which, when executed by a processor, implements the aforementioned method for optimizing data transmission performance of FPGA heterogeneous accelerators based on a hybrid backhaul mechanism.

[0032] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0033] 1. Halved interruption count and significantly reduced latency: This invention completes the configuration of the read operation descriptor at the same time as issuing the write operation descriptor. The device does not need to report the write completion interruption, but only needs to report the processing completion interruption once after the entire process is completed, reducing the number of interrupt reports by 50% and eliminating the latency overhead caused by interrupt response and secondary configuration.

[0034] 2. Hybrid transmission mechanism to adapt to all scenarios: Dynamically select DMA or BAR transmission mode according to the amount of data to be transmitted. It retains the high bandwidth advantage of DMA when transmitting large data packets, and gives full play to the low latency advantage of BAR when transmitting small data packets. It is especially suitable for hash operation scenarios such as SM3 and SHA256.

[0035] 3. Reusing storage addresses to reduce system overhead: When the length of the returned data is less than the original data and the original data does not need to be retained, the storage address of the original data can be reused directly, avoiding frequent shared memory allocation and release operations, reducing the CPU's memory management overhead, and reducing the risk of memory leaks.

[0036] 4. Improved Transmission Determinism: By completing all transmission configurations in advance, the impact of host-side response delay on overall transmission time in traditional processes is eliminated, improving the determinism of data transmission and meeting the stringent real-time requirements of application scenarios such as industrial control and autonomous driving. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a block diagram of the FPGA heterogeneous accelerator data transmission performance optimization system based on a hybrid backhaul mechanism, according to an embodiment of the present invention.

[0039] Figure 2 This is a descriptor definition in an embodiment of the present invention for a method to optimize data transmission performance in an FPGA heterogeneous accelerator;

[0040] Figure 3 The flowchart shows a method for optimizing data transmission performance of FPGA heterogeneous accelerators based on a hybrid backhaul mechanism.

[0041] Figure 4 This is a structural diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0042] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0043] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0044] like Figure 1 The diagram shows a block diagram of the FPGA heterogeneous accelerator data transmission system based on a hybrid backhaul mechanism, as presented in this invention. The system includes a host end and a device end, which achieve high-speed bidirectional data interaction via a PCIe bus. The system contains two independent data backhaul paths: a DMA backhaul path and a BAR backhaul path. The optimal transmission method can be dynamically selected based on the amount of backhaul data, fully leveraging the performance advantages of different transmission mechanisms.

[0045] Furthermore, the host terminal includes three core functional modules: a data return judgment module, a return data storage and processing module, and a descriptor configuration module.

[0046] The data return judgment module is responsible for determining whether the amount of data to be returned exceeds the user-defined preset threshold before the DMA write operation is executed, so as to provide a decision basis for the subsequent transmission method selection.

[0047] The backhaul data storage processing module determines the storage address of the backhaul data based on the length of the backhaul data and the overwriteability of the original data. When the length of the backhaul data is not greater than the length of the original data and the original data does not need to be retained in the host memory, the storage address of the original data is directly reused to avoid frequent shared memory allocation and release operations.

[0048] The descriptor configuration module is responsible for configuring both DMA write and read operation descriptors simultaneously, including setting the transfer mode flag and the return data destination address, and sending the complete descriptor list to the device at once. The host communicates with the device through a unified PCIe interface to issue control commands, transmit descriptors, and receive processing results.

[0049] Furthermore, the device uses the PCIe interface as its external communication entry point and integrates five core units: a transmission module, a bridging module, an interrupt module, a DDR memory, and a user logic module.

[0050] The transmission module comprises two main sub-modules: a DMA interface and a BAR interface. The DMA interface is further divided into an H2C (host to device) channel and a C2H (device to host) channel, corresponding to the DMA write interface and the DMA read interface, respectively, and is responsible for realizing high-speed, large-data-volume transmission between the host memory and the device's DDR memory. The BAR interface is connected to the AXI-Lite bus through a bridging module and includes a BAR write interface and a BAR read interface, used to realize low-latency transmission of control commands, status parameters, and small data packets.

[0051] The bridging module completes the protocol conversion between the PCIe BAR space and the AXI-Lite bus, enabling the CPU to directly access the device-side registers via memory mapping.

[0052] The interrupt module is connected to the PCIe interface through the interrupt interface. It only reports a single processing completion interrupt to the host after the entire data processing and transmission process is completed, which greatly reduces the number of interrupt reports.

[0053] The DDR memory is used to cache the data to be processed, intermediate processing results and final output data received by the device.

[0054] The user logic module is a user-defined accelerated computing unit responsible for performing specific accelerated tasks such as deep learning inference and cryptographic operations.

[0055] like Figure 2 The diagram illustrates one embodiment of the descriptor definition in this invention. Each descriptor group contains at least 32 bits of write operation source address, 32 bits of write operation destination address, 32 bits of write operation data transfer length, 32 bits of write operation checksum, 32 bits of read operation source address, 32 bits of read operation destination address, 32 bits of read operation data transfer length, 32 bits of read operation checksum, and 32 bits of transmission mode flag.

[0056] like Figure 3 As shown, another embodiment of the present invention provides a method for optimizing data transmission performance of FPGA heterogeneous accelerators based on a hybrid backhaul mechanism. This method consists of two main parts: a host-side preprocessing process and a device-side hardware execution process. It achieves efficient data transmission logic of "one-time configuration, automatic backhaul, and single interruption," specifically including the following steps:

[0057] (1) Host-side preprocessing process:

[0058] After the process is started, the data feedback judgment module first determines whether the length of the data to be fed back exceeds the user-defined preset threshold. This threshold can be flexibly adjusted according to the actual application scenario (such as hash operation, deep learning inference, etc.).

[0059] If the judgment result is "yes" (the length of the returned data exceeds the threshold), the returned data storage processing module further determines whether new storage space needs to be requested: if the length of the returned data is greater than the length of the original data or the original data needs to be retained in the host memory, the returned data storage processing module requests new memory space as the destination address of the returned data; after the memory request is completed, the descriptor configuration module configures the DMA write operation descriptor and the read operation descriptor at the same time, and resets the transfer mode flag bit (indicating that DMA return mode is used).

[0060] If the judgment result is "No" (the length of the returned data does not exceed the threshold), then there is no need to apply for new storage space. The descriptor configuration module can directly configure the DMA write operation descriptor and the read operation descriptor at the same time, and set the transmission mode flag (indicating that the BAR return mode is used).

[0061] Once the descriptor is configured, the host will send the complete descriptor list to the device in one go via the PCIe bus, without having to send write and read operation descriptors separately.

[0062] (2) Hardware execution process on the device side

[0063] After receiving the descriptor from the host, the device initiates a DMA data write operation to transfer the data to be processed from the host memory to the device's DDR memory.

[0064] Once the data is written, the user logic module is directly triggered to execute the data processing task, without needing to report the write completion interrupt to the host, thus eliminating the delay overhead caused by the first interrupt.

[0065] After data processing is completed, the device automatically parses the configuration information in the read operation descriptor and selects the corresponding return path according to the transmission mode flag: if the flag is reset, the processing result is returned to the specified memory address on the host through the DMA return path; if the flag is set, the processing result is directly written to the preset BAR mapping address on the host through the BAR return path, without going through the DDR memory cache.

[0066] After the data is transmitted back, the interrupt module on the device side only reports the data processing completion interruption to the host side once, notifying the host side to read the processing result.

[0067] (3) The entire data transmission process is complete.

[0068] This invention proposes a data transmission performance optimization scheme for FPGA heterogeneous accelerators based on a hybrid backhaul mechanism. The core of this scheme lies in the host side's intelligent determination of the amount of data to be backhauled based on a preset threshold, dynamically selecting either DMA or BAR transmission mode, and completing the read / write operation configuration in one step through a descriptor configuration module. After receiving and processing the data, the device side directly backhauls the data through the corresponding path according to the configuration information, with only one interruption during the final processing completion report. This scheme cleverly integrates the high bandwidth advantage of DMA and the low latency characteristics of BAR through a "one-time configuration, two-way transmission" mechanism, effectively eliminating the overhead of write completion interruptions and secondary configurations in traditional processes, and significantly improving the data transmission efficiency, bandwidth utilization, and real-time performance of the FPGA heterogeneous acceleration system.

[0069] like Figure 4 As shown, in another embodiment, an electronic device is provided for implementing a method for optimizing the data transmission performance of FPGA heterogeneous accelerators based on a hybrid backhaul mechanism. The electronic device may include a first processor, a first memory, and a bus, and may also include a computer program stored in the first memory and executable on the first processor, such as a program for optimizing the data transmission performance of FPGA heterogeneous accelerators based on a hybrid backhaul mechanism.

[0070] The first memory includes at least one type of readable storage medium, such as flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the first memory can be an internal storage unit of an electronic device, such as a portable hard drive. In other embodiments, the first memory can be an external storage device of the electronic device, such as a plug-in portable hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the first memory can include both internal and external storage units of the electronic device. The first memory can be used not only to store application software and various types of data installed on the electronic device, such as code for FPGA heterogeneous accelerator data transmission performance optimization programs based on hybrid backhaul mechanisms, but also to temporarily store data that has been output or will be output.

[0071] In some embodiments, the first processor may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits packaged with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The first processor is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It executes programs or modules stored in the first memory and calls data stored in the first memory to perform various functions of the electronic device and process data.

[0072] Figure 4 Only electronic devices with components are shown; it will be understood by those skilled in the art that... Figure 4 The structure shown does not constitute a limitation on the electronic device and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0073] The FPGA heterogeneous accelerator data transmission performance optimization program based on a hybrid backhaul mechanism, stored in the first memory of the electronic device, is a combination of multiple instructions. When run in the first processor, it can achieve the following:

[0074] Before performing a DMA write operation, the host determines whether the amount of data to be returned exceeds a preset threshold through the data return judgment module. Based on the judgment result of the data return judgment module, the corresponding data return method is selected, and the descriptor configuration module simultaneously completes the configuration of the DMA write operation descriptor and the read operation descriptor, and sends the complete descriptor to the device.

[0075] The device performs a data write operation based on the write operation descriptor. After completion, it directly enters the user logic module for data processing without reporting a write completion interrupt to the host. After the device completes the data processing, it sends the processing result back to the host according to the configuration information in the descriptor. The device reports a data processing completion interrupt to the host once through the interrupt module.

[0076] The data return judgment module runs on the host kernel; if the sending data cache is write-cleared and the cache space is larger than the return data, then the read data cache address is the same as the sending data cache address.

[0077] Furthermore, if the modules / units integrated in the electronic device are implemented as software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium. The computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory (ROM).

[0078] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0079] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A method for optimizing data transmission performance in FPGA heterogeneous accelerators based on a hybrid backhaul mechanism, characterized in that, Includes the following steps: Before performing a DMA write operation, the host determines whether the amount of data to be returned exceeds a preset threshold through the data return judgment module. Based on the judgment result of the data return judgment module, the corresponding data return method is selected, and the descriptor configuration module simultaneously completes the configuration of the DMA write operation descriptor and the read operation descriptor, and sends the complete descriptor to the device. The device executes the data write operation according to the write operation descriptor. After completion, it directly enters the user logic module for data processing without reporting a write completion interrupt to the host. After the device completes the data processing, it sends the processing result back to the host according to the configuration information in the descriptor in the corresponding way. The device reports a data processing completion interrupt to the host via the interrupt module; The data return judgment module runs on the host kernel; if the sending data cache is write-cleared and the cache space is larger than the return data, then the read data cache address is the same as the sending data cache address.

2. The data transmission method for an FPGA heterogeneous acceleration system based on a hybrid backhaul mechanism according to claim 1, characterized in that, The process of selecting the corresponding transmission method and configuring the descriptor based on the judgment result includes: If the amount of data to be returned does not exceed the preset threshold, the BAR transmission mode is selected. The descriptor configuration module sets the transmission mode flag in the descriptor and writes the preset BAR return address into the destination address field of the read operation descriptor. If the amount of data to be returned exceeds the preset threshold, the DMA transfer mode is selected. The data return data storage processing module determines the storage address of the returned data based on the length of the returned data and the overwriteability of the original data. The descriptor configuration module writes the storage address into the destination address field of the read operation descriptor and resets the transfer mode flag.

3. The data transmission method for a heterogeneous acceleration system of FPGA based on a hybrid backhaul mechanism according to claim 2, characterized in that, The data storage processing module for returning data determines the storage address of the returned data based on the length of the returned data and the overwriteability of the original data, including: If the length of the returned data is not greater than the length of the original data and the original data can be overwritten, then the storage address of the original data will be used as the destination address of the returned data. Otherwise, the data storage and processing module will request new memory space as the destination address for the returned data.

4. The data transmission method for an FPGA heterogeneous acceleration system based on a hybrid backhaul mechanism according to claim 2, characterized in that, The step of sending the processing result back to the host according to the configuration information in the descriptor in a corresponding manner includes: If the transmission mode flag is set, the device will write the processing result to the host's preset BAR mapping address through the PCIe BAR read / write interface. If the transmission mode flag is reset, the device will write the processing result to the memory address specified by the host through the DMA read interface.

5. The data transmission method for FPGA heterogeneous acceleration systems based on a hybrid backhaul mechanism according to claim 1, characterized in that, The preset threshold is customized by the user according to the actual application scenario.

6. The data transmission method for an FPGA heterogeneous acceleration system based on a hybrid backhaul mechanism according to claim 1, characterized in that, The BAR transmission method is suitable for scenarios with small data volume and fixed length, including SM3 hash operation, SHA256 hash operation and control command interaction scenarios.

7. The data transmission method for an FPGA heterogeneous acceleration system based on a hybrid backhaul mechanism according to any one of claims 1 to 6, characterized in that, The host and device are connected via a PCIe bus, and PCIe supports DMA transfer functionality.

8. A data transmission performance optimization system for FPGA heterogeneous accelerators based on a hybrid backhaul mechanism, characterized in that, The method for optimizing the data transmission performance of FPGA heterogeneous accelerators based on a hybrid backhaul mechanism, as described in any one of claims 1-7, includes a host end and a device end connected via a PCIe bus: The host includes a data return judgment module, used to determine whether the amount of data to be returned exceeds a preset threshold, and whether the returned data can overwrite the original data. The data storage processing module is used to request memory space for data return when needed and send the storage address information to the descriptor configuration module. The descriptor configuration module is used to configure DMA write operation descriptors and read operation descriptors simultaneously, including setting the transfer mode flag and the return data destination address; The device includes: a transmission module for performing DMA write, DMA read, and BAR read / write data transmission operations according to the descriptor configuration information; a DDR memory for storing the data to be processed and intermediate processing results received by the device; a user logic module for executing user-defined accelerated computing tasks; and an interrupt module for reporting a single processing completion interrupt to the host after data processing and transmission are completed.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores computer program instructions that can be executed by the at least one processor, which enables the at least one processor to perform the FPGA heterogeneous accelerator data transmission performance optimization method based on a hybrid backhaul mechanism as described in any one of claims 1-7.

10. A computer-readable storage medium storing a program, characterized in that, When the program is executed by the processor, it implements the FPGA heterogeneous accelerator data transmission performance optimization method based on the hybrid backhaul mechanism as described in any one of claims 1-7.

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