High-speed serial interface and method of data reception thereof

Abstract

High-speed serial interface and its data receiving method. The high-speed serial interface includes a physical layer and a logical physical layer. The physical layer receives high-speed serial data based on a first clock, and the logical physical layer operates according to a second clock with a frequency lower than the first clock. The physical layer is built-in with a control circuit, a serial-to-parallel circuit, and a data sampling path including a first flip-flop and a second flip-flop. The control circuit generates a multi-phase clock signal group and an adjustable sampling clock using the first and second clocks. In operation, the serial-to-parallel circuit generates initial parallel data according to the multi-phase clock signal group; the first flip-flop converts the initial parallel data into bit-shifted parallel data according to the adjustable sampling clock; and the second flip-flop outputs the bit-shifted parallel data to the logical physical layer according to the second clock, thereby realizing data transmission between different clock domains.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit (IC) design technology, and in particular to a high-speed serial interface and its data receiving method applied to high-speed serial deserializer (SerDes) or chiplet interconnect technology. Background Technology

[0002] In modern high-speed communication systems, the functional blocks (IPs) of high-speed serial interfaces are typically divided into a Physical Layer (EPHY) and a Logical Physical Layer (LPHY). The EPHY is responsible for handling data transmission at high-speed serial clocks (e.g., 8 GHz or 16 GHz), while the LPHY handles parallel data converted from serial to parallel by the EPHY, and operates at a relatively lower frequency (e.g., 1.6 GHz or 800 MHz).

[0003] In practical applications, data interaction between the Physical Layer (EPHY) and the Logical Physical Layer (LPHY) faces the problem of clock domain inconsistency. The recovery clock (CDR clock) of the Physical Layer (EPHY) typically originates from the received peer device, while the data clock of the Logical Physical Layer (LPHY) typically originates from the local Main PLL. Dynamic phase drift can occur between these two clock domains due to factors such as temperature drift, voltage fluctuations, and differences in data patterns.

[0004] Traditional technologies typically introduce a buffer architecture on the physical logic layer (LPHY) side for clock domain translation, as used in protocols such as PCIe or USB. While this approach is reliable, synthesizable, and can tolerate a wide range of phase drift, it introduces significant latency. This solution is feasible for applications that are not sensitive to overall latency (such as PCIe / USB). However, with the rise of chiplet interconnect architectures, systems have placed higher demands on minimizing latency. The high latency overhead of traditional LPHY-side buffer architectures is no longer sufficient to meet the requirements of high-performance interconnect scenarios such as chiplets.

[0005] How to achieve low-latency clock domain switching, especially within the physical layer, while ensuring data transmission reliability has become a pressing technical problem in this field. Summary of the Invention

[0006] In view of the excessive latency problem in the existing technology, the main objective of this application is to provide a high-speed serial interface and its data receiving method. This application utilizes a high-speed serial clock to construct an analog first-in-first-out (Analog FIFO) buffer architecture within the physical layer (EPHY), achieving rapid switching from the recovery clock domain to the logic physical layer (LPHY) clock domain. This significantly reduces link latency while ensuring data transmission reliability, making it particularly suitable for latency-sensitive chiplet interconnect scenarios.

[0007] To achieve the above objectives, this application provides a high-speed serial interface, including a physical layer and a logic physical layer. The physical layer receives high-speed serial data parsed based on a first clock (e.g., a high-speed serial clock), while the logic physical layer operates based on a lower-frequency second clock. The physical layer internally includes a control circuit, a serial-to-parallel conversion circuit, and a data sampling path. The control circuit generates a multi-phase clock signal group and an adjustable sampling clock based on the first and second clocks. The serial-to-parallel conversion circuit uses the multi-phase clock signal group to convert the serial data into initial parallel data, which is then sampled by a first flip-flop using the adjustable sampling clock to obtain shifted parallel data. Finally, a second flip-flop uses the second clock to output the data to the logic physical layer.

[0008] In one embodiment, the control circuit includes a multi-phase clock generator that generates a multi-phase clock signal group containing (n+1) phases in response to a first clock with a frequency that is (n+1) times that of the second clock; these phases are alternately set during one cycle of the second clock for precise extraction of high-speed serial data.

[0009] To address phase drift between clock domains, the control circuit of this application further includes an automatic phase adjuster and a phase detector. The automatic phase adjuster selects a specific phase from a multi-phase clock signal group as the adjustable sampling clock. The phase detector monitors the phase relationship between the adjustable sampling clock and the second clock in real time. When the rising edge of the second clock is detected to fall into a preset warning interval (e.g., a warning interval between the rising edge of the adjustable sampling clock and the rising edge of the next phase, or a warning interval between the rising edge of the previous phase and the rising edge of the adjustable sampling clock), the phase detector outputs a phase adjustment signal, driving the automatic phase adjuster to dynamically shift the adjustable sampling clock forward or backward, thereby maintaining the correctness of data sampling.

[0010] Furthermore, this application may incorporate a digital filter and an initial timing alignment circuit. The digital filter filters the phase adjustment signal to eliminate jitter interference and ensure the stability of phase switching. The initial timing alignment circuit detects the initial phase relationship between the first and second clocks during system startup to prevent timing violations during startup.

[0011] This application also provides a corresponding high-speed serial data receiving method, which includes the corresponding steps of the operation of the above-mentioned device.

[0012] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Attached Figure Description

[0013] Figure 1 According to one embodiment of this application, a high-speed serial interface 100 is illustrated, including a physical layer (EPHY) 102 and a logical physical layer (LPHY) 104.

[0014] Figure 2 The waveform diagram illustrates an example where the rising edge of the second clock fclk falls within a warning interval between the rising edge of the adjustable sampling clock ck1 and the rising edge of the subsequent phase clock ck2.

[0015] Figure 3 The waveform diagram illustrates an example where the rising edge of the second clock fclk falls within a warning interval between the rising edge of the preceding phase clock ck0 and the rising edge of the adjustable sampling clock ck1.

[0016] Figure 4 This is a flowchart illustrating a high-speed serial data rcad_init receiving method applied to a high-speed serial interface 100 according to one embodiment of this application; and

[0017] Figure 5 This is a flowchart illustrating the negative feedback regulation mechanism of this application according to one embodiment.

[0018] [Symbol Explanation]

[0019] 100: High-speed serial interface

[0020] 102: Physical Layer

[0021] 104: Logical-Physical Layer

[0022] 106: Serial-to-Parallel Circuit

[0023] 108, 110: Triggers

[0024] 112: Control Circuit

[0025] 114: Multiphase Clock Generator

[0026] 116: Automatic Phase Adjuster

[0027] 118: Phase detector

[0028] 120: Digital Filter

[0029] 122: Initial Timing Alignment Circuit

[0030] ck0: Front phase clock

[0031] ck1: Adjustable sampling clock

[0032] ck2: Back phase clock

[0033] clk: First clock

[0034] en: System enable signal

[0035] en1: The first positive edge of the second clock signal fclk after the system enable signal en is set.

[0036] en2: Alignment enable signal

[0037] fclk: Second clock

[0038] ph <m:0>ph: Phase selection signal

[0039] rcad_init: High-speed serial data

[0040] rcad <n:0>Initial parallel data

[0041] rcad_out <n:0>Output parallel data

[0042] rcad_shift <n:0>Parallel displacement data

[0043] st <n:0>st0~n: Multi-phase clock signal group

[0044] up / dn: Phase adjustment signal Detailed Implementation

[0045] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the following content is only for illustrating the general principles of this disclosure and is not intended to limit the scope of this disclosure. The actual scope of protection of this disclosure shall be determined by the scope defined in the appended claims. The various functional blocks described herein can be implemented by hardware, software, firmware, or a combination thereof, and may also include dedicated circuitry. Furthermore, these functional blocks are not limited to individual implementations, and may be integrated or share resources and functions as appropriate.

[0046] Figure 1 According to one embodiment of this application, a high-speed serial interface 100 is illustrated, including a physical layer (EPHY) 102 and a logical physical layer (LPHY) 104. The operating clock of the physical layer (EPHY) 102 is a first clock clk. The operating clock of the logical physical layer (LPHY) 104 is a second clock fclk, with a frequency lower than that of the first clock clk. For example, the frequency of the first clock is (n+1) times the frequency of the second clock, where n is a positive integer.

[0047] The physical layer (EPHY) 102 includes a serial-to-parallel converter 106, a data sampling path (108 and 110), and a control circuit 112. The data sampling path includes flip-flops (such as D flip-flops) 108 and 110 cascaded between the serial-to-parallel converter 106 and the logic physical layer (LPHY) 104. Thus, the physical layer (EPHY) 102 incorporates an analog first-in-first-out (AFIFO) buffer architecture, with its operating clock provided by the control circuit 112.

[0048] Specifically, the control circuit 112 is configured to generate a multi-phase clock signal group st based on the first clock clk and the second clock fclk. <n:0>And an adjustable sampling clock ck1. This multi-phase clock signal group st <n:0>The control circuit 112 controls the serial-to-parallel conversion circuit 106 to convert the high-speed serial data rcad_init into an initial parallel data rcad. <n:0>The control circuit 112 also operates the flip-flop 108 with the adjustable sampling clock ck1 to process the initial parallel data rcad. <n:0>Convert to parallel displacement data rcad_shift <n:0>The second clock fclk operates the trigger 110 according to the parallel shift data rcad_shift. <n:0>Convert to a parallel output data rcad_out <n:0>This allows the logical physical layer (LPHY) 104 to supply the data. In this architecture, the physical layer (EPHY) 102, in addition to performing serial-to-parallel conversion, also adapts the appropriate displacement parallel data rcad_shift. <n:0>This allows the slower second clock fclk to accurately obtain the parallel output data rcad_out. <n:0>.

[0049] The following discusses the details of the control circuit 112, which includes a multi-phase clock generator 114, an automatic phase adjuster 116, a phase detector 118, a digital filter 120, and an initial time alignment circuit 122.

[0050] The multi-phase clock generator 114 receives the first clock clk and generates the multi-phase clock signal group st. <n:0>In response to the first clock clk, the multi-phase clock signal group st <n:0>It includes (n+1) phases, where n is a positive integer. This multi-phase clock signal group st <n:0>The bit is set sequentially within the period of the second clock fclk. The serial-to-parallel circuit 106 uses the multi-phase clock signal group st, which includes (n+1) phases. <n:0>Extract the high-speed serial data rcad_init and generate (n+1) bits of initial parallel data rcad. <n:0>.

[0051] The automatic phase adjuster 116 is coupled to the multi-phase clock generator 114 and is used to adjust the multi-phase clock signal group st. <n:0>This generates the adjustable sampling clock ck1.

[0052] The phase detector 118 is used to detect the phase relationship between the adjustable sampling clock ck1 and the second clock fclk, and outputs a phase adjustment signal up / dn to the automatic phase adjuster 116 to dynamically adjust the phase of the adjustable sampling clock ck1.

[0053] In particular, the automatic phase adjuster 116 is also configured to output a preceding phase clock ck0 that leads the adjustable sampling clock ck1 and a following phase clock ck2 that lags the adjustable sampling clock ck1. The phase detector 118 is configured to receive the adjustable sampling clock ck1, the preceding phase clock ck0, the following phase clock ck2, and the second clock fclk, and to activate the phase adjustment signal up / dn in response to the rising edge of the second clock fclk falling into a warning interval between the rising edge of the adjustable sampling clock ck1 and the rising edge of the following phase clock ck2, or falling into a warning interval between the rising edge of the preceding phase clock ck0 and the rising edge of the adjustable sampling clock ck1.

[0054] In one embodiment, in response to the rising edge of the second clock fclk falling into a warning interval between the rising edge of the adjustable sampling clock ck1 and the rising edge of the subsequent phase clock ck2, the phase detector 118 causes the phase adjustment signal up / dn to issue a phase forward indication (up), thereby shifting the phase of the adjustable sampling clock ck1 forward.

[0055] In one embodiment, in response to the rising edge of the second clock fclk falling into a warning interval between the rising edge of the previous phase clock ck0 and the rising edge of the adjustable sampling clock ck1, the phase detector 118 causes the phase adjustment signal up / dn to issue a phase shift indication (dn), thereby shifting the phase of the adjustable sampling clock ck1 backward.

[0056] The digital filter 120 is coupled between the phase detector 118 and the automatic phase adjuster 116. The digital filter 120 is configured to receive the phase adjustment signal up / dn, filter the phase adjustment signal up / dn to remove noise or jitter, and output a phase selection signal ph. <m:0>The automatic phase adjuster 118 is then used to control the automatic phase adjuster 118 to update the phase of the adjustable sampling clock ck1.

[0057] The initial timing alignment circuit 122 is configured to receive the first clock clk, the second clock fclk, and a system enable signal en, detect the initial phase relationship between the first clock clk and the second clock fclk, and generate an alignment enable signal en2 to the multi-phase clock generator 114, causing the multi-phase clock generator 114 to start the multi-phase clock signal group st. <n:0>The generation sequence.

[0058] In one embodiment, one clock cycle of the first clock clk is T. The preceding phase clock ck0 leads the adjustable sampling clock ck1 by one T. The following phase clock ck2 lags the adjustable sampling clock ck1 by one T. The automatic phase adjuster 116 adjusts the phase of the preceding phase clock ck0 of the adjustable sampling clock ck1 relative to the multi-phase clock signal group st. <n:0>The number one clock in the middle <0> The movement ranges from -0.5T to (n-0.5)T, with the amount of movement based on the phase selection signal ph. <m:0>Set (m is a positive integer) and adjust in 1T units.

[0059] Figure 2 The waveform diagram illustrates an example where the rising edge of the second clock fclk falls within a warning interval between the rising edge of the adjustable sampling clock ck1 and the rising edge of the subsequent phase clock ck2. In addition to the aforementioned signals, en1 indicates the first positive edge of the second clock signal fclk after en is set. The phase detector 118 causes the phase adjustment signal up / dn to provide a phase forward indication (up=1), shifting the phase of the adjustable sampling clock ck1 forward. The phase selection signal ph... <m:0>The phase of the adjustable sampling clock ck1 is changed from 2.5 to 1.5, which is related to the phase of the multi-phase clock signal group st. <n:0>The 2.5T setting of the primary clock st0 is changed to a 1.5T setting to achieve phase forward shift. Correspondingly, the phase adjustment signal up / dn continuously provides a phase forward shift indication (up=1), and the phase selection signal ph... <m:0>Changing the value from 1.5 to 0.5 causes the phase of the adjustable sampling clock ck1 to change from a 1.5T setting at st0 to a 0.5T setting, continuing to shift the phase forward. Since the preceding phase clock ck0 has already shifted forward to be half a T ahead of st0 (-0.5T), the phase shift operation pauses. In the diagram, shifting the phase of the adjustable sampling clock ck1 forward by two T is sufficient to properly extract the displacement parallel data rcad_shift. <n:0>The second clock fclk is used by trigger 110 to correctly extract the parallel output data rcad_out. <n:0>.

[0060] Figure 3 The waveform diagram illustrates an example where the rising edge of the second clock fclk falls within a warning zone between the rising edge of the preceding phase clock ck0 and the rising edge of the adjustable sampling clock ck1. The phase detector 118 causes the phase adjustment signal up / dn to provide a phase shift indication (dn=1), shifting the phase of the adjustable sampling clock ck1 backward. The phase selection signal ph... <m:0>Changing the phase from 2.5T to 3.5T shifts the phase of the adjustable sampling clock ck1 from the 2.5T setting of st0 to the 3.5T setting, thus achieving a phase shift. Correspondingly, the phase adjustment signal up / dn continuously provides a phase shift indication (dn = 1), and the phase selection signal ph... <m:0>The phase shift is changed from 3.5T to 4.5T, changing the phase setting of the adjustable sampling clock ck1 from 3.5T at st0 to 4.5T at st0, and then the phase shift continues. Since the previous phase clock ck0 has already shifted back to 3.5T behind st0, the phase shift operation is paused. In the diagram, shifting the phase of the adjustable sampling clock ck1 back by two T is sufficient to properly extract the displacement parallel data rcad_shift. <n:0>The second clock fclk is used by trigger 110 to correctly extract the parallel output data rcad_out. <n:0>.

[0061] Figure 4 The flowchart illustrates a high-speed serial data rcad_init receiving method applied to a high-speed serial interface 100 according to one embodiment of this application, which can be implemented by operating the firmware of the high-speed serial interface 100.

[0062] Step S402 receives high-speed serial data rcad_init based on the first clock clk. Step S404 generates a multi-phase clock signal group st based on the first clock clk and the second clock fclk. <n:0>And the adjustable sampling clock ck1. Step S406 utilizes this multi-phase clock signal group st <n:0>Convert the high-speed serial data rcad_init into initial parallel data rcad <n:0>Step S408 utilizes the adjustable sampling clock ck1 to process the initial parallel data rcad. <n:0>Sampling is performed, and the data is converted into parallel displacement data rcad_shift <n:0>Step S410 utilizes the second clock fclk to process the parallel displacement data rcad_shift. <n:0>Sampling is performed to convert the output parallel data rcad_out. <n:0>.

[0063] The method first performs serial-to-parallel conversion using a high-speed first clock clk, then uses an adjustable sampling clock ck1 to shift the data to match the low-speed second clock fclk, ensuring correct data extraction. The adjustable sampling clock ck1 is adjusted to the appropriate phase using a negative feedback mechanism.

[0064] Figure 5 This is a flowchart illustrating the negative feedback adjustment mechanism according to one embodiment of this application. Step S502, in response to the first clock clk, generates the multi-phase clock signal group st, comprising (n+1) phases. <n:0>Step S504 is based on the multi-phase clock signal group st <n:0>Step S506 generates the adjustable sampling clock ck1. Step S506 detects the phase relationship between the adjustable sampling clock ck1 and the second clock fclk, and generates the phase adjustment signal up / dn. Step S508 dynamically adjusts the phase of the adjustable sampling clock ck1 according to the phase adjustment signal up / dn. In this way, the adjustable sampling clock ck1 is dynamically adjusted to an appropriate phase.

[0065] The beneficial effects of this application are as follows: Unlike traditional schemes that use large-capacity FIFOs for buffering at the logic and physical layers, this application utilizes high-speed clocks for fine-grained phase adjustment and sampling switching at the physical layer. This "analog FIFO" mechanism uses high-speed clock cycles as the adjustment granularity, which not only significantly reduces the latency of data transmission across clock domains, but also provides extremely high phase drift tolerance through a negative feedback adjustment mechanism. It can adapt to large frequency deviations and jitter without data loss, effectively improving the performance and stability of high-speed interconnect systems. All serial-to-parallel conversion technologies implemented at the physical layer using the aforementioned concepts fall within the scope of protection of this application.

[0066] Although this disclosure has been provided above with reference to embodiments, it is not intended to limit this disclosure. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the scope defined in the appended claims.

Claims

1. A high-speed serial interface, comprising: The physical layer is configured to receive high-speed serial data based on a first clock. as well as The logical physical layer is configured to operate according to a second clock with a frequency lower than that of the first clock. The physical layer includes: Serial-to-parallel conversion circuit; The data sampling path includes a first flip-flop and a second flip-flop cascaded between the serial-to-parallel circuit and the logic physical layer; and The control circuit is configured to generate a multi-phase clock signal group and an adjustable sampling clock according to the first clock and the second clock, control the serial-to-parallel circuit to convert the high-speed serial data into initial parallel data according to the multi-phase clock signal group, operate the first flip-flop to convert the initial parallel data into displacement parallel data according to the adjustable sampling clock, and operate the second flip-flop to convert the displacement parallel data into output parallel data to the logic physical layer according to the second clock.

2. The high-speed serial interface as described in claim 1, wherein: The frequency of the first clock is (n+1) times the frequency of the second clock, where n is a positive integer; The control circuit also includes a multi-phase clock generator, which receives the first clock and generates the multi-phase clock signal group, wherein, in response to the first clock, the multi-phase clock signal group includes (n+1) phases. The multi-phase clock signal group is set in turn during the period of the second clock; and The serial-to-parallel conversion circuit extracts the high-speed serial data based on the multi-phase clock signal group, which includes (n+1) phases, and generates (n+1) bits of initial parallel data.

3. The high-speed serial interface as described in claim 2, wherein, The control circuit also includes: An automatic phase adjuster, coupled to the multi-phase clock generator, is used to generate the adjustable sampling clock based on the multi-phase clock signal group; and A phase detector is used to detect the phase relationship between the adjustable sampling clock and the second clock, and outputs a phase adjustment signal to the automatic phase adjuster to dynamically adjust the phase of the adjustable sampling clock.

4. The high-speed serial interface as described in claim 3, wherein: The automatic phase adjuster is also configured to output a front-phase clock whose phase leads the adjustable sampling clock and a rear-phase clock whose phase lags the adjustable sampling clock. The phase detector is configured to receive the adjustable sampling clock, the preceding phase clock, the following phase clock, and the second clock, and to determine whether to activate the phase adjustment signal in response to the phase difference of the second clock relative to the adjustable sampling clock, the preceding phase clock, or the following phase clock.

5. The high-speed serial interface as described in claim 4, wherein: In response to the rising edge of the second clock falling into the warning interval between the rising edge of the adjustable sampling clock and the rising edge of the subsequent phase clock, the phase detector causes the phase adjustment signal to issue a phase forward indication, thereby shifting the phase of the adjustable sampling clock forward.

6. The high-speed serial interface as described in claim 5, wherein: In response to the rising edge of the second clock falling into the warning interval between the rising edge of the previous phase clock and the rising edge of the adjustable sampling clock, the phase detector causes the phase adjustment signal to issue a phase shift indication, thereby shifting the phase of the adjustable sampling clock backward.

7. The high-speed serial interface as described in claim 6, wherein, The control circuit also includes: A digital filter is coupled between the phase detector and the automatic phase adjuster, wherein the digital filter is configured to receive the phase adjustment signal, filter the phase adjustment signal to remove noise or jitter, and output a phase selection signal to the automatic phase adjuster to control the automatic phase adjuster to update the phase of the adjustable sampling clock.

8. The high-speed serial interface as described in claim 7, wherein, The control circuit also includes: The initial timing alignment circuit is configured to receive the first clock, the second clock, and the system enable signal, detect the initial phase relationship between the first clock and the second clock, and generate an alignment enable signal to the multi-phase clock generator, causing the multi-phase clock generator to start the timing of the generation of the multi-phase clock signal group.

9. The high-speed serial interface as described in claim 8, wherein: One clock cycle of the first clock is T; The preceding phase clock leads the adjustable sampling clock by one T; and The subsequent phase clock lags the adjustable sampling clock by one T.

10. The high-speed serial interface as described in claim 9, wherein: The automatic phase adjuster causes the phase of the preceding phase clock of the adjustable sampling clock to shift relative to the first clock in the multi-phase clock signal group from -0.5T to (n-0.5)T, with the shift amount based on the phase selection signal and adjusted in units of 1T.

11. A method for receiving high-speed serial data using a high-speed serial interface, the high-speed serial interface comprising a physical layer and a logical physical layer, the method comprising: It receives high-speed serial data based on a first clock and provides a second clock with a frequency lower than the first clock for the operation of the logic physical layer; Based on the first clock and the second clock, a multi-phase clock signal group and an adjustable sampling clock are generated; This multi-phase clock signal group is used to convert the high-speed serial data into initial parallel data; The initial parallel data is sampled using this adjustable sampling clock to convert it into displacement parallel data; as well as The displacement parallel data is sampled using the second clock to convert it into output parallel data and transmit it to the logic physical layer.

12. The high-speed serial data receiving method as described in claim 11, wherein: The frequency of the first clock is set to be (n+1) times the frequency of the second clock, where n is a positive integer; The steps for generating this multi-phase clock signal group include: In response to the first clock, a multi-phase clock signal group comprising (n+1) phases is generated, such that the multi-phase clock signal group is sequentially set within the period of the second clock; and The steps for converting the high-speed serial data into the initial parallel data include: Based on the (n+1) phases of the multi-phase clock signal group, the high-speed serial data is extracted sequentially to generate (n+1) bits of initial parallel data.

13. The high-speed serial data receiving method as described in claim 12, further comprising: The adjustable sampling clock is generated based on the multi-phase clock signal group; Detect the phase relationship between the adjustable sampling clock and the second clock; as well as Based on the phase relationship between the adjustable sampling clock and the second clock, a phase adjustment signal is generated to dynamically adjust the phase of the adjustable sampling clock.

14. The high-speed serial data receiving method as described in claim 13, further comprising: The output phase leads the previous phase clock of the adjustable sampling clock and lags the next phase clock. The step of detecting the phase relationship between the adjustable sampling clock and the second clock includes: The system receives the adjustable sampling clock, the front phase clock, the rear phase clock, and the second clock, and determines the phase difference of the second clock relative to the adjustable sampling clock, the front phase clock, or the rear phase clock, and decides whether to activate the phase adjustment signal.

15. The high-speed serial data receiving method as described in claim 14, wherein: In response to the rising edge of the second clock falling into the warning interval between the rising edge of the adjustable sampling clock and the rising edge of the subsequent phase clock, the phase adjustment signal provides a phase forward indication, causing the phase of the adjustable sampling clock to be forward.

16. The high-speed serial data receiving method as described in claim 15, wherein: In response to the rising edge of the second clock falling into the warning interval between the rising edge of the previous phase clock and the rising edge of the adjustable sampling clock, the phase adjustment signal provides a phase shift indication, causing the phase of the adjustable sampling clock to shift backward.

17. The high-speed serial data receiving method as described in claim 16, further comprising: The phase adjustment signal is digitally filtered to remove noise or jitter, and a phase selection signal is output to update the phase selection of the adjustable sampling clock.

18. The high-speed serial data receiving method as described in claim 17, further comprising: Receive the first clock, the second clock, and the system enable signal; as well as The initial phase relationship between the first clock and the second clock is detected to generate an alignment enable signal and initiate the timing of the generation of the multi-phase clock signal group.

19. The high-speed serial data receiving method as described in claim 18, wherein: One clock cycle of the first clock is defined as T; The preceding phase clock leads the adjustable sampling clock by one T; and The subsequent phase clock lags the adjustable sampling clock by one T.

20. The high-speed serial data receiving method as described in claim 19, wherein, The steps for dynamically adjusting the adjustable sampling clock include: Based on the phase selection signal, the phase of the preceding phase clock of the adjustable sampling clock is shifted relative to the first clock in the multi-phase clock signal group between -0.5T and (n-0.5)T, and the adjustment unit of the shift is 1T.

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