Embedded device interface control circuit and method, embedded device

Abstract

The application provides an embedded device interface control circuit and method and an embedded device. The embedded device interface control circuit comprises an interface connector, an interface controller and a switch tube. The interface connector is used for connecting the embedded device with an external device. The interface controller is coupled to the interface connector and is used for identifying the external device connected to the interface connector. If it is identified that the external device is a host, the output end of the interface controller outputs a first level. The switch tube is coupled to the output end of the interface controller and an upgrade activation pin of the host. Under the control of the first level, the switch tube makes the input level of the upgrade activation pin an activation enable level, so that the host upgrades the embedded device through the interface connector. The embedded device interface control circuit can improve the automation degree of system upgrade and improve the reliability of system upgrade.

Description

Technical Field

[0001] This application relates to the field of embedded systems technology, and more specifically, to an embedded device interface control circuit and method, and an embedded device. Background Technology

[0002] In existing technologies, system upgrades for embedded devices, industrial controllers, etc., are mainly achieved through two types of solutions, both of which suffer from the core defect of "insufficient automation." One type uses a dedicated USB (Universal Serial Bus) port as an upgrade port. Although this eliminates the need for manual upgrade triggering, it consumes additional hardware resources, increases costs, creates design redundancy, and reduces interface reuse. The other type reuses existing USB ports, but requires manually shorting the Recovery pin using mechanical switches such as jumpers and DIP switches to trigger the upgrade. This is not only cumbersome and prone to errors, but also affects upgrade reliability. Summary of the Invention

[0003] This application provides an embedded device interface control circuit and method, and an embedded device, which aims to improve the automation level and reliability of system upgrades.

[0004] In view of the above, the first aspect of this application provides an embedded device interface control circuit, including: an interface connector, an interface controller, and a switching transistor; the interface connector is used for connecting the embedded device to an external device; the interface controller is coupled to the interface connector and is used to identify the external device connected to the interface connector, and when the external device is identified as a host, the output terminal of the interface controller outputs a first level; the switching transistor is coupled to the output terminal of the interface controller and the upgrade activation pin of the host, wherein, under the control of the first level, the input level of the upgrade activation pin is set to the activation enable level, thereby the host upgrades the embedded device through the interface connector.

[0005] In the above technical solution, the interface controller can identify the type of external device and output the corresponding level signal. By automatically identifying the external device, if the interface controller determines that the external device is a host capable of upgrading embedded devices, it will output a first level to control the switching transistor. The switching transistor is a switching component controlled by a level signal. The action of the switching transistor enables the upgrade activation pin on the host, which receives the upgrade trigger signal, to obtain an activation level, thereby enabling the host's upgrade function and realizing automatic upgrades of embedded devices by the host through the interface. This allows for upgrade triggering without human intervention, improving the automation level of the upgrade operation; at the same time, it utilizes existing interfaces to implement the upgrade function, eliminating the need for additional dedicated upgrade interfaces, saving hardware resources, reducing hardware costs, and avoiding the risk of misoperation that may occur with manual operation, thus ensuring the reliability of the system upgrade.

[0006] Optionally, in some technical solutions of this application, when the external device is identified as a non-host device, the output terminal of the interface controller outputs a second level, and the switching transistor, under the control of the second level, makes the input level of the upgrade activation pin a non-activation enable level, so that the embedded device exchanges data with other devices through the interface connector.

[0007] In the above technical solution, when the interface controller identifies an external device as a non-host device (e.g., a device that lacks the capability to upgrade the embedded device and can only perform routine interactions such as information transmission and data reading / writing), the interface controller outputs a second-level control switch. The switch's action deactivates the upgrade activation pin to a non-activation enable level, thereby enabling the embedded device to exchange data with other non-host devices. This ensures the embedded device does not enter upgrade mode and can perform normal data exchange. This allows for automatic identification and adaptive mode switching of different types of external devices by the embedded device, eliminating the need for manual adjustment of the interface's operating mode and improving the flexibility and convenience of interface use. Simultaneously, it avoids upgrade failures or data exchange anomalies caused by incorrect mode switching, ensuring device stability and adapting to interface usage requirements in various scenarios.

[0008] In some technical solutions of this application, optionally, the switching transistor is an N-channel metal-oxide-semiconductor transistor, the output terminal of the interface controller is coupled to the gate of the N-channel metal-oxide-semiconductor transistor, the source of the N-channel metal-oxide-semiconductor transistor is grounded, the drain of the N-channel metal-oxide-semiconductor transistor is coupled to the upgrade activation pin, and the upgrade activation pin is also coupled to the first power supply through the first pull-up resistor.

[0009] The first level is high, which turns on the N-channel metal-oxide-semiconductor transistor and activates the enable level to go low, enabling the host to upgrade the embedded device. The second level is low, which turns off the N-channel metal-oxide-semiconductor transistor and activates the enable level to go high under the action of the first power supply and the first pull-up resistor, enabling the host not to upgrade the embedded device.

[0010] In the above technical solution, an N-channel metal-oxide-semiconductor (MOSFET) is used as the switching transistor. The output of the interface controller is coupled to the gate of the N-channel MOSFET, the source of the N-channel MOSFET is grounded, and the drain is coupled to the upgrade activation pin. The upgrade activation pin is also coupled to the first power supply through a first pull-up resistor. The first voltage level is high, and the second voltage level is low. The N-channel MOSFET controls the switching between the source and drain through the gate voltage level, which has the advantages of fast switching response and low power consumption, and also makes the circuit structure clearer and more feasible. The first pull-up resistor is connected to the first power supply at one end and to the upgrade activation pin at the other end, which can stabilize the voltage level of the upgrade activation pin when there is no trigger signal, ensuring the reliability of the voltage level. The control logic of high-level conduction and low-level turn-off conforms to conventional circuit design habits, which can further improve the stability and accuracy of circuit control.

[0011] Optionally, in some technical solutions of this application, the embedded device interface control circuit may further include: a power load switch, used to control the supply of operating power to other devices;

[0012] Specifically, when the second level is input to the enable terminal of the power load switch, the output terminal of the power load switch outputs the operating power of other devices; when the first level is input to the enable terminal of the power load switch, the output terminal of the power load switch does not output the operating power of other devices.

[0013] In the above technical solution, the power load switch is a component used to control the on / off state of the power output. It has functions such as load protection and current limiting, enabling precise control of the power supply to non-host devices. In scenarios where other non-host devices are connected, the power load switch stably outputs power, ensuring the normal operation of these devices. In upgrade scenarios, the power load switch stops supplying power, reducing system power consumption and preventing power supply interference from affecting the upgrade process. This improves system energy efficiency, strengthens the isolation between different operating modes, ensures precise matching between power supply and operating modes, and enhances overall system stability.

[0014] Optionally, in some technical solutions of this application, the embedded device interface control circuit further includes a first mode resistor and a second mode resistor. The first mode resistor is coupled between the second power supply and the first mode pin of the interface controller, and the second mode resistor is coupled between the second power supply and the second mode pin of the interface controller. The first mode output pin of the interface controller is coupled to the first mode input pin of the interface connector, and the second mode output pin of the interface connector is coupled to the second mode input pin of the external device.

[0015] In the above technical solution, the first-mode resistor and the second-mode resistor are used to set the operating mode of the interface controller, enabling flexible configuration of the interface controller in master-slave mode. Master mode is the operating mode where the interface controller acts as the data transmission leader; slave mode is the operating mode where the interface controller acts as the passive party. The interface controller can accurately transmit mode information to external devices through the interface connector, improving the compatibility and versatility of the embedded device interface, allowing it to stably adapt to external devices in different modes. The configuration method of the first-mode resistor and the second-mode resistor is simple and reliable, requiring no complex software configuration, thus reducing system design complexity; through hardware-level mode identification transmission, accurate mode matching between external devices and embedded devices can be ensured, guaranteeing a stable and efficient interaction process.

[0016] Optionally, in some technical solutions of this application, when the interface controller needs to operate in master mode, the first mode pin is coupled to the first mode output pin, so that the first mode output pin outputs a first mode current. The first mode current flows sequentially through the first mode input pin and the second mode output pin into the second mode input pin, which is used to notify the external device that it is in slave mode. When the interface controller needs to operate in slave mode, the second mode pin is coupled to the first mode output pin, so that the first mode output pin outputs a second mode current. The second mode current flows sequentially through the first mode input pin and the second mode output pin into the second mode input pin, which is used to notify the external device that it is in master mode.

[0017] In the above technical solution, the master mode is the operating mode in which the interface controller actively sends signals; the slave mode is the operating mode in which the interface controller receives external signals and responds. By using different connection methods between the mode pins and output pins corresponding to the first and second mode resistors, corresponding mode currents are output, achieving accurate transmission of mode status. When the interface controller operates in master mode, it notifies the external device of its slave mode via the first mode current; when the interface controller operates in slave mode, it notifies the external device of its master mode via the second mode current, ensuring coordinated matching between the two modes. This enables fast and accurate transmission of mode information, improving the efficiency and stability of connections between devices; mode switching can be achieved simply through pin connections, simplifying operation, eliminating the need for complex software configuration, and reducing usage and maintenance costs.

[0018] Optionally, in some technical solutions of this application, there are multiple second-mode resistors, each with a different resistance value and corresponding to a different host type. The multiple second-mode resistors are respectively coupled between a second power supply and multiple second-mode pins. When the interface controller needs to operate in slave mode, the second-mode pin corresponding to the host type is coupled to the first-mode output pin, so that the first-mode output pin outputs a second-mode current corresponding to the host type. The second-mode current flows sequentially through the first-mode input pin and the second-mode output pin into the second-mode input pin, which is used to notify the host type that the host is in master mode.

[0019] In the above technical solution, multiple second-mode resistors with different resistance values ​​are used to adapt to different host types, enabling accurate identification and adaptation of various host devices. Multiple second-mode pins are mode setting pins on the interface controller, each corresponding to one of the multiple second-mode resistors. In slave mode, the corresponding second-mode pin is selected and connected to the output pin according to the connected host type, outputting a matched second-mode current. This allows the external host to accurately identify the adaptation status of the embedded device. This significantly expands the applicability of embedded devices, meeting the upgrade and adaptation needs of various host devices in different scenarios. Host type differentiation is achieved through differences in resistance values; the hardware implementation is simple, reliable, and low-cost, balancing compatibility and economy, thus enhancing the practical value of the solution.

[0020] The second aspect of this application provides an embedded device, including: an embedded device interface control circuit as provided in any of the above technical solutions. Therefore, it can achieve all the same technical effects, and to avoid repetition, it will not be described again here.

[0021] A third aspect of this application provides an embedded device interface control method, comprising:

[0022] Identify external devices coupled to the interface connector of embedded devices;

[0023] If the external device is identified as the host, the first level is output;

[0024] By controlling the switch transistor at the first level, the input level of the host's upgrade activation pin is set to the activation enable level, thereby enabling the host to upgrade the embedded device through the interface connector;

[0025] If the external device is identified as a non-host device, a second level is output.

[0026] By controlling the switch transistor with the second level, the input level of the host's upgrade activation pin is set to the inactive enable level, thus preventing the host from upgrading the embedded device.

[0027] In the above technical solution, the embedded device interface control method can realize the automated control of external device identification and embedded device interface mode switching. It can complete the embedded device upgrade triggering or data exchange preparation between the embedded device and the external device without human intervention, which significantly improves the automation level of embedded device interface control. At the same time, it can avoid problems such as accidental triggering and accidental switching of embedded device interface modes caused by manual operation, ensure the stable execution of embedded device interface control actions, and improve the reliability of embedded device system upgrades.

[0028] In some technical solutions of this application, optionally, the embedded device interface control method is executed by the embedded device interface control circuit;

[0029] Before identifying external devices coupled to the interface connector of the embedded device, the embedded device interface control method also includes:

[0030] When it is necessary to upgrade an embedded device, couple the external device to the interface connector, and then power on the interface control circuit of the embedded device.

[0031] Without needing to upgrade the embedded device, power on the embedded device interface control circuit and then couple the external device to the interface connector.

[0032] In the above technical solution, power-on is the operation of providing power to the embedded device interface control circuit; the power-on sequence is the order in which power is supplied to the embedded device interface control circuit and external devices are connected.

[0033] In the above technical solution, in upgrade scenarios, the external device is connected first before powering on the embedded device interface control circuit; in non-upgrade scenarios, the embedded device interface control circuit is powered on first before connecting the external device. This ensures that the embedded device interface control circuit can accurately identify the type of external device and stably enter the corresponding working mode in different scenarios. It also standardizes the power-on process, reduces user difficulty, improves ease of operation, and guarantees stable operation of the embedded device in different usage scenarios.

[0034] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0035] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0036] Figure 1 A circuit structure diagram of the interface controller provided in the embodiments of this application;

[0037] Figure 2A circuit structure diagram of the interface connector provided in the embodiments of this application;

[0038] Figure 3 The circuit structure diagram of the switching transistor provided in the embodiments of this application;

[0039] Figure 4 A circuit diagram of a power load switch provided in an embodiment of this application;

[0040] Figure 5 A structural block diagram of an embedded device provided in an embodiment of this application;

[0041] Figure 6 One of the flowcharts for an embedded device interface control method provided in this application embodiment;

[0042] Figure 7 A second flowchart illustrating an embedded device interface control method provided in this application embodiment;

[0043] Figure 8 A flowchart of an embedded device interface control method provided in this application embodiment is shown as the third one.

[0044] Figure 9 This is the fourth flowchart of an embedded device interface control method provided in an embodiment of this application.

[0045] Reference numerals: 1 Embedded device; 2 External device; 10 Interface connector; 20 Interface controller; Q1 Switch; 31 Upgrade activation pin; Rs First pull-up resistor; 32 First power supply; 40 Power load switch; 21 First mode pin; 22 Second mode pin; 13 First mode input pin; 23 First mode output pin; 24 Second mode input pin; 14 Second mode output pin; 25 Second power supply; R5 First mode resistor; R1, R2, R3, R4 Second mode resistors; 100 Embedded device interface control circuit. Detailed Implementation

[0046] To better understand the above-mentioned objectives, features, and advantages of this application, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0047] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Therefore, the scope of protection of this application is not limited to the specific embodiments disclosed below.

[0048] The following reference Figures 1 to 9This application describes an embedded device interface control circuit and method, and an embedded device, according to some embodiments thereof.

[0049] like Figures 1 to 3 As shown, the first aspect of this application provides an embedded device interface control circuit 100, including an interface connector 10, an interface controller 20, and a switch Q1; the interface connector 10 is used to connect an embedded device 1 to an external device 2; the interface controller 20 is coupled to the interface connector 10 and is used to identify the external device 2 connected to the interface connector 10, and when the external device 2 is identified as a host, the output terminal of the interface controller 20 outputs a first level; the switch Q1 is coupled to the output terminal of the interface controller 20 and the upgrade activation pin 31 of the host, wherein, under the control of the first level, the switch Q1 makes the input level of the upgrade activation pin 31 an activation enable level, so that the host upgrades the embedded device 1 through the interface connector 10.

[0050] In the above embodiment, the interface controller 20 can identify the type of external device 2 and output a corresponding level signal. By automatically identifying the external device 2, if the interface controller 20 determines that the external device 2 is a host capable of upgrading the embedded device 1, the interface controller 20 will output a first level to control the switch Q1. The switch Q1 is an on / off component controlled by a level signal. The action of the switch Q1 enables the upgrade activation pin 31 on the host, which receives the upgrade trigger signal, to obtain an activation enable level, thereby enabling the host's upgrade function and realizing automatic upgrade of the embedded device 1 by the host through the interface. This allows for upgrade triggering without human intervention, improving the automation level of the upgrade operation; at the same time, it utilizes the existing interface to implement the upgrade function, eliminating the need for an additional dedicated upgrade interface, saving hardware resources, reducing hardware costs, and avoiding the risk of misoperation that may occur during manual operation, thus ensuring the reliability of the system upgrade.

[0051] It should be noted that, as Figure 1 As shown, in Figure 1In this context, +5V is an example of an input voltage of +5V; VBUS (VoltageBus) is used to indicate the power supply line of the power bus. USBC_OUT1 (USB Type-C Output 1) corresponds to OUT1 of interface controller 20, and USBC_OUT2 (USB Type-C Output 2) corresponds to OUT2 of interface controller 20. These are the external control signal output terminals of interface controller 20, enabling interactive control with external devices. VCONN_FAULT# (Voltage Connection Fault) is connected to VCONN_FAULT of interface controller 20 and is a power fault detection pin, monitoring abnormal VCONN power conditions. USBC_IMODE (USB Type-C Interface Mode) is connected to CURRENT_MODE of interface controller 20 and serves as the interface mode configuration terminal, setting the interface's operating mode. USBC_DIR (USB Type-C Direction) corresponds to DIR of interface controller 20 and is a data direction indicator pin, indicating the direction of data transmission. VDD (Voltage Drain) of interface controller 20... The Drain (positive power terminal) is the power input port, providing operating power to the interface controller 20; ID (Identification) is connected to USBC_ID (USB Type-C Identification) to identify the type of device connected to the interface; VBUS_DET (VBUS Detection) detects the power supply status of VBUS (Voltage Bus); PORT (Port Configuration) is connected to the external signal TP1 to configure the port operating mode of the interface controller 20; GND (Ground) provides an electrical reference ground for the circuit; CC1 (Configuration Channel 1) and CC2 (Configuration Channel 2) are the core pins of the USB Type-C interface, negotiating parameters such as the master / slave mode and power supply capability of the interface. C1, C2, and C3 are all filter capacitors, and C1, C2, and C3 are all coupled to DGND (Digital Ground).

[0052] For example, such as Figure 2As shown, R6 is a resistor, which can be 910K ohms; R9 can be 10K ohms or 0 ohms; R10 can be 10K ohms or 0 ohms; C1 is a filter capacitor, which can be 0.1 microfarads with a rated operating voltage of 20V; C2 and C3 are filter capacitors, which can be 100 picofarads with a rated operating voltage of 50V and made of C0G material, used to filter out noise.

[0053] It should be noted that, as Figure 2 As shown, USB_VBUS (Voltage Bus) is the power supply line for the USB interface; UA corresponds to the first group of differential signal channels; UB corresponds to the second group of differential signal channels; the inductor in the left differential signal link is used to suppress high-frequency interference of the data signal, and TVS1 (transient voltage suppressor diode) is coupled to DGND (Digital Ground) to suppress data signal surge voltage and ensure transmission stability; U_CC1 and U_CC2 (corresponding to the CC1 and CC2 pins of the interface controller 20) are USB The Type-C configuration channel pins are coupled to DGND via TVS2 and TVS3 for surge protection. Internally, U_Dp1 / U_Dn1 and U_Dp2 / U_Dn2 are USB differential data pins, U_SSTxp1 / U_SSTxn1 and U_SSTxp2 / U_SSTxn2 are USB ultra-high-speed transmit differential data pins, and U_SSRXp1 / U_SSRXn1 and U_SSRXp2 / U_SSRXn2 are USB ultra-high-speed receive differential data pins. The data pins are divided into two parts, each responsible for data transmission at different rates. Pins U_VBUS1 to U_VBUS4 are all connected to USB_VBUS to provide power to the interface. Pins U_GND1 to U_GND4 are coupled to DGND to form the electrical reference ground of the circuit. Pins U_SBU1 and U_SBU2 are sideband pins that support the expansion functions of the USB interface. The right-side SHIELD pins G1 to G4 are connected to PE (protective ground) to achieve electromagnetic shielding of the interface and improve anti-interference capability.

[0054] For example, such as Figure 3 As shown, in Figure 3 In the diagram, R17 and R18 are resistors; R17 can be 0 ohms and R18 can be 1 megohm. C9 is a filter capacitor; C9 can be a capacitor with a capacitance of 1000 picofarads, a rated operating voltage of 50V, and a C0G material.

[0055] For example, both the interface connector 10 and the interface controller use USB Type-C ports.

[0056] like Figures 1 to 3As shown, in some embodiments of this application, optionally, when the external device 2 is identified as another device that is not the host, the output terminal of the interface controller 20 outputs a second level, and the switch Q1, under the control of the second level, makes the input level of the upgrade activation pin 31 a non-activation enable level, so that the embedded device 1 exchanges data with other devices through the interface connector 10.

[0057] In the above embodiments, when the interface controller 20 identifies the external device 2 as a non-host device, such as a device that does not have the capability to upgrade the embedded device 1 and can only perform conventional interactions such as information transmission and data reading / writing with the embedded device 1, the interface controller 20 will output a second level to control the switch Q1. The action of the switch Q1 can put the upgrade activation pin 31 at a non-activation enable level, thereby enabling the embedded device 1 to exchange data with other non-host devices, ensuring that the embedded device 1 does not enter upgrade mode and can carry out normal data exchange. In this way, the embedded device 1 can automatically identify and adaptively switch modes for different types of external devices 2 without manually adjusting the interface working mode, improving the flexibility and convenience of interface use; at the same time, it can avoid upgrade failure or data exchange abnormalities caused by incorrect mode switching, ensuring the stability of device operation and adapting to the interface usage requirements in multiple scenarios.

[0058] like Figure 3 As shown, in some embodiments of this application, optionally, the switching transistor Q1 is an N-channel metal-oxide-semiconductor transistor, the output terminal of the interface controller 20 is coupled to the gate of the N-channel metal-oxide-semiconductor transistor, the source of the N-channel metal-oxide-semiconductor transistor is grounded, the drain of the N-channel metal-oxide-semiconductor transistor is coupled to the upgrade activation pin 31, and the upgrade activation pin 31 is also coupled to the first power supply 32 through the first pull-up resistor Rs.

[0059] The first level is high, which turns on the N-channel metal-oxide-semiconductor transistor and activates the enable level to go low, enabling the host to upgrade the embedded device 1; the second level is low, which turns off the N-channel metal-oxide-semiconductor transistor and activates the enable level to go high under the action of the first power supply 32 and the first pull-up resistor Rs, enabling the host not to upgrade the embedded device 1.

[0060] In the above embodiment, an N-channel metal-oxide-semiconductor (MOSFET) is used as the switch Q1. The output of the interface controller 20 is coupled to the gate of the N-channel MOSFET, the source of the N-channel MOSFET is grounded, and the drain is coupled to the upgrade activation pin 31. The upgrade activation pin 31 is also coupled to the first power supply 32 through a first pull-up resistor Rs. The first level is high, and the second level is low. The N-channel MOSFET controls the switching between the source and drain through the gate level, which has the advantages of fast switching response and low power consumption, and also makes the circuit structure clearer and more feasible. Among them, one end of the first pull-up resistor Rs is connected to the first power supply 32, and the other end is connected to the upgrade activation pin 31, which can stabilize the level of the upgrade activation pin 31 when there is no trigger signal, ensuring the reliability of the level state. The control logic of high-level conduction and low-level turn-off conforms to conventional circuit design habits, which can further improve the stability and accuracy of circuit control.

[0061] like Figure 4 As shown, in some embodiments of this application, the embedded device interface control circuit 100 may optionally include: a power load switch 40 for controlling the supply of operating power to other devices;

[0062] Specifically, when the second level is input to the enable terminal of the power load switch 40, the output terminal of the power load switch 40 outputs the operating power of other devices; when the first level is input to the enable terminal of the power load switch 40, the output terminal of the power load switch 40 does not output the operating power of other devices.

[0063] In the above embodiments, the power load switch 40 is a component used to control the on / off state of the power output. It has functions such as load protection and current limiting, and can achieve precise control over the power supply of other devices that are not the host. In scenarios where other devices are connected, the power load switch 40 stably outputs power to ensure the normal operation of these devices. In upgrade scenarios, the power load switch 40 stops supplying power, which reduces system power consumption and avoids the impact of power supply interference on the upgrade process. This improves system energy efficiency, strengthens the isolation between different operating modes, ensures precise matching between power supply and operating mode, and enhances overall system stability.

[0064] It should be noted that, as Figure 4 As shown, in Figure 4In the configuration, a +5V power supply is connected, and VOUT outputs voltage to USB_VBUS (Voltage Bus) as the interface power bus power supply line. EN is an active-low enable pin, ILIM (pin 4) is used to configure the current threshold, IN is the signal input pin, OUT is the output pin, FAULT is an active-low open-drain fault indicator pin, OVCUR outputs overvoltage / overcurrent status, TP2 is the overvoltage / overcurrent status test point, EP (Exposed Pad) is the exposed pad pin used for heat dissipation, GND is coupled to DGND (Digital Ground) to form an electrical reference ground, FB1 monitors the VOUT load status, and TVS4 is a transient suppression diode coupled between USB_VBUS and DGND to suppress power surge voltage.

[0065] For example, R13 and R14 are resistors, R13 can be 10 kΩ and R14 can be 10 kΩ; R15 can be 0 Ω and R16 can be 44.2 kΩ; C4 is a filter capacitor, C4 can be 10 μF with a rated operating voltage of 20V; C5 is a filter capacitor, C5 can be 0.1 μF with a rated operating voltage of 50V; C6 and C7 are filter capacitors, C6 and C7 can be 4.7 μF with a rated operating voltage of 16V; C8 is a filter capacitor, C8 can be 0.1 μF with a rated operating voltage of 50V.

[0066] like Figure 1 , Figure 2 and Figure 3 As shown, in some embodiments of this application, the embedded device interface control circuit 100 may optionally include a first mode resistor R5 and second mode resistors R1, R2, R3, and R4. The first mode resistor R5 is coupled between the second power supply 25 and the first mode pin 21 of the interface controller 20. The second mode resistors R1, R2, R3, and R4 are coupled between the second power supply 25 and the second mode pin 22 of the interface controller 20. The first mode output pin 23 of the interface controller 20 is coupled to the first mode input pin 13 of the interface connector 10. The interface connector 10 is coupled to the second mode input pin 24 of the external device 2.

[0067] In the above embodiments, the first mode resistor R5 and the second mode resistors R1, R2, R3, and R4 are used to set the operating mode of the interface controller 20, enabling flexible configuration of the interface controller 20 in master-slave mode. The master mode is the operating mode in which the interface controller 20 acts as the data transmission leader; the slave mode is the operating mode in which the interface controller 20 acts as the passive party. The interface controller 20 can accurately transmit mode information to the external device 2 through the interface connector 10, improving the compatibility and versatility of the embedded device 1's interface, allowing it to stably adapt to external devices 2 in different modes. The configuration of the first mode resistor R5 and the second mode resistors R1, R2, R3, and R4 is simple and reliable, requiring no complex software configuration and reducing system design complexity. Through hardware-level mode identification transmission, accurate mode matching between the external device 2 and the embedded device 1 is ensured, guaranteeing a stable and efficient interaction process.

[0068] It should be noted that, as Figure 2 As shown, the first mode input pin 13 and the second mode output pin 14 are the same pin in a physical sense (i.e., the U_CC1 / U_CC2 pins of the interface connector 10), and their functions are divided only based on the different signal flow directions: when this pin receives the mode signal output by the interface controller 20, the corresponding function is the first mode input pin 13; when this pin outputs the mode signal to the external device 2, the corresponding function is the second mode output pin 14.

[0069] like Figure 1 As shown, the first mode output pin (23) and the second mode input pin (24) are the same pin in a physical sense (i.e., the CC1 / CC2 pins of the interface controller (20)). The functions are divided only based on the different signal flow directions: when this pin outputs a mode signal to the interface connector (10), the corresponding function is the first mode output pin (23); when this pin receives the mode signal transmitted by the interface connector (10), the corresponding function is the second mode input pin of the interface controller (20).

[0070] like Figure 1 , Figure 2 and Figure 3 As shown, in some embodiments of this application, optionally, when the interface controller 20 needs to work in master mode, the first mode pin 21 is coupled to the first mode output pin 23, so that the first mode output pin 23 outputs the first mode current. The first mode current flows sequentially through the first mode input pin 13 and the second mode output pin 14 into the second mode input pin 24, which is used to notify the external device 2 that it is in slave mode.

[0071] When the interface controller 20 needs to operate in slave mode, the second mode pin 22 is coupled to the first mode output pin 23, so that the first mode output pin 23 outputs the second mode current. The second mode current flows sequentially through the first mode input pin 13 and the second mode output pin 14 into the second mode input pin 24, which is used to notify the external device 2 that it is in master mode.

[0072] In the above embodiments, the master mode is the operating mode in which the interface controller 20 actively sends signals; the slave mode is the operating mode in which the interface controller 20 receives external signals and responds. By using different connection methods between the mode pins and output pins corresponding to the first mode resistor R5 and the second mode resistors R1, R2, R3, and R4, corresponding mode currents are output to achieve accurate transmission of mode status. When the interface controller 20 operates in master mode, it notifies the external device 2 that it is in slave mode via the first mode current; when the interface controller 20 operates in slave mode, it notifies the external device 2 that it is in master mode via the second mode current, ensuring that the modes of both devices are matched. This enables fast and accurate transmission of mode information, improving the efficiency and stability of inter-device connections; mode switching can be achieved simply through pin connections, making operation simple, requiring no complex software configuration, and reducing usage and maintenance costs.

[0073] like Figure 1 , Figure 2 and Figure 3 As shown, in some embodiments of this application, optionally, there are multiple second-mode resistors R1, R2, R3, and R4, each with a different resistance value and corresponding to a different host type. The multiple second-mode resistors R1, R2, R3, and R4 are respectively coupled between the second power supply 25 and multiple second-mode pins 22. When the interface controller 20 needs to operate in slave mode, the second-mode pin 22 corresponding to the host type is coupled to the first-mode output pin 23, so that the first-mode output pin 23 outputs a second-mode current corresponding to the host type. The second-mode current flows sequentially through the first-mode input pin 13 and the second-mode output pin 14 into the second-mode input pin 24 to notify the host type that the host is in master mode.

[0074] In the above embodiments, multiple second-mode resistors R1, R2, R3, and R4 with different resistance values ​​are used to adapt to different host types, enabling accurate identification and adaptation of various host devices. Multiple second-mode pins 22 are mode setting pins on the interface controller 20 that correspond one-to-one with the multiple second-mode resistors R1, R2, R3, and R4. In slave mode, the corresponding second-mode pin 22 is selected and connected to the output pin according to the connected host type, outputting a matching second-mode current, allowing the external host to accurately identify the adaptation status of the embedded device 1. This significantly expands the applicability of the embedded device 1, meeting the upgrade and adaptation needs of various host devices in different scenarios; host type differentiation is achieved through resistance value differences, the hardware implementation is simple, reliable, and low-cost, balancing compatibility and economy, and enhancing the practical value of the solution.

[0075] For example, the first mode resistor R5 can be 10K ohms, R1 can be 10K ohms, and R2, R3, and R4 can be 200K ohms.

[0076] like Figure 5 As shown, the second aspect of this application provides an embedded device 1, including: an embedded device interface control circuit 100 as provided in any of the above embodiments. Therefore, all the same technical effects can be achieved, and to avoid repetition, further details are omitted here.

[0077] like Figure 6 and Figure 7 As shown, a third aspect of this application provides an embedded device interface control method, comprising:

[0078] S100: Identifies external devices coupled to the interface connector of embedded devices;

[0079] S110a: When the external device is identified as the host, the first level is output;

[0080] S120a: By controlling the switching transistor with the first level, the input level of the host's upgrade activation pin is set to the activation enable level, thereby enabling the host to upgrade the embedded device through the interface connector;

[0081] S110b: When the external device is identified as a non-host device, output the second level;

[0082] S120b: By controlling the switch transistor with the second level, the input level of the host's upgrade activation pin is set to the inactive enable level, so that the host does not upgrade the embedded device.

[0083] In the above embodiments, the embedded device interface control method can realize the automated control of external device identification and embedded device interface mode switching. It can complete the embedded device upgrade triggering or the data exchange preparation between the embedded device and the external device without human intervention, which significantly improves the automation level of embedded device interface control. At the same time, it can avoid problems such as accidental triggering and accidental switching of embedded device interface modes caused by manual operation, ensure the stable execution of embedded device interface control actions, and improve the reliability of embedded device system upgrades.

[0084] like Figure 8 and Figure 9 As shown, in some embodiments of this application, optionally, the embedded device interface control method is executed by the embedded device interface control circuit;

[0085] Before identifying external devices coupled to the interface connector of the embedded device, the embedded device interface control method also includes:

[0086] S90a: When it is necessary to upgrade the embedded device, couple the external device to the interface connector, and then power on the interface control circuit of the embedded device.

[0087] S90b: Power on the embedded device interface control circuit without upgrading the embedded device, and then couple the external device to the interface connector.

[0088] In the above embodiments, power-on is the operation of providing power to the embedded device interface control circuit; the power-on sequence is the order in which power is supplied to the embedded device interface control circuit and external devices are connected.

[0089] In the above embodiments, in upgrade scenarios, the external device is connected first before powering on the embedded device interface control circuit; in non-upgrade scenarios, the embedded device interface control circuit is powered on first before connecting the external device. This ensures that the embedded device interface control circuit can accurately identify the type of external device and stably enter the corresponding working mode in different scenarios. It also standardizes the power-on process, reduces user difficulty, improves ease of operation, and guarantees stable operation of the embedded device in different usage scenarios.

[0090] In the claims, description, and accompanying drawings of this application, the term "plural" refers to two or more objects. Unless otherwise explicitly defined, the terms "upper," "lower," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used solely for the convenience of describing this application and simplifying the descriptive process, and are not intended to indicate or imply that the device or element referred to must have the described specific orientation, or be constructed and operated in a specific orientation. Therefore, these descriptions should not be construed as limitations on this application. The terms "connection," "installation," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection between multiple objects, a detachable connection between multiple objects, or an integral connection; it can be a direct connection between multiple objects or an indirect connection between multiple objects through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in this application can be understood based on the specific circumstances described above.

[0091] In the claims, description, and accompanying drawings of this application, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this application. In the claims, description, and accompanying drawings of this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0092] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An embedded device interface control circuit, characterized in that, include: Interface connectors are used to connect embedded devices to external devices. An interface controller, coupled to the interface connector, is used to identify the external device connected to the interface connector, and when the external device is identified as a host, the output terminal of the interface controller outputs a first level. A switching transistor is coupled to the output of the interface controller and the upgrade activation pin of the host. Under the control of the first level, the switching transistor makes the input level of the upgrade activation pin an activation enable level, so that the host can upgrade the embedded device through the interface connector.

2. The embedded device interface control circuit according to claim 1, characterized in that, When the external device is identified as a non-host device, the interface controller outputs a second level. Under the control of the second level, the switch makes the input level of the upgrade activation pin a deactivation enable level, so that the embedded device exchanges data with the other device through the interface connector.

3. The embedded device interface control circuit according to claim 2, characterized in that, The switching transistor is an N-channel metal-oxide-semiconductor transistor. The output terminal of the interface controller is coupled to the gate of the N-channel metal-oxide-semiconductor transistor. The source of the N-channel metal-oxide-semiconductor transistor is grounded. The drain of the N-channel metal-oxide-semiconductor transistor is coupled to the upgrade activation pin. The upgrade activation pin is also coupled to the first power supply through a first pull-up resistor. Wherein, the first level is a high level, which turns on the N-channel metal-oxide-semiconductor transistor, and the activation enable level becomes a low level, enabling the host to upgrade the embedded device; the second level is a low level, which turns off the N-channel metal-oxide-semiconductor transistor, and the activation enable level becomes a high level under the action of the first power supply and the first pull-up resistor, enabling the host not to upgrade the embedded device.

4. The embedded device interface control circuit according to claim 2, characterized in that, Also includes: A power load switch is used to control the supply of operating power to the other devices. Specifically, when the second level is input to the enable terminal of the power load switch, the output terminal of the power load switch outputs the operating power of the other devices; when the first level is input to the enable terminal of the power load switch, the output terminal of the power load switch does not output the operating power of the other devices.

5. The embedded device interface control circuit according to claim 1, characterized in that, It also includes a first mode resistor and a second mode resistor. The first mode resistor is coupled between the second power supply and the first mode pin of the interface controller. The second mode resistor is coupled between the second power supply and the second mode pin of the interface controller. The first mode output pin of the interface controller is coupled to the first mode input pin of the interface connector. The second mode output pin of the interface connector is coupled to the second mode input pin of the external device.

6. The embedded device interface control circuit according to claim 5, characterized in that, When the interface controller needs to operate in master mode, the first mode pin is coupled to the first mode output pin, so that the first mode output pin outputs a first mode current. The first mode current flows sequentially through the first mode input pin and the second mode output pin into the second mode input pin, which is used to notify the external device that it is in slave mode. When the interface controller needs to operate in slave mode, the second mode pin is coupled to the first mode output pin, so that the first mode output pin outputs a second mode current. The second mode current flows sequentially through the first mode input pin and the second mode output pin into the second mode input pin, which is used to notify the external device that it is in master mode.

7. The embedded device interface control circuit according to claim 5, characterized in that, There are multiple second-mode resistors, each with a different resistance value and corresponding to a different host type. The multiple second-mode resistors are respectively coupled between the second power supply and multiple second-mode pins. When the interface controller needs to operate in slave mode, the second mode pin corresponding to the host type is coupled to the first mode output pin, so that the first mode output pin outputs the second mode current corresponding to the host type. The second mode current flows sequentially through the first mode input pin and the second mode output pin into the second mode input pin, which is used to notify the host of the host type that it is in master mode.

8. An embedded device, characterized in that, It includes an embedded device interface control circuit as described in any one of claims 1 to 7.

9. An embedded device interface control method, characterized in that, include: Identify external devices coupled to the interface connector of the embedded device; If the external device is identified as the host, a first level is output; By controlling the switch transistor at the first level, the input level of the upgrade activation pin of the host is set to the activation enable level, thereby enabling the host to upgrade the embedded device through the interface connector; If the external device is identified as a non-host device, a second level is output; By controlling the switch transistor at the second level, the input level of the upgrade activation pin of the host is set to an inactive enable level, so that the host does not upgrade the embedded device.

10. The embedded device interface control method according to claim 9, characterized in that, The embedded device interface control method is executed by the embedded device interface control circuit. Before identifying external devices coupled to the interface connector of the embedded device, the embedded device interface control method further includes: In the event that the embedded device needs to be upgraded, the external device is coupled to the interface connector, and then the interface control circuit of the embedded device is powered on. Without needing to upgrade the embedded device, power on the embedded device interface control circuit and then couple the external device to the interface connector.

Images