PCIe-cip interconnect chiplet conversion interface circuit supporting redundant transmission

Abstract

The application discloses a PCIe-CIP interconnection core particle conversion interface circuit supporting redundant transmission, and realizes conversion of PCIe and CIP protocols through cooperative work of a data transmission control module, a configuration transmission control module and a reset control module, and solves the transmission congestion problem caused by single link failure. The data transmission module supports unified redundant transmission of data / register read / write events, each transmission event contains three-mode redundant check and virtual channel retransmission after transmission exception; the configuration module realizes configuration and monitoring of PCIe controllers, PHYs and internal registers of the conversion interface by address gating logic and cross-clock domain mechanism; the reset control module supports reset initiated by multiple master devices such as PCIe Master, in-chip micro control unit, core particle CIP inter-chip transmission master device and in-chip opposite end master device, and is synchronously released to each clock domain. The application significantly improves the reliability and flexibility of core particle interconnection, and is suitable for multi-core particle heterogeneous integration scenes.

Description

Technical Field

[0001] This invention relates to the field of high-speed interconnect technology, and in particular to a PCIe-CIP interconnect chip-to-chip conversion interface circuit that supports redundant transmission. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express), as the most widely used high-speed peripheral interconnect protocol, has become the core interface for communication between chiplet systems and external devices, as well as for cross-protocol interconnection between chiplets, thanks to its core advantages of high bandwidth, low latency, and high reliability. It plays an indispensable role in multi-chiplet heterogeneous integration scenarios such as data centers, high-performance computing, and industrial control. CIP (Chiplet Interconnect Protocol) is the core interconnect protocol in chiplet heterogeneous integration systems. It clarifies the data interaction specifications and communication processes at the transaction layer, possesses strong multi-protocol compatibility, and supports multi-chiplet system interconnection and integration encapsulation with mainstream interfaces and protocols such as PCIe, SRIO, DDR, and AXI. Furthermore, it can flexibly expand the interconnection topology through inter-chip CIP interfaces, providing a high-speed, unified communication foundation for collaborative work between multiple chiplets.

[0003] However, existing PCIe-CIP conversion interfaces rely on a single channel for data transmission. When faced with packet loss or verification failures due to link interference or signal attenuation, they cannot guarantee transmission continuity through backup paths, resulting in insufficient transmission robustness and difficulty in meeting the high reliability requirements of complex interconnection scenarios. In terms of configuration, they only support unified configuration of all interfaces on the chip by the on-chip microcontroller unit. Other master interfaces in the on-chip network cannot achieve cross-device or cross-chip configuration, resulting in insufficient system configuration flexibility and difficulty in meeting the application requirements of multi-master device collaborative management. In addition, the conversion interface lacks link observation and recovery mechanisms, making it difficult to locate problems such as transmission packet loss, congestion, and PCIe link mapping errors. When anomalies such as interface freezing occur, the system's fault recovery capability is insufficient.

[0004] These issues collectively make it difficult for existing PCIe-CIP conversion interfaces to meet the core requirements of multi-core systems for redundant transmission, flexible configuration, fault observation, and rapid recovery. This restricts the overall reliability, flexibility, and maintainability of multi-core systems. Therefore, there is an urgent need for a PCIe-CIP interconnect core conversion interface circuit that features redundant transmission paths, supports mutual configuration of multiple master devices, and integrates link observation and flexible reset functions. Summary of the Invention

[0005] The purpose of this invention is to provide a PCIe-CIP interconnect chip conversion interface circuit that supports redundant transmission, so as to realize unified redundant transmission of data reading and writing and register reading and writing in multi-chip heterogeneous integrated systems, as well as configuration management and fault recovery of multi-master devices.

[0006] To address the aforementioned technical problems, this invention provides a PCIe-CIP interconnect chip conversion interface circuit that supports redundant transmission, comprising: a data transmission control module, a configuration transmission control module, and a reset control module; The data transmission control module uses PCIe as the initiating master device to realize the data path conversion between PCIe and CIP protocols. It also supports data read / write events and register read / write events. The CIP data packets for both types of events integrate a triple-modulus redundancy check field and ensure transmission reliability through a dual network retransmission mechanism. The configuration transmission control module receives configuration requests from CIP inter-chip / intra-chip master devices, selects the AXI / APB path through the 33rd bit of the 64-bit CIP address, and distributes the requests to the corresponding registers after crossing the clock domain via an asynchronous bridge, supporting configuration and monitoring. The reset control module supports PCIe host computer, on-chip microcontroller unit, and CIP inter-chip / on-chip master device to initiate reset through different buses; The data transmission control module and the configuration transmission control module are connected to the on-chip CIP network through a two-to-one multiplexer. The interface dynamically selects the path according to the type of transmission event: register read / write events select the configuration transmission path, and other data read / write events select the data transmission path, so as to realize differentiated processing of different transactions.

[0007] In one embodiment, the data transmission control module includes an MSI control module, a data stream protocol conversion module, a network interface kernel, and an asynchronous FIFO. The data stream protocol conversion module parses requests initiated by the PCIe host into two types of transactions: those with data payload and those without, and encapsulates them into CIP protocol format data packets. The network interface kernel adds a triple modulo redundancy check field to the CIP data packets and caches them. The MSI control module sends an MSI interrupt to the PCIe host after the transmission transaction is completed. The asynchronous FIFO enables cross-domain data transmission between the PCIe and CIP clock domains.

[0008] In one implementation, the retransmission process for write requests / register write requests in the data transmission control module is as follows: After the network interface kernel sends a request, it enters a blocked state. If a response packet is received from the peer, an interrupt is triggered through the MSI control module. If no response packet is received within a timeout period or the response information fails the triple redundancy check, a virtual channel is switched for retransmission. If no response packet is received after retransmission, a NACK notification is generated and an interrupt is sent to the PCIe host through the MSI control module.

[0009] In one implementation, the retransmission process for read requests / register read requests in the data transmission control module is as follows: After the network interface kernel sends a request, it enters a blocked state. If a response packet is received from the peer, an interrupt is triggered through the MSI control module. If no response packet is received within a timeout period, the response information fails the three-mode redundancy check, or the read data verification fails, a virtual channel is switched for retransmission. If no response packet is received after retransmission, a NACK notification is generated and an interrupt is sent to the PCIe host. If the read data verification still fails after retransmission, a CHECK_ERR notification is generated and an interrupt is sent to the PCIe host.

[0010] In one implementation, the configuration transmission control module includes an AXI configuration interface, an APB configuration interface, a cfg_from_external module, and an asynchronous FIFO. The cfg_from_external module receives register read / write request packets sent by the CIP network peer master device, first performs parity checking, and if the check passes, extracts the 64-bit address and data and proceeds to the subsequent parsing process; if the check fails, the request is discarded, no response is returned, and no configuration register group is written. The `cfg_from_external` module parses the 64-bit CIP address, following a unified gating rule: the lower 32 bits are the valid register address, written to the corresponding configuration register group; the 33rd bit is the path selection bit: 1'b1 selects the AXI path to access the PCIe controller registers; 1'b0 selects the APB path to access the PCIe PHY and the interface's own registers. After cross-domain synchronization from the CIP clock domain to the AXI / APB clock domain is completed via an asynchronous bridge, the request is distributed to the corresponding bus interface for execution. After the register operations are completed, the `cfg_from_external` module packages the write response or read data into a CIP register read / write response packet and returns it to the CIP peer master device that initiated the request.

[0011] In one implementation, the registers supported by the APB path include: PCIe controller / PHY register: Address offset 32'h0, supports read and write; Custom reset register: address offset 32'h100, write-enabled; Transmission monitoring register set: address offset 32'h200, read supported; Address configuration register group: address offset 32'h800, supports read and write; where... The transmission monitoring register group performs real-time monitoring of the link status of the conversion interface. The transmission monitoring register group includes read / write address, length, data, and whether the handshake was successful. The address configuration register group configures the read and write addresses of the conversion interface, and the addresses include request address, interrupt address, cache address, and reset address.

[0012] In one implementation, the 64-bit CIP address rule of the configuration transmission control module is as follows: the lower 32 bits are the effective address, the 33rd bit is the path selection bit, 1'b1 selects the AXI bus, and 1'b0 selects the APB bus.

[0013] In one implementation, the reset control module receives configuration signals from the PCIe host, the on-chip microcontroller unit, and the configuration transmission control module, sets the reset register low, and then releases it synchronously to all clock domains through an asynchronous bridge to achieve a global reset triggered by multiple master devices. The base address of the reset register is 32'h100. The reset signal is active low. The PCIe host writes wdata[0] = 1'b0 to 32'h100 via the AXI bus, and the write length awlen = 0, triggering the reset. The on-chip microcontroller or the CIP peer master device writes pwdata[0] = 1'b0 to the offset address 32'h20100 via the APB bus, triggering the reset. After receiving a valid reset command, the reset control module sets its internal reset register low and synchronizes it to all clock domains via the asynchronous bridge to achieve a global reset of the conversion interface. After the reset, the interface returns to its initial IDLE state.

[0014] The present invention provides a PCIe-CIP interconnect chip conversion interface circuit that supports redundant transmission, which has the following beneficial effects: (1) The system configuration flexibility and robustness are greatly improved: The new CIP register read and write event configuration path breaks the original limitation of only supporting the unified configuration of the on-chip microcontroller unit, and realizes the mutual configuration of all master devices between / on-chip CIP chips; at the same time, the transmission monitoring and address configuration register group are integrated, which can observe the link status in real time, dynamically adjust the configuration, accurately locate faults and adapt to the scenario, significantly improving the system maintainability and fault recovery capability; (3) Significantly enhanced data transmission reliability: The introduction of a dual-network retransmission mechanism based on virtual channel management, combined with three-mode redundancy check, effectively addresses anomalies such as link interference and check failure, ensures transmission continuity through backup paths, solves congestion problems caused by single data link failure, and adapts to the high reliability requirements of multi-core heterogeneous integration. (3) Improved fault recovery mechanism: Supports global reset triggered by multiple master devices, clarifies reset parameters and cross-clock domain synchronization logic, realizes rapid recovery after interface abnormality, and ensures stable system operation. Attached Figure Description

[0015] Figure 1This is a block diagram of the overall architecture of the PCIe-CIP interconnect chip conversion interface circuit of the present invention; Figure 2 This is a block diagram of the internal circuit architecture of the configuration transmission control module of the present invention; Figure 3 This is a schematic diagram illustrating the transmission monitoring register group information of the present invention; Figure 4 This is a schematic diagram illustrating the address configuration register group information of the present invention; Figure 5 This is a block diagram of the reset control module circuit architecture of the present invention; Figure 6 This is a flowchart illustrating the process of a PCIe host initiating a request; Figure 7 This is a schematic diagram of the data transmission control module's transmission process; Figure 8 This is a schematic diagram of the write request transmission process for the configuration transmission control module register; Figure 9 This is a schematic diagram of the register read request transmission process of the configuration transmission control module. Detailed Implementation

[0016] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a PCIe-CIP interconnect chip conversion interface circuit supporting redundant transmission proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0017] This invention provides a PCIe-CIP interconnect chip-to-chip interface circuit that supports redundant transmission. By constructing a data transmission path, configuring the transmission path, and establishing a link recovery mechanism, it solves the transmission congestion problem caused by the failure of a single data link or the configuration link, and significantly improves the reliability, flexibility, and maintainability of chip-to-chip interconnect.

[0018] like Figure 1As shown, the conversion interface circuit of this invention consists of a data transmission control module, a configuration transmission control module, and a reset control module. These modules work together to complete the conversion between PCIe and CIP protocols, redundant transmission, and fault recovery. The data transmission control module initiates the request as a master device using PCIe, responsible for protocol conversion, redundancy verification, and retransmission of data / register read / write operations. The configuration transmission control module acts as a CIP network slave device, receiving register read / write requests from on-chip network peer master devices (including inter-chip CIP transmission master devices and intra-chip peer master devices), enabling multi-master device configuration and link debugging. The reset control module supports multi-master device-triggered global reset, ensuring rapid recovery in abnormal interface scenarios. The data transmission control module and the configuration transmission control module are connected to the on-chip CIP network via a 2-to-1 multiplexer. The interface dynamically selects the path based on the transmission event type: register read / write events (register read / register write requests) select the configuration transmission path, while other data read / write events select the data transmission path, achieving differentiated processing for different transactions.

[0019] The data transmission control module includes an MSI control module, a data stream protocol conversion module, a kernel module, and an asynchronous FIFO. Its core functions are as follows: The data stream protocol conversion module is responsible for protocol conversion and transaction classification. It parses requests initiated by PCIe hosts into two types of transactions: requests with data payload (such as write requests and register write requests) and requests without data payload (such as read requests and register read requests). The parsing results are then encapsulated into data packets in the format specified by the CIP protocol.

[0020] The kernel module includes redundancy check, caching, and virtual channel retransmission mechanisms. It adds a triple modulo redundancy check field to all chips (header chip, body chip, and tail chip) sent to the CIP network, and caches the complete data packet in the retransmission buffer to provide data support for retransmission recovery. It also listens for response packets returned by the CIP network. If the response packet passes the triple modulo redundancy check and parity check, the retransmission buffer is released and the response information is synchronized to the PCIe clock domain. If the response packet fails to verify or times out without response, retransmission is triggered: the virtual channel 0 / 1 control logic switches to the backup Layer 2 network, reads the original request data from the retransmission buffer, and retransmits it. If the verification still fails or there is no response after retransmission, the exception information (such as NACK, CHECK_ERR) is synchronized to the PCIe clock domain.

[0021] The MSI control module is responsible for interrupt feedback. After a transaction is completed (including normal completion and abnormal termination), the MSI control module sends an MSI interrupt to the PCIe host. The PCIe host reads back the response status and data through the interrupt register or data buffer.

[0022] like Figure 2As shown, the configuration transmission control module includes an AXI configuration interface, an APB configuration interface, a cfg_from_external (on-chip network configuration interface) module, and an asynchronous FIFO. The cfg_from_external module receives register read / write request packets sent by the CIP network peer master device. It first performs parity checking. If the check passes, it extracts the 64-bit address and data (for register read requests, only the address is extracted) and proceeds to the subsequent parsing process. If the check fails, the request is discarded, no response is returned, and no configuration register is written.

[0023] The `cfg_from_external` module parses the 64-bit CIP address, following a unified gating rule: the lower 32 bits are the valid register address, written to the corresponding configuration register group; the 33rd bit is the path selection bit: 1'b1 selects the AXI path to access the PCIe controller registers; 1'b0 selects the APB path to access the PCIe PHY and the interface's own registers. After cross-domain synchronization from the CIP clock domain to the AXI / APB clock domain is completed via an asynchronous bridge, the request is distributed to the corresponding bus interface for execution. After the register operations are completed, the `cfg_from_external` module packages the write response or read data into a CIP register read / write response packet and returns it to the CIP peer master device that initiated the request.

[0024] The APB configuration interface supports two links: the on-chip microcontroller APB interface and the CIP2APB interface. The CIP2APB interface access address requires an offset of 32'h20000. The accessible registers are categorized as follows: PCIe EP register: Address offset 32'h0, supports reading and writing, used to configure PCIe EP device parameters; Custom reset register: address offset 32'h100, write-only, used to receive reset trigger commands; Transmission monitoring register set: Address offset 32'h2xx, read-only, contains register set information such as Figure 3 As shown, it can monitor the read / write address of a successful handshake, the read / write address received this time, the length, data, etc., and can locate problems such as packet loss, congestion, and PCIe link mapping errors. Address configuration register group: Address offset 32'h8xx, supports read and write, contains register group information such as Figure 4 As shown, the soft reset address, test register address, transmission information address, and various interrupt / data addresses can be dynamically configured to adapt to different transmission scenarios.

[0025] like Figure 5As shown, the reset control module receives configuration signals from the host, microcontroller, and configuration transmission control module, sets the reset register low, and then releases it synchronously to all clock domains through the asynchronous bridge to achieve a global reset triggered by multiple master devices. The base address of the reset register is 32'h100. The reset signal is active low. The PCIe host writes wdata[0] = 1'b0 to 32'h100 through the AXI bus, and the write length awlen = 0, triggering the reset. The on-chip microcontroller or the peer master device of CIP writes pwdata[0] = 1'b0 to the offset address 32'h20100 (base address + 32'h20000) through the APB bus to trigger the reset. After receiving a valid reset instruction, the reset control module sets the internal reset register low and synchronizes it to all clock domains (CIP, AXI, APB, etc.) through the asynchronous bridge to achieve a global reset of the conversion interface. After the reset, the interface is restored to the initial IDLE state.

[0026] like Figure 6 As shown, the PCIe host, acting as the request initiator, follows this process in its transport state: IDLE: The PCIe host is in an initial idle state, waiting for new transmission commands to be issued by upper-layer applications or drivers; Transmission Information: The PCIe host sends a transmission information packet containing fields such as transmission event type, transaction ID, routing node, data length, and destination address. Upon receiving this packet, the data flow protocol conversion module of the data transmission control module determines whether the transmission carries a data payload based on the event type: if it is a payload-type transmission such as a write request, register write request, or shared write request, it enters the data state; if it is a payload-free transmission such as a read request, register read request, or DMA read request, it directly enters the Busy state. Data: For payload event types such as write requests, register write requests, and shared write requests, the PCIe host continues to send data payloads of the corresponding length. The data stream protocol conversion module counts the data based on the length field in the transmission information, and automatically jumps to the Busy state after receiving the specified length of data. Busy: The data transmission control module encapsulates the received transmission information and data payload into a data packet in the format specified by the CIP protocol, completes cross-clock domain synchronization through an asynchronous FIFO, and sends it to the CIP on-chip network. The data transmission control module enters a blocking state, waiting for all responses (including normal and abnormal responses) from the CIP on-chip network. After the current transmission transaction is completely completed, the MSI interrupt control module sends an interrupt signal to the PCIe host. MSI Interrupt: After an MSI interrupt is triggered, the PCIe host reads the transfer response status and data payload from the cache to confirm the transfer result (including success / failure / error). After reading is complete, the state machine returns to IDLE, and the next transfer transaction can be initiated.

[0027] CIP request sending and redundant retransmission control flow are as follows: Figure 7 As shown, after the data transmission control module completes the protocol conversion, the process of sending the micro-scale data packet request to the CIP on-chip network is as follows: Header chip: Add three-mode redundancy check to the chip header information, add parity check bits to the control data such as transmission events and routing nodes in the asynchronous FIFO and send it to the CIP on-chip network. At the same time, cache the chip information in the retransmission buffer for subsequent retransmission recovery. Microchip: Add triple redundancy check to the microchip information, add parity check bits to fields such as data length and target address in asynchronous FIFO before sending to CIP on-chip network, and synchronously buffer to retransmission buffer; Data volume micro-chip: In the transmission transaction carrying data payload, triple modulo redundancy check is added to the data volume micro-chip information, parity check bit is added to the data payload in the asynchronous FIFO and then sent to the CIP on-chip network, while being buffered in the retransmission buffer; Tail microchip: After adding three-modulus redundancy check to the tail information of the microchip, it is sent to the CIP on-chip network to mark the completion of the current request packet transmission; Wait: After all microchips have been sent, the data transmission control module enters a waiting state, receives the response packet returned by the CIP on-chip network, and performs triple modulo redundancy check and parity check on the response data. If the check passes, the response information is synchronized to the buffer in the PCIe clock domain via an asynchronous FIFO, and the retransmission buffer resources are released, waiting for the next transaction. If the check fails or there is no response after a timeout, the original request data is read from the retransmission buffer, and the virtual channel 0 / 1 control logic switches to the backup Layer 2 network for retransmission. If the check passes after retransmission, the response information is synchronized to the PCIe clock domain and the retransmission resources are released. If the check still fails or there is no response after a timeout after retransmission, the exception information (such as NACK, CHECK_ERR) is synchronized to the PCIe clock domain, triggering an exception interrupt to notify the host.

[0028] like Figure 8 As shown, the process for configuring the transmission control module as a CIP on-chip network slave device and handling CIP register write requests is as follows: Wait: Module initial state, waiting for register read / write requests to be initiated by the CIP inter-chip / inter-chip master device; Receive register write request: The config_from_external module receives CIP register write requests sent by the peer master device; Parity check: Perform parity check on the data slice of the register write request. If the check fails, discard the request and return to the Wait state; if the check passes, enter the parsing request state. Parsing Request: Parse the 64-bit address field, where the lower 32 bits are the valid address and the 33rd bit is the AXI / APB path strobe bit (1'b1 strobes AXI, 1'b0 strobes APB). Based on the strobe bits and address offset, determine the path to which the target register belongs; Send register write response: After the request packet is fully received, the configuration module packages the write response information into a CIP register write response packet and sends it back to the CIP peer master device. Then it returns to the Wait state and waits for the next request. Request dispatch and execution: After cross-domain synchronization from the CIP clock domain to the AXI / APB clock domain is completed via the asynchronous bridge, the write request is dispatched to the corresponding bus interface to execute the register write operation.

[0029] like Figure 9 As shown, the process for the transmission control module to handle CIP register read requests is as follows: Wait: Module initial state, waiting for register read / write requests to be initiated by the CIP inter-chip / inter-chip master device; Receive register read request: The config_from_external module receives CIP register read requests sent by the peer master device; Parity check: Perform parity check on the register read request packet. If the check fails, discard the request and return to the Wait state; if the check passes, enter the parsing request state. Parse request: Parse the 64-bit address field, and determine the target register and corresponding AXI / APB path based on the 33rd bit strobe and the address offset; Request distribution and reading: After synchronization across clock domains via the asynchronous bridge, the read request is distributed to the corresponding bus interface to read the target register value (such as the transmission monitoring register, address configuration register, etc.). Packed response transmission: Pack the read register values ​​into a CIP register read response packet and send it back to the CIP peer master device, then return to the Wait state.

[0030] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A PCIe-CIP interconnect chip conversion interface circuit supporting redundant transmission, characterized in that, include: Data transmission control module, configuration transmission control module, and reset control module; The data transmission control module uses PCIe as the initiating master device to realize the data path conversion between PCIe and CIP protocols. It also supports data read / write events and register read / write events. The CIP data packets for both types of events integrate a triple-modulus redundancy check field and ensure transmission reliability through a dual network retransmission mechanism. The configuration transmission control module receives configuration requests from CIP inter-chip / intra-chip master devices, selects the AXI / APB path through the 33rd bit of the 64-bit CIP address, and distributes the requests to the corresponding registers after crossing the clock domain via an asynchronous bridge, supporting configuration and monitoring. The reset control module supports PCIe host computer, on-chip microcontroller unit, and CIP inter-chip / on-chip master device to initiate reset through different buses; The data transmission control module and the configuration transmission control module are connected to the on-chip CIP network through a two-to-one multiplexer. The interface dynamically selects the path according to the type of transmission event: register read / write events select the configuration transmission path, and other data read / write events select the data transmission path, so as to realize differentiated processing of different transactions.

2. The PCIe-CIP interconnect chip conversion interface circuit supporting redundant transmission as described in claim 1, characterized in that, The data transmission control module includes an MSI control module, a data stream protocol conversion module, a network interface kernel, and an asynchronous FIFO. The data stream protocol conversion module parses the requests initiated by the PCIe host into two types of transactions: those with data payload and those without data payload, and encapsulates them into CIP protocol format data packets. The network interface kernel adds a triple modulo redundancy check field to the CIP data packets and caches them. The MSI control module sends an MSI interrupt to the PCIe host after the transaction is completed. The asynchronous FIFO enables cross-domain data transmission between the PCIe and CIP clock domains.

3. The PCIe-CIP interconnect chip conversion interface circuit supporting redundant transmission as described in claim 2, characterized in that, The retransmission process for write requests / register write requests in the data transmission control module is as follows: After the network interface kernel sends a request, it enters a blocking state. If a response packet is received from the other end, an interrupt is triggered through the MSI control module. If no response packet is received within a timeout or the response information fails the three-mode redundancy check, the virtual channel is switched for retransmission. If no response packet is received after retransmission, a NACK notification is generated and an interrupt is sent to the PCIe host through the MSI control module.

4. The PCIe-CIP interconnect chip conversion interface circuit supporting redundant transmission as described in claim 2, characterized in that, The retransmission process for read requests / register read requests in the data transmission control module is as follows: After the network interface kernel sends a request, it enters a blocking state. If a response packet is received from the other end, an interrupt is triggered through the MSI control module. If no response packet is received within a timeout period, the response information fails the three-mode redundancy check, or the read data check fails, the virtual channel is switched for retransmission. If no response packet is received after retransmission, a NACK notification is generated and an interrupt is sent to the PCIe host; if the data read still fails to be verified after retransmission, a CHECK_ERR notification is generated and an interrupt is sent to the PCIe host.

5. The PCIe-CIP interconnect chip conversion interface circuit supporting redundant transmission as described in claim 1, characterized in that, The configuration transmission control module includes an AXI configuration interface, an APB configuration interface, a cfg_from_external module, and an asynchronous FIFO. The cfg_from_external module receives register read / write request packets sent by the CIP network peer master device. It first performs parity checking. If the check passes, it extracts the 64-bit address and data and proceeds to the subsequent parsing process. If the check fails, it discards the request, does not return a response, and does not write to the configuration register group. The `cfg_from_external` module parses the 64-bit CIP address, following a unified gating rule: the lower 32 bits are the valid register address, written to the corresponding configuration register group; the 33rd bit is the path selection bit: 1'b1 selects the AXI path to access the PCIe controller registers; 1'b0 selects the APB path to access the PCIe PHY and the interface's own registers. After cross-domain synchronization from the CIP clock domain to the AXI / APB clock domain is completed via an asynchronous bridge, the request is distributed to the corresponding bus interface for execution. After the register operations are completed, the `cfg_from_external` module packages the write response or read data into a CIP register read / write response packet and returns it to the CIP peer master device that initiated the request.

6. The PCIe-CIP interconnect chip conversion interface circuit supporting redundant transmission as described in claim 5, characterized in that, The registers supported by the APB path include: PCIe controller / PHY register: Address offset 32'h0, supports read and write; Custom reset register: address offset 32'h100, write-enabled; Transmission monitoring register set: address offset 32'h200, read supported; Address configuration register group: address offset 32'h800, supports read and write; where... The transmission monitoring register group performs real-time monitoring of the link status of the conversion interface. The transmission monitoring register group includes read / write address, length, data, and whether the handshake was successful. The address configuration register group configures the read and write addresses of the conversion interface, and the addresses include request address, interrupt address, cache address, and reset address.

7. The PCIe-CIP interconnect chip conversion interface circuit supporting redundant transmission as described in claim 5, characterized in that, The 64-bit CIP address rule for the configuration transmission control module is as follows: the lower 32 bits are the effective address, the 33rd bit is the path selection bit, 1'b1 selects the AXI bus, and 1'b0 selects the APB bus.

8. The PCIe-CIP interconnect chip conversion interface circuit supporting redundant transmission as described in claim 1, characterized in that, The reset control module receives configuration signals from the PCIe host, the on-chip microcontroller unit, and the configuration transmission control module, sets the reset register low, and then releases it synchronously to all clock domains through the asynchronous bridge to achieve a global reset triggered by multiple master devices. The base address of the reset register is 32'h100. The reset signal is active low. The PCIe host writes wdata[0] = 1'b0 to 32'h100 via the AXI bus, and the write length awlen = 0, triggering the reset. The on-chip microcontroller or the CIP peer master device writes pwdata[0] = 1'b0 to the offset address 32'h20100 via the APB bus, triggering the reset. After receiving a valid reset command, the reset control module sets its internal reset register low and synchronizes it to all clock domains via the asynchronous bridge to achieve a global reset of the conversion interface. After the reset, the interface returns to its initial IDLE state.

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