FPGA and RK3588 platform-based pcie communication integration design system and method

By integrating the FPGA with the RK3588 platform for PCIE communication, the efficiency problem of multi-data type communication in heterogeneous systems was solved, achieving efficient resource utilization and improved system stability, thus meeting the diverse needs of airborne display products.

CN122432093APending Publication Date: 2026-07-21SUZHOU CHANGFENG AVIATION ELECTRONICS
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SUZHOU CHANGFENG AVIATION ELECTRONICS
Filing Date
2026-03-26
Publication Date
2026-07-21

AI Technical Summary

Technical Problem

Traditional PCIe IP core designs cannot efficiently handle the communication needs of diverse data types in heterogeneous FPGA and RK3588 systems, resulting in low resource utilization and low development efficiency.

Method used

An integrated PCIe communication design system based on FPGA and RK3588 platform is adopted, including a transceiver data interface bus control module, an address dynamic mapping control module, a cache control module, a DMA read/write channel controller, and a PCIe hard core module. Through data classification, address dynamic mapping, and cache management, resource utilization is optimized.

Benefits of technology

Significantly reduce R&D costs, improve development efficiency, optimize FPGA resource utilization, enhance system stability, and reduce power consumption, adapting to the differentiated needs of various airborne display products.

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Abstract

The application discloses a PCIE communication integration design system and method based on an FPGA and an RK3588 platform, and belongs to the technical field of airborne display. The system comprises a transceiving data interface bus control module, an address dynamic mapping control module, a cache control module and a DMA read-write channel controller. The transceiving data interface bus control module is used for classifying transmission data, distributing fixed address space and register definition, and generating enabling configuration information. The address dynamic mapping control module receives the enabling configuration information, rearranges and continuously maps effective register addresses. The cache control module allocates BRAM resources according to the mapped addresses. The DMA read-write channel controller controls the DMA read-write between the cache and a PCIE hard core. The PCIE hard core module realizes the underlying data transmission with the RK3588. Through data classification and dynamic address mapping, the BRAM resources are allocated on demand, the resource occupation is greatly reduced, and the system stability and development efficiency are improved.
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