Parallel spi controller, control system and communication method

Abstract

The application discloses a parallel SPI controller, a control system and a communication method, and belongs to the technical field of SPI communication. The parallel SPI controller comprises a frame generation module, which is used for acquiring a control frame and a to-be-sent data frame in a corresponding register group to generate an instruction frame after receiving an enabling signal; a frame cache module, which is connected with the frame generation module and is used for storing at least one instruction frame; and a timing generation module, which is connected with the frame cache module and is used for sequentially reading one instruction frame when the frame cache module is not empty and automatically generating a corresponding group of SPI communication timing. Thus, the application realizes the decoupling of the time of the host instruction issuing and the SPI timing execution, eliminates the performance bottleneck caused by the serial polling, and significantly improves the system throughput and communication efficiency in the multi-peripheral communication scene.

Description

Technical Field

[0001] This application relates to the field of Serial Peripheral Interface (SPI) communication technology, specifically to a parallel SPI controller, control system, and communication method. Background Technology

[0002] In multi-peripheral systems based on microcontroller units (MCUs) or system-on-chips (SoCs), the host needs to communicate with multiple slave devices and external peripherals via the SPI bus. As the number of external SPI devices increases, the control complexity increases, requiring the expansion of more SPI bus interfaces and improvement of communication efficiency.

[0003] To address the aforementioned need for multi-slave / peripheral SPI communication, a common solution is to expand the number of SPI channels. However, the number of channels in the SPI controller built into the MCU or SoC is fixed in the chip hardware, resulting in extremely poor scalability. There are two main expansion solutions commonly used in the industry: one is to connect a dedicated SPI bus expansion chip to the host's native SPI interface to expand the number of SPI channels; the other is to utilize the logic resources of a Field Programmable Gate Array (FPGA) to instantiate multiple SPI controller soft cores, thereby expanding the number of SPI interfaces.

[0004] However, implementations based on dedicated SPI expansion chips significantly increase system hardware costs and design complexity. Furthermore, communication across all expansion channels still requires serial forwarding via the host's native SPI interface, making parallel independent communication among multiple slave devices impossible. FPGA-based SPI expansion schemes, still employing a serial polling mode, require the host to sequentially send communication commands and data even with multiple independent SPI controllers instantiated. The host must wait for the previous SPI communication to complete before initiating the next, again failing to achieve true parallel independent communication among multiple slave devices. Moreover, in multi-slave scenarios, the total communication time increases linearly with the number of slave devices. Additionally, in both of these schemes, the host needs to query the SPI controller's status in real-time for each SPI communication, resulting in a high proportion of idle waiting time per communication. Consequently, both schemes suffer from high host-side communication control overhead and low overall system communication efficiency. Summary of the Invention

[0005] This application provides a parallel SPI controller, a control system, and a communication method to solve the problem that existing SPI expansion schemes cannot achieve parallel independent communication among multiple slave devices.

[0006] According to a first aspect, one embodiment provides a parallel SPI controller, comprising:

[0007] The frame generation module is used to obtain the control frame and the data frame to be sent from the corresponding register group after receiving the enable signal to generate an instruction frame; wherein, the instruction frame is configured to include the timing configuration parameters and the data to be sent required to execute a complete SPI communication transaction;

[0008] A frame buffer module, connected to the frame generation module, is used to store at least one of the instruction frames;

[0009] The timing generation module is connected to the frame buffer module and is used to sequentially read one instruction frame from the frame buffer module when the frame buffer module is not empty, and automatically generate and output a set of SPI communication timing corresponding to the read instruction frame.

[0010] In one embodiment, the SPI communication timing includes at least: an SPI clock signal, a chip select signal, and an SPI write data signal;

[0011] The timing generation module includes:

[0012] A state machine is used to generate at least one state to control the generation process of the SPI communication timing.

[0013] A control configuration latch module, connected to the state machine, is used to parse and latch timing configuration parameters in the instruction frame read from the frame buffer module under the control of the state machine. The timing configuration parameters include at least: chip select control, front delay, back delay, and clock division number.

[0014] The chip select signal generation module is connected to the state machine and the control configuration latch module respectively, and is used to generate the chip select signal by adjusting the level state of the chip select pin according to the chip select control, the pre-delay, and the post-delay under the control of the state machine.

[0015] A clock divider is connected to the state machine and the control configuration latch module respectively, and is used to divide the system working clock according to the clock division number under the control of the state machine to generate the SPI clock signal.

[0016] A data latch module, connected to the state machine, is used to parse and latch the data frame to be sent from the instruction frame read from the frame buffer module under the control of the state machine.

[0017] The data transmission module is connected to the state machine and the data latch module respectively, and is used to convert the data frame to be transmitted in the instruction frame from a parallel data stream to a serial data stream under the control of the state machine to obtain the SPI write data signal.

[0018] In one embodiment, the state machine is used to sequentially execute the following states: idle state, load state, pre-delay state, shift state, post-delay state, and end state, in order to control the generation process of the SPI communication timing.

[0019] In one embodiment, the timing configuration parameters further include: the number of transmission cycles;

[0020] The state machine is configured as follows:

[0021] In the idle state, it is detected whether the frame buffer module is not empty; if so, it enters the loading state.

[0022] In the loading state, the control configuration latch module is triggered to parse and latch the timing configuration parameters from the currently read instruction frame, and the data latch module is triggered to parse and latch the data frame to be sent. After completion, the state of pre-delay is entered.

[0023] In the pre-delay state, the chip select signal generation module is triggered to pull down the corresponding chip select pin according to the chip select control, and performs a first delay count according to the pre-delay. After the first delay count reaches the pre-delay, the shift state is entered.

[0024] In the shift state, the clock divider is triggered to generate the SPI clock signal according to the clock division number, and the data transmission module is triggered to convert the data frame to be transmitted into a serial data stream to output the SPI write data signal. The number of shifts is controlled according to the number of transmission cycles. After the number of shifts reaches the number of transmission cycles, the post-delay state is entered.

[0025] In the post-delay state, the chip select signal generation module is triggered to perform a second delay count according to the post-delay parameter. After the second delay count reaches the post-delay, the chip select pin is pulled high and the process enters the end state.

[0026] In the end state, the state machine is triggered to return to the idle state in preparation for processing the next instruction frame in the frame buffer module.

[0027] In one embodiment, the frame generation module generates a command frame by concatenating the control frame and the data frame to be sent.

[0028] In one embodiment, the frame buffer module is a FIFO queue used to store at least one instruction frame in a first-in-first-out manner.

[0029] In one embodiment, the control frame is used to carry timing configuration parameters, which include one or more of the following: SPI operating mode, transmission bit sequence mode, chip select control, front delay, back delay, number of transmission cycles, and number of clock divisions.

[0030] According to a second aspect, one embodiment provides a parallel SPI control system, comprising: a register module, an enable generation module, and one or more parallel SPI controllers as described in the first aspect of this application; wherein:

[0031] The register module includes at least one register group, each register group including at least a control register for storing control frames and a write data register for storing data frames to be sent; the register group is used to receive control frames and data frames to be sent in the configuration data stream;

[0032] The enable generation module is used to receive the SPI controller identifier in the configuration data stream and generate an enable signal for the parallel SPI controller corresponding to the SPI controller identifier.

[0033] Each of the parallel SPI controllers is connected to the enable generation module and the register module respectively. After receiving the enable signal from the enable generation module, the controller obtains the control frame and the data frame to be sent in the corresponding register group in the register module to generate an instruction frame and generates the corresponding SPI communication timing based on the instruction frame. Each of the parallel SPI controllers corresponds to a unique SPI controller identifier and a unique register group.

[0034] In one embodiment, parallel SPI controllers within the same system-defined channel are connected to the same register set to share the same register set.

[0035] In one embodiment, the system further includes:

[0036] The bus interface module is used to receive instruction data from the host via a high-speed bus.

[0037] The protocol parsing module, connected to the bus interface module, is used to parse the instruction data and generate the configuration data stream.

[0038] In one embodiment, the operation of the host sending instruction data through the bus interface module and the operation of the parallel SPI controller generating and outputting the SPI communication timing sequence are executed independently of each other.

[0039] In one embodiment, the high-speed bus is an AXI-Lite bus, and the bus interface module is an AXI-Lite bus interface.

[0040] In one embodiment, the system further includes:

[0041] A multiplexer includes a first input terminal and a second input terminal. The first input terminal is connected to the native SPI controller of the host, and the second input terminal is connected to the at least one parallel SPI controller. The output terminal of the multiplexer is connected to the SPI bus.

[0042] The multiplexer is used to select the receiving data source of the SPI bus to achieve dynamic switching of the SPI communication path.

[0043] According to a third aspect, one embodiment provides a parallel SPI communication method applied to a parallel SPI controller as described in any embodiment of the first aspect of this application, comprising:

[0044] Upon receiving the enable signal, the corresponding control frame and data frame to be sent are acquired to generate an instruction frame; wherein, the instruction frame is configured to include timing configuration parameters and data to be sent required to execute a complete SPI communication transaction;

[0045] Store at least one of the instruction frames to the frame buffer module;

[0046] When the frame buffer module is detected to be non-empty, one instruction frame is read from it sequentially, and a set of SPI communication timing corresponding to the read instruction frame is automatically generated and output.

[0047] Return to the instruction frame reading step until all instruction frames in the frame buffer module have been executed.

[0048] According to the parallel SPI controller, control system, and communication method described in the above embodiments, the frame generation module acquires a control frame and a data frame to be sent after receiving an enable signal to generate a complete instruction frame, which is then stored in the frame buffer module. Simultaneously, the timing generation module actively and sequentially reads the instruction frames and automatically generates the corresponding SPI communication timing when the frame buffer module is not empty. Because this architecture pre-encapsulates the timing configuration data and data to be sent from the external host into instruction frames and caches them, the instruction issuance from the external host and the instruction execution from the SPI controller are completely decoupled in time. The external host does not need to wait for the current SPI transaction to complete before continuously writing subsequent instructions, nor does it need to query the SPI controller's status in real time, thus eliminating the serial polling and... The performance bottleneck caused by idle waiting significantly reduces the control overhead on the host side, realizes batch pre-storage of instructions and pipelined automatic execution, and greatly improves the system throughput and overall communication efficiency in multi-slave / peripheral communication scenarios. In addition, the above-mentioned parallel SPI controller solution creates the conditions for realizing true parallel independent communication of multiple slaves / peripherals. That is, when multiple parallel SPI controllers as described in the above embodiments are instantiated in the system, since each parallel SPI controller has its own independent frame generation module, frame buffer module and timing generation module, it can execute its own instruction queue independently. Therefore, they can work simultaneously without interfering with each other, thus truly realizing parallel independent communication of multiple slaves / peripherals, rather than traditional serial polling time-sharing communication. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of a communication connection for a multi-slave, multi-peripheral system according to one embodiment;

[0050] Figure 2 This is a schematic diagram of the structure of a parallel SPI controller according to one embodiment;

[0051] Figure 3 This is a schematic diagram of a register group structure according to one embodiment;

[0052] Figure 4 This is a schematic diagram of a control frame format according to one embodiment;

[0053] Figure 5 An example of chip select signal control in one embodiment;

[0054] Figure 6 Another example of chip select signal control in one embodiment;

[0055] Figure 7 This is a schematic diagram of an SPI communication timing according to one embodiment;

[0056] Figure 8 This is a schematic diagram of the structure of a timing generation module according to one embodiment;

[0057] Figure 9 This is a structural example diagram of a parallel SPI controller according to one embodiment;

[0058] Figure 10 This is a schematic diagram of a state machine state transition process according to one embodiment;

[0059] Figure 11 This is a schematic diagram of the structure of a parallel SPI control system according to one embodiment;

[0060] Figure 12 This is a structural example diagram of a parallel SPI control system according to one embodiment;

[0061] Figure 13 This is a connection diagram of a multiplexer according to one embodiment;

[0062] Figure 14 This is a flowchart illustrating a parallel SPI communication method according to one embodiment. Detailed Implementation

[0063] The present application will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by related similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the present application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present application are not shown or described in the specification. This is to avoid obscuring the core parts of the present application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0064] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0065] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0066] Understandably, with the increasing complexity of the overall system design, the master unit needs to communicate frequently with multiple slave units, and the slave units in turn need to control multiple external devices. A specific connection diagram is shown below. Figure 1 As shown, slave devices 1 through N are responsible for implementing different functions. Each slave device is connected to several external devices (such as switching chips, filter chips, digital-to-analog converter chips, etc.), and the operating status of all devices is controlled by the master. Communication between the master and slave devices, and between slave devices and peripherals, is carried out through the SPI bus. Since the master's own SPI bus interface is limited and cannot meet the needs of multiple slave devices / peripherals for SPI communication, it is necessary to expand the number of SPI channels.

[0067] One expansion solution involves connecting a dedicated SPI bus expansion chip to the host's native SPI interface. This solution increases the bill of materials and the area and number of layers on the printed circuit board (PCB), thereby increasing the hardware cost of the system. It also increases the complexity of system design, such as PCB routing and software development. Furthermore, all SPI expansion channels still need to be serially forwarded through the host's native SPI interface, thus failing to achieve true parallel independent communication among multiple slave devices.

[0068] Another expansion scheme involves instantiating multiple SPI controller soft cores using an FPGA. This scheme still employs a serial polling mechanism, which involves sequentially polling the status of the SPI controller currently communicating with the master. Only after the current SPI communication is completely completed can the next SPI communication operation be initiated. In other words, in this scheme, the master sends communication commands and data sequentially, and it also cannot achieve true parallel independent communication among multiple slave devices.

[0069] In addition, the two SPI channel expansion schemes mentioned above not only fail to achieve true parallel independent communication among multiple slave devices, but also suffer from a high proportion of idle waiting time in a single communication, resulting in high communication control overhead on the master side and low overall system communication efficiency.

[0070] To address the aforementioned issues, this application proposes a parallel SPI controller scheme. The core idea is to implement instruction caching by introducing a cache module into the SPI controller, and to automatically generate and output SPI communication timing without host intervention. This decouples the host's parameter configuration operations from the SPI controller's parameter execution operations, thereby breaking the traditional host serial polling mechanism and laying the foundation for true parallel independent communication among multiple slave devices.

[0071] Please refer to Figure 2 Some embodiments provide a parallel SPI controller 100, including: a frame generation module 110, a frame buffer module 120, and a timing generation module 130. The following is a detailed description of each module.

[0072] The frame generation module 110 is used to obtain the control frame and the data frame to be sent from the corresponding register group after receiving the enable signal to generate an instruction frame; wherein the instruction frame is configured to include timing configuration parameters and data to be sent required to execute a complete SPI communication transaction.

[0073] The enable signal is a control signal sent by an external host to trigger the parallel SPI controller 100 to perform SPI communication.

[0074] The corresponding register group refers to the register group used to store the timing configuration parameters and data to be sent by the external host regarding the parallel SPI controller 100.

[0075] In some embodiments, a register set includes a control register for storing timing configuration parameters and a write data register for storing data to be transmitted.

[0076] A control frame is a frame format transmission unit in which the host encapsulates the timing configuration parameters of the parallel SPI controller 100 according to the format agreed upon in the protocol, and then sends and stores them in the corresponding register group.

[0077] A data frame to be transmitted refers to a frame format transmission unit in which the host encapsulates the data to be transmitted (data written to the slave / peripheral) of the parallel SPI controller 100 according to the format agreed upon by the protocol, and then sends it down and stores it in the corresponding register group.

[0078] In some embodiments, control frames are stored in the control register of the corresponding register group, and data frames to be sent are stored in the write data register of the corresponding register group.

[0079] A command frame is a frame format transmission unit that is a secondary encapsulation of a control frame and a data frame to be transmitted by the frame generation module 110 according to a preset format. A command frame contains all the information required to execute a complete SPI communication transaction, including timing configuration parameters and data to be transmitted, without requiring an external host to provide additional information or intervene in real time during execution.

[0080] In some embodiments, the frame generation module 110 generates a command frame by concatenating the control frame and the data frame to be sent.

[0081] In some embodiments, the input of the frame generation module 110 is simultaneously connected to the output of both the control register and the write data register. Once the host completes writing instructions to the register group, no further operation is required. When the parallel SPI controller 100 receives an enable signal, the frame generation module 110 is triggered. Within the same clock cycle, the frame generation module 110 simultaneously captures the control frame in the control register of the corresponding register group and the data frame to be transmitted in the write data register, and concatenates them into a fixed-format "instruction frame." The bit width of this instruction frame is equal to the sum of the control register bit width (assuming M) and the write data register bit width (assuming N) (i.e., M+N), where the first part (e.g., the high M bits) is the control frame, containing all timing configuration parameters; the second part (e.g., the low N bits) is the data frame to be transmitted, containing all data to be transmitted; or it can be arranged according to other predefined formats.

[0082] It is understandable that by generating instruction frames through the frame generation module 110, the control frame and the data frame to be sent corresponding to the same SPI communication transaction are bound into a whole, so that one instruction frame uniquely corresponds to one complete SPI communication transaction; at the same time, the format of scattered register values ​​is standardized, which facilitates the orderly management of multiple SPI transactions to be executed by the parallel SPI controller 100 in the future.

[0083] Through the above splicing operation, the control frame and the data frame to be sent, which were originally stored separately in two registers, are bound into an indivisible hardware executable unit—the instruction frame. This enables the frame buffer module 120 to store and manage the SPI transactions to be executed in a unified format, providing a structural basis for the "read once, execute once" of the subsequent timing generation module 130.

[0084] For example, Figure 3 A schematic diagram of a register bank structure is provided. Please refer to it. Figure 3 In some embodiments, a register set also includes a read data register for storing data sent from the slave / peripheral to the host.

[0085] The frame buffer module 120, connected to the frame generation module 110, is used to store at least one of the instruction frames.

[0086] Understandably, to break the original serial polling mechanism of the external host to the SPI controller, it is necessary to decouple the instruction issuance from the external host from the instruction execution of the SPI controller. By setting up the frame buffer module 120, the instruction frame can be directly buffered after the frame generation module 110 generates the instruction frame. Since one instruction frame corresponds to a complete SPI communication transaction, containing all the timing configuration parameters and data to be sent required for one SPI communication, the timing generation module 130 of the parallel SPI controller 100, which is responsible for subsequent instruction execution, can independently retrieve the instruction frame from the frame buffer module 120 and execute it automatically, without the external host needing to query or intervene in real time. Therefore, the external host can immediately return to processing other tasks after issuing the instruction, thereby achieving decoupling between the instruction issuance from the external host and the instruction execution of the SPI controller.

[0087] In some embodiments, the frame buffer module 120 is a FIFO queue used to store at least one of the instruction frames in a first-in-first-out manner.

[0088] In some embodiments, the FIFO queue has a write port and a read port. The write port is connected to the output of the frame generation module 110. When the frame generation module 110 generates a new instruction frame, the instruction frame is written to the tail of the FIFO queue. The read port is connected to the input of the timing generation module 130. When the timing generation module 130 needs to obtain an instruction frame, it reads an instruction frame from the head of the FIFO queue. After reading, the instruction frame is popped from the FIFO queue, and the next instruction frame becomes the new head.

[0089] In some embodiments, the FIFO queue also outputs an empty flag and a full flag. The timing generation module 130 determines whether there are any pending instruction frames in the FIFO by detecting the empty flag (a non-empty flag indicates that there are pending instructions). When the empty flag is invalid (i.e., the FIFO is not empty), the timing generation module 130 actively initiates a read operation. The full flag can be used to indicate to the external host that the FIFO is full, prompting the external host to pause issuing new instructions to avoid overflow.

[0090] It is understandable that by using a FIFO queue as the frame buffer module 120, the instruction frames are executed sequentially according to the order in which they are sent by the external host, and the pipelined parallel processing of instructions sent by the external host and instructions executed by the timing generation module 130 is realized.

[0091] The timing generation module 130 is connected to the frame buffer module 120 and is used to sequentially read one instruction frame from the frame buffer module 120 when the frame buffer module 120 is not empty, and automatically generate and output a set of SPI communication timing corresponding to the read instruction frame.

[0092] Understandably, the timing generation module 130, as the instruction execution module of the parallel SPI controller 100, needs to read instruction frames and generate the corresponding SPI communication timing based on the timing configuration parameters and data to be sent contained in the instruction frames. Therefore, the timing generation module 130 needs to continuously monitor whether the frame buffer module 120 is empty. When it detects that the frame buffer module 120 is not empty, the timing generation module 130 reads instruction frames from the frame buffer module 120 to generate and output the corresponding SPI communication timing. This process does not require any real-time querying or intervention from an external host and is entirely completed autonomously by the hardware.

[0093] In one embodiment, an external host can continuously issue multiple instructions to cause the frame generation module 110 to generate multiple corresponding instruction frames and cache them in the frame buffer module 120. When there are multiple instruction frames in the frame buffer module 120, the timing generation module 130 can sequentially read the instruction frames according to the order in which they were stored in the frame buffer module 120 to generate the corresponding SPI communication timing.

[0094] In one embodiment, the parallel SPI controller 100 is located on the programmable logic (PL) end of a heterogeneous computing platform, which also includes a processing system (PS) end, and the external host is the PS end.

[0095] According to the parallel SPI controller in the above embodiment, after receiving the enable signal, the frame generation module acquires the control frame and the data frame to be sent to generate a complete instruction frame, which is then stored in the frame buffer module. Simultaneously, the timing generation module actively and sequentially reads the instruction frames and automatically generates the corresponding SPI communication timing when the frame buffer module is not empty. Because this architecture pre-encapsulates the timing configuration data and the data to be sent from the external host into instruction frames and caches them in a queue, the instruction issuance from the external host and the instruction execution from the SPI controller are completely decoupled in time. The external host does not need to wait for the current SPI transaction to complete before continuously writing subsequent instructions, nor does it need to query the SPI controller's status in real time, thus eliminating the serial polling and idle waiting issues present in traditional solutions. The performance bottleneck introduced by this significantly reduces the control overhead on the host side, enabling batch pre-storage of instructions and pipelined automatic execution, greatly improving system throughput and overall communication efficiency in multi-slave / peripheral communication scenarios. In addition, the above-mentioned parallel SPI controller solution creates conditions for realizing true parallel independent communication among multiple slaves / peripherals. That is, when multiple parallel SPI controllers as described in the above embodiments are instantiated in the system, since each parallel SPI controller has its own independent frame generation module, frame buffer module, and timing generation module, it can independently execute its own instruction queue. Therefore, they can work simultaneously without interfering with each other, thus truly realizing parallel independent communication among multiple slaves / peripherals, rather than traditional serial polling time-sharing communication.

[0096] Furthermore, in some embodiments, the control frame is used to carry timing configuration parameters, which include one or more of the following: SPI operating mode, transmission bit sequence mode, chip select control, front delay, back delay, number of transmission cycles, and number of clock divisions.

[0097] Among them, the SPI working modes define four working modes (Mode0, Mode1, Mode2, Mode3), which correspond to different states of clock polarity (CPOL) and clock phase (CPHA), and determine the clock idle state and data sampling edge.

[0098] Transmission bit order mode: Defines whether to transmit in the most significant bit (MSB) mode or the least significant bit (LSB) mode, and determines the direction of data shift.

[0099] Chip select control: Defines which chip select signal (such as CS0 or CS1) is output to extend applications and distinguish which slave device or which peripheral device on the slave device is currently communicating with the master via SPI.

[0100] Pre-delay: Defines the waiting time from when the chip select signal is pulled low until the start of the first SPI clock pulse, used to meet the chip select setup time requirements of some slave devices.

[0101] Post-delay: Defines the waiting time from the end of the last SPI clock pulse until the chip select signal goes high, used to meet the chip select hold time requirements of some slave devices.

[0102] Transmission cycles: Defines the number of clock pulses required for this SPI communication, which also corresponds to the bit length of the transmitted data. This parameter enables the SPI controller to support arbitrary bit lengths that are not multiples of 8.

[0103] Clock divider: Defines the division relationship between the generated SPI clock frequency and the module's operating clock frequency. For example, when the module's operating clock is 400MHz, different clock dividers can be set to generate SPI clock frequencies in the range of 10kHz to 200MHz.

[0104] For example, please refer to Figure 4 The diagram shows the control frame format. In this example, the timing configuration parameters carried by the control frame include: SPI operating mode, transmission bit sequence mode, chip select control, lead time, trailing time, number of transmission cycles, and clock divider.

[0105] It is understandable that the main configurable parameters of existing SPI controllers generally only include: operating mode (clock polarity and clock phase), clock frequency, data frame format (usually supporting 4-bit, 8-bit, and 16-bit) and chip select signal. This application enables the parallel SPI controller 100 to adapt to a variety of custom SPI protocol modules with different timing requirements by flexibly configuring the above timing configuration parameters, thereby solving the problems of limited parameter configuration and poor compatibility in the prior art.

[0106] Furthermore, in some embodiments, the SPI communication timing includes at least: an SPI clock signal, a chip select signal, and an SPI write data signal.

[0107] In the SPI communication, the clock signal (CLK) is generated by the master and output to the slave for synchronous data transmission. Within each clock cycle, the master and slave sample or change the level on the data lines at agreed-upon edges (rising or falling edges). The clock frequency determines the SPI communication rate.

[0108] The Chip Select (CS) signal is an enable signal output from the master SPI controller to the slave device (or its internal peripheral), and is typically active low. Physically, the SPI controller's chip select pin is connected to the chip select pins of different slave devices (or their internal peripherals) via multiple chip select signal lines. Its core function is to uniquely select the target to communicate with from among multiple possible targets by pulling the chip select pin of a specific target low (which is high by default), while keeping the chip select pins of unselected targets high, thus avoiding SPI bus conflicts.

[0109] In some embodiments, each parallel SPI controller can output two chip select signals: CS0 and CS1. These two signals can be used not only to distinguish SPI communication between the master and two different slave devices (e.g., slave 1 and slave 2), but also to further extend the application to distinguish SPI communication between the master and a slave device itself, as well as with peripheral modules on that slave device.

[0110] For example, please refer to Figure 5 CS0 is used as the chip select signal for SPI communication between the master and slave X itself, and CS1 is used as the chip select signal for SPI communication between the master and peripherals 1, 2, ..., N on slave X. Specifically, when the master only needs to communicate with slave X itself via SPI, it pulls the chip select pin corresponding to CS0 low while keeping the chip select pin corresponding to CS1 high (assuming that the chip select pins corresponding to CS0 and CS1 have been restored to their default high level before the master communicates with slave X). At this time, the master generates the SPI communication timing sequence to configure the registers inside slave X. When the master needs to communicate with any peripheral on slave X, such as peripheral 1, it first pulls the chip select pin corresponding to CS0 low while keeping the chip select pin corresponding to CS1 high (assuming that the chip select pins corresponding to CS0 and CS1 have been restored to the default high level before the master communicates with peripheral 1). At this time, the master generates the corresponding SPI communication timing sequence 1 and sends it to slave X to inform slave X of the selected peripheral. For example, the identification information corresponding to peripheral 1 is included in SPI communication timing sequence 1. Then, slave X parses SPI communication timing sequence 1 and writes the identification information corresponding to peripheral 1 contained therein into slave X's internal register. Then, slave X's internal register passes the identification information corresponding to peripheral 1 to the multiplexer to select the communication link between slave X and peripheral 1. After that, the master pulls the chip select pin corresponding to CS0 high and pulls the chip select pin corresponding to CS1 low. At this time, the master generates the corresponding SPI communication timing sequence 2 and sends it to slave X. Then, slave X parses SPI communication timing sequence 2 and passes the parsed SPI communication timing sequence 2 to peripheral 1 through the communication link selected by the multiplexer.

[0111] For example, please refer to Figure 6 CS0 is used as the chip select signal for SPI communication between the master and slave 1, and CS1 is used as the chip select signal for SPI communication between the master and slave 2. When the master needs to communicate with slave 1 via SPI, the chip select pin corresponding to CS0 is pulled low, and the master generates the corresponding SPI communication timing for slave 1; when the master needs to communicate with slave 2 via SPI, the chip select pin corresponding to CS1 is pulled low, and the master generates the corresponding SPI communication timing for slave 2.

[0112] It should be noted that, for Figure 6 In the chip select example shown, when the master needs to communicate with any peripheral on the slave device, such as the peripheral on slave 1, the master can first generate an SPI communication timing sequence through CS0 and send it to slave 1, and then slave 1 can generate a new SPI communication timing sequence and send it to the peripheral on slave 1.

[0113] In some embodiments, a parallel SPI controller can output more than two chip select signals. In this case, for Figure 6 The chip select example shown allows the master to establish SPI communication with more than two slave devices.

[0114] The SPI write data signal (Master Out Slave In, MOSI) is output by the master and input by the slave. The master outputs the data to be sent bit by bit (usually starting from the most significant bit (MSB) or least significant bit (LSB)) sequentially onto the MOSI line. The slave samples this signal at the edge of the clock to receive the data. This signal is only used for data transmission from the master to the slave and is a unidirectional data transmission signal.

[0115] For example, please refer to Figure 7 The diagram shows the SPI communication timing. In this example, the SPI operating mode is Mode0 (CPOL=0, CPHA=0), the transmission bit sequence mode is LSB, the chip select control is the chip select pin CS0 pulled low, the lead time is parameter START_DELAY, the follow time is parameter END_DELAY, and the number of cycles is 8.

[0116] Please refer to Figure 8 In some embodiments, the timing generation module 130 includes: a state machine 131, a control configuration latch module 132, a chip select signal generation module 133, a clock divider 134, a data latch module 135, and a data transmission module 136. Wherein:

[0117] State machine 131 is used to generate at least one state to control the generation process of the SPI communication timing.

[0118] In some embodiments, the state machine 131 serves as the core control unit of the timing generation module 130, transitioning according to a predefined state sequence, and triggering the corresponding sub-module to perform a specific operation in each state.

[0119] The control configuration latch module 132 is connected to the state machine 131 and is used to parse and latch the timing configuration parameters in the instruction frame read from the frame buffer module 120 under the control of the state machine 131. The timing configuration parameters include at least: chip select control, front delay, back delay and clock division number.

[0120] In some embodiments, the input of the control configuration latch module 132 is connected to the read port of the frame buffer module 120. When the state machine 131 enters the loading state, the control configuration latch module 132 is triggered, and the timing configuration parameters are parsed from the currently read instruction frame and latched into the internal register.

[0121] The chip select signal generation module 133 is connected to the state machine 131 and the control configuration latch module 132 respectively. Under the control of the state machine 131, it adjusts the level state of the chip select pin according to the chip select control, the pre-delay, and the post-delay to generate the chip select signal.

[0122] In some embodiments, the chip select signal generation module 133 receives timing control parameters such as chip select control, pre-delay, and post-delay from the control configuration latch module 132, and, under the control of the state machine 131, adjusts the level state of the chip select pin according to these timing control parameters to generate the final chip select signal. For example, when the level state of the chip select pin is all high by default, in the pre-delay state, the chip select signal generation module 133 pulls down the chip select pin specified by the chip select control, and in the post-delay state, performs a delay count to pull up the pulled-down chip select pin again after the delay ends, thereby obtaining the corresponding chip select signal.

[0123] The clock divider 134 is connected to the state machine 131 and the control configuration latch module 132 respectively. Under the control of the state machine 131, it divides the system working clock according to the clock division number to generate the SPI clock signal.

[0124] For example, when the system operating clock is 400MHz, an SPI clock frequency in the range of 10kHz to 200MHz can be generated by setting different clock division numbers.

[0125] The data latch module 135 is connected to the state machine 131 and is used, under the control of the state machine 131, to parse and latch the data frame to be sent from the instruction frame read from the frame buffer module 120.

[0126] In some embodiments, the input of the data latch module 135 is connected to the read port of the frame buffer module 120. When the state machine 131 enters the loading state, the data latch module 135 is triggered, parses the data frame to be sent from the currently read instruction frame, and latches it into an internal register for use by the subsequent data sending module 136.

[0127] The data transmission module 136 is connected to the state machine 131 and the data latch module 135 respectively, and is used to convert the data frame to be transmitted in the instruction frame from a parallel data stream to a serial data stream under the control of the state machine 131 to obtain the SPI write data signal.

[0128] In some embodiments, the data transmission module 136 internally includes a shift register with a bit width equal to the bit width of the data frame to be transmitted (e.g., 8 bits, 16 bits, or a user-defined number of cycles). After state machine 131 enters the "shift state," the data transmission module 136 first loads the data frame to be transmitted in parallel data stream format from the data latch module 135 into the shift register. Subsequently, on each valid edge of the SPI clock signal (generated by clock divider 134) (determined by the SPI operating mode, e.g., rising edge output in Mode 0), the data transmission module 136 outputs the most significant bit (MSB mode) or the least significant bit (LSB mode) of the shift register to the MOSI signal line according to the "transmission bit sequence mode" parameter, while simultaneously shifting the shift register left or right by one bit. This process is repeated, with one bit of data output for each SPI clock pulse until the total number of output bits reaches the value specified by the "transmission cycle number" parameter. After all data bits have been output, the shift register is cleared or retains its last state, awaiting the loading of the next instruction frame. The entire process is synchronously controlled by state machine 131, without the need for external host or software intervention, thus realizing automatic hardware conversion from parallel data to serial MOSI signal.

[0129] For example, please refer to Figure 9 The example shown is a parallel SPI controller 100, in which the frame generation module 110 is implemented by a frame splicing module, and the frame buffer module 120 is implemented by a FIFO queue. Furthermore, this example also includes a data receiving module for receiving data from slave / peripheral devices and transmitting it to the master.

[0130] In some embodiments, the state machine is used to sequentially execute the following states: idle state, load state, pre-delay state, shift state, post-delay state, and end state, to control the generation process of the SPI communication timing. Wherein:

[0131] Idle state (IDLE): The initial state of the state machine, waiting for a new instruction frame to arrive.

[0132] Load status (LOAD): Load configuration parameters and data to be sent from the instruction frame.

[0133] START_DELAY state: Pull the chip select pin low and wait for a lead time.

[0134] Shift state (SHIFT): Generates the SPI clock and shifts out data one bit at a time.

[0135] End-delay state (END_DELAY): After performing an end-delay wait, the chip select pin is pulled high.

[0136] End Status: The current SPI transaction is complete, and the system is ready to process the next instruction frame.

[0137] The above state sequence ensures that the SPI communication timing corresponding to each instruction frame can be generated in the correct order and timing relationship.

[0138] In some embodiments, the timing configuration parameters further include: the number of transmission cycles;

[0139] State machine 131 is configured as follows:

[0140] In the idle state, it is detected whether the frame buffer module 120 is not empty; if so, it enters the loading state.

[0141] In the loading state, the trigger control configuration latch module 132 parses and latches the timing configuration parameters from the currently read instruction frame, and triggers the data latch module 135 to parse and latch the data frame to be sent. After completion, it enters the pre-delay state.

[0142] In the pre-delay state, the trigger chip select signal generation module 133 pulls down the corresponding chip select pin according to the chip select control, and performs a first delay count according to the pre-delay. After the first delay count reaches the pre-delay, it enters the shift state.

[0143] In the shift state, the clock divider 134 is triggered to generate the SPI clock signal according to the clock division number, and the data transmission module 136 is triggered to convert the data frame to be transmitted into a serial data stream to output the SPI write data signal, and the number of shifts is controlled according to the number of transmission cycles. After the number of shifts reaches the number of transmission cycles, the post-delay state is entered.

[0144] In the post-delay state, the chip select signal generation module 133 triggers a second delay count based on the post-delay parameter. After the second delay count reaches the post-delay, the chip select pin is pulled high and the process enters the end state.

[0145] In the end state, the trigger state machine 131 returns to the idle state to prepare for processing the next instruction frame in the frame buffer module 120.

[0146] For example, please refer to Figure 10 The diagram shows the state transition process of the state machine, and its control flow is as follows:

[0147] When the state machine is in the IDLE state, the enable module controls the FIFO to write configuration data, writing the values ​​of the write data register and control register into the FIFO. When the FIFO is not empty and the state machine is in the IDLE state, a set of configuration data (i.e., an instruction frame) is read from the FIFO and the SPI controller is started. When the FIFO reads valid data, a pulse signal (start_flag) is generated as a start flag; when the start flag is received, the process jumps to the LOAD state.

[0148] When the state machine is in the LOAD state, it loads configuration data, reads a configuration data (the values ​​of the control register and the write data register, i.e., the control frame and the data frame to be sent) from the FIFO, populates the buffer, and jumps to the START_DELAY state.

[0149] When the state machine is in the START_DELAY state, it pulls the chip select pin specified by the configuration data low and uses a counter to count for a delay. When the count reaches the value of the previous delay, it generates a previous delay end flag (hdelay_end_flag) and jumps to the SHIFT state.

[0150] When the state machine is in the SHIFT state, it starts generating SPI communication timing according to the configured SPI working mode. When the number of SPI transmission cycles is met, a shift end flag (shift_end_flag) is generated, and the machine jumps to the END_DELAY state.

[0151] When the state machine is in the END_DELAY state, it stops generating the SPI clock, sets MOSI to 0, uses a counter to delay counting, and generates a delay end flag (tdelay_end_flag) when the count reaches the delay value, pulls the chip select pin specified by the configuration data high, and jumps to the END state.

[0152] When the state machine is in the END state, it automatically transitions to the IDLE state.

[0153] When the state machine returns to IDLE, the above process is repeated until the FIFO is empty and the state machine is in the IDLE state, indicating that all configuration instructions (i.e. all instruction frames) have been executed.

[0154] Understandably, the state machine autonomously flows according to a predefined state sequence (idle → load → pre-delay → shift → post-delay → end), requiring no real-time intervention from the external host. Once an instruction frame is pushed into the frame buffer module, the state machine automatically starts, executes, and completes the entire SPI communication transaction. Furthermore, the state machine independently reads and executes instruction frames from the frame buffer module (FIFO), allowing the external host to continuously write multiple instructions to the frame buffer module, which the state machine processes automatically in sequence. This overlap between "issuing" and "executing" in time forms pipelined parallel processing, eliminating the performance bottleneck caused by host polling in traditional solutions. In addition, since the state machine is entirely controlled by hardware logic, the external host does not need to query status bits in real-time, initiate interrupts, or require software intervention throughout the SPI communication process. This allows the external host to dedicate valuable time to processing upper-layer applications or other real-time tasks, thereby reducing host-side control overhead.

[0155] Furthermore, the state machine handles pre-delay, shift output, and post-delay stages separately through different states, allowing the duration of each stage to be independently adjusted by the corresponding timing configuration parameters (such as pre-delay, post-delay, clock division, and transmission cycle number) in the control frame. This structural design enables the parallel SPI controller of this application to accurately adapt to various external devices with special timing requirements, significantly improving compatibility.

[0156] Please refer to Figure 11 Some embodiments provide a parallel SPI control system 200, including: a register module 210, an enable generation module 220, and one or more parallel SPI controllers 100 as described in any of the above embodiments of this application. Wherein:

[0157] Register module 210 includes at least one register group, each register group including at least a control register for storing control frames and a write data register for storing data frames to be sent; the register group is used to receive control frames and data frames to be sent in the configuration data stream.

[0158] In some embodiments, register module 210 receives a configuration data stream from the host via a data bus. This configuration data stream carries an SPI controller identifier, a control frame to be written, and a data frame to be sent. Register module 210 writes the control frame into the control register of the corresponding register group and writes the data frame to be sent into the write data register of the corresponding register group, based on the address information corresponding to the SPI controller identifier.

[0159] Enable generation module 220 is used to receive the SPI controller identifier in the configuration data stream and generate an enable signal for the parallel SPI controller corresponding to the SPI controller identifier.

[0160] In some embodiments, the enable generation module 220 internally includes address decoding logic capable of resolving the parallel SPI controller corresponding to the SPI controller identifier and generating an enable signal specific to that parallel SPI controller. This enable signal is output to the corresponding parallel SPI controller to trigger it to start working.

[0161] Understandably, the traditional SPI controller configuration process, besides writing control frames to the control register and writing data frames to be sent to the write data register, also includes a dedicated enable configuration step to start the SPI controller. However, in this application, by setting up an enable generation module 220 and including the SPI controller identifier of the parallel SPI controller to be configured in the configuration data stream, the enable generation module 220 can generate the corresponding enable signal for the parallel SPI controller by recognizing the SPI controller identifier in the configuration data stream. This reduces the traditional enable configuration step for starting the SPI controller and optimizes the overall configuration logic.

[0162] Each parallel SPI controller 100 is connected to the enable generation module 220 and the register module 210 respectively. After receiving the enable signal from the enable generation module 220, it obtains the control frame and the data frame to be sent in the corresponding register group in the register module 210 to generate an instruction frame, and generates the corresponding SPI communication timing based on the instruction frame. Each parallel SPI controller 100 corresponds to a unique SPI controller identifier and a unique register group.

[0163] In some embodiments, when the parallel SPI controller 100 receives the enable signal from the enable generation module 220, the frame generation module 110 inside the parallel SPI controller 100 immediately obtains the control frame and the data frame to be sent from its corresponding register group, concatenates them to generate an instruction frame, and stores the instruction frame in the frame buffer module 120 inside the parallel SPI controller 100. Subsequently, the timing generation module 130 inside the parallel SPI controller 100 reads the instruction frame from the frame buffer module 120, automatically generates and outputs a corresponding set of SPI communication timing sequences.

[0164] With the above structure, this embodiment enables multiple parallel SPI controllers to coexist independently in the same system. Each controller has its own independent register group and enable control, and they do not interfere with each other.

[0165] In some embodiments, the parallel SPI controller 100 within the same system-defined channel is connected to the same register group to share the same register group.

[0166] In this context, a system-defined channel can be understood as an independent SPI communication link logically defined during system design. For example, based on functional requirements, system designers group external devices that need to communicate with the host, and each group is called a "system-defined channel." For instance, all sensors might be placed on channel 0, and all actuators on channel 1.

[0167] In some embodiments, when the system has multiple system-defined channels, each system-defined channel is configured with an independent register group and associated with one or more parallel SPI controllers 100. When there is only one parallel SPI controller 100 in a system-defined channel, the parallel SPI controller 100 exclusively occupies the register group of the system-defined channel; when there are multiple parallel SPI controllers 100 in a system-defined channel, the multiple parallel SPI controllers 100 share the register group of the system-defined channel.

[0168] It is understandable that by configuring an independent register set (corresponding to an independent register base address) for each system-defined channel, when the system contains multiple system-defined channels, different system-defined channels can be distinguished by accessing different register base addresses. Compared to adding parameters (such as channel numbers) specifically for distinguishing different system-defined channels in the configuration data or setting up independent configuration functions for each system-defined channel, the method of this application simplifies software configuration. Furthermore, when a system-defined channel contains multiple parallel SPI controllers 100, the multiple parallel SPI controllers 100 share the same register set, that is, they share the same register base address. In software, the multiple parallel SPI controllers 100 can also share the same configuration function, thus also simplifying software configuration.

[0169] In some embodiments, the parallel SPI control system 200 further includes: a bus interface module and a protocol parsing module. Wherein:

[0170] The bus interface module is used to receive instruction data from the host via a high-speed bus.

[0171] In some embodiments, the bus interface module is located in the programmable logic (PL), and its input is connected to the host (processing system PS) via a high-speed bus to receive instruction data issued by the host. This high-speed bus can be any bus protocol suitable for on-chip communication, such as AXI, AHB, or PCIe.

[0172] The protocol parsing module, connected to the bus interface module, is used to parse the instruction data and generate the configuration data stream.

[0173] In some embodiments, the parsing module parses the address, data, and control information according to the bus protocol specification (such as the AXI-Lite protocol) to generate a configuration data stream. This configuration data stream includes at least: an SPI controller identifier, a control frame, and a data frame to be sent. The configuration data stream is output to register module 210 and enable generation module 220 respectively: register module 210 writes the control frame and data frame into the corresponding register group according to the address information corresponding to the SPI controller identifier; enable generation module 220 generates the corresponding enable signal according to the SPI controller identifier.

[0174] In some embodiments, the operation of the host sending instruction data through the bus interface module and the operation of the parallel SPI controller 100 generating and outputting the SPI communication timing are executed independently of each other.

[0175] In some embodiments, the process of the host (PS) writing instruction data to the protocol parsing module through the bus interface module is completely decoupled in time from the process of the frame buffer module 120 (FIFO) storing instruction frames and the timing generation module 130 reading and executing instruction frames within the parallel SPI controller 100. After completing the write operation, the host can immediately return to processing other tasks without waiting for the current or subsequent SPI communication timing generation tasks to complete. The parallel SPI controller 100 then independently and automatically reads instruction frames from its frame buffer module and generates SPI timing.

[0176] Understandably, this design, which allows for independent execution, enables a pipelined parallel operating mode between the host and the parallel SPI controller: the host can continuously issue multiple instructions, while the parallel SPI controller executes them automatically in sequence. The host does not need to query the controller status in real time, eliminating the polling overhead of traditional solutions and significantly improving the overall communication efficiency of the system.

[0177] In some embodiments, the high-speed bus is an AXI-Lite bus, and the bus interface module is an AXI-Lite bus interface.

[0178] Understandably, AXI-Lite is a simplified version of the Advanced Extensible Interface (AXI) protocol introduced by ARM, designed specifically for register-level access of low-bandwidth, simple peripherals. This protocol supports word or byte-level transmission and features simple address mapping, concise control logic, and low hardware overhead. The AXI-Lite bus can achieve transmission rates exceeding 800 Mb / s, far exceeding the rates of traditional PS-side native SPI controllers (typically tens of Mb / s). Utilizing the high-speed characteristics of the AXI-Lite bus ensures that the host can quickly issue instructions without becoming a bottleneck to system performance. This, combined with the efficient automatic execution capabilities of the parallel SPI controller, enables high-speed, low-latency SPI communication control.

[0179] For example, please refer to Figure 12 An example of a parallel SPI control system 200 is given. In this example, the bus interface module is an AXI-Lite bus interface, which also serves as the input terminal of the protocol parsing module. That is, the protocol parsing module directly parses the instruction data sent by the host through the AXI-Lite bus and generates a configuration data stream, which is then input to the enable generation module and the register module.

[0180] In some embodiments, the parallel SPI control system 200 further includes: a multiplexer, including a first input terminal and a second input terminal, the first input terminal being connected to the native SPI controller of the host, the second input terminal being connected to at least one parallel SPI controller 100, and the output terminal of the multiplexer being connected to the SPI bus; the multiplexer is used to select the receiving data source of the SPI bus to realize dynamic switching of the SPI communication path.

[0181] The native SPI controller can be understood as the SPI controller integrated into the PS side and embedded in the hardware (such as the two hard-core SPI controllers on the PS side of the ZYNQ chip).

[0182] In some embodiments, the multiplexer is configured with a selection control terminal. Depending on the state of the selection control terminal, the multiplexer decides whether to pass the signal from the first input terminal (the output of the native SPI controller) or the signal from the second input terminal (the output of the parallel SPI controller 100) to the output terminal, thereby sending it to the corresponding slave / peripheral.

[0183] By adding a multiplexer, dynamic switching of the SPI communication path can be achieved, allowing the system to flexibly select the data source according to actual application requirements: when simple communication is required using the native SPI controller, the first input terminal can be selected; when complex multi-slave / peripheral communication is required using the parallel, high-efficiency, parameter-configurable SPI controller of this application, the second input terminal can be selected.

[0184] For example, please refer to Figure 13 Path selector connection diagram. Through the multiplexer, the data source can choose to receive data generated by the native SPI controller on the PS side, or it can choose to receive data generated by the parallel SPI controller on the PL side. This makes it more flexible and controllable in practical applications, facilitating deployment in communication across different application scenarios and complex system architectures.

[0185] Please refer to Figure 14 Some embodiments provide a parallel SPI communication method 300, applied to the parallel SPI controller 100 as described in any of the above embodiments of this application, including the following steps:

[0186] Step 310: After receiving the enable signal, acquire the corresponding control frame and data frame to be sent to generate an instruction frame; wherein, the instruction frame is configured to include timing configuration parameters and data to be sent required to execute a complete SPI communication transaction;

[0187] Step 320: Store at least one of the instruction frames to the frame buffer module;

[0188] Step 330: When the frame buffer module is detected to be non-empty, read one instruction frame from it in sequence, and automatically generate and output a set of SPI communication timing corresponding to the read instruction frame;

[0189] Step 340: Return to the instruction frame reading step until all instruction frames in the frame buffer module have been executed.

[0190] The parallel SPI communication method 300 described in this embodiment can be executed by the parallel SPI controller 100 described in any embodiment of this application, and has the same beneficial effects. For details, please refer to any embodiment of the parallel SPI controller 100 described above, which will not be repeated here.

[0191] In the above embodiments, implementation can be achieved, in whole or in part, by software, hardware, firmware, or any combination thereof. Furthermore, as those skilled in the art will understand, the principles herein can be reflected in a computer program product on a computer-readable storage medium pre-loaded with computer-readable program code. Any tangible, non-transitory computer-readable storage medium may be used, including magnetic storage devices (hard disks, floppy disks, etc.), optical storage devices (CDs, DVDs, Blu-ray discs, etc.), flash memory, and / or the like. These computer program instructions can be loaded onto a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to form a machine, such that instructions executing on the computer or other programmable data processing apparatus can generate means for performing a specified function. These computer program instructions can also be stored in a computer-readable storage medium that can instruct the computer or other programmable data processing apparatus to operate in a particular manner, such that instructions stored in the computer-readable storage medium can form an article of manufacture, including means for implementing the specified function. The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to perform a series of operational steps on the computer or other programmable apparatus to produce a computer-implemented process, such that instructions executing on the computer or other programmable apparatus can provide steps for implementing the specified function.

[0192] This document describes various exemplary embodiments with reference to them. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope of this document. For example, various operational steps and components for performing operational steps can be implemented in different ways depending on the specific application or considering any number of cost functions associated with the operation of the system (e.g., one or more steps can be deleted, modified, or combined with other steps).

[0193] While the principles herein have been illustrated in various embodiments, numerous modifications to the structures, arrangements, proportions, elements, materials, and components, particularly suited to specific environments and operational requirements, may be used without departing from the principles and scope of this disclosure. These modifications and other alterations or alterations will be included within the scope of this document. Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the fundamental principles of the invention.

Claims

1. A parallel SPI controller, characterized in that, include: The frame generation module is used to obtain the control frame and the data frame to be sent from the corresponding register group after receiving the enable signal to generate an instruction frame; wherein, the instruction frame is configured to include the timing configuration parameters and the data to be sent required to execute a complete SPI communication transaction; A frame buffer module, connected to the frame generation module, is used to store at least one of the instruction frames; The timing generation module is connected to the frame buffer module and is used to sequentially read one instruction frame from the frame buffer module when the frame buffer module is not empty, and automatically generate and output a set of SPI communication timing corresponding to the read instruction frame.

2. The parallel SPI controller according to claim 1, characterized in that, The SPI communication timing sequence includes at least: SPI clock signal, chip select signal and SPI write data signal; The timing generation module includes: A state machine is used to generate at least one state to control the generation process of the SPI communication timing. A control configuration latch module, connected to the state machine, is used to parse and latch timing configuration parameters in the instruction frame read from the frame buffer module under the control of the state machine. The timing configuration parameters include at least: chip select control, front delay, back delay, and clock division number. The chip select signal generation module is connected to the state machine and the control configuration latch module respectively, and is used to generate the chip select signal by adjusting the level state of the chip select pin according to the chip select control, the pre-delay, and the post-delay under the control of the state machine. A clock divider is connected to the state machine and the control configuration latch module respectively, and is used to divide the system working clock according to the clock division number under the control of the state machine to generate the SPI clock signal. A data latch module, connected to the state machine, is used to parse and latch the data frame to be sent from the instruction frame read from the frame buffer module under the control of the state machine. The data transmission module is connected to the state machine and the data latch module respectively, and is used to convert the data frame to be transmitted in the instruction frame from a parallel data stream to a serial data stream under the control of the state machine to obtain the SPI write data signal.

3. The parallel SPI controller according to claim 2, characterized in that, The state machine is used to execute the following states sequentially: idle state, load state, pre-delay state, shift state, post-delay state, and end state, in order to control the generation process of the SPI communication timing.

4. The parallel SPI controller according to claim 3, characterized in that, The timing configuration parameters also include: number of transmission cycles; The state machine is configured as follows: In the idle state, it is detected whether the frame buffer module is not empty; if so, it enters the loading state. In the loading state, the control configuration latch module is triggered to parse and latch the timing configuration parameters from the currently read instruction frame, and the data latch module is triggered to parse and latch the data frame to be sent. After completion, the state of pre-delay is entered. In the pre-delay state, the chip select signal generation module is triggered to pull down the corresponding chip select pin according to the chip select control, and performs a first delay count according to the pre-delay. After the first delay count reaches the pre-delay, the shift state is entered. In the shift state, the clock divider is triggered to generate the SPI clock signal according to the clock division number, and the data transmission module is triggered to convert the data frame to be transmitted into a serial data stream to output the SPI write data signal. The number of shifts is controlled according to the number of transmission cycles. After the number of shifts reaches the number of transmission cycles, the post-delay state is entered. In the post-delay state, the chip select signal generation module is triggered to perform a second delay count according to the post-delay parameter. After the second delay count reaches the post-delay, the chip select pin is pulled high and the process enters the end state. In the end state, the state machine is triggered to return to the idle state in preparation for processing the next instruction frame in the frame buffer module.

5. The parallel SPI controller according to claim 1, characterized in that, The frame generation module generates a command frame by concatenating the control frame and the data frame to be sent.

6. The parallel SPI controller according to claim 1, characterized in that, The frame buffer module is a FIFO queue used to store at least one instruction frame in a first-in-first-out manner.

7. The parallel SPI controller according to claim 1, characterized in that, The control frame is used to carry timing configuration parameters, which include one or more of the following: SPI operating mode, transmission bit sequence mode, chip select control, front delay, back delay, number of transmission cycles, and number of clock divisions.

8. A parallel SPI control system, characterized in that, include: A register module, an enable generation module, and one or more parallel SPI controllers as described in any one of claims 1-7; wherein: The register module includes at least one register group, each register group including at least a control register for storing control frames and a write data register for storing data frames to be sent; the register group is used to receive control frames and data frames to be sent in the configuration data stream; The enable generation module is used to receive the SPI controller identifier in the configuration data stream and generate an enable signal for the parallel SPI controller corresponding to the SPI controller identifier. Each of the parallel SPI controllers is connected to the enable generation module and the register module respectively. After receiving the enable signal from the enable generation module, the controller obtains the control frame and the data frame to be sent in the corresponding register group in the register module to generate an instruction frame and generates the corresponding SPI communication timing based on the instruction frame. Each of the parallel SPI controllers corresponds to a unique SPI controller identifier and a unique register group.

9. The parallel SPI control system according to claim 8, characterized in that, Parallel SPI controllers within the same system-defined channel are connected to the same register set to share the same register set.

10. The parallel SPI control system according to claim 8, characterized in that, Also includes: The bus interface module is used to receive instruction data from the host via a high-speed bus. The protocol parsing module, connected to the bus interface module, is used to parse the instruction data and generate the configuration data stream.

11. The parallel SPI control system according to claim 10, characterized in that, The operation of the host sending instruction data through the bus interface module and the operation of the parallel SPI controller generating and outputting the SPI communication timing are executed independently of each other.

12. The parallel SPI control system according to claim 10, characterized in that, The high-speed bus is an AXI-Lite bus, and the bus interface module is an AXI-Lite bus interface.

13. The parallel SPI control system according to any one of claims 10-12, characterized in that, Also includes: A multiplexer includes a first input terminal and a second input terminal. The first input terminal is connected to the native SPI controller of the host, and the second input terminal is connected to the at least one parallel SPI controller. The output terminal of the multiplexer is connected to the SPI bus. The multiplexer is used to select the receiving data source of the SPI bus to achieve dynamic switching of the SPI communication path.

14. A parallel SPI communication method, applied to a parallel SPI controller as described in any one of claims 1-7, characterized in that, include: Upon receiving the enable signal, the corresponding control frame and data frame to be sent are acquired to generate an instruction frame; wherein, the instruction frame is configured to include timing configuration parameters and data to be sent required to execute a complete SPI communication transaction; Store at least one of the instruction frames to the frame buffer module; When the frame buffer module is detected to be non-empty, one instruction frame is read from it sequentially, and a set of SPI communication timing corresponding to the read instruction frame is automatically generated and output. Return to the instruction frame reading step until all instruction frames in the frame buffer module have been executed.

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