Design method of parallel acceleration framework for domestic embedded real-time system
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING INST OF COMP TECH & APPL
- Filing Date
- 2026-03-26
- Publication Date
- 2026-07-21
AI Technical Summary
The existing domestic edge embedded computing platforms have weak parallel computing capabilities, mainly due to their reliance on foreign Linux operating systems, which results in insufficient real-time processing performance.
Design a parallel acceleration framework for domestic embedded real-time systems. It adopts a master-slave architecture, including host nodes and device nodes. It realizes task decomposition, computation and data transmission through a custom network communication protocol and caching system.
It achieves parallel acceleration of computing tasks in domestic embedded real-time systems, meets real-time requirements, and significantly improves computing performance.
Smart Images
Figure CN122432098A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of parallel computing technology, specifically relating to a design method for a parallel acceleration framework for domestically produced embedded real-time systems. Background Technology
[0002] With the continuous development of IoT and edge computing technologies, network edge devices are handling increasingly more data and more complex computing tasks. The most typical example is the application of intelligent algorithms, exemplified by deep learning. Deep learning algorithms have complex network structures and require massive amounts of data, thus placing higher demands on computing resources. The core concept of edge computing is to complete computing tasks at the edge device level to reduce latency and alleviate pressure on cloud computing centers. Therefore, accelerating computing speed and improving the real-time response capability of applications are significant challenges facing edge computing platforms.
[0003] However, Moore's Law has gradually become obsolete, and it's increasingly difficult to improve computing system performance by simply increasing clock frequencies or optimizing chip manufacturing processes. Improving computing architecture has become a crucial method for enhancing computing system performance in the future. To achieve high-performance computing, researchers have focused on parallel computing. Parallel computing architectures significantly improve computational efficiency by allowing processors to execute computational tasks in parallel simultaneously. However, current research on parallel computing largely focuses on general-purpose computing platforms, while research on parallel computing for edge embedded computing platforms, especially domestically developed edge embedded computing platforms, is relatively rare.
[0004] Currently, researchers have designed parallel computing frameworks based on OpenCL for domestically produced DSPs and verified the feasibility and effectiveness of the proposed frameworks through experiments. Other researchers have designed unified parallel programming models for Huawei's processors and performed specific performance optimizations for the supported domestic devices. While these studies have proposed parallel computing frameworks and models for domestic hardware platforms, these frameworks and models rely on the foreign Linux operating system. Furthermore, as a general-purpose operating system, Linux typically performs worse than real-time operating systems in real-time processing.
[0005] Therefore, designing a parallel acceleration framework based on domestically developed embedded real-time systems is a breakthrough for improving the performance of domestically developed edge embedded computing platforms and is a problem that needs to be solved.
[0006] Current research on parallel computing in domestic edge embedded computing platforms mainly relies on foreign general-purpose operating systems such as Linux. However, general-purpose operating systems are inferior to real-time operating systems in terms of real-time processing, resulting in limited improvement in the computing power of domestic edge embedded computing platforms. To address this issue, this invention proposes a parallel acceleration framework design method based on a domestic embedded real-time system. Summary of the Invention
[0007] (a) Technical problems to be solved The technical problem to be solved by this invention is how to provide a design method for a parallel acceleration framework for domestically produced embedded real-time systems, so as to solve the problem of weak parallel computing capabilities of existing domestically produced edge embedded computing platforms.
[0008] (II) Technical Solution To address the aforementioned technical problems, this invention proposes a parallel acceleration framework design method for domestically developed embedded real-time systems, comprising: Step 1: Design the overall architecture The parallel acceleration framework adopts a master-slave architecture, consisting of a host and devices. The host is a multi-core CPU, and the devices are one or more CPUs, GPUs, DSPs, or other acceleration devices. The host and devices are also referred to as host nodes and device nodes. The host node is responsible for task scheduling, and the device node is responsible for task computation. The nodes interact with each other through specific communication protocols and node caching systems to exchange messages and data. Step 2: Design the host node Task scheduling on a host node specifically includes two processes: task partitioning and task mapping. Task partitioning is the process of breaking down a task into several smaller, independently executable subtasks based on task characteristics or data characteristics. Task mapping refers to the process of scheduling the subtasks obtained from the partitioning to device nodes. Step 3: Design Equipment Nodes The core responsibility of a device node is to execute computing tasks. The computing tasks that can be executed are predefined by the proposed parallel acceleration framework. The parallel acceleration framework provides users with two types of computing tasks, also known as two types of computing kernels: classic computing kernels and custom computing kernels. Step 4: Design the communication protocol Nodes transmit information and data through a customized network communication protocol; the customized network communication protocol defines the communication protocol format, which consists of a protocol header and protocol content; Step 5: Design the caching system The caching system is used for message relay between nodes; the implementation of task scheduling, calculation result return, and device node status monitoring all rely on the caching system. The parallel acceleration framework has designed a caching system on each node.
[0009] (III) Beneficial Effects This invention proposes a parallel acceleration framework design method for domestic embedded real-time systems. The proposed parallel acceleration framework adopts a master-slave architecture and designs and implements host nodes and device nodes to complete the decomposition and computation of computing tasks. Through a custom network transmission protocol and caching system, the transmission of messages and data in the system is realized, thereby ultimately achieving parallel acceleration of computing tasks. Attached Figure Description
[0010] Figure 1 This is a diagram of the parallel acceleration framework architecture of the present invention; Figure 2 This is a schematic diagram of the communication protocol format; Figure 3 This is a schematic diagram of a data message format. Detailed Implementation
[0011] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0012] This invention provides a design method for a parallel acceleration framework for domestically developed embedded real-time systems. Addressing the weakness of existing domestic edge embedded computing platforms in parallel computing capabilities, this invention proposes a design method for a parallel acceleration framework for domestically developed embedded real-time systems. Specifically, it includes: building a parallel acceleration framework based on a self-developed domestic embedded real-time operating system and database; the parallel acceleration framework adopts a master-slave architecture, designing and implementing host nodes and device nodes separately to complete the decomposition and computation of computing tasks; realizing the transmission of messages and data in the system through a custom network transmission protocol and caching system, thereby ultimately achieving parallel acceleration of computing tasks; the proposed parallel acceleration framework supports both classic computing kernels and custom computing kernels.
[0013] This invention proposes a parallel acceleration framework design method based on a domestically developed embedded real-time system. The proposed parallel acceleration framework adopts a master-slave architecture and designs and implements host nodes and device nodes to complete the decomposition and computation of computing tasks. Through a custom network transmission protocol and caching system, it realizes the transmission of messages and data within the system, thereby ultimately achieving parallel acceleration of computing tasks.
[0014] The specific process is as follows: Step 1: Design the overall architecture 1) The parallel acceleration framework in this invention adopts a master-slave architecture, consisting of a host and devices. The host is typically a multi-core CPU, while the devices can be one or more CPUs, GPUs, DSPs, or other acceleration devices. The host and devices are also referred to as host nodes and device nodes. The host node is primarily responsible for task scheduling, while the device nodes are primarily responsible for task computation. Nodes interact with each other through specific communication protocols and a node caching system to exchange messages and data. The overall architecture is as follows: Figure 1 As shown.
[0015] 2) In the parallel acceleration framework system of this invention, the host node is started first, followed by the device nodes. After starting, the device nodes first check their current status, and then periodically send status information to the host node, including computation-related information such as node load. Based on the status information of the device nodes, the host node selects a suitable device node and issues a computation task. Upon receiving the computation task, the device node immediately calls the corresponding function to process it. After the computation is completed, the device node returns the computation result to the host node, which then merges and organizes the computation results from different device nodes.
[0016] Step 2: Design the host node 1) Task scheduling is a core function of the host node. Host node task scheduling specifically includes two processes: task partitioning and task mapping. Task partitioning is the process of breaking down a task into several smaller, independently executable subtasks based on task characteristics or data characteristics. Task mapping refers to the process of scheduling the partitioned subtasks onto device nodes.
[0017] 2) In the task partitioning phase, the host node breaks down the computational task based on the device node information within the current system. Taking general matrix operations in linear algebra as an example, the host node can break down the matrix to be computed into several smaller matrices based on the number of device nodes. In the task mapping phase, the host node maps the smaller matrices obtained in the previous phase to the corresponding device nodes based on the status information of the system device nodes, such as whether the nodes are available. Table 1 lists the main functions designed for the task scheduling function.
[0018] Table 1 List of Task Scheduling Functions
[0019] Step 3: Design Equipment Nodes 1) The core responsibility of a device node is to execute computational tasks. The specific computational tasks that can be executed are predefined by the proposed parallel acceleration framework. This framework provides users with two types of computational tasks, also known as two types of computational kernels: classic computational kernels and custom computational kernels. Classical computational kernels refer to computational operations frequently used in various computing applications, such as convolution and Fourier transform operations. Custom computational kernels refer to computational operations that classic kernels cannot directly satisfy, requiring users to implement them from scratch based on their specific application needs.
[0020] 2) For classic computing kernels, a BLAS library is established, allowing users to directly call the corresponding computing kernels to complete computational tasks. For custom computing kernels, the proposed parallel acceleration framework provides an environment for users to add custom computing kernels. After writing the function for the custom computing kernel, the user calls the proposed parallel acceleration framework's computing kernel addition interface to add the custom computing kernel to the list of executable computing kernels on the device node. After startup, the device node will periodically send status information, including the list of executable computing kernels, to the host node.
[0021] Step 4: Design the communication protocol To better suit small cluster environments, the proposed parallel acceleration framework specifically implements a network communication protocol. Nodes transmit information and data through this customized network communication protocol. The customized network communication protocol defines a communication protocol format, which consists of a protocol header and protocol content, as shown below. Figure 2 As shown in Tables 2 and 3, the protocol header defines the protocol type and status type based on the different data types transmitted and the different stages of task execution. The protocol content mainly includes four different types of data: computation task data packets, computation result data packets, device node heartbeat messages, and host node heartbeat messages. The data packet format is as follows: Figure 3 As shown.
[0022] Table 2 Protocol Type Table 1. task_type_data_len 0b00000001<<0 Data length type 2. task_type_part_packet 0b00000001<<1 Packet type data packet 3. task_type_compute_task 0b00000001<<2 Computational task types 4. task_type_compute_task_result 0b00000001<<3 Calculation task result types 5. task_type_compute_task_result_ack 0b00000001<<4 Result type accepted. 6. task_type_memory_communicate_compute_task 0b00000001<<5 Memory communication computing tasks 7. task_type_client_info 0b00000001<<6 Server information 8. task_type_server_info 0b00000001<<7 Client Information 9. task_type_client_config 0b00000001<<8 Client configuration package 10. task_type_client_msg 0b00000001<<9 Client messages 11. task_type_enum_max 0b00000001<<10 Task type ended Table 3 Status Type Table 1. TASK_STATUS_CREATED 0 Task created 2. TASK_STATUS_STARTED 1 Task sent, received, pending calculation 3. TASK_STATUS_FINISHED 2 Calculation completed 4. TASK_STATUS_SENDING_RESULT 3 Calculation complete, sending results. 5. TASK_STATUS_SENT 4 Sending computation task 6. TASK_STATUS_ACK 5 Task received, calculation completed. 7. TASK_STATUS_RESEND 6 The task needs to be resent. 8. TASK_STATUS_COMPUTING 7 The task is being calculated. 9. TASK_STATUS_COMPUTED 8 Task calculation complete 10. TASK_STATUS_COMPUTE_FAILED 9 Task calculation failed 11. TASK_STATUS_UNDEFINED 10 Task status undefined Step 5: Design the caching system The caching system can be considered the core hub of the proposed parallel acceleration framework, undertaking the crucial function of message relay. The implementation of functions such as task scheduling, computation result return, and device node status monitoring all rely on the caching system. The parallel acceleration framework incorporates a caching system on each node. When scheduling tasks, the host node first places the task allocation information in the caching system and then transmits the information to the device node's caching system via a communication protocol. The device node retrieves the information from its caching system, completes the computation, writes the result back to its caching system, and then returns the computation result to the host node via the communication protocol. Furthermore, the device node also writes its status information to the caching system for the host node to check and analyze. Therefore, the reliability and performance of the caching system are paramount. To ensure high reliability and high-speed real-time processing, the caching system design utilizes a self-developed embedded real-time database. The proposed parallel acceleration framework uses this self-developed embedded real-time database as a high-speed in-memory database to guarantee efficient data query and write operations.
[0023] Example 1 To verify the effectiveness of this invention, Example 1 was conducted on a domestically produced processor, the configuration of which is shown in Table 4. The experiment used general matrix multiplication, frequently used in parallel computing research and practical tasks, as the test method. First, the correctness of the calculation results was verified using the parallel acceleration framework. Then, it was compared with an implementation using only a self-developed operating system without the parallel acceleration framework. By comparing the computation time of the two implementations, it was demonstrated whether the parallel acceleration framework has a computational acceleration effect on the domestically produced embedded platform.
[0024] Table 4 Configuration of Domestic Processors Phytium 2000+ It has 64 FTC662 computing cores, is compatible with the ARMv8 instruction set, and has a main frequency of 1.8-2.2GHz. host node Phytium D2000 It features 8 FTC663 processor cores, is compatible with the ARMv8 instruction set, and has a maximum clock speed of 2.3GHz. Device Node The domestically produced hardware platform used in Example 1, excluding special-function boards, can be configured with a maximum of five processor boards in actual operation. Therefore, Example 1 uses a total of five domestically produced processors, which are connected to each other via a network cable to form a cluster system. The parallel acceleration framework host node runs on Phytium 2000+, and the device nodes run on Phytium D2000. The nodes exchange data and information through network communication protocols.
[0025] Example 1 uses matrix multiplication to evaluate the performance of the proposed parallel acceleration framework. By setting different numbers of nodes and matrix sizes, the performance and scalability of the proposed parallel acceleration framework are fully verified. The experimental parameters are set according to common settings in embedded environments in actual work scenarios to simulate real-world task scenarios. The matrix data in the experiment is of type double. The experiment uses shell commands to control the initialization of nodes, setting the number of nodes, and executing test cases. To verify the correctness of the calculation results of the proposed parallel acceleration framework, the experiment manually compares whether the calculation results of the proposed parallel acceleration framework are consistent with those of not using the proposed parallel acceleration framework. If they are consistent, the calculation of the proposed parallel acceleration framework is considered to be error-free; otherwise, the calculation results of the proposed parallel acceleration framework are considered questionable and require further analysis. To collect information such as the system running and calculation time of the proposed parallel acceleration framework, timestamps are added to the test cases to detect the time consumed by task partitioning, task mapping, task calculation, and calculation result integration. To ensure the reliability of the collected data, the experiment executes the test for each setting five times and takes the average of the recorded times as the experimental data.
[0026] In analyzing the experimental results, we first manually compared the consistency of the computation results of the test cases using the proposed parallel acceleration framework with those not using it under various settings. The results showed that the computation results were the same for both, therefore, the computation results of the proposed parallel acceleration framework are considered correct. The experimental results will be analyzed in detail below.
[0027] Table 5 lists the complete test records for various configurations under multi-machine, multi-core conditions. The number of device nodes in the table refers to the actual number of device nodes participating in the computation. Computation time refers to the total time spent executing the task, i.e., the time spent by the host node from task partitioning to the completion of integrating the computation results from the device nodes. Task splitting time refers to the time spent by the host node splitting data according to the number of device nodes. Task transmission time refers to the sum of the time spent by the host node from creating the task package to all device nodes receiving the task, the time spent transmitting the computation results back to the host after the task computation is completed, and the time spent by the host aggregating the computation results. Task computation time is the time spent by the device nodes executing the task computation. When the number of device nodes is 1, it indicates that the computation was not accelerated using the proposed parallel acceleration framework.
[0028] Table 5 Performance Test Results
[0029] Experimental results show that the proposed parallel acceleration framework can significantly accelerate computation for the two matrix sizes commonly used in practical work, and the experimental results of the accelerated computation all meet the real-time requirements of practical work tasks.
[0030] The parallel acceleration framework proposed in this invention adopts a master-slave architecture and designs and implements host nodes and device nodes to complete the decomposition and computation of computing tasks. Through a custom network transmission protocol and caching system, the transmission of messages and data in the system is realized, thereby ultimately achieving parallel acceleration of computing tasks.
[0031] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A design method for a parallel acceleration framework for domestically produced embedded real-time systems, characterized in that, The method includes: Step 1: Design the overall architecture The parallel acceleration framework adopts a master-slave architecture, consisting of a host and devices. The host is a multi-core CPU, and the devices are one or more CPUs, GPUs, DSPs, or other acceleration devices. The host and devices are also referred to as host nodes and device nodes. The host node is responsible for task scheduling, and the device node is responsible for task computation. The nodes interact with each other through specific communication protocols and node caching systems to exchange messages and data. Step 2: Design the host node Task scheduling on a host node specifically includes two processes: task partitioning and task mapping. Task partitioning is the process of breaking down a task into several smaller, independently executable subtasks based on task characteristics or data characteristics. Task mapping refers to the process of scheduling the subtasks obtained from the partitioning to device nodes. Step 3: Design Equipment Nodes The core responsibility of a device node is to execute computing tasks. The computing tasks that can be executed are predefined by the proposed parallel acceleration framework. The parallel acceleration framework provides users with two types of computing tasks, also known as two types of computing kernels: classic computing kernels and custom computing kernels. Step 4: Design the communication protocol Nodes transmit information and data through a customized network communication protocol; the customized network communication protocol defines the communication protocol format, which consists of a protocol header and protocol content; Step 5: Design the caching system The caching system is used for message relay between nodes; the implementation of task scheduling, calculation result return, and device node status monitoring all rely on the caching system. The parallel acceleration framework has designed a caching system on each node.
2. The parallel acceleration framework design method for domestically produced embedded real-time systems as described in claim 1, characterized in that, In step one, when the parallel acceleration framework system is running, it first starts the host node and then starts the device nodes. After the device nodes start, they first check their current status and then periodically send status information to the host node, which includes computation-related information. The host node selects a suitable device node based on the status information of the device nodes and publishes the computation task. After receiving the computation task, the device node immediately calls the corresponding function to process it. After the computation is completed, the device node returns the computation result to the host node, which then merges and organizes the computation results from different device nodes.
3. The parallel acceleration framework design method for domestically produced embedded real-time systems as described in claim 1, characterized in that, In step two, during the task partitioning phase, the host node will split the computation task according to the device node information in the current system; for general matrix operations in linear algebra, the host node will decompose the matrix to be calculated into several smaller matrices according to the number of device nodes; in the task mapping phase, the host node will map the smaller matrices to the corresponding device nodes according to the status information of the system device nodes.
4. The parallel acceleration framework design method for domestically produced embedded real-time systems as described in claim 1, characterized in that, In step three, the classical computing kernel refers to the computing operations frequently used in various computing applications, including convolution operations and Fourier transform operations.
5. The parallel acceleration framework design method for domestically produced embedded real-time systems as described in claim 1, characterized in that, In step three, a custom computing kernel refers to computing operations that cannot be directly satisfied by the classic computing kernel and that users need to implement from scratch according to their actual application requirements.
6. The parallel acceleration framework design method for domestically produced embedded real-time systems as described in claim 5, characterized in that, In step three, a BLAS library is established for classic computing kernels, allowing users to directly call the corresponding computing kernels to complete computing tasks. For custom computing kernels, the parallel acceleration framework provides an environment for users to add custom computing kernels. After writing the function for the custom computing kernel, the user calls the proposed parallel acceleration framework's computing kernel addition interface to add the custom computing kernel to the list of executable computing kernels on the device node. After the device node starts up, it will periodically send status information, including the list of executable computing kernels, to the host node.
7. The parallel acceleration framework design method for domestically produced embedded real-time systems as described in claim 1, characterized in that, In step four, the protocol header defines the protocol type and status type content according to the different data types transmitted and the different stages of task execution. The protocol types include: data length type, packet type data packet, calculation task type, calculation task result type, result type acceptance confirmation, memory communication calculation task, server information, client information, client configuration packet, client message, and task type end. The status types include: task created, task sent and received pending calculation, calculation completed, calculation completed, sending calculation result, sending calculation task, task received and completed, task needs to be resent, task is being calculated, task calculation completed, task calculation failed, and task status undefined.
8. The parallel acceleration framework design method for domestically produced embedded real-time systems as described in claim 7, characterized in that, In step four, the protocol content includes four different types of data: calculation task data packet, calculation result data packet, device node heartbeat message, and host node heartbeat message.
9. The parallel acceleration framework design method for domestically produced embedded real-time systems as described in claim 1, characterized in that, In step five, when scheduling tasks, the host node first places the task allocation information in the cache system, and then transmits the information to the device node's cache system through the communication protocol. The device node retrieves the information from its cache system, completes the calculation, writes the result into its cache system, and then returns the calculation result to the host node through the communication protocol. In addition, the device node also writes the node's status information into the cache system for the host node to check and analyze.
10. The parallel acceleration framework design method for domestically produced embedded real-time systems as described in claim 9, characterized in that, The caching system uses an embedded real-time database, and the parallel acceleration framework uses the embedded real-time database as a high-speed in-memory database to ensure efficient data query and write operations.