System on chip based on risc-v architecture and packaged chip

Abstract

The application provides an on-chip system based on a RISC-V architecture and a packaged chip. The on-chip system comprises: an interconnection interface, which establishes an inter-grain communication link with at least one remote grain and transmits and receives inter-grain data packets; a protocol conversion bridge, which is used for bidirectional protocol conversion between the inter-grain data packets and AXI bus transactions; an AXI on-chip bus, which is used for carrying AXI bus transactions and arbitrating and forwarding access requests from different access initiators; a RISC-V processor, which is used for configuring a protocol conversion bridge and a PCIe base address register mapping relationship and can initiate an access request to a remote grain; and a PCIe interface module, which is used for converting a PCIe side access request into an AXI bus transaction or converting an AXI access request from the AXI on-chip bus into a PCIe transaction. By using the above technical solution, the compatibility, expansibility and data transmission efficiency of the on-chip system can be improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a system-on-a-chip and its packaged chip based on the RISC-V architecture. Background Technology

[0002] As Moore's Law approaches its physical limits, traditional system-on-a-chip (SoC) solutions suffer from numerous problems, including high manufacturing costs, long iteration cycles, poor versatility, and low yields. Chiplet heterogeneous integration technology has become the mainstream development direction for high-end integrated circuits.

[0003] Among them, the chip-particle heterogeneous integration technology is to design and fabricate bare dies with different functions and processes separately, and then integrate them into the same package through advanced packaging technology, which has the advantages of high performance, low cost and high flexibility.

[0004] However, the inter-chip interconnect protocol is incompatible with the local on-chip bus protocol.

[0005] The information disclosed in the background section is only intended to enhance the understanding of the background of this application, and therefore may contain information that is not part of the prior art known to those skilled in the art. Summary of the Invention

[0006] This application provides a RISC-V-based system-on-a-chip and its packaged chip, which can improve the compatibility, scalability, and data transmission efficiency of the system-on-a-chip.

[0007] A first aspect of this application provides a system-on-a-chip based on a RISC-V architecture, comprising: Interconnection interface, establishes inter-core communication link with at least one remote core, and sends and receives inter-core data packets; A protocol conversion bridge, connected to the interconnection interface, is used to perform bidirectional protocol conversion between inter-core data packets and AXI bus transactions; The AXI on-chip bus, connected to the protocol conversion bridge, is used to carry the AXI bus transactions and to arbitrate and forward access requests from different access initiators. The RISC-V processor, connected to the AXI on-chip bus, is used to configure the mapping relationship between the protocol conversion bridge and the PCIe base address register, and is able to initiate access requests to the remote chip. The PCIe interface module is connected to the AXI on-chip bus and is used to convert PCIe access requests into AXI bus transactions, or to convert AXI access requests from the AXI on-chip bus into PCIe transactions, so as to realize bidirectional access between the PCIe device and the remote chip.

[0008] Optionally, the protocol conversion bridge is internally configured with a system address mapping table, which includes the correspondence between the global address range and the chip identifier of the remote chip, as well as the correspondence between the global address range and the PCIe base address register mapping space; The protocol conversion bridge is configured as follows: When an AXI access request from the AXI on-chip bus hits the address space of a remote chip, the system address mapping table is looked up according to the address in the AXI access request to determine the chip identifier and remote access address of the target remote chip. The AXI access request is then encapsulated into an inter-chip data packet containing the chip identifier of the target remote chip and sent to the target remote chip via the interconnect interface. When the destination address in the inter-chip data packet from the remote chip falls into the PCIe base address register mapping address window, the inter-chip data packet is converted into an AXI bus transaction and sent to the PCIe interface module via the AXI on-chip bus to access the corresponding PCIe base address register mapping space.

[0009] Optionally, the protocol conversion bridge includes: The protocol parsing unit is used to parse the core identifier, transaction type, inter-core transaction identifier, address, transmission length, and access attributes in the inter-core data packet; The address mapping unit is used to determine the corresponding remote chip access address or PCIe base address register mapping address based on the address in the inter-chip data packet or the address in the AXI bus transaction. The permission verification unit is used to verify the permission of access requests from the remote chip that point to the PCIe base address register mapping space. The management unit is used to maintain the correspondence between the inter-chip transaction identifier and the AXI bus transaction; The transaction generation unit is used to generate an AXI read transaction or an AXI write transaction based on the parsing result of the inter-core data packet. The encapsulation unit is used to generate inter-core request packets or inter-core response packets based on AXI bus transactions or AXI responses. The flow control and error handling unit is used to perform flow control management, timeout management, retransmission management, or error response management on the conversion process between the inter-core data packets and the AXI bus transactions.

[0010] Optionally, when the protocol conversion bridge is configured to convert the AXI bus transaction into the inter-core data packet: Use the write address signal in the AXI write address channel or the read address signal in the AXI read address channel as the address mapping index; The system address mapping table is searched according to the write address signal or the read address signal to obtain the chip identifier of the target remote chip and the remote access address; The management unit establishes the correspondence between the AXI transaction identifier in the AXI bus transaction and the inter-chip transaction identifier. Convert the AXI burst transmission length signal and transmission size signal into the transmission length field in the inter-core data packet; Convert the AXI cache attribute signal into a cache attribute field in the inter-core data packet; Convert the AXI protection attribute signal into the access attribute field in the inter-core data packet; The write data signal and write byte valid signal in the AXI write data channel are encapsulated into the data payload field of the inter-core data packet.

[0011] Optionally, the protocol conversion bridge is configured to convert inter-core packets from the remote core that point to the PCIe base address register mapping space into the AXI bus transaction: The destination address in the inter-core data packet is mapped to an AXI write address signal or an AXI read address signal after address translation. The management unit establishes a correspondence between the inter-chip transaction identifier and the AXI transaction identifier in the AXI bus transaction. The data beat size and burst transmission length of the AXI burst transmission are calculated based on the transmission length in the inter-core data packet, and the AXI transmission size signal and AXI burst transmission length signal are generated. Map the cache attribute fields in the inter-core data packets to AXI cache attribute signals; Map the address pattern field or access attribute field in the inter-core data packet to an AXI protection attribute signal; The write data payload in the inter-core data packet is mapped to the write data signal and write byte valid signal in the AXI write data channel; Furthermore, the protocol conversion bridge calculates the AXI burst transmission parameters based on the transmission length, starting address, AXI data bus width, and the single burst transmission length allowed by the AXI protocol in the inter-core data packet or the AXI bus transaction. When the corresponding data transmission exceeds the AXI single burst transmission length, crosses a preset address boundary, or the starting address is not aligned with the AXI data bus width, the protocol conversion bridge splits an inter-core transaction into multiple AXI burst transactions, or reassembles multiple AXI burst transactions into a single inter-core transaction.

[0012] Optionally, the management unit includes a transaction context table; The transaction context table is used to record at least one of the following: inter-core transaction identifier, AXI transaction identifier, source core identifier, target remote core identifier, transaction type, access address, transmission length, transaction status, retransmission count, sequence number, and retry attribute. The correspondence between the AXI transaction identifier and the inter-core transaction identifier is established through the transaction context table; or, the inter-core transaction identifier is obtained by truncating, expanding, hashing, or reallocating the AXI transaction identifier; or, the AXI transaction identifier is obtained by truncating, expanding, hashing, or reallocating the inter-core transaction identifier.

[0013] Optionally, the flow control and error handling unit includes: The timeout management unit is used to start a timeout counter after establishing the correspondence between inter-chip transactions and AXI transactions in the protocol conversion bridge and issuing the corresponding transaction. If no corresponding response is received within the preset timeout threshold, a timeout error response is generated and the timeout error response is returned to the access initiator or an interrupt is triggered to notify the RISC-V processor. The retransmission management unit is used to re-initiate the corresponding access request based on the retry attribute of the corresponding transaction and the maximum number of retransmissions configured in the software when a timeout error, link verification error or data packet transmission failure occurs, and to return an error response after the maximum number of retransmissions is reached. Before retransmitting a write transaction, the retransmission management unit queries the transaction status, sequence number, or retryable attribute in the transaction context table. When the write transaction has been received by the AXI-side target module and does not have a retryable attribute, the retransmission management unit does not resubmit the write transaction, but instead generates an error response or triggers an interrupt notification to the RISC-V processor.

[0014] Optionally, the flow control and error handling unit includes a flow control management unit, wherein: The flow control management unit includes: The AXI-side flow control processing module is used to perform backpressure control on AXI-side transmission based on the AXI active / ready handshake mechanism. The inter-core flow control credit value management module is used to manage logic for controlling the transmission of inter-core data packets based on available flow control credit values. Specifically, when the available flow control credit value is zero, the transmission of inter-core data packets to the corresponding remote core is suspended; after receiving the flow control credit value returned by the corresponding remote core, the transmission of inter-core data packets is resumed. Furthermore, the inter-core flow control credit value management module is configured to: send the number of data packets that can be received by the local end to the remote core after the link initialization is completed, and receive the number of data packets that can be received by the remote core; decrement the corresponding flow control credit value by one for each inter-core data packet sent; and return a flow control credit value to the remote core after each inter-core data packet from the remote core is processed.

[0015] Optionally, the protocol conversion bridge is configured to convert between inter-chip response error codes and AXI response signals; When the inter-chip response error code is successful, it is mapped to a normal AXI response; When the inter-chip response error code is an address error, it is mapped to the AXI decoding error response; When the inter-core response error code is an authorization error, timeout error, or data verification error, it is mapped to an AXI slave device error response; Furthermore, the protocol conversion bridge is configured to convert AXI's normal response, decoding error response, or device error response into the corresponding inter-chip response error code.

[0016] Optionally, when the interconnection interface connects multiple remote cores, the protocol conversion bridge looks up the system address mapping table according to the address in the AXI access request to obtain the core identifier of the corresponding target remote core, and selects the corresponding inter-core link, inter-core packet encapsulation format, permission policy, cache attribute or flow control parameter based on the core identifier of the target remote core. The protocol conversion bridge also includes a chip capability table; The chip capability table is used to record at least one of the following for different remote chips: protocol type, protocol version, maximum data packet length, data bit width, flow control credit value depth, cache attribute support capability, atomic operation support capability, timeout parameters, and retransmission parameters. The protocol conversion bridge adapts the packet encapsulation format, packet length, access attributes, cache attributes, or flow control parameters between kernels based on the kernel capability table.

[0017] Optionally, the protocol translation bridge is configured to allow the remote chip to actively access the PCIe base address register mapping space; The RISC-V processor is configured to configure the PCIe base address register address mapping relationship and remote chip access permissions in the protocol conversion bridge, so that inter-chip data packets from the remote chip are converted into AXI bus transactions through the protocol conversion bridge after the permission verification is passed, and sent to the PCIe interface module through the AXI on-chip bus, and the PCIe interface module accesses the base address register space of the corresponding PCIe device. The protocol conversion bridge performs permission verification on requests from remote kernels to access the PCIe base address register mapping space. The permission verification includes at least one of the following: verifying whether the source kernel identifier has permission to access the corresponding PCIe base address register mapping address window; verifying whether the access type is an allowed read access, write access, or read-write access; verifying whether the access address falls within the pre-configured PCIe base address register mapping address range; and verifying whether the transaction type is an allowed PCIe mapping transaction. Data transmission between the PCIe device and the remote chip can be completed via the PCIe interface module, the AXI on-chip bus, and the protocol conversion bridge without the RISC-V processor handling the data.

[0018] Optionally, the protocol conversion bridge includes an AXI slave interface, an AXI master interface, an inter-core data packet transceiver interface, a configuration register group, an address comparison unit, and an authorization judgment unit; The AXI slave interface is connected to the AXI on-chip bus and is used to receive AXI access requests initiated by the RISC-V processor via the AXI on-chip bus, or to receive AXI access requests sent via the AXI on-chip bus after the PCIe side access request is converted by the PCIe interface module. The inter-core data packet transceiver interface is connected to the interconnection interface and is used to send inter-core data packets to or receive inter-core data packets from remote cores. The AXI master interface is connected to the AXI on-chip bus and is used to initiate AXI read transactions or AXI write transactions to the PCIe interface module after the data packets from the remote chip are converted into AXI bus transactions. The configuration register group can be configured by the RISC-V processor via the AXI on-chip bus. The configuration register group is used to store at least a portion of the entries of the system address mapping table, and includes at least a remote chip address window register, a PCIe base address register mapping window register, and a remote chip access permission register. The address comparison unit is used to compare the address in the AXI access request with the address range in the remote kernel address window register, and when the comparison result shows that the AXI access request hits the remote kernel address space, it triggers the protocol conversion bridge to encapsulate the AXI access request into an inter-kernel data packet. The address comparison unit is also used to compare the destination address in the inter-chip data packet from the remote chip with the address range in the PCIe base address register mapping window register, and when the comparison result shows that the destination address hits the PCIe base address register mapping space, the permission judgment unit determines whether the remote chip has access rights according to the remote chip access permission register. When the remote core has access rights, the protocol conversion bridge converts the inter-core data packets into AXI read transactions or AXI write transactions, and sends them to the PCIe interface module through the AXI master interface.

[0019] A second aspect of this application provides a packaged chip, comprising: At least one distal core; The RISC-V-based system-on-a-chip as described in any of the foregoing embodiments is connected to the remote chip. The PCIe device is connected to the RISC-V-based system-on-a-chip.

[0020] Compared with the prior art, the technical solution of this application embodiment has the following beneficial effects: In the RISC-V architecture-based on-chip system provided in this application embodiment, the protocol conversion bridge is located between the AXI on-chip bus and the interconnect interface. It can convert inter-chip data packets from remote chips into AXI bus transactions, and AXI-side access requests can also be converted into inter-chip data packets. Furthermore, the protocol conversion bridge, the RISC-V processor, and the PCIe interface module form a unified interconnect path through the AXI on-chip bus. In this way, PCIe devices do not need to directly support the inter-chip interconnect protocol, and remote chips do not need to directly support the PCIe protocol to achieve bidirectional access between PCIe peripherals and remote chips, thereby improving the compatibility and peripheral expansion capabilities of heterogeneous chip systems. Moreover, since the RISC-V processor can configure the mapping relationship between the protocol conversion bridge and the PCIe base address register, data access between PCIe peripherals and remote chips can be completed through the PCIe interface module, the AXI on-chip bus, and the protocol conversion bridge. Therefore, the need for the RISC-V processor to participate in data transfer can be reduced, improving system data transmission efficiency. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of a system-on-a-chip based on the RISC-V architecture provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a protocol conversion bridge provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a packaged chip provided in an embodiment of this application. Detailed Implementation

[0022] As described in the background section, the chip interconnect protocol is incompatible with the local on-chip bus protocol.

[0023] Specifically, mainstream D2D (Die-to-Die) interconnect interfaces mostly adopt dedicated high-speed serial protocols or dedicated interconnect standards such as UCIe and ACC1.0. Their data frame format, transmission timing, and handshake logic are quite different from the AXI on-chip bus protocol commonly used in traditional SoCs, and they cannot directly connect to local CPUs, high-speed peripherals, and other IP cores.

[0024] For example, the D2D protocol is a packet-based transmission mode that encapsulates data into individual packets containing routing information. AXI, on the other hand, is an address-based read-write transaction transmission mode. Both have an address field, but AXI selects the destination slave based on the address field, while D2D selects the destination slave based on the Die ID (granular identification information).

[0025] Meanwhile, traditional chip-to-chip interconnect architecture suffers from low integration and poor scalability.

[0026] For example, most solutions only achieve point-to-point data transmission between chips, and cannot integrate remote chip resources, local RISC-V, and PCIe high-speed peripherals into a unified bus architecture, resulting in complex system scheduling and high data transmission latency, making it difficult to meet the needs of edge computing and high-speed data transmission scenarios.

[0027] In short, existing solutions lack an integrated Chiplet interconnect architecture that can seamlessly convert the D2D chiplet interconnect protocol to the AXI bus protocol and is compatible with heterogeneous CPUs and high-speed PCIe peripherals.

[0028] To address the aforementioned technical problems, this application provides a system-on-a-chip (SoC) based on a RISC-V architecture. A protocol conversion bridge is located between the AXI on-chip bus and the interconnect interface, enabling the conversion of inter-chip data packets from remote chips into AXI bus transactions. Access requests from the AXI side can also be converted into inter-chip data packets via the same bridge. Furthermore, the protocol conversion bridge, the RISC-V processor, and the PCIe interface module form a unified interconnect path through the AXI on-chip bus. This eliminates the need for PCIe devices to directly support inter-chip interconnect protocols, and remote chips do not need to directly support the PCIe protocol, thus enabling bidirectional access between PCIe peripherals and remote chips, thereby improving the compatibility and peripheral expansion capabilities of heterogeneous chip systems. Moreover, since the RISC-V processor can configure the mapping relationship between the protocol conversion bridge and the PCIe base address register, data access between PCIe peripherals and remote chips can be completed via the PCIe interface module, the AXI on-chip bus, and the protocol conversion bridge. This reduces the need for the RISC-V processor to participate in data transfer, improving system data transmission efficiency.

[0029] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0030] In this embodiment of the application, the remote chip refers to a chip that is connected to the system on-chip via a D2D interface and interacts with the system on-chip for data exchange.

[0031] See Figure 1 , Figure 1 This is a schematic diagram of a RISC-V-based system-on-a-chip (SoC) according to an embodiment of this application. The RISC-V-based SoC 100 may include: Interconnection interface 110 establishes an inter-core communication link with at least one remote core and sends and receives inter-core data packets; Protocol conversion bridge 120, connected to interconnect interface 110, is used for bidirectional protocol conversion between inter-core data packets and AXI bus transactions; The AXI on-chip bus 130, connected to the protocol conversion bridge 120, is used to carry AXI bus transactions and to arbitrate and forward access requests from different access initiators. The RISC-V processor 140 is connected to the AXI on-chip bus 130 and is used to configure the mapping relationship between the protocol conversion bridge 120 and the PCIe base address register, and is able to initiate access requests to remote chips. The PCIe interface module 150 is connected to the AXI on-chip bus 130 and is used to convert PCIe-side access requests into AXI bus transactions, or to convert AXI access requests from the AXI on-chip bus into PCIe transactions, so as to realize bidirectional access between PCIe devices and remote chips.

[0032] Specifically, the interconnect interface 110 can be used to establish an inter-core communication link with at least one remote core and to send and receive inter-core data packets between the local system and the remote core.

[0033] The interconnect interface 110 can perform functions such as link initialization, data packet sending, data packet receiving, link status detection, link verification, and flow control management.

[0034] In this embodiment, the interconnect interface 110 includes a Die-to-Die interface.

[0035] Protocol conversion bridge 120 is used for bidirectional protocol conversion between inter-chip data packets and AXI bus transactions. In other words, the protocol conversion bridge can convert AXI access requests from the AXI on-chip bus into inter-chip data packets suitable for inter-chip transmission, and it can also convert inter-chip data packets from remote chips into AXI bus transactions. Thus, the AXI on-chip bus can arbitrate and forward requests from different initiators based on the address, access type, or preset arbitration policy of the access request.

[0036] In this embodiment, the protocol conversion bridge 120 may include a Die2AXI bridge.

[0037] In some embodiments, the RISC-V processor can be connected to the AXI on-chip bus as an AXI master device. The RISC-V processor can be used to configure the protocol conversion bridge, configure the PCIe base address register mapping, and initiate access requests to remote chips.

[0038] For example, RISC-V processors can configure address mappings, access permissions, timeout thresholds, retransmission thresholds, and flow control parameters during system initialization.

[0039] The PCIe interface module is used to connect PCIe devices. PCIe devices can access remote chips via the PCIe interface module, AXI on-chip bus, and protocol conversion bridge; remote chips can also access the base address register space of PCIe devices via the protocol conversion bridge, AXI on-chip bus, and PCIe interface module.

[0040] By adopting the above structure, the embodiments of this disclosure can realize bidirectional access between PCIe peripherals and remote chips without requiring PCIe peripherals to directly support the inter-chip interconnection protocol or remote chips to directly support the PCIe protocol, thereby improving the compatibility and scalability of heterogeneous chip systems.

[0041] In some embodiments, the PCIe interface module includes a transaction layer, a data link layer, a physical layer, and a PCIe to AXI protocol conversion bridge.

[0042] The transaction layer is used to process PCIe transaction layer packets; the data link layer is used for link reliability control, cyclic redundancy check, retransmission and flow control; the physical layer is used for physical layer signal transmission, serial-to-parallel conversion, clock recovery and link training; the PCIe to AXI protocol conversion bridge is used to perform protocol conversion between PCIe transactions and AXI transactions.

[0043] Accordingly, the PCIe interface module is configured to receive direct memory access read requests or direct memory access write requests initiated by PCIe devices, and convert the direct memory access read requests or direct memory access write requests into AXI bus transactions before sending them to the AXI on-chip bus; when an AXI bus transaction hits the address space of a remote chip, the AXI bus transaction is converted into an inter-chip data packet via a protocol conversion bridge before accessing the remote chip.

[0044] In one example, a direct memory access read request or a direct memory access write request is a DMA read request or a DMA write request.

[0045] In some embodiments, the protocol conversion bridge is internally configured with a system address mapping table, which includes the correspondence between the global address range and the chip identifier of the remote chip, as well as the correspondence between the global address range and the PCIe base address register mapping space.

[0046] The system address mapping table includes at least one of the following fields: global address start address, global address end address or address window length, target remote kernel kernel kernel identifier, remote address offset, PCIe base address register mapping address information, access permissions, cache attributes, access attributes, address mode, remote kernel kernel type, inter-kernel link identifier, maximum transmission length, and flow control parameters.

[0047] In this scenario, the protocol conversion bridge is configured as follows: when an AXI access request from the AXI on-chip bus hits the address space of a remote chip, the system address mapping table is looked up based on the address in the AXI access request to determine the chip identifier and remote access address of the target remote chip. The AXI access request is then encapsulated into an inter-chip data packet containing the chip identifier of the target remote chip and sent to the target remote chip via the interconnect interface. When the destination address in the inter-chip data packet from the remote chip falls into the PCIe base address register mapping address window, the inter-chip data packet is converted into an AXI bus transaction and sent to the PCIe interface module via the AXI on-chip bus to access the corresponding PCIe base address register mapping space.

[0048] Specifically, the protocol translation bridge can be configured with a system address mapping table. The system address mapping table can be used to describe the affiliation of different address ranges in the global address space.

[0049] When an AXI access request from the AXI on-chip bus hits the address space of a remote chip, the interconnect interface can send the inter-chip data packet to the corresponding remote chip.

[0050] When the destination address in an inter-chip packet from a remote chip falls into the PCIe base address register mapped address window, the remote chip accesses the base address register space of the corresponding PCIe device.

[0051] In some examples, the RISC-V processor can configure the system address mapping table during system startup. For instance, the first address window can be configured as the access address space of the first remote die, the second address window as the access address space of the second remote die, and the third address window as the PCIe base address register mapping space.

[0052] Therefore, by configuring the system address mapping table, both core paths—AXI-side access to the remote chip and remote chip access to the PCIe base address register mapping space—can be implemented through a unified address mapping mechanism, thereby reducing the addressing complexity between different protocol domains and improving the determinism of access paths and system scalability.

[0053] See Figure 2 , Figure 2 This is a schematic diagram of a protocol conversion bridge provided in an embodiment of this application. The protocol conversion bridge 120 may include: The protocol parsing unit 121 is used to parse the kernel identifier, transaction type, inter-kernel transaction identifier, address, transmission length and access attributes in the inter-kernel data packets; Address mapping unit 122 is used to determine the corresponding remote chip access address or PCIe base address register mapping address based on the address in the inter-chip data packet or the address in the AXI bus transaction. The permission verification unit 123 is used to verify the permission of access requests from remote chips that point to the PCIe base address register mapping space. Management unit 124 is used to maintain the correspondence between the inter-chip transaction identifier and the AXI bus transaction; The transaction generation unit 125 is used to generate AXI read transactions or AXI write transactions based on the parsing results of inter-core data packets. Encapsulation unit 126 is used to generate inter-core request packets or inter-core response packets based on AXI bus transactions or AXI responses; The flow control and error handling unit 127 is used to perform flow control management, timeout management, retransmission management, or error response management on the conversion process between inter-core data packets and AXI bus transactions.

[0054] Specifically, the protocol parsing unit 121 performs parsing processing, which can determine the core identifier, transaction type, inter-core transaction identifier, address, transmission length, and access attributes in the inter-core data packet.

[0055] The kernel identifier can include the kernel identifier of the source kernel and the kernel identifier of the target remote kernel, and the transaction type can include read request, write request, read response, write response or error response, etc.

[0056] In this way, the address mapping unit 122 can determine the corresponding remote chip access address or PCIe base address register mapping address.

[0057] For example, when the address of an AXI access request hits the address space of a remote kernel, the address mapping unit 122 can determine the kernel identifier and remote access address of the target remote kernel; when the destination address of an inter-kernel data packet hits the PCIe base address register mapping address window, the address mapping unit 122 can determine the corresponding PCIe base address register mapping address.

[0058] After the corresponding address information is matched, the permission verification unit 123 can perform a permission verification operation. Through permission verification, unauthorized remote chips can be prevented from accessing the base address register space of the PCIe device.

[0059] The management unit 124 can record the mapping relationship between the inter-core transaction identifier and the AXI transaction identifier so that the response can be accurately returned to the corresponding access initiator when the response is returned.

[0060] Through the cooperation between the transaction generation unit 125 and the encapsulation unit 126, inter-core request packets or inter-core response packets can be generated.

[0061] During this process, the flow control and error handling unit 127 can be used to perform flow control management, timeout management, retransmission management, and error response management.

[0062] By adopting the above scheme and dividing the protocol conversion bridge into the aforementioned functional units, the conversion process between the inter-core protocol and the AXI protocol can be made clearer, thereby improving the security, reliability, and maintainability of the cross-protocol access process.

[0063] As an example, after the protocol conversion bridge receives inter-core data packets from a remote core, the protocol parsing unit parses the source core identifier, destination address, transaction type, inter-core transaction identifier, transmission length, and access attributes in the inter-core data packets.

[0064] The address mapping unit determines whether the destination address falls within the PCIe base address register mapping address window based on the destination address, and the permission verification unit performs permission verification based on the source core identifier, destination address, and access type.

[0065] After the permission verification is passed, the transaction generation unit converts the inter-chip data packets into AXI read transactions or AXI write transactions to access the PCIe base address register mapping space through the AXI on-chip bus.

[0066] In one example, the permission verification unit performs verification based on at least one of the following: source chip identifier, access address, access type, address mode, and access permission table. If the verification fails, it prevents the access request from entering the AXI on-chip bus or generates a permission error response to return to the remote chip.

[0067] In some embodiments, the management unit includes a transaction context table, which records at least one of the following: inter-core transaction identifier, AXI transaction identifier, source core identifier, target remote core identifier, transaction type, access address, transmission length, transaction status, retransmission count, sequence number, and retryable attribute.

[0068] Specifically, since AXI bus transactions and inter-core packets may use different inter-core transaction identifier bit widths, transaction sorting rules, and response return methods, it is necessary to maintain the correspondence between the two during protocol conversion. A transaction context table can be used to record the inter-core transaction identifiers before and after conversion, enabling the protocol conversion bridge to determine the original request corresponding to the received response.

[0069] Correspondingly, the correspondence between AXI transaction identifiers and inter-granular transaction identifiers is established through a transaction context table; or, inter-granular transaction identifiers are obtained by truncating, extending, hashing, or reallocating AXI transaction identifiers; or, AXI transaction identifiers are obtained by truncating, extending, hashing, or reallocating inter-granular transaction identifiers.

[0070] By employing the above scheme, the protocol translation bridge can support concurrent processing of multiple incomplete transactions through a transaction context table, and avoid transaction mismatches when responses are returned. Furthermore, by recording transaction status, retransmission count, sequence number, and retryability attributes, it can also provide a basis for timeout handling, retransmission control, and duplicate transaction identification, thereby improving the reliability of cross-protocol transaction processing.

[0071] In some embodiments, the flow control and error handling unit includes: The timeout management unit is used to start the timeout counter after establishing the correspondence between inter-chip transactions and AXI transactions in the protocol conversion bridge and issuing the corresponding transaction. If no corresponding response is received within the preset timeout threshold, a timeout error response is generated and returned to the access initiator or an interrupt is triggered to notify the RISC-V processor. The retransmission management unit is used to re-initiate the corresponding access request based on the retry attribute of the corresponding transaction and the maximum number of retransmissions configured in the software when a timeout error, link verification error or data packet transmission failure occurs, and to return an error response after the maximum number of retransmissions is reached. Before retransmitting a write transaction, the retransmission management unit queries the transaction status, sequence number, or retryable attribute in the transaction context table. When a write transaction has been received by the target module on the AXI side and does not have a retryable attribute, the retransmission management unit does not resubmit the write transaction, but instead generates an error response or triggers an interrupt notification to the RISC-V processor.

[0072] Specifically, the timeout management unit can start the timeout counter after establishing the correspondence between inter-core transactions and AXI transactions and issuing the corresponding transactions at the protocol conversion bridge.

[0073] If a corresponding response is received within the preset timeout threshold, the timeout management unit can stop counting.

[0074] If no corresponding response is received within the preset timeout threshold, the timeout management unit can generate a timeout error response and return the timeout error response to the access initiator, or trigger an interrupt notification to the RISC-V processor.

[0075] Accordingly, when a timeout error, link verification error, or data packet transmission failure occurs, the retransmission management unit can re-initiate the corresponding access request based on the retry attribute of the corresponding transaction and the maximum number of retransmissions configured in the software. When the maximum number of retransmissions is reached, the retransmission management unit can return an error response.

[0076] Furthermore, not all transactions are suitable for retransmission. For example, for a write transaction that has already been received by the target module on the AXI side, if it does not have a retryable attribute, resubmitting the write transaction may cause the target device to repeatedly execute the write operation. To avoid this situation, the retransmission management unit can query the transaction status, sequence number, or retryable attribute in the transaction context table before retransmitting the write transaction.

[0077] If a write transaction has been received by the target module on the AXI side and does not have a retry attribute, the retransmission management unit may not resubmit the write transaction, but instead generate an error response or trigger an interrupt notification to the RISC-V processor.

[0078] By configuring timeout management and retransmission management units, the recovery capability in scenarios of link transmission failure can be improved. Furthermore, it can prevent some write operations from being executed repeatedly, improving the security of system anomaly handling.

[0079] In some embodiments, the flow control and error handling unit includes a flow control management unit. The flow control management unit includes: an AXI-side flow control processing module, used for backpressure control of AXI-side transmission based on the AXI active / ready handshake mechanism; and an inter-core flow control credit value management module, used for management logic to control the transmission of inter-core data packets based on available flow control credit values.

[0080] Specifically, when the available flow control credit value is zero, the transmission of inter-core data packets to the corresponding remote core is suspended; after receiving the flow control credit value returned by the corresponding remote core, the transmission of inter-core data packets is resumed.

[0081] Furthermore, the flow control credit value management module between core particles is configured to: send the number of data packets that can be received by the local end to the remote core particle after the link initialization is completed, and receive the number of data packets that can be received by the remote core particle; decrement the corresponding flow control credit value by one for each data packet sent between core particles; and return a flow control credit value to the remote core particle after processing each data packet between core particles from the remote core particle.

[0082] Specifically, when the target module on the AXI side is temporarily unable to receive requests or data, it can apply back pressure through a ready signal to cause the protocol conversion bridge to suspend or delay sending AXI transactions.

[0083] The inter-core flow control credit value management module can control the transmission of inter-core data packets based on the available flow control credit value. The flow control credit value represents the number of data packets that the peer can currently receive. When the available flow control credit value is zero, the protocol conversion bridge can suspend the transmission of inter-core data packets to the corresponding remote core; when it receives the flow control credit value returned by the corresponding remote core, the protocol conversion bridge can resume the transmission of inter-core data packets.

[0084] Specifically, the flow control credit value management module decrements the corresponding flow control credit value by one for each inter-core data packet it sends; and returns a flow control credit value to the remote core after processing each inter-core data packet from the remote core.

[0085] By combining the AXI-side active / ready handshake mechanism and the inter-core flow control credit value mechanism, the protocol conversion bridge can achieve transmission rhythm matching between different protocol domains, avoiding buffer overflow, request loss, or link congestion.

[0086] In some embodiments, the protocol conversion bridge has different processing logic based on different conversion directions.

[0087] Example 1: The protocol conversion bridge converts AXI bus transactions into inter-core data packets.

[0088] Specifically, when the protocol conversion bridge is configured to convert AXI bus transactions into inter-core data packets: it uses the write address signal in the AXI write address channel or the read address signal in the AXI read address channel as an address mapping index; it looks up the system address mapping table based on the write address signal or the read address signal to obtain the core identifier and remote access address of the target remote core; it establishes the correspondence between the AXI transaction identifier in the AXI bus transaction and the inter-core transaction identifier through the management unit; it converts the AXI burst transmission length signal and transmission size signal into the transmission length field in the inter-core data packet; it converts the AXI cache attribute signal into the cache attribute field in the inter-core data packet; it converts the AXI protection attribute signal into the access attribute field in the inter-core data packet; and it encapsulates the write data signal and write byte valid signal in the AXI write data channel into the data payload field of the inter-core data packet.

[0089] The write address signal includes AWADDR, the read address signal includes ARADDR, the AXI burst transfer length signal includes AWLEN or ARLEN, the transfer size signal includes AWSIZE or ARSIZE, the AXI cache attribute signal includes AWCACHE or ARCACHE, the AXI protection attribute signal includes AWPROT or ARPROT, the write data signal includes WDATA, and the write byte valid signal includes WSTRB.

[0090] Through the field mapping mechanism, the protocol conversion bridge can completely convert the access information in the AXI protocol domain into the data packet information in the inter-core protocol domain, enabling the remote core to correctly identify and process access requests from the AXI side.

[0091] Example 2: The protocol conversion bridge converts inter-chip data packets into AXI bus transactions.

[0092] Specifically, when the protocol conversion bridge is configured to convert inter-core packets from remote cores pointing to the PCIe base address register mapping space into AXI bus transactions, it: maps the destination address in the inter-core packet to an AXI write address signal or an AXI read address signal after address translation; establishes a correspondence between the inter-core transaction identifier and the AXI transaction identifier in the AXI bus transaction through the management unit; calculates the data tick size and burst length of the AXI burst transmission based on the transmission length in the inter-core packet, and generates the AXI transmission size signal and the AXI burst transmission length signal; maps the buffer attribute field in the inter-core packet to the AXI buffer attribute signal; and maps the address modulo field in the inter-core packet to the AXI buffer attribute signal. The protocol conversion bridge maps the format field or access attribute field to AXI protection attribute signals; it maps the write data payload in the inter-core packet to the write data signal and write byte valid signal in the AXI write data channel; and it calculates the AXI burst transmission parameters based on the transmission length, starting address, AXI data bus width, and the single burst transmission length allowed by the AXI protocol in the inter-core packet or AXI bus transaction; when the corresponding data transmission exceeds the AXI single burst transmission length, crosses the preset address boundary, or the starting address is not aligned with the AXI data bus width, the protocol conversion bridge splits an inter-core transaction into multiple AXI burst transactions, or reassembles multiple AXI burst transactions into one inter-core transaction.

[0093] Therefore, the protocol conversion bridge can adapt to the differences between inter-core protocols and the AXI protocol in terms of packet length, address boundaries, and burst transmission capabilities. This avoids AXI transaction anomalies caused by excessive transmission length, address misalignment, or cross-boundary access, and improves the reliability of data transmission when remote cores access the PCIe base address register mapping space.

[0094] In practice, the protocol conversion bridge is configured to convert between inter-chip response error codes and AXI response signals.

[0095] Specifically, when the inter-chip response error code is successful, it is mapped to an AXI normal response; when the inter-chip response error code is an address error, it is mapped to an AXI decoding error response; when the inter-chip response error code is an authorization error, timeout error, or data verification error, it is mapped to an AXI slave device error response; and the protocol conversion bridge is also configured to convert the AXI normal response, decoding error response, or slave device error response into the corresponding inter-chip response error code.

[0096] AXI's normal response includes the OKAY response, AXI's decoding error response includes the DECERR response, and AXI's slave device error response includes the SLVERR response.

[0097] See Table 1, which shows the mapping relationship between inter-core response error codes and AXI responses.

[0098]

[0099] In some application scenarios, the interconnect interface connects to multiple remote cores.

[0100] Accordingly, when the interconnection interface connects multiple remote cores, the protocol conversion bridge looks up the system address mapping table based on the address in the AXI access request to obtain the core identifier of the corresponding target remote core, and selects the corresponding inter-core link, inter-core packet encapsulation format, permission policy, cache attribute or flow control parameter based on the core identifier of the target remote core.

[0101] Specifically, different remote kernels can have different protocol types, protocol versions, data bit widths, maximum packet lengths, flow control credit values, or access permission policies.

[0102] When an AXI access request hits the address space of a remote kernel, the protocol translation bridge can look up the system address mapping table based on the address in the AXI access request to obtain the kernel identifier of the corresponding target remote kernel. The protocol translation bridge can then select the appropriate inter-kernel link, inter-kernel packet encapsulation format, permission policy, caching attributes, or flow control parameters based on the kernel identifier of the target remote kernel.

[0103] In this embodiment, the protocol conversion bridge also includes a core capability table; the core capability table is used to record at least one of the following for different remote cores: protocol type, protocol version, maximum data packet length, data bit width, flow control credit value depth, cache attribute support capability, atomic operation support capability, timeout parameters, and retransmission parameters; the protocol conversion bridge adapts the data packet encapsulation format, data packet length, access attributes, cache attributes, or flow control parameters between cores according to the core capability table.

[0104] Specifically, the kernel capability table records at least one of the following for different remote kernels: protocol type, protocol version, maximum data packet length, data bit width, flow control credit value depth, cache attribute support capability, atomic operation support capability, timeout parameters, and retransmission parameters.

[0105] If the first remote core supports a larger data packet length, while the second remote core only supports a smaller data packet length, the protocol conversion bridge can use different encapsulation lengths for data packets sent to different remote cores according to the core capability table.

[0106] If different remote kernels correspond to different protocol versions, the protocol conversion bridge can select the appropriate data packet format based on the kernel identifier of the target remote kernel.

[0107] Through the chip capability table, the protocol conversion bridge can perform differentiated adaptation for multiple remote chips, enabling the system to be compatible with remote chips from different manufacturers, different protocol versions, or different capability levels.

[0108] In some embodiments, the protocol conversion bridge is configured to allow remote chips to actively access the PCIe base address register mapping space.

[0109] In this scenario, the RISC-V processor is configured to configure the PCIe base address register address mapping and remote chip access permissions in the protocol conversion bridge. This allows inter-chip data packets from remote chips to be converted into AXI bus transactions via the protocol conversion bridge after the permission verification is passed, and then sent to the PCIe interface module via the AXI on-chip bus. The PCIe interface module then accesses the base address register space of the corresponding PCIe device.

[0110] In one example, the protocol translation bridge performs permission verification on requests from remote kernels to access the PCIe base address register mapping space. The permission verification includes at least one of the following: verifying whether the source kernel identifier has permission to access the corresponding PCIe base address register mapping address window; verifying whether the access type is an allowed read access, write access, or read-write access; verifying whether the access address falls within the pre-configured PCIe base address register mapping address range; and verifying whether the transaction type is an allowed PCIe mapping transaction.

[0111] Correspondingly, the RISC-V processor performs at least one of the following operations: initialization, address mapping configuration, PCIe base address register mapping configuration, permission configuration, task scheduling, status query, exception handling, and fault recovery. Thus, data transfer between PCIe devices and remote chips can be completed via the PCIe interface module, AXI on-chip bus, and protocol conversion bridge without requiring data to be moved through the RISC-V processor.

[0112] In some embodiments, the protocol conversion bridge includes an AXI slave interface, an AXI master interface, an inter-chip packet transceiver interface, a configuration register group, an address comparison unit, and an authorization judgment unit, wherein: The AXI slave interface connects to the AXI on-chip bus and is used to receive AXI access requests initiated by the RISC-V processor via the AXI on-chip bus, or to receive AXI access requests sent via the AXI on-chip bus after the PCIe-side access request has been converted by the PCIe interface module. The inter-chip data packet transceiver interface connects to the interconnect interface and is used to send inter-chip data packets to or receive inter-chip data packets from remote chips. The AXI master interface connects to the AXI on-chip bus and is used to initiate AXI read transactions to the PCIe interface module after inter-chip data packets from remote chips have been converted into AXI bus transactions. Alternatively, it can handle AXI write transactions; the configuration register set can be configured by the RISC-V processor via the AXI on-chip bus. The configuration register set is used to store at least a portion of the entries in the system address mapping table, and includes at least the remote chip address window register, the PCIe base address register mapping window register, and the remote chip access permission register; the address comparison unit is used to compare the address in the AXI access request with the address range in the remote chip address window register, and when the comparison result shows that the AXI access request hits the remote chip address space, it triggers the protocol conversion bridge to encapsulate the AXI access request into an inter-chip data packet.

[0113] Specifically, the remote kernel address window register is used to configure one or more remote kernel address windows. Each remote kernel address window may include a window base address, a window size, a target remote kernel identifier, and a window enable bit.

[0114] The window base address and window size are used to determine the address range of the remote kernel address window in the local system address space; the target remote kernel identifier is used to indicate the remote kernel to which the AXI access request that hits the address window should be forwarded; and the window enable bit is used to indicate whether the corresponding address window is valid.

[0115] It should be noted that when there are multiple remote kernel address windows, the protocol conversion bridge can match multiple address windows according to the window number, priority field, or preset matching order.

[0116] Furthermore, the address comparison unit is also used to compare the destination address in the inter-core packet from the remote core with the address range in the PCIe base address register mapping window register. When the comparison result shows that the destination address hits the PCIe base address register mapping space, the permission judgment unit determines whether the remote core has the access permission based on the remote core access permission register. If the remote core has the access permission, the protocol conversion bridge converts the inter-core packet into an AXI read transaction or an AXI write transaction and sends it to the PCIe interface module through the AXI master interface.

[0117] Specifically, the PCIe base address register mapping window register is used to configure one or more PCIe base address register mapping windows corresponding to the PCIe interface module. Each PCIe base address register mapping window may include the PCIe BAR mapping base address, mapping window size, corresponding PCIe BAR number, access attributes, and window enable bits.

[0118] The PCIe BAR mapping base address and mapping window size are used to limit the range of local PCIe address mappings that remote dies are allowed to access; the PCIe BAR number is used to identify the PCIe base address register resource corresponding to the mapping window; access attributes may include at least one of read enable, write enable, cache, or security attributes. By configuring the PCIe base address register mapping window register, the RISC-V processor can limit the range of PCIe mapping space accessible to remote dies.

[0119] Thus, when an AXI access request is an AXI write request, the protocol conversion bridge generates an inter-core write request data packet based on the write address, write data, write strobe signal, write burst length, and transaction identifier in the AXI write request, and carries the write data in the payload field of the inter-core write request data packet.

[0120] When the AXI access request is an AXI read request, the protocol conversion bridge generates an inter-core read request data packet based on the read address, read burst length, and transaction identifier in the AXI read request.

[0121] After the remote core completes the corresponding access, it can return a read response data packet or a write response data packet through the interconnection between cores. After receiving the corresponding response data packet, the protocol conversion bridge converts it into an AXI read response or an AXI write response and returns it to the original AXI access initiator through the AXI interface.

[0122] In some embodiments, when the remote chip has access rights, the protocol conversion bridge converts inter-chip data packets into AXI read transactions or AXI write transactions and sends them to the PCIe interface module through the AXI master interface.

[0123] If the remote core does not have access rights, the protocol conversion bridge can reject the access request and generate an access error response.

[0124] In this way, the protocol conversion bridge can convert local AXI access requests to remote kernel access requests, and remote kernel access requests to local PCIe interface module AXI transactions, based on the system address mapping table formed by the configuration register set. Simultaneously, through the cooperation of the address comparison unit and the permission judgment unit, the protocol conversion bridge can perform hardware-level judgments on access addresses and access permissions during cross-kernel access, thereby enhancing the controllability, security, and configurability of PCIe resource sharing and remote access in multi-kernel systems while ensuring access efficiency.

[0125] This application also provides a packaged chip. See also... Figure 3 , Figure 3 This is a schematic diagram of a packaged chip provided in an embodiment of this application. The packaged chip may include: At least one distal core 210; The RISC-V-based system-on-chip 100 as described in any of the foregoing embodiments is connected to a remote chip. PCIe device 220 is connected to RISC-V based system-on-chip 100.

[0126] For more details on the RISC-V-based System-on-Chip 100, please refer to the examples above.

[0127] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0128] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A system-on-a-chip based on RISC-V architecture, characterized in that, include: Interconnection interface, establishes inter-core communication link with at least one remote core, and sends and receives inter-core data packets; A protocol conversion bridge, connected to the interconnection interface, is used to perform bidirectional protocol conversion between inter-core data packets and AXI bus transactions; The AXI on-chip bus, connected to the protocol conversion bridge, is used to carry the AXI bus transactions and to arbitrate and forward access requests from different access initiators. The RISC-V processor, connected to the AXI on-chip bus, is used to configure the mapping relationship between the protocol conversion bridge and the PCIe base address register, and is able to initiate access requests to the remote chip. The PCIe interface module is connected to the AXI on-chip bus and is used to convert PCIe access requests into AXI bus transactions, or to convert AXI access requests from the AXI on-chip bus into PCIe transactions, so as to realize bidirectional access between the PCIe device and the remote chip.

2. The system-on-a-chip according to claim 1, characterized in that, The protocol conversion bridge is internally configured with a system address mapping table, which includes the correspondence between the global address range and the chip identifier of the remote chip, as well as the correspondence between the global address range and the PCIe base address register mapping space. The protocol conversion bridge is configured as follows: When an AXI access request from the AXI on-chip bus hits the address space of a remote chip, the system address mapping table is looked up according to the address in the AXI access request to determine the chip identifier and remote access address of the target remote chip. The AXI access request is then encapsulated into an inter-chip data packet containing the chip identifier of the target remote chip and sent to the target remote chip via the interconnect interface. When the destination address in the inter-chip data packet from the remote chip falls into the PCIe base address register mapping address window, the inter-chip data packet is converted into an AXI bus transaction and sent to the PCIe interface module via the AXI on-chip bus to access the corresponding PCIe base address register mapping space.

3. The system-on-a-chip according to claim 2, characterized in that, The protocol conversion bridge includes: The protocol parsing unit is used to parse the core identifier, transaction type, inter-core transaction identifier, address, transmission length, and access attributes in the inter-core data packet; The address mapping unit is used to determine the corresponding remote chip access address or PCIe base address register mapping address based on the address in the inter-chip data packet or the address in the AXI bus transaction. The permission verification unit is used to verify the permission of access requests from the remote chip that point to the PCIe base address register mapping space. The management unit is used to maintain the correspondence between the inter-chip transaction identifier and the AXI bus transaction; The transaction generation unit is used to generate an AXI read transaction or an AXI write transaction based on the parsing result of the inter-core data packet. The encapsulation unit is used to generate inter-core request packets or inter-core response packets based on AXI bus transactions or AXI responses. The flow control and error handling unit is used to perform flow control management, timeout management, retransmission management, or error response management on the conversion process between the inter-core data packets and the AXI bus transactions.

4. The system-on-a-chip according to claim 3, characterized in that, When the protocol conversion bridge is configured to convert the AXI bus transaction into the inter-core data packet: Use the write address signal in the AXI write address channel or the read address signal in the AXI read address channel as the address mapping index; The system address mapping table is searched according to the write address signal or the read address signal to obtain the chip identifier of the target remote chip and the remote access address; The management unit establishes the correspondence between the AXI transaction identifier in the AXI bus transaction and the inter-chip transaction identifier. Convert the AXI burst transmission length signal and transmission size signal into the transmission length field in the inter-core data packet; Convert the AXI cache attribute signal into a cache attribute field in the inter-core data packet; Convert the AXI protection attribute signal into the access attribute field in the inter-core data packet; The write data signal and write byte valid signal in the AXI write data channel are encapsulated into the data payload field of the inter-core data packet.

5. The system-on-a-chip according to claim 3, characterized in that, When the protocol conversion bridge is configured to convert inter-core packets from the remote core that point to the PCIe base address register mapping space into the AXI bus transaction: The destination address in the inter-core data packet is mapped to an AXI write address signal or an AXI read address signal after address translation. The management unit establishes a correspondence between the inter-chip transaction identifier and the AXI transaction identifier in the AXI bus transaction. The data beat size and burst transmission length of the AXI burst transmission are calculated based on the transmission length in the inter-core data packet, and the AXI transmission size signal and AXI burst transmission length signal are generated. Map the cache attribute fields in the inter-core data packets to AXI cache attribute signals; Map the address pattern field or access attribute field in the inter-core data packet to an AXI protection attribute signal; The write data payload in the inter-core data packet is mapped to the write data signal and write byte valid signal in the AXI write data channel; Furthermore, the protocol conversion bridge calculates the AXI burst transmission parameters based on the transmission length, starting address, AXI data bus width, and the single burst transmission length allowed by the AXI protocol in the inter-core data packet or the AXI bus transaction. When the corresponding data transmission exceeds the AXI single burst transmission length, crosses a preset address boundary, or the starting address is not aligned with the AXI data bus width, the protocol conversion bridge splits an inter-core transaction into multiple AXI burst transactions, or reassembles multiple AXI burst transactions into a single inter-core transaction.

6. The system-on-a-chip according to claim 3, characterized in that, The management unit includes a transaction context table; The transaction context table is used to record at least one of the following: inter-core transaction identifier, AXI transaction identifier, source core identifier, target remote core identifier, transaction type, access address, transmission length, transaction status, retransmission count, sequence number, and retry attribute. The correspondence between the AXI transaction identifier and the inter-core transaction identifier is established through the transaction context table; or, the inter-core transaction identifier is obtained by truncating, expanding, hashing, or reallocating the AXI transaction identifier; or, the AXI transaction identifier is obtained by truncating, expanding, hashing, or reallocating the inter-core transaction identifier.

7. The system-on-a-chip according to claim 3, characterized in that, The flow control and error handling unit includes: The timeout management unit is used to start a timeout counter after establishing the correspondence between inter-chip transactions and AXI transactions in the protocol conversion bridge and issuing the corresponding transaction. If no corresponding response is received within the preset timeout threshold, a timeout error response is generated and the timeout error response is returned to the access initiator or an interrupt is triggered to notify the RISC-V processor. The retransmission management unit is used to re-initiate the corresponding access request based on the retry attribute of the corresponding transaction and the maximum number of retransmissions configured in the software when a timeout error, link verification error or data packet transmission failure occurs, and to return an error response after the maximum number of retransmissions is reached. Before retransmitting a write transaction, the retransmission management unit queries the transaction status, sequence number, or retryable attribute in the transaction context table. When the write transaction has been received by the AXI-side target module and does not have a retryable attribute, the retransmission management unit does not resubmit the write transaction, but instead generates an error response or triggers an interrupt notification to the RISC-V processor.

8. The system-on-a-chip according to claim 3, characterized in that, The flow control and error handling unit includes a flow control management unit, wherein: The flow control management unit includes: The AXI-side flow control processing module is used to perform backpressure control on AXI-side transmission based on the AXI active / ready handshake mechanism. The inter-core flow control credit value management module is used to manage logic for controlling the transmission of inter-core data packets based on available flow control credit values. Specifically, when the available flow control credit value is zero, the transmission of inter-core data packets to the corresponding remote core is suspended; after receiving the flow control credit value returned by the corresponding remote core, the transmission of inter-core data packets is resumed. Furthermore, the inter-core flow control credit value management module is configured to: send the number of data packets that can be received by the local end to the remote core after the link initialization is completed, and receive the number of data packets that can be received by the remote core; decrement the corresponding flow control credit value by one for each inter-core data packet sent; and return a flow control credit value to the remote core after each inter-core data packet from the remote core is processed.

9. The system-on-a-chip according to claim 1, characterized in that, The protocol conversion bridge is configured to convert between inter-chip response error codes and AXI response signals; When the inter-chip response error code is successful, it is mapped to a normal AXI response; When the inter-chip response error code is an address error, it is mapped to the AXI decoding error response; When the inter-core response error code is an authorization error, timeout error, or data verification error, it is mapped to an AXI slave device error response; Furthermore, the protocol conversion bridge is configured to convert AXI's normal response, decoding error response, or device error response into the corresponding inter-chip response error code.

10. The system-on-a-chip according to claim 2, characterized in that, When the interconnection interface connects multiple remote cores, the protocol conversion bridge looks up the system address mapping table according to the address in the AXI access request to obtain the core identifier of the corresponding target remote core, and selects the corresponding inter-core link, inter-core packet encapsulation format, permission policy, cache attribute or flow control parameter based on the core identifier of the target remote core. The protocol conversion bridge also includes a chip capability table; The chip capability table is used to record at least one of the following for different remote chips: protocol type, protocol version, maximum data packet length, data bit width, flow control credit value depth, cache attribute support capability, atomic operation support capability, timeout parameters, and retransmission parameters. The protocol conversion bridge adapts the packet encapsulation format, packet length, access attributes, cache attributes, or flow control parameters between kernels based on the kernel capability table.

11. The system-on-a-chip according to claim 1, characterized in that, The protocol conversion bridge is configured to allow the remote chip to actively access the PCIe base address register mapping space; The RISC-V processor is configured to configure the PCIe base address register address mapping relationship and remote chip access permissions in the protocol conversion bridge, so that inter-chip data packets from the remote chip are converted into AXI bus transactions through the protocol conversion bridge after the permission verification is passed, and sent to the PCIe interface module through the AXI on-chip bus, and the PCIe interface module accesses the base address register space of the corresponding PCIe device. The protocol conversion bridge performs permission verification on requests from remote kernels to access the PCIe base address register mapping space. The permission verification includes at least one of the following: verifying whether the source kernel identifier has permission to access the corresponding PCIe base address register mapping address window; verifying whether the access type is an allowed read access, write access, or read-write access; verifying whether the access address falls within the pre-configured PCIe base address register mapping address range; and verifying whether the transaction type is an allowed PCIe mapping transaction. Data transmission between the PCIe device and the remote chip can be completed via the PCIe interface module, the AXI on-chip bus, and the protocol conversion bridge without the RISC-V processor handling the data.

12. The system-on-a-chip according to claim 2, characterized in that, The protocol conversion bridge includes an AXI slave interface, an AXI master interface, an inter-core packet transceiver interface, a configuration register group, an address comparison unit, and an authorization judgment unit. The AXI slave interface is connected to the AXI on-chip bus and is used to receive AXI access requests initiated by the RISC-V processor via the AXI on-chip bus, or to receive AXI access requests sent via the AXI on-chip bus after the PCIe side access request is converted by the PCIe interface module. The inter-core data packet transceiver interface is connected to the interconnection interface and is used to send inter-core data packets to or receive inter-core data packets from remote cores. The AXI master interface is connected to the AXI on-chip bus and is used to initiate AXI read transactions or AXI write transactions to the PCIe interface module after the data packets from the remote chip are converted into AXI bus transactions. The configuration register group can be configured by the RISC-V processor via the AXI on-chip bus. The configuration register group is used to store at least a portion of the entries of the system address mapping table, and includes at least a remote chip address window register, a PCIe base address register mapping window register, and a remote chip access permission register. The address comparison unit is used to compare the address in the AXI access request with the address range in the remote kernel address window register, and when the comparison result shows that the AXI access request hits the remote kernel address space, it triggers the protocol conversion bridge to encapsulate the AXI access request into an inter-kernel data packet. The address comparison unit is also used to compare the destination address in the inter-chip data packet from the remote chip with the address range in the PCIe base address register mapping window register, and when the comparison result shows that the destination address hits the PCIe base address register mapping space, the permission judgment unit determines whether the remote chip has access rights according to the remote chip access permission register. When the remote core has access rights, the protocol conversion bridge converts the inter-core data packets into AXI read transactions or AXI write transactions, and sends them to the PCIe interface module through the AXI master interface.

13. A packaged chip, characterized in that, include: At least one distal core; The RISC-V-based system-on-a-chip as described in any one of claims 1 to 12 is connected to the remote chip. The PCIe device is connected to the RISC-V-based system-on-a-chip.

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