Semiconductor test yield prediction method and system based on deep learning
By constructing a dynamic knowledge graph and a heterogeneous graph neural network, combined with a contrastive learning-driven degradation prediction network, the problem of deep correlation and temporal evolution characteristics of multi-source heterogeneous data in temperature stress accelerated aging tests of semiconductor packaging products was solved, enabling accurate prediction of failure modes and root cause analysis.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHONGKE (HEFEI) MICROELECTRONICS RESEARCH INSTITUTE CO LTD
- Filing Date
- 2026-04-02
- Publication Date
- 2026-07-21
AI Technical Summary
Existing technologies struggle to effectively capture the deep correlations and temporal evolution characteristics between multi-source heterogeneous data in temperature stress accelerated aging tests of semiconductor packaged products. This results in insufficient failure mechanism characterization capabilities, and the reliance on expert experience leads to poor scalability and an inability to accurately predict yield.
A dynamic knowledge graph is constructed, multi-source heterogeneous data is encoded through a heterogeneous graph neural network, multi-level recursive aggregation is performed using temporal evolution edges, and a degradation prediction network driven by contrastive learning is combined to extract the state evolution trajectory features of failure mode nodes. Finally, the failure mode node with the highest contribution is identified by reverse tracing.
It improves the accuracy and interpretability of semiconductor test yield prediction, systematically models the multi-physics coupling and time accumulation effect in the temperature stress accelerated aging process, and significantly enhances the ability to distinguish failure modes.
Smart Images
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