Chip wafer sorting method and device, electronic equipment and storage medium

Abstract

The present application relates to the technical field of chip design, and discloses a chip screening grading method and device, electronic equipment and a storage medium, the method comprising: obtaining multi-dimensional characteristic parameters of a chip in a production test stage; obtaining a maximum working frequency prediction value of the chip based on the multi-dimensional characteristic parameters and a trained frequency prediction model; the frequency prediction model is obtained by pre-training based on a regression algorithm; and based on the maximum working frequency prediction value, a conservative grading strategy is used to dynamically adjust the voltage and frequency of the chip for grading, which effectively improves the accuracy of chip screening and realizes the precision and energy saving of chip grading.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and more specifically to chip sieve grading methods, apparatus, electronic devices, and storage media. Background Technology

[0002] Chip screening (also known as chip sieving or wafer screening) is an indispensable and critical step in the semiconductor mass production process. Its core purpose is to screen out chips that meet performance and specifications, and to remove chips that are faulty, have substandard performance, or have defects.

[0003] Existing chip screening methods suffer from long testing cycles, large system-level testing workload, low screening efficiency, and difficulty in accurately fitting the actual performance curve of the chip based on fixed thresholds, resulting in poor classification consistency. Summary of the Invention

[0004] This invention provides a chip sieving and grading method, apparatus, electronic device, and storage medium to solve the problems of long testing cycles, low sieving efficiency, and poor grading consistency in existing chip sieving solutions.

[0005] In a first aspect, the present invention provides a chip wafer sieving and grading method, the method comprising: Obtain multidimensional characteristic parameters of the chip during the production and testing phase; Based on multidimensional feature parameters and a trained frequency prediction model, the predicted maximum operating frequency of the chip is obtained; the frequency prediction model is pre-trained based on a regression algorithm. Based on the predicted maximum operating frequency, a conservative grading strategy is adopted to classify the chip for dynamic voltage and frequency adjustment.

[0006] This invention provides a chip screening and grading method that obtains multi-dimensional characteristic parameters of the chip during the production and testing phase, and directly obtains the predicted value of the chip's maximum operating frequency using a trained frequency prediction model. This eliminates the need for system-level testing at multiple voltage levels, thereby shortening the testing cycle, reducing the testing workload, and improving screening efficiency. Simultaneously, a conservative grading strategy is adopted for dynamic voltage and frequency adjustment grading, avoiding grading deviations caused by grading based on fixed thresholds, improving grading consistency, and solving the problems of long testing cycles, low screening efficiency, and poor grading consistency in existing chip screening solutions.

[0007] In one alternative implementation, the trained frequency prediction model is constructed in the following manner: Collect multidimensional feature parameters of multiple training sample chips during the production testing phase; System-level testing was conducted on multiple training sample chips to obtain the measured maximum operating frequency of each training sample chip. Using the multidimensional feature parameters of the training sample chip as input and the corresponding measured maximum operating frequency as output, a regression algorithm is used to train the preset basic regression model to obtain the trained frequency prediction model.

[0008] In the above technical solution, by collecting multi-dimensional feature parameters of training sample chips during the production testing phase, and using the measured value of the maximum operating frequency obtained from system-level testing as the training target, a regression algorithm is used to train the prediction model. This enables the model to accurately predict the maximum operating frequency of the chip based solely on the feature parameters from the production testing phase. As a result, in actual chip screening applications, it is not necessary to perform system-level testing at multiple voltage levels on each chip, reducing the testing workload and shortening the testing cycle.

[0009] In one optional implementation, obtaining the measured maximum operating frequency of each training sample chip includes: Load system-level performance test cases and run the test cases on the training sample chips at different voltage levels to test the maximum operating frequency of the training sample chips at each voltage level. An incremental maximum operating frequency search method is adopted. During the search process, the current frequency prediction model is updated, and the maximum operating frequency predicted by the updated frequency prediction model is used as the initial clock frequency for linear search. The maximum operating frequency of each training sample chip is gradually approached and locked, and the measured values ​​of the maximum operating frequency of each training sample chip under different voltage levels are obtained.

[0010] In the above technical solution, the maximum operating frequency of each voltage level is obtained by running system-level performance test cases at different voltage levels. An incremental maximum operating frequency search method is adopted. During the search process, the predicted value of the current frequency prediction model is used as the initial clock frequency for linear search, so that the starting point of each search is closer to the true value. This reduces the number of search steps required for step-by-step approximation, shortens the time for obtaining the measured maximum operating frequency of each training sample chip, and reduces the workload of system-level testing.

[0011] In one optional implementation, the maximum operating frequency predicted by the updated frequency prediction model is used as the initial clock frequency for the linear search, including: For the first training sample chip, a search is performed using a preset default frequency as the initial clock frequency to obtain the measured value of the maximum operating frequency of the first training sample chip. After obtaining the measured maximum operating frequency of each training sample chip, the current frequency prediction model is updated. The updated frequency prediction model is used to provide an optimized initial clock frequency for the search of the next training sample chip.

[0012] In the above technical solution, by setting a preset default frequency as the search starting point for the first training sample chip, and updating the current frequency prediction model after obtaining the measured value of the maximum operating frequency of each training sample chip, the updated model can provide an optimized initial clock frequency for the search of the next training sample chip. As the number of training samples increases, the search starting point of subsequent chips gradually approaches their true maximum operating frequency, reducing the number of linear search steps required for each chip and shortening the total time for obtaining the measured values ​​of batch training sample chips.

[0013] In one optional implementation, the predicted maximum operating frequency of the chip is obtained based on multidimensional feature parameters and a trained frequency prediction model, including: By inputting multidimensional feature parameters into the trained frequency prediction model, the maximum operating frequency prediction value output by the frequency prediction model can be obtained.

[0014] In the above technical solution, by directly inputting the multi-dimensional feature parameters obtained by the chip during the production testing phase into the trained frequency prediction model, the maximum operating frequency prediction value of the model output can be obtained. There is no need to perform system-level testing of the chip at multiple voltage levels, thereby shortening the testing time of a single chip, reducing the occupation of testing equipment, and improving the chip screening efficiency.

[0015] In one optional implementation, a conservative grading strategy is used to perform dynamic voltage and frequency adjustment grading on the chip, including: Based on the predicted maximum operating frequency of the chip, the chip is classified into the corresponding dynamic voltage and frequency adjustment level according to the preset classification rules.

[0016] In the above technical solution, the dynamic voltage frequency adjustment classification can be completed without actual testing of the chip by predicting the maximum operating frequency of the chip and classifying it according to the preset classification rules. This avoids the time overhead caused by multi-voltage level system-level testing. At the same time, the classification rules based on the predicted value can achieve consistent judgment standards and ensure the stability of the classification results of the same batch of chips.

[0017] In one optional implementation, the chip is classified into a corresponding dynamic voltage frequency adjustment level according to a preset classification rule, including: Obtain the predicted maximum operating frequency of the chip and the standard deviation of the prediction error distribution of the frequency prediction model; Based on the predicted maximum operating frequency of the chip, a conservative estimate is calculated. The conservative estimate is the predicted maximum operating frequency minus the standard deviation of a preset multiple. Compare the conservative estimate with the frequency threshold corresponding to each dynamic voltage frequency adjustment level; When a conservative estimate falls within the frequency range corresponding to a dynamic voltage frequency adjustment level, the chip is classified into the corresponding dynamic voltage frequency adjustment level.

[0018] In the above technical solution, by obtaining the predicted value of the chip's maximum operating frequency and the standard deviation of the prediction error distribution, a conservative estimate is calculated by subtracting a preset multiple standard deviation from the predicted value of the maximum operating frequency. This conservative estimate is then compared with the frequency threshold corresponding to each dynamic voltage frequency adjustment level to complete the classification. Thus, in the case of errors in the prediction value, subtracting the preset multiple standard deviation reduces the risk of the chip being mistakenly classified into a higher performance level due to prediction deviation, thereby improving the accuracy of the classification.

[0019] In a second aspect, the present invention provides a chip sieve grading device, the device comprising: The parameter acquisition module is used to acquire multi-dimensional characteristic parameters of the chip during the production and testing phase. The prediction module is used to obtain the predicted maximum operating frequency of the chip based on multidimensional feature parameters and a trained frequency prediction model; the frequency prediction model is pre-trained based on a regression algorithm. The grading module is used to dynamically adjust the voltage and frequency of the chip based on the predicted maximum operating frequency and a conservative grading strategy.

[0020] Thirdly, the present invention provides an electronic device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the chip sieving and grading method of the first aspect or any corresponding embodiment described above.

[0021] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the chip sieving and grading method of the first aspect or any corresponding embodiment described above.

[0022] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the chip sieve grading method described in the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0023] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the first process of the chip sieving and grading method according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a second process for a chip sieve grading method according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the third process of the chip sieve grading method according to an embodiment of the present invention; Figure 4 This is a structural block diagram of a chip sieve grading device according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0027] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0028] According to an embodiment of the present invention, a chip sieve grading method is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0029] This embodiment provides a chip sieving and grading method, which can be used in the aforementioned electronic devices. Figure 1 This is a flowchart of a chip sieve grading method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps: Step S101: Obtain the multi-dimensional feature parameters of the chip during the production testing phase.

[0030] The chip production testing phase refers to all the electrical performance tests that the chip undergoes from the completion of wafer manufacturing to final packaging and shipment.

[0031] Multidimensional feature parameters refer to multiple parameters collected during the chip manufacturing and testing phase, which are used as inputs to a frequency prediction model to predict the chip's maximum operating frequency. The chip manufacturing and testing phase includes the CP (Chip Probe) and FT (Final Test) phases.

[0032] Specifically, during the wafer probe testing (CP) and final product testing (FT) stages of the chip, 10 characteristic parameters are collected, including 5 OSC parameters, 3 temperature calibration parameters, and 2 power consumption calibration parameters. The OSC (Oscillator) parameters refer to the parameters of the Ring Oscillator (ROSC) circuit, which characterize the speed characteristics at different locations of the chip; the power consumption calibration parameters are the static power consumption (Sp), which is obtained by testing at different voltage levels; and the temperature calibration parameters are obtained by testing at different voltage levels.

[0033] The first part of the calculation method (FT) uses power consumption test cases to measure the static circuit power consumption Sp at different voltage levels; the second part uses light load excitation test cases collected at different voltage levels, selecting a total of 5 frequency parameters, 3 power consumption parameters, and 2 temperature parameters. A total of 10 parameters from each chip are used as inputs for training, resulting in a more accurate prediction of the maximum operating frequency Fmax.

[0034] Step S102: Based on the multidimensional feature parameters and the trained frequency prediction model, the predicted value of the chip's maximum operating frequency is obtained; the frequency prediction model is pre-trained based on a regression algorithm.

[0035] Among them, the trained frequency prediction model refers to a calculation model that is based on a regression algorithm, takes the multi-dimensional feature parameters of the training sample chip in the production testing stage as input, and takes the measured value of the maximum operating frequency obtained from the system-level test as output, and is used to output the predicted value of the chip's maximum operating frequency based on the input feature parameters after training the preset basic regression model.

[0036] The maximum operating frequency prediction value of a chip refers to the operating frequency value calculated and output by a trained frequency prediction model after inputting the multi-dimensional feature parameters obtained during the chip's production and testing phase into the model. This value characterizes the chip's performance boundary under dynamic voltage and frequency adjustment conditions.

[0037] In this embodiment, Bayesian linear regression is applied to learn a prediction model for the maximum operating frequency Fmax. Compared with prediction learning methods such as Gaussian process, support vector machine (SVM) regression, and random forest regression, Bayesian linear regression can provide more accurate result predictions when the training samples are limited.

[0038] Step S103: Based on the predicted maximum operating frequency, a conservative grading strategy is adopted to perform dynamic voltage and frequency adjustment grading of the chip.

[0039] The conservative grading strategy refers to: calculating a conservative estimate (the predicted maximum operating frequency minus the standard deviation of a preset multiple) based on the predicted maximum operating frequency of the chip and the standard deviation of the prediction error distribution of the frequency prediction model, and comparing this conservative estimate with the frequency threshold corresponding to each dynamic voltage frequency adjustment level to determine the grading method of the chip's level.

[0040] Dynamic voltage and frequency scaling (DVFS) is a classification process that categorizes chips into different performance levels based on their performance under DVFS conditions. The purpose is to ensure that chips within the same level have consistent performance under dynamic voltage changes.

[0041] Specifically, based on the predicted maximum operating frequency of the chip (or a conservative estimate calculated based on that predicted value), the chip is classified into different dynamic voltage frequency adjustment performance levels according to a preset classification rule.

[0042] The chip screening and grading method provided in this embodiment obtains the multi-dimensional characteristic parameters of the chip during the production and testing phase, and directly obtains the predicted value of the chip's maximum operating frequency using a trained frequency prediction model. This eliminates the need for system-level testing at multiple voltage levels, thereby shortening the testing cycle, reducing the testing workload, and improving screening efficiency. At the same time, it adopts a conservative grading strategy for dynamic voltage and frequency adjustment grading, avoiding grading deviations caused by grading based on fixed thresholds, improving grading consistency, and solving the problems of long testing cycles, low screening efficiency, and poor grading consistency in existing chip screening solutions.

[0043] This embodiment provides a chip sieving and grading method, which can be used in the aforementioned electronic devices. Figure 2 This is a flowchart of a chip sieve grading method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps: Step S201: Obtain the multi-dimensional characteristic parameters of the chip during the production testing phase. For details, please refer to [link to relevant documentation]. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0044] Step S202: Based on the multidimensional feature parameters and the trained frequency prediction model, the predicted value of the chip's maximum operating frequency is obtained; the frequency prediction model is pre-trained based on a regression algorithm.

[0045] In one alternative implementation, the trained frequency prediction model is constructed in the following manner: Collect multidimensional feature parameters of multiple training sample chips during the production testing phase; perform system-level testing on multiple training sample chips to obtain the measured maximum operating frequency of each training sample chip; use the multidimensional feature parameters of the training sample chips as input and the corresponding measured maximum operating frequency as output, and use a regression algorithm to train a preset basic regression model to obtain a trained frequency prediction model.

[0046] This embodiment provides a strategy to shorten the test time for the measured maximum operating frequency Fmax of the training samples: because it is necessary to test the maximum operating frequency Fmax of the chips under different voltages, even if each round of testing only has a system test time of 200s, as the number of chips and the combination of power levels are added, it will inevitably cause an exponential increase in time and manpower costs.

[0047] This embodiment is further optimized by gradually updating the learned maximum operating frequency Fmax model while collecting the maximum operating frequency Fmax, and then gradually updating the maximum operating frequency Fmax predicted by the model. The maximum operating frequency Fmax can be found quickly and accurately without using the gradual increase of the linear step size. This greatly reduces the number of test rounds to find the maximum operating frequency Fmax of the trained model.

[0048] During the model construction process, the measured maximum operating frequency of each training sample chip was obtained, including: Load system-level performance test cases and run them on the training sample chips at different voltage levels to test the maximum operating frequency of the training sample chips at each voltage level. Use an incremental maximum operating frequency search method to update the current frequency prediction model during the search process, and use the maximum operating frequency predicted by the updated frequency prediction model as the initial clock frequency for linear search. Gradually approach and lock the maximum operating frequency of each training sample chip to obtain the measured maximum operating frequency of each training sample chip at different voltage levels.

[0049] In one optional implementation, the maximum operating frequency predicted by the updated frequency prediction model is used as the initial clock frequency for the linear search, including: searching for the first training sample chip with a preset default frequency as the initial clock frequency to obtain the measured value of the maximum operating frequency of the first training sample chip; after obtaining the measured value of the maximum operating frequency of each training sample chip, updating the current frequency prediction model, and using the updated frequency prediction model to provide an optimized initial clock frequency for the search of the next training sample chip.

[0050] Specifically, a Bayesian linear regression model for predicting the maximum operating frequency Fmax is established, where the maximum operating frequency Fmax of the chip under test is denoted as y. t , consisting of m response feature vectors X t Its weight array W is represented by a linear function, namely: (1); in, This is a predicted value for the chip's maximum operating frequency. For weight array, The response feature vector, where m is the number of features. Let the weight of the j-th feature be , Let j be the j-th feature parameter.

[0051] Each time new training sample data is added to the model, for the i-th training sample to be added, the distribution parameters are updated using the following formula (2). Then, the weight parameter Wi is updated using formula (3): (2); (3); in, For the first The distribution parameters updated for each training sample For the first The distribution parameters updated for each training sample For the first The feature vectors of each training sample for The transpose of , For the first The updated weight vector of each training sample The inverse of the initial covariance matrix. For the first The updated weight vector of each training sample For the first The measured maximum operating frequency of a training sample.

[0052] For example, model training fit use case selection: such as Figure 3 The process shown requires obtaining accurate and real system maximum operating frequency (Fmax) data for the training sample chips. It also requires batch searching for the maximum operating frequency (Fmax) of performance test cases. When selecting test cases, the system business is mapped to reflect the real business scenario as much as possible. This method selects some heavy-load business slices such as integer arithmetic performance test dhrystone, embedded processor performance test coremark, and integer performance test suite specINT.

[0053] Set up an incremental maximum operating frequency Fmax model search module: while collecting real maximum operating frequency Fmax data, incrementally update the learned maximum operating frequency Fmax frequency prediction model; and use the maximum operating frequency Fmax predicted by the real-time updated frequency prediction model as the initial clock frequency for subsequent linear search.

[0054] In the early stages of training, the accuracy of the Fmax model, which is the maximum working frequency of incremental updates, may differ significantly from that of the final converged model. The model ultimately used for DVFS binning is the high-precision converged model.

[0055] However, since the coarse model in the early stage of training is only used to provide a better initial clock frequency in the maximum operating frequency Fmax search phase, it can still effectively reduce the number of iterations of linear search and significantly accelerate the sample collection process, even if there is a certain error in the prediction.

[0056] Step S202 above includes: Step a: Input the multidimensional feature parameters into the trained frequency prediction model to obtain the maximum working frequency prediction value output by the frequency prediction model.

[0057] Specifically, the multi-dimensional feature parameters (including ring oscillator frequency parameters, power consumption parameters, and temperature parameters) collected during the chip's production testing phase are organized into feature vectors according to the model input format and input into the trained frequency prediction model. This model is built based on the Bayesian linear regression algorithm and internally stores the weight parameters learned through training samples. The model performs linear weighted calculations on the input feature vectors and outputs a scalar value as the predicted maximum operating frequency of the chip.

[0058] Step S203: Based on the predicted maximum operating frequency, a conservative grading strategy is adopted to perform dynamic voltage and frequency adjustment grading of the chip.

[0059] Specifically, step S203 includes: Step b: Based on the predicted maximum operating frequency of the chip, the chip is classified into the corresponding dynamic voltage and frequency adjustment level according to the preset classification rules.

[0060] In some alternative implementations, step b above includes: Step b1: Obtain the predicted maximum operating frequency of the chip and the standard deviation of the prediction error distribution of the frequency prediction model.

[0061] Specifically, after adding all n training sample data, the final Wn can be used as weight data to predict the maximum operating frequency Fmax of the unknown chip. The standard deviation of the error distribution is set to the maximum operating frequency prediction value in this embodiment. Reduce the standard deviation of the prediction error distribution by 4 times Standard deviation of prediction error distribution The formula is as follows: (4); in, Let be the posterior covariance matrix.

[0062] Step b2: Based on the predicted maximum operating frequency of the chip, calculate a conservative estimate. The conservative estimate is the predicted maximum operating frequency minus the standard deviation of a preset multiple.

[0063] The standard deviation of the preset multiple is 4 times the standard deviation.

[0064] The Dynamic Voltage Frequency Adjustment (DVFS) hierarchical framework achieves higher accuracy, thanks to a statistically conservative setting. (Error range), which effectively avoids misplacing slower chips in faster Dynamic Voltage Frequency Adjustment (DVFS) levels, thus preventing customer returns.

[0065] Step b3: Compare the conservative estimate with the frequency threshold corresponding to each dynamic voltage frequency adjustment level; when the conservative estimate falls into the frequency range corresponding to a dynamic voltage frequency adjustment level, classify the chip into the corresponding dynamic voltage frequency adjustment level.

[0066] Specifically, the calculated conservative estimate is compared one by one with the frequency threshold ranges corresponding to each of the pre-set dynamic voltage frequency adjustment levels. If the conservative estimate falls within the frequency range corresponding to a certain level (for example, greater than or equal to the lower threshold of that level and less than the upper threshold), the chip is classified into that dynamic voltage frequency adjustment level, which is the final classification result of the chip.

[0067] The chip grading method provided in this embodiment selects 10 specially chosen OSC parameters and temperature calibration parameters of the chip as core features to construct a machine learning framework. Based solely on the data collected during the wafer probe testing (CP) and final product testing (FT) stages, the dynamic voltage-frequency adjustment (DVFS) grading of the chip can be completed without the need for lengthy system-level testing. The core machine learning techniques employed include Bayesian linear regression for model fitting, stepwise regression for feature selection, and an incremental maximum operating frequency (Fmax) model search method to shorten the data collection and testing time required for each training sample.

[0068] To verify the effectiveness of this method, experiments were conducted on 249 industrial-grade SoC (System on Chip) test chips. The experimental results show that the framework proposed in this invention can achieve a high accuracy rate in dynamic voltage frequency adjustment (DVFS) classification of chips, ensuring that slower chips are not classified into the faster DVFS classification. The incremental maximum operating frequency (Fmax) model search method can save system-level testing workload.

[0069] The chip grading method provided in this embodiment addresses the core limitations of existing chip grading solutions, such as insufficient grading accuracy and limited DVFS chip compatibility. It aims to effectively improve the accuracy of chip screening, achieve precise and energy-efficient chip grading, and solve the technical pain point that existing solutions struggle to balance screening accuracy, efficiency, and energy efficiency.

[0070] As one or more specific application embodiments of the present invention, combined with Figure 3 The chip sieve grading provided by the present invention will be further described in detail, such as... Figure 3 As shown, the specific process is as follows: Step S301: Chip test data acquisition: During the wafer probe test (CP) and final product test (FT) stages of the chip, acquire 10 ring oscillator parameters (OSC parameters), temperature calibration parameters, and power consumption calibration parameters.

[0071] Step S302: Test case selection: Select heavy-load business slices such as dhrystone, coremark, and specINT as system-level performance test cases.

[0072] Step S303: Batch maximum operating frequency Fmax linear search: Perform a batch performance test case maximum operating frequency Fmax search on the training sample chips to obtain the actual measured value of the chip's maximum operating frequency Fmax under different voltage levels.

[0073] Step S304: Incremental Bayesian linear regression model update: After obtaining the measured value of the true maximum operating frequency Fmax of each training sample chip, add the sample data into the model: input new sample features, update the distribution parameter Si, and then update the weight parameter Wi.

[0074] Step S305: Model Predicts Maximum Operating Frequency Fmax: The updated frequency prediction model is used to predict the maximum operating frequency of the chip, the predicted frequency value is output, and settings are configured. The conservative limit of error is 4 times the standard deviation.

[0075] Step S306: Hot-start linear search: Use the maximum operating frequency Fmax predicted by the model as the initial clock frequency for the next training sample chip linear search to accelerate the search process.

[0076] Step S307: Model convergence: Repeat steps 3 to 6 to gradually update the model until the model accuracy converges, and obtain the final high-precision maximum operating frequency Fmax prediction model.

[0077] Step S308: DVFS Hierarchical Framework: Based on the predicted values ​​output by the converged high-precision maximum operating frequency Fmax prediction model, the following is adopted: A conservative strategy (predicted value minus 4 times the standard deviation) is used to dynamically adjust the voltage and frequency levels, classifying the chips into the corresponding performance levels.

[0078] It should be noted that the embodiments of the present invention also provide an alternative to the chip sieve grading method, the specific steps of which are as follows: 1. Data Acquisition: Only during the wafer probe testing (CP) stage and the final product testing (FT) stage, 10 specially selected OSC parameters and temperature calibration parameters of the chip are acquired, avoiding lengthy system testing.

[0079] 2. Feature optimization: The stepwise regression algorithm is used to select core features from the collected parameters to reduce model fitting redundancy.

[0080] 3. Model Building: A chip performance prediction model is built based on core features using the Bayesian linear regression algorithm.

[0081] 4. Efficiency optimization: Incremental maximum working frequency Fmax model search is enabled to shorten the time spent collecting training sample data and replace the traditional search mode.

[0082] 5. Classification Determination: Based on the model output, complete the dynamic voltage frequency adjustment (DVFS) classification of the chip, strictly control the accuracy of classification, and prevent slow chips from being classified as fast chips.

[0083] 6. Results Output: Synchronously output chip grading results and test workload data to support comparative verification.

[0084] 7. Solution Comparison: The incremental maximum operating frequency Fmax model search is compared with traditional median linear search and binary search to verify its advantage of saving more than 50% of system-level testing workload.

[0085] 8. Experimental verification: Using 300 industrial-grade SoC test chips as a sample, the grading accuracy and testing efficiency were verified.

[0086] 9. Effect Confirmation: Summarize the experimental data to confirm the technical advantages and feasibility of the present invention, which features precise grading and high efficiency and energy saving.

[0087] This invention also provides an alternative to the chip sieve grading method, with the following specific steps: 1. Test Data Acquisition Module: Performs data acquisition tasks during the chip probe test (CP) stage and the finished product test (FT) stage, focusing on acquiring 10 selected OSC parameters and temperature calibration parameters to provide basic data for subsequent processing.

[0088] 2. Feature Filtering Process: The collected multidimensional parameters are filtered using a stepwise regression algorithm to remove invalid and redundant features, and to extract the feature parameters that have a core impact on the chip's dynamic voltage frequency adjustment (DVFS) classification.

[0089] 3. Prediction Model Fitting: Based on the core features selected, a chip performance prediction model is constructed using Bayesian linear regression technology to achieve accurate prediction of chip performance under all operating conditions.

[0090] 4. Search algorithm optimization: The incremental maximum working frequency Fmax model search method is applied to optimize the training sample data collection process, shorten the testing time, and solve the problem of low efficiency in traditional search.

[0091] 5. Dynamic Voltage Frequency Adjustment (DVFS) Classification Execution: Based on the output of the prediction model, the chip dynamic voltage frequency adjustment (DVFS) classification is determined to ensure accurate classification results and avoid classifying chips with performance lag into higher speed levels.

[0092] 6. Grading result output: After completing the chip dynamic voltage frequency adjustment (DVFS) grading, the final grading result is output, and relevant test data is recorded simultaneously.

[0093] The chip screening and grading method provided in this embodiment uses traditional median linear search and traditional binary search as comparison groups to statistically analyze the system-level testing workload and compare the energy-saving and high-efficiency advantages of the incremental maximum operating frequency Fmax model search module (which can save more than 50% of the system-level testing workload). Experimental verification: The grading results were experimentally verified based on 300 industrial-grade SoC test chips; Technical effect confirmation: Through experimental output of data such as high classification accuracy and reduced testing workload, the technical feasibility and advantages of the present invention are confirmed.

[0094] This embodiment also provides a chip sieving and grading device, which is used to implement the above embodiments and preferred embodiments, and will not be repeated as described previously. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0095] This embodiment provides a chip sieve grading device, such as... Figure 4 As shown, it includes: The parameter acquisition module 401 is used to acquire multi-dimensional characteristic parameters of the chip during the production and testing phase.

[0096] The prediction module 402 is used to obtain the predicted value of the chip's maximum operating frequency based on multidimensional feature parameters and a trained frequency prediction model; the frequency prediction model is pre-trained based on a regression algorithm.

[0097] The grading module 403 is used to perform dynamic voltage and frequency adjustment grading of the chip based on the predicted value of the maximum operating frequency and a conservative grading strategy.

[0098] In some alternative implementations, the trained frequency prediction model is constructed in the following manner: Multiple training sample chips are collected during the production testing phase, collecting multidimensional feature parameters. System-level testing is performed on the multiple training sample chips to obtain the measured maximum operating frequency of each chip. Using the multidimensional feature parameters of the training sample chips as input and the corresponding measured maximum operating frequency as output, a regression algorithm is used to train a preset basic regression model to obtain a trained frequency prediction model. In one optional implementation, obtaining the measured maximum operating frequency of each training sample chip includes: Load system-level performance test cases and run them on the training sample chips at different voltage levels to test the maximum operating frequency of the training sample chips at each voltage level. Use an incremental maximum operating frequency search method to update the current frequency prediction model during the search process, and use the maximum operating frequency predicted by the updated frequency prediction model as the initial clock frequency for linear search. Gradually approach and lock the maximum operating frequency of each training sample chip to obtain the measured maximum operating frequency of each training sample chip at different voltage levels.

[0099] In one optional implementation, the maximum operating frequency predicted by the updated frequency prediction model is used as the initial clock frequency for the linear search, including: For the first training sample chip, a search is performed using a preset default frequency as the initial clock frequency to obtain the measured value of the maximum operating frequency of the first training sample chip. After obtaining the measured value of the maximum operating frequency of each training sample chip, the current frequency prediction model is updated. The updated frequency prediction model is used to provide an optimized initial clock frequency for the search of the next training sample chip.

[0100] In some alternative implementations, the prediction module 402 includes: The model prediction unit is used to input multidimensional feature parameters into the trained frequency prediction model to obtain the maximum working frequency prediction value output by the frequency prediction model.

[0101] In one alternative implementation, the hierarchical module 403 includes: The grading rule grading unit is used to classify the chip into the corresponding dynamic voltage and frequency adjustment level according to the chip's maximum operating frequency prediction value and preset grading rules.

[0102] In one optional implementation, the hierarchical rule hierarchical unit includes: The standard deviation acquisition subunit is used to obtain the predicted maximum operating frequency of the chip and the standard deviation of the prediction error distribution of the frequency prediction model.

[0103] The conservative estimate calculation subunit is used to calculate a conservative estimate based on the predicted maximum operating frequency of the chip. The conservative estimate is the predicted maximum operating frequency minus the standard deviation of a preset multiple.

[0104] The comparison and classification sub-unit is used to compare the conservative estimate with the frequency threshold corresponding to each dynamic voltage frequency adjustment level; when the conservative estimate falls into the frequency range corresponding to a dynamic voltage frequency adjustment level, the chip is classified into the corresponding dynamic voltage frequency adjustment level.

[0105] The chip sieve grading device provided in this embodiment of the invention can execute the chip sieve grading method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects for executing the method. Further functional descriptions of the various modules and units described above are the same as in the corresponding embodiments described above, and will not be repeated here.

[0106] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0107] The following is a detailed reference. Figure 5The diagram illustrates a structural schematic suitable for implementing an electronic device according to embodiments of the present invention. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 501, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 502 or a program loaded from memory 508 into random access memory (RAM) 503. The RAM 503 also stores various programs and data required for the operation of the electronic device. The processor 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0108] Typically, the following devices can be connected to I / O interface 505: input devices 506 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 507 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 508 including, for example, magnetic tapes, hard disks, etc.; and communication devices 509. Communication device 509 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 5 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0109] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 509, or installed from a memory 508, or installed from a ROM 502. When the computer program is executed by the processor 501, it performs the functions defined in the chip sieving and grading method of the embodiments of the present invention.

[0110] Figure 5 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0111] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the chip grading method shown in the above embodiments is implemented.

[0112] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0113] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A chip sieve grading method, characterized in that, The method includes: Obtain multidimensional characteristic parameters of the chip during the production and testing phase; Based on multidimensional feature parameters and a trained frequency prediction model, the predicted maximum operating frequency of the chip is obtained; the frequency prediction model is pre-trained based on a regression algorithm. Based on the predicted maximum operating frequency, a conservative grading strategy is adopted to dynamically adjust the voltage and frequency of the chip.

2. The method according to claim 1, characterized in that, The trained frequency prediction model is constructed in the following manner: Collect multidimensional feature parameters of multiple training sample chips during the production testing phase; System-level testing was conducted on multiple training sample chips to obtain the measured maximum operating frequency of each training sample chip. Using the multidimensional feature parameters of the training sample chip as input and the corresponding measured maximum operating frequency as output, a regression algorithm is used to train the preset basic regression model to obtain the trained frequency prediction model.

3. The method according to claim 2, characterized in that, The process of obtaining the measured maximum operating frequency of each training sample chip includes: Load system-level performance test cases and run the test cases on the training sample chip at different voltage levels to test the maximum operating frequency of the training sample chip at each voltage level; An incremental maximum operating frequency search method is adopted. During the search process, the current frequency prediction model is updated, and the maximum operating frequency predicted by the updated frequency prediction model is used as the initial clock frequency for linear search. The maximum operating frequency of each training sample chip is gradually approached and locked, and the measured values ​​of the maximum operating frequency of each training sample chip under different voltage levels are obtained.

4. The method according to claim 3, characterized in that, The step of using the maximum operating frequency predicted by the updated frequency prediction model as the initial clock frequency for the linear search includes: For the first training sample chip, a search is performed using a preset default frequency as the initial clock frequency to obtain the measured value of the maximum operating frequency of the first training sample chip. After obtaining the measured maximum operating frequency of each training sample chip, the current frequency prediction model is updated. The updated frequency prediction model is used to provide an optimized initial clock frequency for the search of the next training sample chip.

5. The method according to claim 1, characterized in that, The method for predicting the maximum operating frequency of the chip based on multidimensional feature parameters and a trained frequency prediction model includes: The multidimensional feature parameters are input into the trained frequency prediction model to obtain the maximum operating frequency prediction value output by the frequency prediction model.

6. The method according to claim 1, characterized in that, The method of employing a conservative grading strategy to dynamically adjust the voltage and frequency of the chip includes: Based on the predicted maximum operating frequency of the chip, the chip is classified into the corresponding dynamic voltage and frequency adjustment level according to the preset classification rules.

7. The method according to claim 6, characterized in that, The step of classifying the chip into a corresponding dynamic voltage frequency adjustment level according to a preset classification rule includes: Obtain the predicted maximum operating frequency of the chip and the standard deviation of the prediction error distribution of the frequency prediction model; Based on the predicted maximum operating frequency of the chip, a conservative estimate is calculated, wherein the conservative estimate is the predicted maximum operating frequency minus the standard deviation of a preset multiple. The conservative estimate is compared with the frequency threshold corresponding to each dynamic voltage frequency adjustment level; When the conservative estimate falls within the frequency range corresponding to a dynamic voltage frequency adjustment level, the chip is classified into the corresponding dynamic voltage frequency adjustment level.

8. A chip sieve grading device, characterized in that, The device includes: The parameter acquisition module is used to acquire multi-dimensional characteristic parameters of the chip during the production and testing phase. The prediction module is used to obtain the predicted maximum operating frequency of the chip based on multidimensional feature parameters and a trained frequency prediction model; the frequency prediction model is pre-trained based on a regression algorithm. The grading module is used to perform dynamic voltage and frequency adjustment grading of the chip based on the predicted maximum operating frequency value and using a conservative grading strategy.

9. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory storing computer instructions, and the processor executing the computer instructions to perform the chip sieving and grading method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the chip sieving and grading method according to any one of claims 1 to 7.

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