A deep learning kernel fusion method and device based on image-driven analysis

Abstract

The application discloses a deep learning kernel fusion method and device based on portrait driving analysis, and belongs to the technical field of automatic code generation. The method comprises the following steps: obtaining a computation graph representation of a to-be-optimized deep learning model, performing conflict and dependency analysis, and obtaining a candidate fusion subgraph; performing benefit-driven cost evaluation on the candidate fusion subgraph to obtain a high-value candidate subgraph set; constructing a structured code generation context for the high-value candidate subgraph, calling a large language model to generate candidate fusion kernel code; performing correctness verification, portrait feedback and iterative repair on the candidate fusion kernel code, and outputting a target fusion kernel that passes the verification. The application can improve the fusion success rate under the premise of guaranteeing semantic correctness, reduce the performance loss caused by intermediate tensor materialization, register overflow and memory access mismatch, and is suitable for deep learning compilation and inference optimization scenes such as PyTorch and Triton.

Description

Technical Field

[0001] This invention relates to the fields of deep learning compilation optimization, program analysis and automatic code generation technology, and in particular to a deep learning kernel fusion method and apparatus based on profile-driven analysis. Background Technology

[0002] With the widespread deployment of deep learning models in training and inference scenarios, model execution efficiency is increasingly constrained by storage bandwidth and data transfer overhead. For models consisting of convolution, normalization, activation, matrix multiplication, element-wise operations, and reduction operations, arithmetic computation itself is not the only bottleneck. Frequent global memory access, kernel startup overhead, and repeated materialization of intermediate tensors often consume a significant amount of runtime. Kernel fusion, by merging multiple adjacent operators into a single execution unit, can reduce intermediate tensor write-backs and re-reads, improving the reuse rate of registers or on-chip memory, and is therefore considered a key means to alleviate the "memory wall."

[0003] However, existing fusion techniques still have significant shortcomings. Traditional rule-driven compilers typically perform fusion based on fixed patterns or simple heuristics, making it difficult to fully consider the complex hardware-level effects such as tensor lifetime overlap, register pressure, occupancy decline, and cache contention. When dealing with irregular subgraphs, cross-reduction boundaries, or multi-branch dependency structures, excessive fusion may actually increase peak memory usage or even cause register overflows. On the other hand, while large language models have gained some GPU code generation capabilities in recent years, without a clear execution context and hardware constraints, the generated results often suffer from problems such as being uncompileable, having inefficient memory access patterns, or experiencing performance degradation.

[0004] Therefore, there is an urgent need for a deep learning kernel fusion scheme that can simultaneously combine graph-level structure analysis, runtime hardware profiling, and large language model code generation capabilities, so that the fusion decision is not only semantically valid, but also achievable, verifiable, and iteratively optimized on specific hardware. Summary of the Invention

[0005] The purpose of this invention is to provide a deep learning kernel fusion method and apparatus based on profile-driven analysis, so as to solve the problems in the prior art where fusion decisions rely on static heuristics, it is difficult to effectively characterize hardware feasibility, and generative code lacks verification feedback.

[0006] The objective of this invention is achieved through the following technical solution: a deep learning kernel fusion method based on profile-driven analysis, comprising the following steps:

[0007] (1) Obtain the computation graph representation of the deep learning model to be optimized, and perform conflict and dependency analysis on the computation graph to identify candidate fusion subgraphs;

[0008] (2) Perform a benefit-driven cost evaluation on the candidate fusion subgraphs, and take the ones that pass the evaluation as high-value candidate subgraphs to obtain a set of high-value candidate subgraphs;

[0009] (3) Construct a structured code generation context for the high-value candidate subgraph and call the large language model to generate candidate fusion kernel code;

[0010] (4) Verify the correctness of the candidate fusion kernel code, provide profile feedback and iterative repair, and output the target fusion kernel that has passed the verification.

[0011] Further, step (1) includes: sinking the deep learning model to be optimized into a directed acyclic graph, where nodes represent atomic operators and edges represent tensor dependencies; maintaining the active subgraph in topological order, and simultaneously checking semantic closure constraints and resource capacity constraints when merging subsequent nodes; if the temporary subgraph obtained after merging the subsequent nodes satisfies both the semantic closure constraints and the resource capacity constraints, then absorbing the subsequent nodes into the current candidate subgraph; if the temporary subgraph does not satisfy the semantic closure constraints or the resource capacity constraints, then determining the current candidate subgraph before merging as a candidate fusion subgraph, and reconstructing the current candidate subgraph with the subsequent nodes; wherein, if the tensors generated by the nodes inside the active subgraph are consumed by the non-output nodes outside the subgraph, it is determined that the semantic closure constraints are not satisfied.

[0012] Furthermore, the resource capacity constraints include setting upper limits on the number of operators, fusion depth, or estimated complexity in the active subgraph to pre-eliminate high-risk fusion regions with excessive register pressure, decreased thread concurrency, or excessive shared storage before code generation.

[0013] Further, step (2) includes: identifying a set of intermediate tensors that can be eliminated materialized within the candidate fusion subgraph, wherein the set of intermediate tensors includes tensors generated and consumed within the candidate fusion subgraph and not output as part of the candidate fusion subgraph; for any intermediate tensor in the set of intermediate tensors, estimating the global memory write-back and global memory read traffic generated by the intermediate tensor during non-fusion execution based on the byte size of the intermediate tensor and the number of times it is consumed within the candidate fusion subgraph, and summing the traffic corresponding to each intermediate tensor to obtain the predicted eliminateable memory traffic B. pred ; Construct a non-integrated execution baseline and collect runtime profile metrics, wherein the profile metrics include at least GPU time T. base Global storage access bytes V mem Thread register count R reg Achieve occupancy rate of 0 occ and storage throughput BW util Based on the prediction, storage traffic B can be eliminated. predWith the storage throughput BW util Estimated expected execution time T after fusion est And based on GPU time T base Expected execution time T after fusion est The ratio determines the fusion yield, and candidate fusion subgraphs whose fusion yield meets the first threshold and are not high-risk candidates are selected as high-value candidate subgraphs.

[0014] Furthermore, the high-risk candidates include the following information: the number of thread registers in baseline execution exceeds the second threshold, the implementation occupancy rate is lower than the third threshold, or they belong to a duplicate subgraph determined by structure hashing and have historical profile results.

[0015] Further, in step (3), the structured code generation context includes the following information: subgraph logic code re-emitted based on intermediate representation, shape and step size information of input tensors, model parameter specification information, fusion scheduling constraints, hardware profile indicators and target backend description; the large language model outputs a fusion kernel compatible with the target deep learning framework and its calling interface based on the structured code generation context.

[0016] Furthermore, step (4) includes: constructing a two-layer verification feedback mechanism, specifically:

[0017] The first layer verifies the numerical correctness, materialization degree, and local storage access status of the candidate fusion kernels to determine whether the predicted intermediate tensor traffic reduction is implemented in hardware. The materialization degree (MRS) is calculated based on the global storage access bytes V of the non-fusion execution baseline. base Number of bytes of global storage access performed after merging, V fused The difference, relative to the predicted eliminateable storage traffic B pred With the preset normalization lower limit B floor The ratio of the larger value is calculated; when the materialized realization degree MRS reaches the fourth threshold and the local storage access volume is lower than the fifth threshold, the second layer of verification is entered.

[0018] The second layer continues to detect the actual acceleration effect and memory access efficiency after passing the first layer, and generates repair feedback based on the failure mode attribution results to drive the large language model to iteratively rewrite the fusion kernel code; wherein, the failure mode includes at least one or more of semantic materialization failure, register overflow failure, memory access merging failure and cost model mismatch.

[0019] This invention also provides a deep learning kernel fusion device based on profile-driven analysis, comprising:

[0020] The candidate subgraph identification module is used to obtain the computation graph representation of the deep learning model to be optimized, and to perform conflict and dependency analysis on the computation graph to identify candidate fusion subgraphs.

[0021] The revenue and risk assessment module is used to perform revenue-driven cost assessment on the candidate fusion subgraphs, and to obtain a set of high-value candidate subgraphs by taking those that pass the assessment as high-value candidate subgraphs.

[0022] The context construction and code generation module is used to construct a structured code generation context for the high-value candidate subgraph and call a large language model to generate candidate fusion kernel code.

[0023] The verification feedback module is used to verify the correctness of the candidate fusion kernel code, provide profile feedback and iterative repair, and output the target fusion kernel that has passed the verification.

[0024] The present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the method when executing the computer program.

[0025] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described thereon.

[0026] Compared with the prior art, the present invention has at least the following beneficial effects:

[0027] 1. Use semantic closure constraints and resource capacity constraints to jointly limit the fusion space, avoiding blindly expanding the fusion scope solely from the perspective of graph structure;

[0028] 2. Incorporating intermediate tensors into the revenue assessment can eliminate profiling metrics such as flow rate, register pressure, and occupancy rate, thereby improving the accuracy of candidate selection;

[0029] 3. By explicitly injecting IR logic, tensor metadata, and hardware information into the large language model through structured context, semantic ambiguity and resource mismatch in the generated code are reduced;

[0030] 4. A two-layer verification feedback mechanism based on materialized realization degree MRS and local storage access monitoring is proposed, further constraining "theoretically fusionable" to "hardware implemented and with practical benefits";

[0031] 5. It can attribute semantic materialization failure, register overflow failure, memory access merging failure, and cost model mismatch to the cause, providing a clear direction for fusion repair. Attached Figure Description

[0032] Figure 1 This is a flowchart illustrating the overall process framework of the method of this invention.

[0033] Figure 2 This is a schematic diagram of candidate subgraph selection and context construction in this invention;

[0034] Figure 3 This is a flowchart illustrating the verification feedback and failure mode attribution process for this invention. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0036] like Figure 1 As shown in the figure, this invention proposes a deep learning kernel fusion method based on profile-driven analysis, which generally includes four stages: candidate subgraph identification, benefit and risk assessment, context construction and fusion code generation, and verification feedback and optimal implementation output. Specifically, it includes:

[0037] Phase 1, Candidate Subgraph Identification: The deep learning model and its corresponding computational graph representation are received. Subsequently, conflict and dependency analysis is performed on the computational graph to identify candidate fusion subgraphs, which represent the fusion region to be expanded.

[0038] Preferably, deep learning models can be subdivided into directed acyclic graphs using FX tracing, Torch IR, or other intermediate representations. Each node in the graph represents an atomic operator such as convolution, normalization, activation, element-wise operation, matrix multiplication, or reduction, and each side represents the production-consumption relationship between tensors.

[0039] Phase Two: Benefit and Risk Assessment: For each candidate fusion subgraph, a non-fusion execution baseline is constructed. Profiling indicators such as GPU time, memory traffic, register count, utilization rate, and storage throughput are collected to estimate the potential benefits before and after fusion. Candidates with high register risk or insufficient benefits are screened out to obtain high-value candidate subgraphs.

[0040] Phase 3, Context Construction and Fusion Code Generation: Based on the selected high-value candidate subgraphs, structured prompts are constructed and used as context input to the large language model to generate fusion kernel code and wrapper interfaces for the target backend.

[0041] Phase 4, Verification Feedback and Optimal Implementation Output: First, verify whether the generated fusion kernel truly reduces intermediate tensor materialization and local storage overflow, and then further examine whether it delivers the expected acceleration; if the conditions are not met, generate repair feedback in failure mode and drive regeneration until a verified high-performance fusion implementation is obtained or the stopping conditions are met.

[0042] In a preferred embodiment, such as Figure 2 As shown, in order to avoid resource mismatch caused by unconstrained fusion, this invention considers both structural legality and hardware feasibility in the candidate subgraph identification stage.

[0043] On the one hand, semantic closure constraints are used to suppress semantic materialization failures. For any internal node in the active subgraph, if its generated tensor is still consumed by non-output nodes outside the subgraph, it means that the tensor must remain visible outside the fusion region, making it difficult to completely eliminate its intermediate materialization. In this case, the node is not considered a valid candidate for combination. This constraint ensures that most intermediate tensors inside the subgraph can be locally stored in registers or shared memory after fusion.

[0044] On the other hand, resource capacity constraints are used to suppress register overflow failures. In a preferred implementation, an upper limit can be set on the number of operators in the candidate subgraph, for example, no more than 20; alternatively, indicators such as operator type weight, reduction depth, tensor shape complexity, or estimated shared storage requirements can be introduced to set a complexity threshold for the active subgraph. When attempting to absorb subsequent nodes according to the topological order, if the temporary subgraph obtained after absorbing the subsequent node does not exceed the complexity threshold, the expansion is accepted; if the temporary subgraph exceeds the complexity threshold, the expansion is abandoned, and the current candidate subgraph that still satisfies the resource capacity constraint before expansion is determined as the candidate fusion subgraph. Through this constraint, high-risk fusion regions with excessive register pressure, decreased thread concurrency, or shared storage exceeding limits are pre-eliminated before code generation.

[0045] In a preferred embodiment, during the benefit and risk assessment phase, the set of intermediate tensors within the candidate fusion subgraph that are produced and consumed only within the subgraph is first identified, and the eliminateable flow B is estimated accordingly. pred Subsequently, key metrics M={T} were collected by executing a non-fusion baseline and invoking hardware profiling tools. base V mem ,R reg O occ BW util}, where T base Indicates GPU time, V mem Represents the number of bytes accessed globally, R reg Indicates the number of thread registers, O occ Indicates the utilization rate, BW utilThis represents storage throughput. Based on the aforementioned key metrics, the fusion benefit can be estimated in the following form: T est ≈T base -B pred / BW util Furthermore, the register threshold and occupancy rate threshold are combined to form a fusion judgment condition. If a candidate meets the revenue threshold and is not a high-risk object, it is judged as a high-value candidate subgraph and enters the subsequent code generation stage.

[0046] In practical engineering, isomorphic subgraphs may appear repeatedly in multi-layer networks. To reduce the cost of repeated profiling, structural hashes can be calculated for candidate subgraphs, and existing profiling results can be reused for subgraphs that have already been analyzed, thereby improving the overall efficiency of the process.

[0047] like Figure 2 As shown, this invention does not directly input the original source code into the large language model, but rather preferably re-emits Python logic based on the intermediate representation, making operator calls, parameter dependencies, data flow direction and tensor read / write boundaries clear.

[0048] In a preferred embodiment, the structured context constructed based on high-value candidate subgraphs includes at least the following:

[0049] (1) IR-level logic code, used to describe the operator sequence and data flow of the candidate subgraph;

[0050] (2) Input tensor shape, stride, layout and necessary data type information to support the model's understanding of continuous memory access methods;

[0051] (3) Specifications of weight, bias or other parameter tensors, used to constrain parameter indexing methods;

[0052] (4) Key indicators and fusion constraints from profile analysis are used to prompt the model to pay attention to registers, occupancy rate and memory access overhead;

[0053] (5) Target backend description, such as the target being a Triton kernel, PyTorch extension or other framework compatible implementation.

[0054] Based on the above context, the large language model generates fusion kernel code and corresponding wrapper call code. The generation goal is not simply to make the code "runnable," but rather to maintain intermediate tensors residing in registers or shared memory within the kernel as much as possible, reducing the number of global memory accesses. By structuring the prompt content, this invention can significantly reduce fusion boundary errors, parameter indexing errors, and inefficient memory access patterns caused by incomplete context in the large language model.

[0055] In a preferred embodiment, such as Figure 3As shown, this invention does not directly accept the fusion result after code generation, but instead uses a two-layer verification feedback mechanism to verify the feasibility of the result.

[0056] The first layer is implementation verification. The materialization implementation measure (MRS) is calculated by comparing the number of global memory access bytes for non-fused and fused executions. If the MRS reaches a preset threshold and `local_bytes` is detected as zero or below the allowed threshold, it indicates that the predicted intermediate tensor flow reduction has been largely implemented in hardware, and no significant register overflow has occurred. If the requirements are not met, repair feedback is generated based on the exception type: when `local_bytes` is too high, suggestions are made to reduce the tile size, decrease the thread block size, or simplify the intermediate variable lifecycle; when the MRS is too low, suggestions are made to check candidate subgraph boundaries and eliminate unexpected intermediate tensor materialization.

[0057] The second layer focuses on performance optimization. For fusion kernels that have passed the first layer, the actual speedup ratio is further compared with the predicted gains. If the MRS is high but the actual speedup is insufficient, the problem may not lie in the semantic implementation, but rather in a deviation between the memory access pattern or cost model and the actual hardware performance. In this case, failure mode attribution is performed based on performance counters: if poor memory access merging efficiency or excessive cache transactions are found, it is attributed to memory access merging failure, and the model is fed back to reconstruct the access order; if storage throughput, concurrency, etc., deviate significantly from the prediction, it is attributed to cost model mismatch, and the model is fed back to try a new automatic parameter tuning configuration. It is possible to terminate the iteration when the gains from two consecutive rounds are less than a preset threshold.

[0058] This invention also provides a deep learning kernel fusion device based on profile-driven analysis. The device can be integrated as part of a compiler plugin, graph optimization module, or model deployment toolchain, or provided as a standalone service. The device includes at least:

[0059] The candidate subgraph recognition module is used to obtain the computation graph representation of the deep learning model to be optimized, and to perform topological traversal, constraint checking and candidate region division on the computation graph.

[0060] The revenue and risk assessment module is used to perform revenue-driven cost assessment on the candidate fusion subgraphs to obtain a set of high-value candidate subgraphs. The assessment includes identifying intermediate tensors, calculating eliminable traffic, and collecting runtime profile data.

[0061] The context construction and code generation module is used to construct a structured code generation context for the high-value candidate subgraph and call a large language model to generate candidate fusion kernel code.

[0062] The verification feedback module is used to perform correctness verification, MRS calculation, failure mode attribution, and iterative repair control on the candidate fusion kernel code, and output the target fusion kernel that has passed the verification.

[0063] If a candidate program fails in the verification feedback and optimal implementation output stage, it returns to the code generation stage to search again; if the maximum number of search attempts is reached, the fusion subgraph is automatically abandoned to ensure stable system operation.

[0064] The present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor, when executing the computer program, implements the method described in any embodiment.

[0065] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in any embodiment.

[0066] The computer-readable storage medium can be an internal storage unit of any data processing device described in any of the foregoing embodiments, such as a hard disk or memory. The computer-readable storage medium can also be any data processing device, such as a plug-in hard disk, smart media card (SMC), SD card, flash card, etc., equipped on the device. Furthermore, the computer-readable storage medium can include both internal storage units of any data processing device and external storage devices. The computer-readable storage medium is used to store the computer program and other programs and data required by the data processing device, and can also be used to temporarily store data that has been output or will be output. The deep learning kernel fusion method and apparatus based on image-driven analysis provided by this invention can be directly applied to scenarios such as deep learning compilation optimization, operator execution optimization, model inference acceleration, and training performance improvement, and has clear industrial applicability.

[0067] Specifically, this invention is applicable to the following scenarios, including but not limited to:

[0068] 1. Deep learning framework optimization scenarios

[0069] It can be deployed in deep learning compilers, graph optimization engines, or runtime systems to automatically analyze, fuse, and verify candidate operator subgraphs in computation graphs, thereby improving model execution efficiency.

[0070] 2. Accelerating Model Training and Inference Scenarios

[0071] It is suitable for convolutional neural networks, Transformer-type models, multimodal models and other deep learning tasks that involve a large number of combinations of basic operators, and is especially suitable for automatic fusion optimization of hot operator sequences during training or inference.

[0072] 3. Multiple hardware platform adaptation scenarios

[0073] This invention can adjust the fusion strategy according to the parallel computing characteristics, storage hierarchy and resource constraints of different hardware platforms. It is applicable to GPUs, AI accelerators and other processing devices that support parallel computing, and has good platform scalability.

[0074] 4. Automatic code generation and intelligent optimization scenarios

[0075] This invention combines profile-driven analysis with large language model generation capabilities, which reduces reliance on human experience, lowers the development threshold of high-performance fusion kernels, and is suitable for engineering environments that require rapid generation, iteration, and verification optimization.

[0076] 5. High-reliability execution scenarios

[0077] This invention introduces a high-precision verification, anomaly identification, and failure rollback mechanism. Even if the candidate fusion scheme is unstable or unsuitable, the original task can still be executed correctly through the rollback path. Therefore, it is suitable for industrial application environments with high requirements for stability and correctness.

[0078] In summary, this invention can improve the automation and execution performance of deep learning operator fusion while ensuring the correctness of the results and the stability of the system. It can be mass-produced, repeatedly deployed, and directly used in actual engineering systems, thus possessing outstanding industrial practical value.

[0079] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process may be rearranged without departing from the scope of this disclosure. The appended method claims provide elements of various steps in an exemplary order and are not intended to limit the scope to the specific order or hierarchy described.

Claims

1. A deep learning kernel fusion method based on profile-driven analysis, characterized in that, Includes the following steps: (1) Obtain the computation graph representation of the deep learning model to be optimized, and perform conflict and dependency analysis on the computation graph to identify candidate fusion subgraphs; (2) Perform a benefit-driven cost evaluation on the candidate fusion subgraphs, and designate those that pass the evaluation as high-value candidate subgraphs to obtain a set of high-value candidate subgraphs; including: identifying a set of intermediate tensors that can be eliminated and materialized within the candidate fusion subgraphs, wherein the set of intermediate tensors includes tensors generated within the candidate fusion subgraphs and consumed within the candidate fusion subgraphs, and not output as candidate fusion subgraphs; for any intermediate tensor in the set of intermediate tensors, estimate the global storage generated by the intermediate tensor in non-fusion execution based on the byte size of the intermediate tensor and the number of times it is consumed within the candidate fusion subgraphs. The write-back and global storage read traffic are calculated, and the traffic corresponding to each intermediate tensor is summed to obtain the predicted eliminateable storage traffic. A non-fusion execution baseline is constructed, and runtime profile indicators are collected. The profile indicators include at least GPU time, global storage access bytes, thread register count, implementation utilization, and storage throughput. The expected execution time after fusion is estimated based on the predicted eliminateable storage traffic and the storage throughput, and the fusion benefit is determined based on the ratio of GPU time to the expected execution time after fusion. Candidate fusion subgraphs that meet the first threshold of fusion benefit and are not high-risk candidates are designated as high-value candidate subgraphs. (3) Construct a structured code generation context for the high-value candidate subgraph and call the large language model to generate candidate fusion kernel code; (4) Perform correctness verification, profile feedback, and iterative repair on the candidate fusion kernel code, and output the target fusion kernel that has passed the verification; wherein, step (4) includes constructing a two-layer verification feedback mechanism, specifically: The first layer performs materialization implementation verification and local storage access detection on candidate fusion kernels to determine whether the predicted intermediate tensor traffic reduction is implemented in hardware. The materialization implementation score (MRS) is calculated as the ratio of the difference between the global storage access bytes of the non-fusion execution baseline and the global storage access bytes of the fusion execution, relative to the larger value among the predicted eliminateable storage traffic and the preset normalized lower limit. When the materialization implementation score (MRS) reaches the fourth threshold and the local storage access volume is lower than the fifth threshold, the second layer of verification is initiated. The second layer continues to detect the actual acceleration effect and memory access efficiency after passing the first layer, and generates repair feedback based on the failure mode attribution results to drive the large language model to iteratively rewrite the fusion kernel code; wherein, the failure mode includes at least one or more of semantic materialization failure, register overflow failure, memory access merging failure and cost model mismatch.

2. The method according to claim 1, characterized in that, Step (1) includes: sinking the deep learning model to be optimized into a directed acyclic graph, where nodes represent atomic operators and edges represent tensor dependencies; maintaining the active subgraph according to the topological order, and checking semantic closure constraints and resource capacity constraints when merging subsequent nodes; if the temporary subgraph obtained after merging the subsequent nodes satisfies both the semantic closure constraints and the resource capacity constraints, then absorbing the subsequent nodes into the current candidate subgraph; if the temporary subgraph does not satisfy the semantic closure constraints or the resource capacity constraints, then determining the current candidate subgraph before merging as the candidate fusion subgraph, and reconstructing the current candidate subgraph with the subsequent nodes; wherein, if the tensors generated by the nodes inside the current candidate subgraph are consumed by the non-output nodes outside the subgraph, it is determined that the semantic closure constraints are not satisfied.

3. The method according to claim 2, characterized in that, The resource capacity constraints include setting upper limits on the number of operators, fusion depth, or estimated complexity in the active subgraph to pre-eliminate high-risk fusion regions with excessive register pressure, decreased thread concurrency, or excessive shared storage before code generation.

4. The method according to claim 1, characterized in that, The high-risk candidates include at least one of the following: the number of thread registers in the baseline execution exceeds the second threshold, the implementation occupancy rate is lower than the third threshold, or it belongs to a duplicate subgraph determined by structure hashing and has a historical profile result.

5. The method according to claim 1, characterized in that, In step (3), the structured code generation context includes the following information: subgraph logic code re-emitted based on intermediate representation, shape and step size information of input tensors, model parameter specification information, fusion scheduling constraints, hardware profile indicators and target backend description; the large language model outputs a fusion kernel compatible with the target deep learning framework and its calling interface based on the structured code generation context.

6. A deep learning kernel fusion device based on image-driven analysis, used to implement the method according to any one of claims 1-5, characterized in that, include: The candidate subgraph identification module is used to obtain the computation graph representation of the deep learning model to be optimized, and to perform conflict and dependency analysis on the computation graph to identify candidate fusion subgraphs. The revenue and risk assessment module is used to perform revenue-driven cost assessment on the candidate fusion subgraphs, and to obtain a set of high-value candidate subgraphs by taking those that pass the assessment as high-value candidate subgraphs. The context construction and code generation module is used to construct a structured code generation context for the high-value candidate subgraph and call a large language model to generate candidate fusion kernel code. The verification feedback module is used to verify the correctness of the candidate fusion kernel code, provide profile feedback and iterative repair, and output the target fusion kernel that has passed the verification.

7. An electronic device, characterized in that, The method includes a memory and a processor, wherein the memory stores a computer program, and the processor, when executing the computer program, implements the method according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1 to 5.

Images