A radio frequency diode parameter extraction method based on a heterogeneous integrated micro-assembly package

Abstract

The application discloses a radio frequency diode parameter extraction method based on a heterogeneous integrated micro-assembly package, and relates to the field of semiconductor device packaging. The method comprises the following steps: providing a heterogeneous integrated micro-assembly package structure, testing a radio frequency diode die in the package structure, and extracting direct-current static parameters according to a measurement result; performing three-dimensional electromagnetic simulation on the package structure to obtain parasitic parameters; designing a rectifier circuit based on the direct-current static parameters and the parasitic parameters; performing physical testing and circuit simulation on the rectifier circuit to obtain actual measurement results and simulation results; taking the simulation results approximating the actual measurement results as an optimization target, iteratively optimizing the direct-current static parameters and the parasitic parameters by using a grey wolf optimization algorithm, and outputting the optimized parameters. The application can accurately obtain the parameters of an equivalent circuit model of a radio frequency diode.

Description

Technical Field

[0001] This application relates to the field of semiconductor device packaging, and in particular to a method for extracting parameters of radio frequency diodes based on heterogeneous integrated micro-assembly packaging. Background Technology

[0002] With the rapid development of Wireless Power Transfer (WPT) technology, higher demands are being placed on the energy conversion efficiency of rectifier circuits. As a core component of rectifier circuits, the Schottky barrier diode (SBD) directly affects the overall performance of the rectifier circuit due to its radio frequency (RF) characteristics. Therefore, accurately obtaining the high-frequency equivalent circuit model parameters of the SBD is crucial for reducing circuit design deviations and achieving high-performance WPT systems.

[0003] However, in practical applications, SBDs typically operate in high-frequency environments, where the devices exhibit significant nonlinear characteristics. Traditional SBD model parameter extraction methods are mostly based on static or low-frequency measurement data, which cannot accurately reflect the device behavior at high frequencies. This leads to a large deviation between the model parameters and actual characteristics, thus affecting the design accuracy and efficiency of the rectifier circuit. Furthermore, related parameter extraction methods often ignore parasitic parameters introduced by the package structure, which further increases the inaccuracy of the model.

[0004] In addition, the related technologies also have the following drawbacks: The parameter extraction conditions do not match the actual working conditions: most of the relevant methods extract SBD model parameters based on static or low-frequency measurement results, without considering the nonlinear characteristics of the device under high-frequency working conditions, which makes the model unable to accurately characterize the SBD behavior under high-frequency conditions.

[0005] Insufficient research on key parameters: There is a lack of in-depth research on the nonlinear changes of parameters such as nonlinear junction capacitance and series resistance at high frequencies, making it impossible to accurately describe the impact mechanism of these parameters on the performance of rectifier circuits.

[0006] No clear error accuracy indicators: The relevant extraction methods do not provide clear model error accuracy, resulting in poor energy conversion efficiency of rectifier circuits designed based on these parameters, making it difficult to meet the high-performance requirements of wireless power transmission systems.

[0007] Iterative optimization is inefficient: some methods require repeated fitting to obtain parameters, resulting in long design cycles, poor timeliness, and an inability to meet the needs of efficient circuit development.

[0008] Therefore, there is an urgent need for a method that can accurately extract the parameters of the SBD high-frequency equivalent circuit model to meet the design requirements of high-performance rectifier circuits. Summary of the Invention

[0009] The purpose of this application is to provide a method for extracting parameters of RF diodes based on heterogeneous integrated micro-assembly packaging. This method considers the parasitic parameters introduced by the packaging structure, significantly improves the accuracy of parameter extraction, and thus reduces circuit design deviations.

[0010] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides a method for extracting parameters of a radio frequency diode based on heterogeneous integrated micro-assembly packaging, including: A heterogeneous integrated micro-assembly packaging structure is provided, the packaging structure including a radio frequency diode die, a SiP substrate, gold wires connecting the radio frequency diode die to the radio frequency circuit on the SiP substrate, and a metal cap sealing the SiP substrate. The RF diode die in the package structure is tested, and the DC static parameters are extracted based on the measurement results; The parasitic parameters introduced by the packaging structure are obtained by performing a three-dimensional electromagnetic simulation using electromagnetic simulation software. Based on the DC static parameters and the parasitic parameters, an equivalent circuit model of the RF diode is constructed, and a rectifier circuit is designed according to the equivalent circuit model. The rectifier circuit was subjected to physical testing and circuit simulation to obtain the measured load rectification efficiency curve, the measured load reflectivity efficiency curve, the simulated load rectification efficiency curve, and the simulated load reflectivity efficiency curve. With the goal of approximating the measured load rectification efficiency curve and the simulated load reflectivity efficiency curve approximating the measured load reflectivity efficiency curve, the Grey Wolf optimization algorithm is used to iteratively optimize the DC static parameters and the parasitic parameters, and the optimized parameters are output.

[0011] Optionally, the diameter of the gold wire is 20μm to 30μm, the span is 100μm to 200μm, and the highest point of the arc is 50μm to 150μm from the surface of the SiP substrate.

[0012] Optionally, the parasitic parameters include grounding capacitance; the DC static parameters include series resistance, saturation current, ideality factor, zero-bias junction capacitance, built-in potential, and power exponent. With the optimization objectives of approximating the measured load rectification efficiency curve and the simulated load reflectivity efficiency curve approximating the measured load reflectivity efficiency curve, the Grey Wolf optimization algorithm is used to iteratively optimize the DC static parameters and the parasitic parameters, outputting the optimized parameters, specifically including: Step A: Initialize the gray wolf population, divide the population into a positive parameter subgroup and a capacitance parameter subgroup, and set the population size and maximum number of iterations; each individual in the positive parameter subgroup includes series resistance, saturation current and ideality factor, and each individual in the capacitance parameter subgroup includes ground capacitance, zero bias junction capacitance, built-in potential and power exponent. Step B: Perform circuit simulation for each individual in the positive parameter subgroup and the capacitance parameter subgroup respectively: For an individual in the positive parameter subgroup, obtain the simulated load rectification efficiency curve based on the parameters represented by that individual, and calculate the fitting error between it and the measured load rectification efficiency curve as the fitness value of that individual; For an individual in the capacitance parameter subgroup, obtain the simulated load reflectivity efficiency curve based on the parameters represented by that individual, and calculate the fitting error between it and the measured load reflectivity efficiency curve as the fitness value of that individual; Step C: Based on the fitness values ​​from largest to smallest, divide the individuals in the positive parameter subgroup and the capacitance parameter subgroup into four levels: α wolf, β wolf, δ wolf and ω wolf; Step D: For the current positive parameter subgroup, based on the individual positions of α wolf, β wolf, and δ wolf, update the individual position of ω wolf according to the position update formula of the gray wolf algorithm to generate a new generation of positive parameter subgroup; In the contemporary capacitance parameter subgroup, based on the individual positions of α wolf, β wolf, and δ wolf, the individual position of ω wolf is updated according to the position update formula of the gray wolf algorithm to generate a new generation of capacitance parameter subgroup; Step E: Repeat steps B to D until the maximum number of iterations is reached or the optimal fitness value of each subgroup is less than the preset error threshold, then stop the iteration; Step F: Output the parameters represented by αwolf in the positive parameter subgroup as optimized positive parameters, and the parameters represented by αwolf in the capacitance parameter subgroup as optimized capacitance parameters.

[0013] Optionally, the position update formula of the Grey Wolf algorithm specifically includes: Step D1: Calculate the convergence factor based on the current iteration number, and calculate the first coefficient vector and the second coefficient vector based on the convergence factor; Step D2: Based on the first coefficient vector, calculate the distance between the individual corresponding to the current ω wolf and the individuals corresponding to α wolf, β wolf, and δ wolf respectively; Step D3: Based on the second coefficient vector and the distance, calculate the candidate positions for the individual corresponding to the current ω wolf to move towards the individuals corresponding to the α wolf, β wolf, and δ wolf, respectively; Step D4: Calculate the average of the candidate positions that the individual corresponding to the current ω wolf can move to towards the individuals corresponding to the α, β, and δ wolves, and use the average value as the updated position of the individual corresponding to the current ω wolf.

[0014] Alternatively, the convergence factor can be calculated using the following formula: ; Where t is the current iteration number, T max The maximum number of iterations, is the convergence factor.

[0015] Optionally, the first coefficient vector and the second coefficient vector can be calculated using the following formula: ; ; in, , A random number within the interval [0,1]. This is the first coefficient vector. This is the second coefficient vector. is the convergence factor.

[0016] Optionally, the SiP substrate has a heat dissipation area, and the RF diode die is fixed to the heat dissipation area by a thermally conductive adhesive material. The heat dissipation area is electrically connected to the ground layer of the SiP substrate.

[0017] Optionally, the DC static parameters include series resistance, saturation current, ideality factor, zero-bias junction capacitance, built-in potential, and power exponent. The RF diode die in the package structure is tested, and the DC static parameters are extracted based on the measurement results, specifically including: A forward current-voltage test is performed on the RF diode die in the package structure to obtain multiple voltage values ​​and their corresponding current values. Based on the electron emission relation, the voltage and current values ​​are fitted using the least squares method to obtain a forward current-voltage fitting curve, and the parameters in the electron emission relation are solved. The parameters include series resistance, ideality factor, and saturation current. A capacitance-voltage test is performed on the RF diode die in the package structure to obtain multiple voltage values ​​and their corresponding capacitance values. Based on the relationship between junction capacitance and bias voltage, the voltage and capacitance values ​​are fitted using the orthogonal distance regression method to obtain a capacitance-voltage curve. The parameters in the relationship between junction capacitance and bias voltage are then solved. The parameters include zero bias junction capacitance, built-in potential, and power exponent.

[0018] Optionally, the electron emission equation is: ; Where I is the forward current; I s q is the saturation current; q is the electron charge; V is the bias voltage applied across the RF diode; R sis the series resistance; N is the ideality factor; K is the Boltzmann constant; T is the absolute temperature.

[0019] Optionally, the relationship between the junction capacitance and the bias voltage is as follows: ; Among them, C j For junction capacitance; C j0 V is the zero-bias junction capacitance, i.e., the junction capacitance when the bias voltage V=0; V is the bias voltage applied across the RF diode; V j M represents the built-in potential; M is the power exponent.

[0020] According to the specific embodiments provided in this application, this application has the following technical effects: This application provides a method for extracting parameters of a radio frequency diode based on heterogeneous integrated micro-assembly packaging. First, this application extracts parameters by matching actual working conditions: considering the nonlinear characteristics of the radio frequency diode under high-frequency working conditions, by combining measured data with electromagnetic simulation, the model parameters of the radio frequency diode operating at high frequency can be extracted more accurately, thereby alleviating the problem of mismatch between parameter extraction conditions and actual working conditions in related technologies.

[0021] Secondly, this application conducts in-depth research on key parameters: it has carried out in-depth research on the nonlinear changes of key parameters such as nonlinear junction capacitance and series resistance at high frequencies, which can more accurately describe the influence mechanism of these parameters on the performance of rectifier circuits and make up for the lack of research on key parameters in related technologies.

[0022] Furthermore, this application uses the Grey Wolf optimization algorithm to iteratively optimize the parameters, with the goal of approximating the measured curve to the simulated curve, until the approximation degree meets the preset accuracy. This provides a clear model error accuracy index, improves the energy conversion efficiency of the rectifier circuit, meets the high-performance requirements of the wireless energy transmission system, and alleviates the technical problem of unclear error accuracy index in the prior art.

[0023] Finally, this application employs the efficient Grey Wolf optimization algorithm, which reduces the number of iterations in the parameter extraction process, shortens the design cycle, improves timeliness, and better meets the needs of efficient circuit development.

[0024] In summary, this application not only improves the accuracy and efficiency of RF diode parameter extraction, but also provides strong support for the design of high-performance rectifier circuits, and promotes the development and application of wireless power transfer technology. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A flowchart illustrating a method for extracting parameters of a radio frequency diode based on heterogeneous integrated micro-assembly packaging, provided in this application; Figure 2 This is a first schematic diagram showing the connection method between the radio frequency diode and the short circuit; Figure 3 This is a second schematic diagram showing the connection method between the radio frequency diode and the short circuit; Figure 4 This is a schematic diagram of a micro-assembled SiP packaging structure; Figure 5 This is a schematic diagram of a heterogeneous integrated SiP packaged circuit board; Figure 6 This is a flowchart of parameter extraction based on the Grey Wolf algorithm. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] To make the objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] This application provides a method for extracting parameters of radio frequency diodes based on heterogeneous integrated micro-assembly packaging, such as... Figure 1 As shown, the process includes steps 101 to 106. Wherein: Step 101 provides a heterogeneous integrated micro-assembly packaging structure, which includes an RF diode die, a SiP substrate, gold wires connecting the RF diode die to the RF circuitry on the SiP substrate, and a metal cap sealing the SiP substrate. The SiP substrate is a System in Package (SiP) substrate. By packaging the SBD using heterogeneous integrated micro-assembly technology and precisely controlling the length and curvature of the bonding wires under an optical microscope, the parasitic inductance and capacitance introduced by the packaging are deterministic and repeatable. This eliminates the interference of the randomness of parasitic parameters on the high-frequency characteristics of the device, laying the physical foundation for the subsequent construction of a high-precision equivalent circuit model.

[0030] As a preferred embodiment, the gold wire has a diameter of 20 μm to 30 μm, a span of 100 μm to 200 μm, and the highest point of the arc is 50 μm to 150 μm from the surface of the SiP substrate. One application example is using a 25 μm diameter gold wire with a span of 150 μm and a highest point of the arc of 100 μm.

[0031] As another preferred embodiment, the SiP substrate has a heat dissipation area, and the RF diode die is fixed to the heat dissipation area by a thermally conductive adhesive material. The heat dissipation area is electrically connected to the ground layer of the SiP substrate, so that the RF diode die can simultaneously achieve heat dissipation and grounding.

[0032] Step 102: Test the RF diode die in the package structure and extract the DC static parameters based on the measurement results. The DC static parameters include series resistance, saturation current, ideality factor, zero-bias junction capacitance, built-in potential, and power exponent.

[0033] Step 103: Perform a three-dimensional electromagnetic simulation of the packaging structure using electromagnetic simulation software to obtain the parasitic parameters introduced by the packaging structure. The parasitic parameters include grounding capacitance, parasitic capacitance, and parasitic inductance.

[0034] Step 104: Based on the DC static parameters and the parasitic parameters, construct an equivalent circuit model of the RF diode, and design a rectifier circuit according to the equivalent circuit model. This application addresses the nonlinear characteristics of the SBD at high frequencies by constructing a complete equivalent circuit model including series resistance, saturation current, ideality factor, zero-bias junction capacitance, built-in potential, power exponent, ground capacitance, parasitic capacitance, and parasitic inductance.

[0035] Step 105: Perform physical testing and circuit simulation on the rectifier circuit to obtain the measured load rectification efficiency curve, the measured load reflectivity efficiency curve, the simulated load rectification efficiency curve, and the simulated load reflectivity efficiency curve. Using Computer Simulation Technology (CST) software, simulate the parasitic parameters generated by the Schottky Barrier Diode (SBD) bonding process. Combined with static DC parameters, construct a rectifier circuit operating in the 5.8GHz frequency band in the Advanced Design System (ADS) software. This circuit includes a matching network, a band-stop structure, a pass-through filter, a gallium nitride (GaN) diode, and a load.

[0036] Step 106: Taking the simulation load rectification efficiency curve as close as the measured load rectification efficiency curve and the simulation load reflectivity efficiency curve as close as the measured load reflectivity efficiency curve as the optimization objectives, the Grey Wolf optimization algorithm is used to iteratively optimize the DC static parameters and the parasitic parameters, and the optimized parameters are output.

[0037] This application optimizes the load rectification efficiency and load reflectivity of the rectifier circuit. It implements the Grey Wolf optimization algorithm in the Matlab environment and automatically calls ADS software for parameter fitting. A wolf population containing the parameters to be optimized is initialized. By calculating the degree of fit of individual individuals to the load rectification efficiency and load reflectivity efficiency curves, the optimal parameter combination is selected for iterative updating. Experiments show that this application can obtain high-precision SBD RF equivalent circuit model parameters in only two iterations.

[0038] By implementing steps 101 to 106 above, this application firstly ensures that the parameter extraction conditions match the actual operating conditions, accurately characterizing high-frequency nonlinear characteristics. Related technologies extract SBD model parameters based on static or low-frequency measurement data, failing to consider the nonlinear characteristics of devices under high-frequency operating conditions, resulting in models that cannot accurately characterize high-frequency behavior. This application, through the heterogeneous integrated micro-assembly packaging structure provided in step 101, precisely controls the length and curvature of the bonding wires, making the parasitic parameters introduced by the packaging deterministic and repeatable, laying a physical foundation for high-frequency modeling. Simultaneously, step 106 uses the measured high-frequency load rectification efficiency curve and load reflectivity efficiency curve as optimization targets, employing the Grey Wolf optimization algorithm for iterative optimization, ensuring that the extracted parameters accurately reflect the nonlinear characteristics of SBD at high frequencies, with simulation and measurement errors within a controllable range.

[0039] Secondly, this application conducts in-depth research on key parameters to accurately describe their impact mechanism on rectifier circuit performance. Related technologies lack in-depth research on the nonlinear changes of parameters such as nonlinear junction capacitance and series resistance at high frequencies, making it impossible to accurately describe the impact mechanism of these parameters on rectifier circuit performance. This application extracts DC static parameters in step 102, extracts parasitic parameters introduced by packaging in step 103, and in step 106, uses the DC static parameters, including series resistance Rs, saturation current Is, ideality factor N, zero-bias junction capacitance Cj0, built-in potential Vj, power exponent M, and parasitic parameters such as grounding capacitance Cd and gold wire inductance Ls, as optimization objects of the Grey Wolf optimization algorithm. Through iterative optimization, these parameters can accurately characterize the nonlinear changes at high frequencies, thereby accurately describing their impact mechanism on rectifier circuit performance.

[0040] Furthermore, a clear error accuracy index is provided to ensure the energy conversion efficiency of the rectifier circuit. Related technologies do not provide a clear model error accuracy, leading to poor energy conversion efficiency of rectifier circuits designed based on these parameters. In step 106, this application sets a preset accuracy as the optimization termination condition, including a fitting error threshold for the load rectification efficiency curve and a fitting error threshold for the load reflectivity efficiency curve, ensuring that the optimized parameters meet the accuracy requirements.

[0041] Finally, iterative optimization is highly efficient, significantly shortening the design cycle. Related technologies require multiple iterations of fitting to obtain parameters, resulting in long design cycles and poor timeliness. Step 106 of this application employs the Grey Wolf optimization algorithm to perform coordinated iterative optimization of DC static parameters and parasitic parameters. Only a small number of iterations are needed to converge to an optimization result that meets the accuracy requirements, significantly reducing the number of design iterations, substantially shortening the design cycle of the rectifier circuit, and improving R&D efficiency.

[0042] Specifically, regarding the heterogeneous integrated micro-assembly packaging structure provided in step 101, the packaging structure includes a SiP substrate, on which radio frequency (RF) circuitry and a heat dissipation area are provided. The size of the heat dissipation area is designed according to the size and power capacity of the RF diode die; the higher the power, the larger the heat dissipation area, to ensure good heat dissipation capability. The heat dissipation area is electrically connected to the ground layer of the SiP substrate, enabling the subsequently mounted RF diode die to simultaneously achieve heat dissipation and RF grounding, effectively reducing grounding inductance and improving high-frequency performance.

[0043] The RF diode die is mounted on the heat dissipation area using a die micro-assembly method. The RF diode die is fixed to the heat dissipation area by a thermally conductive adhesive material. This adhesive material has high thermal conductivity and good electrical conductivity, enabling it to rapidly conduct the heat generated during diode operation to the heat dissipation area. It should be noted that whether the RF diode die has a back metal does not affect the applicability of this package structure.

[0044] like Figure 2 and Figure 3 The diagram illustrates the connection method between an RF diode and a short circuit. The chip pads of the RF diode die are connected to the RF circuitry on the SiP substrate via gold wires. The diameter of the gold wires is 20μm to 30μm, the span is 100μm to 200μm, and the highest point of the arc is 50μm to 150μm from the surface of the SiP substrate. By precisely controlling the diameter, span, and arc of the gold wires, the parasitic inductance and capacitance introduced by the gold wires can be effectively reduced, making them deterministic and repeatable. The number of gold wires is selected based on the power tolerance and operating frequency. When the power is high, gold strips can be used instead of gold wires to improve current carrying capacity and reduce parasitic inductance.

[0045] The SiP substrate has a pre-reserved grounding position around its perimeter. A metal cap is sealed to the grounding position by high-temperature welding to form the package shell of the SiP package structure. Figure 4 This is a schematic diagram of a micro-assembled SiP (System-in-Package) package structure, where the gray area represents the metal cap. The metal cap is made of aluminum or other metal materials, and its thickness is selected based on the circuit board material and operating frequency; this application does not impose any limitations on this. The size of the grounding edge reserved around the circuit board is typically larger than the cap thickness to ensure good sealing and grounding performance.

[0046] At the location where the RF transmission line passes through the metal cap, the metal cap has an opening, which is sealed with black adhesive to reduce interference from the metal cap to the RF signal. The specific size of the opening is not limited in this application and can be adjusted according to the transmission line size. Sealed vias are provided on the SiP substrate for vertical interconnection of RF signals; the specific implementation of these sealed vias is also not limited in this application.

[0047] like Figure 5 The diagram shown is a schematic of a heterogeneous integrated SiP packaged circuit board. The RF input and output of the circuit can be implemented using RF connectors such as sub-miniature version A connectors (SMA), or by soldering methods such as side metallization; this application does not impose any restrictions on this.

[0048] The above-mentioned heterogeneous integrated micro-assembly packaging structure achieves high-precision integration of RF diode dies and SiP substrates. The parasitic parameters introduced by the packaging are controllable and repeatable, providing a reliable physical basis for subsequent high-precision parameter extraction.

[0049] Based on the above heterogeneous integrated micro-assembly packaging structure, in step 102, the RF diode die in the packaging structure is tested, and the DC static parameters are extracted based on the measurement results. Specifically, this includes steps 102-1 and 102-2, wherein: Step 102-1: Perform a forward current-voltage test on the RF diode die in the package structure to obtain multiple voltage values ​​and their corresponding current values; based on the electron emission relation, use the least squares method to fit the voltage and current values ​​to obtain a forward current-voltage fitting curve, and solve for the parameters in the electron emission relation; the parameters include series resistance, ideality factor and saturation current.

[0050] Specifically, when measuring the forward current-voltage curve, the bias scan range is from 0V to the bias value corresponding to the maximum current the diode can withstand, with a scan step size of 0.05V. For example, using a self-developed GaN device with a forward bias of 0V-2V, the bias scan step size is 0.05V. The electron emission relationship is: ; Where I is the forward current; I s q is the saturation current; q is the electron charge; V is the bias voltage applied across the RF diode; R s is the series resistance; N is the ideality factor; K is the Boltzmann constant; T is the absolute temperature.

[0051] Step 102-2: Perform capacitance-voltage testing on the RF diode die in the package structure to obtain multiple voltage values ​​and their corresponding capacitance values. Based on the relationship between junction capacitance and bias voltage, fit the voltage and capacitance values ​​using the orthogonal distance regression method to obtain the capacitance-voltage curve, and solve for the parameters in the relationship between junction capacitance and bias voltage. The parameters include zero bias junction capacitance, built-in potential, and power exponent.

[0052] Specifically, when measuring the capacitance-voltage curve, the test frequency is 1MHz to 10MHz, the bias voltage scan range is 0V to a voltage value lower than the diode breakdown voltage, and the scan step size is 0.1V to 0.5V; for example, the reverse breakdown voltage of the self-developed GaN device is 40V, the test conditions are 1MHz, the bias voltage is 0V-20V, and the bias voltage scan step size is 0.1V. The relationship between the junction capacitance and the bias voltage is as follows: ; Among them, C j For junction capacitance; C j0 V is the zero-bias junction capacitance, i.e., the junction capacitance when the bias voltage V=0; V is the bias voltage applied across the RF diode; V j M represents the built-in potential; M is the power exponent.

[0053] In addition, a reverse current-voltage test is performed on the RF diode die in the package structure to obtain multiple voltage values ​​and their corresponding reverse currents, and a reverse current-voltage curve is obtained based on the multiple voltage values ​​and their corresponding reverse currents.

[0054] Specifically, the bias voltage scan range is from 0V to the diode breakdown voltage, with a scan step of 0.5V. The bias voltage value corresponding to the first time the reverse current exceeds 1mA is determined as the breakdown voltage, and the minimum reverse leakage current when the reverse bias is close to 0V is determined as the saturation current. For example, using a self-developed GaN device with a forward bias of 0V-50V, the bias voltage scan step is 0.5V.

[0055] Furthermore, in step 106, with the optimization objective of the simulated load rectification efficiency curve approximating the measured load rectification efficiency curve and the simulated load reflectivity efficiency curve approximating the measured load reflectivity efficiency curve, the Grey Wolf optimization algorithm is used to iteratively optimize the DC static parameters and the parasitic parameters, and the optimized parameters are output, specifically including: Step A: Initialize the gray wolf population by dividing it into a positive parameter subgroup and a capacitance parameter subgroup, and setting the population size and maximum number of iterations. Each individual in the positive parameter subgroup includes series resistance, saturation current, and ideality factor, while each individual in the capacitance parameter subgroup includes ground capacitance, zero-bias junction capacitance, built-in potential, and power exponent.

[0056] Step B: Perform circuit simulation for each individual in the positive parameter subgroup and the capacitance parameter subgroup respectively: For an individual in the positive parameter subgroup, obtain the simulated load rectification efficiency curve based on the parameters represented by that individual, and calculate the fitting error between it and the measured load rectification efficiency curve as the fitness value of that individual; For an individual in the capacitance parameter subgroup, obtain the simulated load reflectivity efficiency curve based on the parameters represented by that individual, and calculate the fitting error between it and the measured load reflectivity efficiency curve as the fitness value of that individual.

[0057] Step C: Based on the fitness values ​​from largest to smallest, divide the individuals in the positive parameter subgroup and the capacitance parameter subgroup into four levels: α wolf, β wolf, δ wolf and ω wolf.

[0058] Step D: For the current positive parameter subgroup, based on the individual positions of α wolf, β wolf, and δ wolf, update the individual position of ω wolf according to the position update formula of the gray wolf algorithm to generate a new generation of positive parameter subgroup; In the contemporary capacitance parameter subgroup, based on the individual positions of α wolf, β wolf, and δ wolf, the individual position of ω wolf is updated according to the position update formula of the gray wolf algorithm, thus generating a new generation of capacitance parameter subgroup.

[0059] Step E: Repeat steps B to D until the maximum number of iterations is reached or the optimal fitness value of each subgroup is less than the preset error threshold, then stop the iteration.

[0060] Step F: Output the parameters represented by αwolf in the positive parameter subgroup as optimized positive parameters, and the parameters represented by αwolf in the capacitance parameter subgroup as optimized capacitance parameters.

[0061] Step D: The position update formula of the Grey Wolf algorithm specifically includes: Step D1: Calculate the convergence factor based on the current iteration number, and calculate the first coefficient vector and the second coefficient vector based on the convergence factor.

[0062] Step D2: Based on the first coefficient vector, calculate the distance between the individual corresponding to the current ω wolf and the individuals corresponding to α wolf, β wolf, and δ wolf.

[0063] Step D3: Based on the second coefficient vector and the distance, calculate the candidate positions for the individual corresponding to the current ω wolf to move towards the individuals corresponding to the α wolf, β wolf, and δ wolf, respectively.

[0064] Step D4: Calculate the average of the candidate positions that the individual corresponding to the current ω wolf can move to towards the individuals corresponding to the α, β, and δ wolves, and use the average value as the updated position of the individual corresponding to the current ω wolf.

[0065] Specifically, in order to accurately approximate the forward parameters of a diode: series resistance R s saturation current I s Ideal factor N and capacitance parameters: Built-in potential V j Power exponent M, grounding capacitance, C d Zero-bias junction capacitance C j0 This application uses the Grey Wolf Optimizer (GWO) algorithm to iteratively optimize the parameters so that the fitting degree of the load rectification efficiency curve and the load reflectivity efficiency curve meets the preset accuracy requirements.

[0066] like Figure 6 As shown, the first step is the initialization phase, which defines the parameter space: initializes the range of values ​​for the diode's parameters to be optimized, including the forward parameter θ. F ={R s ,Is,N} and capacitance parameter θ C ={V j ,M,C d C j0}

[0067] Population initialization: Set the gray wolf population size N, and divide the population into two independent subpopulations: Positive parameter subgroup P F Each group of individuals is coded as x F =[Rs,Is,N].

[0068] Capacitance parameter subgroup P C Each group of individuals is coded as x C =[V j ,M,C d C j0 ].

[0069] The second step is fitness evaluation, which calculates the fitness for each of the two subgroups to measure how well the parameters fit the target curve. Forward parametric subgroups: Calculate X for each group f The error between the simulated load rectified efficiency curve and the measured load rectified efficiency curve, such as the mean square error (MSE), is used as the fitness value f. f (X f The lower the fitness, the better the fit.

[0070] Capacitance parameter subgroup: Calculate X for each group c The error between the simulated load reflectivity efficiency curve and the measured load reflectivity efficiency curve is used as the fitness value f. c (X c The lower the fitness, the better the fit.

[0071] The third step is to classify the gray wolves into four groups: α wolves, β wolves, δ wolves, and ω wolves. Within each subgroup, the three optimal groups of individuals are selected based on their fitness values, defined as follows: X α The individual with the best fitness (representing the "prey" position, i.e., the current optimal parameter combination), is the α wolf.

[0072] X β The second-best fittest individual, i.e., the β wolf.

[0073] X δ The third most fit individual, i.e., the δ wolf.

[0074] Apart from α-wolves, β-wolves, and δ-wolves, the rest are ω-wolves.

[0075] The fourth step is population position update: Based on the positions of α wolf, β wolf, and δ wolf, update the position of ω wolf in the subpopulation. The core formula is as follows: (1) Determine the convergence factor and coefficient vector Convergence factor a: Decreases linearly from 2 to 0, balancing global exploration and local exploitation capabilities. ; Where t is the current iteration number, T max The maximum number of iterations, is the convergence factor.

[0076] Determine the first coefficient vector and the second coefficient vector: ; ; in, , The random number is set to the interval [0,1] to introduce randomness in the search. This is the first coefficient vector. This is the second coefficient vector. is the convergence factor.

[0077] (2) Calculate the distance between the individual corresponding to the current ω wolf and the individuals corresponding to α wolf, β wolf and δ wolf based on the first coefficient vector; the first coefficient vector includes: α wolf distance coefficient C1, β wolf distance coefficient C2 and δ wolf distance coefficient C3.

[0078] D α =∣C1 x α x(t)∣; D β =∣C2 x β x(t)∣; D δ =∣C3 x δ x(t)∣; Among them, D α Let D be the distance from the current position x(t) of the individual corresponding to the gray wolf to the individual corresponding to wolf α. β Let D be the distance from the current position x(t) of the individual corresponding to the gray wolf to the individual corresponding to the β wolf. δ Let X be the distance from the current position x(t) of the individual corresponding to the gray wolf to the individual corresponding to the δ wolf. α Let X be the position of the individual corresponding to α wolf. β X represents the position of the individual corresponding to β wolf. δ This represents the position of the individual corresponding to δ wolf.

[0079] (3) The second coefficient vector includes: α wolf position coefficient A1, β wolf position coefficient A2, and δ wolf position coefficient A3. Based on the second coefficient vector and the distance, candidate positions for the individual corresponding to the current ω wolf to move towards the individuals corresponding to α wolf, β wolf, and δ wolf are calculated respectively; X1=X α A1 D α ; X2=X β A2 Dβ ; X3=X δ A3 D δ ; Where X1 is the first candidate position, X2 is the second candidate position, and X3 is the third candidate position.

[0080] (4) Next generation position update: Calculate the average of the candidate positions that the individual corresponding to the current ω wolf can move to the individuals corresponding to the α, β, and δ wolves, and use the average value as the updated position of the individual corresponding to the current ω wolf. : ; Perform the above position update operation on the positive parameter subgroup and the capacitance parameter subgroup respectively to generate a new generation of population.

[0081] The fifth step is convergence judgment: check the optimal fitness of the positive parameter subgroup. Does it meet the fitting accuracy requirements of the load rectified efficiency curve, such as MSE being less than the threshold? F. Check the optimal fitness of the capacitance parameter subgroup. Does it meet the fitting accuracy requirements of the load reflectivity efficiency curve, such as MSE being less than the threshold? C. If both subgroups meet the accuracy requirements, output the optimal diode parameters; otherwise, return to the fitness evaluation step and continue iterating.

[0082] The sixth step is to output the results: when the iteration converges, output the approximate diode forward parameters. } and capacitance parameters }

[0083] In one exemplary embodiment, the rectifier circuit is designed and verified: For example, F4B material with a dielectric constant of 2.65, dielectric loss of 0.0015, and a thickness of 0.464 mm is selected as the circuit substrate, and the rectifier circuit is designed based on the extracted RF parameters. A test system including a microwave signal generator, power amplifier, power meter, directional coupler, and other equipment is built to verify the conversion efficiency of the rectifier circuit through actual measurement.

[0084] To improve fitting accuracy and reduce the number of iterations in rectifier circuit design, we adopted the Matlab programming environment and implemented the Grey Wolf Optimization (GWO) algorithm to automate the fitting operation using ADS software. The Grey Wolf algorithm is an intelligent optimization algorithm based on simulating the social behavior of grey wolves. It solves optimization problems by simulating competition and cooperation among individual grey wolves, as well as the dominance of superior individuals within the group. It features strong convergence performance, few parameters, and ease of implementation. In this application, the initial population size of the grey wolf algorithm is set to 50, with each grey wolf corresponding to a combination containing 7 parameters to be optimized.

[0085] The technical solution provided in this application has the following beneficial effects: First, the model parameters are highly accurate. The RF equivalent circuit model of the Schottky diode constructed based on the parameters extracted in this application shows a high degree of agreement between the simulation results and the measured data. Application examples show that for the first Schottky diode (SBD-1), the simulation-to-measurement error is controlled within 6%, with an average deviation of approximately 4%; for the second Schottky diode (SBD-2), the simulation-to-measurement error is as low as 1.5%. These high-precision model parameters lay a solid foundation for the accurate design of the subsequent rectifier circuit.

[0086] Second, the conversion efficiency of the rectifier circuit is significantly improved. Under the conditions of 5.8GHz operating frequency and 28.5dBm input power, the first Schottky diode rectifier designed based on the parameters extracted in this application achieves a rectification conversion efficiency of 80% at an optimal load of 170Ω; the second Schottky diode rectifier achieves a rectification efficiency of 70.2% at an optimal load of 250Ω. These efficiency indicators are significantly better than those of rectifier circuits designed using traditional methods, fully verifying the accuracy and effectiveness of the parameters extracted in this application.

[0087] Third, the parameter extraction efficiency is high and the design cycle is short. This application uses the Grey Wolf optimization algorithm to perform collaborative iterative optimization of DC static parameters and parasitic parameters. Application examples show that only two iterations are needed to converge to the optimization result that meets the accuracy requirements. Compared with the existing methods that require multiple repeated fittings, this application significantly reduces the number of design iterations, significantly shortens the design cycle of the rectifier circuit, and improves R&D efficiency.

[0088] Fourth, it provides effective support for improving the performance of wireless power transfer systems. This application provides accurate equivalent circuit model parameters for RF diodes in the design of high-performance rectifier circuits, which can effectively improve the power transmission efficiency and operational stability of wireless power transfer systems, and has broad engineering application value in microwave wireless power transfer, RF energy harvesting and other fields.

[0089] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0090] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for extracting parameters of a radio frequency diode based on heterogeneous integrated micro-assembly packaging, characterized in that, The method includes: A heterogeneous integrated micro-assembly packaging structure is provided, the packaging structure including a radio frequency diode die, a SiP substrate, gold wires connecting the radio frequency diode die to the radio frequency circuit on the SiP substrate, and a metal cap sealing the SiP substrate. The RF diode die in the package structure is tested, and the DC static parameters are extracted based on the measurement results; The parasitic parameters introduced by the packaging structure are obtained by performing a three-dimensional electromagnetic simulation using electromagnetic simulation software. Based on the DC static parameters and the parasitic parameters, an equivalent circuit model of the RF diode is constructed, and a rectifier circuit is designed according to the equivalent circuit model. The rectifier circuit was subjected to physical testing and circuit simulation to obtain the measured load rectification efficiency curve, the measured load reflectivity efficiency curve, the simulated load rectification efficiency curve, and the simulated load reflectivity efficiency curve. With the goal of approximating the measured load rectification efficiency curve and the simulated load reflectivity efficiency curve approximating the measured load reflectivity efficiency curve, the Grey Wolf optimization algorithm is used to iteratively optimize the DC static parameters and the parasitic parameters, and the optimized parameters are output.

2. The method for extracting RF diode parameters based on heterogeneous integrated micro-assembly packaging according to claim 1, characterized in that, The gold wire has a diameter of 20μm to 30μm, a span of 100μm to 200μm, and the highest point of the arc is 50μm to 150μm from the surface of the SiP substrate.

3. The method for extracting RF diode parameters based on heterogeneous integrated micro-assembly packaging according to claim 1, characterized in that, The parasitic parameters include grounding capacitance; the DC static parameters include series resistance, saturation current, ideality factor, zero-bias junction capacitance, built-in potential, and power exponent. With the optimization objectives of approximating the measured load rectification efficiency curve and the simulated load reflectivity efficiency curve approximating the measured load reflectivity efficiency curve, the Grey Wolf optimization algorithm is used to iteratively optimize the DC static parameters and the parasitic parameters, outputting the optimized parameters, specifically including: Step A: Initialize the gray wolf population, divide the population into a positive parameter subgroup and a capacitance parameter subgroup, and set the population size and maximum number of iterations; each individual in the positive parameter subgroup includes series resistance, saturation current and ideality factor, and each individual in the capacitance parameter subgroup includes ground capacitance, zero bias junction capacitance, built-in potential and power exponent. Step B: Perform circuit simulation for each individual in the positive parameter subgroup and the capacitance parameter subgroup respectively: For an individual in the positive parameter subgroup, obtain the simulated load rectification efficiency curve based on the parameters represented by that individual, and calculate the fitting error between it and the measured load rectification efficiency curve as the fitness value of that individual; For an individual in the capacitance parameter subgroup, obtain the simulated load reflectivity efficiency curve based on the parameters represented by that individual, and calculate the fitting error between it and the measured load reflectivity efficiency curve as the fitness value of that individual; Step C: Based on the fitness values ​​from largest to smallest, divide the individuals in the positive parameter subgroup and the capacitance parameter subgroup into four levels: α wolf, β wolf, δ wolf and ω wolf; Step D: For the current positive parameter subgroup, based on the individual positions of α wolf, β wolf, and δ wolf, update the individual position of ω wolf according to the position update formula of the gray wolf algorithm to generate a new generation of positive parameter subgroup; In the contemporary capacitance parameter subgroup, based on the individual positions of α wolf, β wolf, and δ wolf, the individual position of ω wolf is updated according to the position update formula of the gray wolf algorithm to generate a new generation of capacitance parameter subgroup; Step E: Repeat steps B to D until the maximum number of iterations is reached or the optimal fitness value of each subgroup is less than the preset error threshold, then stop the iteration; Step F: Output the parameters represented by αwolf in the positive parameter subgroup as optimized positive parameters, and the parameters represented by αwolf in the capacitance parameter subgroup as optimized capacitance parameters.

4. The method for extracting RF diode parameters based on heterogeneous integrated micro-assembly packaging according to claim 3, characterized in that, The position update formula of the Grey Wolf algorithm specifically includes: Step D1: Calculate the convergence factor based on the current iteration number, and calculate the first coefficient vector and the second coefficient vector based on the convergence factor; Step D2: Based on the first coefficient vector, calculate the distance between the individual corresponding to the current ω wolf and the individuals corresponding to α wolf, β wolf, and δ wolf respectively; Step D3: Based on the second coefficient vector and the distance, calculate the candidate positions for the individual corresponding to the current ω wolf to move towards the individuals corresponding to the α wolf, β wolf, and δ wolf, respectively; Step D4: Calculate the average of the candidate positions that the individual corresponding to the current ω wolf can move to towards the individuals corresponding to the α, β, and δ wolves, and use the average value as the updated position of the individual corresponding to the current ω wolf.

5. The method for extracting RF diode parameters based on heterogeneous integrated micro-assembly packaging according to claim 4, characterized in that, The convergence factor is calculated using the following formula: ； Where t is the current iteration number, T max The maximum number of iterations, is the convergence factor.

6. The method for extracting RF diode parameters based on heterogeneous integrated micro-assembly packaging according to claim 4, characterized in that, The first and second coefficient vectors are calculated using the following formulas: ； ； in, , A random number within the interval [0,1]. This is the first coefficient vector. This is the second coefficient vector. is the convergence factor.

7. The method for extracting RF diode parameters based on heterogeneous integrated micro-assembly packaging according to claim 1, characterized in that, The SiP substrate has a heat dissipation area, and the radio frequency diode die is fixed to the heat dissipation area by a thermally conductive adhesive material. The heat dissipation area is electrically connected to the ground layer of the SiP substrate.

8. The method for extracting RF diode parameters based on heterogeneous integrated micro-assembly packaging according to claim 1, characterized in that, The DC static parameters include series resistance, saturation current, ideality factor, zero-bias junction capacitance, built-in potential, and power exponent. The RF diode die in the package structure is tested, and the DC static parameters are extracted based on the measurement results, specifically including: A forward current-voltage test is performed on the RF diode die in the package structure to obtain multiple voltage values ​​and their corresponding current values. Based on the electron emission relation, the voltage and current values ​​are fitted using the least squares method to obtain a forward current-voltage fitting curve, and the parameters in the electron emission relation are solved. The parameters include series resistance, ideality factor, and saturation current. A capacitance-voltage test is performed on the RF diode die in the package structure to obtain multiple voltage values ​​and their corresponding capacitance values. Based on the relationship between junction capacitance and bias voltage, the voltage and capacitance values ​​are fitted using the orthogonal distance regression method to obtain a capacitance-voltage curve. The parameters in the relationship between junction capacitance and bias voltage are then solved. The parameters include zero bias junction capacitance, built-in potential, and power exponent.

9. The method for extracting RF diode parameters based on heterogeneous integrated micro-assembly packaging according to claim 8, characterized in that, The electron emission equation is: ； Where I is the forward current; I s q is the saturation current; q is the electron charge; V is the bias voltage applied across the RF diode; R s is the series resistance; N is the ideality factor; K is the Boltzmann constant; T is the absolute temperature.

10. The method for extracting RF diode parameters based on heterogeneous integrated micro-assembly packaging according to claim 8, characterized in that, The relationship between the junction capacitance and the bias voltage is as follows: ; Among them, C j For junction capacitance; C j0 V is the zero-bias junction capacitance, i.e., the junction capacitance when the bias voltage V=0; V is the bias voltage applied across the RF diode; V j M represents the built-in potential; M is the power exponent.

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