Hierarchical and parallel virtual metal fill parasitic parameter extraction, reduction method and apparatus

Abstract

The application discloses a layered and parallel virtual metal filling parasitic parameter extraction and reduction method, comprising the following steps: inputting an original layout file of a chip design area and a process technology file, and obtaining conductive layer physical parameters and layout data; based on the layout data and the conductive layer physical parameters, mapping a signal network into signal nodes and a virtual metal filling network into floating nodes by extracting conductor geometric information and calculating inter-conductor coupling capacitance, and constructing an initial parasitic capacitance network; based on spatial data of the chip design area, expanding a buffer zone of a preset distance threshold outward for each basic tile, and obtaining basic tiles containing internal elements, boundary elements and neighbor elements and corresponding boundary node information of the basic tiles; and based on the initial parasitic capacitance network, the basic tiles and the buffer zone, obtaining a parasitic network not containing floating nodes.

Description

Technical Field

[0001] This invention belongs to the field of computer-aided design technology for integrated circuits, and particularly relates to a hierarchical parallel method and apparatus for extracting and reducing parasitic parameters of virtual metal filling. Background Technology

[0002] As semiconductor processes have progressed to nodes of 130nm and below, the uniformity requirements of chemical mechanical polishing (CMP) have necessitated the widespread introduction of virtual metal fill structures in integrated circuit layouts. While these structures are electrically isolated, they can generate parasitic capacitive coupling with signal networks, impacting signal integrity and circuit power consumption. Therefore, parasitic parameter extraction tools are needed to assess the electrical effects of virtual metal fills.

[0003] Currently, known technical approaches for extracting parasitic parameters containing virtual metal filling include: The first type, field solver extraction method, uses the law of charge conservation to process isolated filled structures. It has high theoretical accuracy, but the computational complexity increases exponentially with the problem size, making it difficult to apply to full-chip level extraction.

[0004] The second type is the full matrix reduction method, which eliminates isolated nodes through Schur complement decomposition. The reduction process is mathematically accurate, but the computational complexity is approximately O(n). )( Typically between 1.5 and 2.5), it consumes a lot of memory and is inefficient when handling massive amounts of data.

[0005] The third type is the pattern matching method, which uses a pre-built standard capacitor model library for rapid matching. However, the limited pattern library is difficult to cover the diversity of actual layouts, resulting in a significant loss of accuracy.

[0006] In summary, existing technologies suffer from low computational efficiency, high resource consumption, or insufficient accuracy when extracting parasitic parameters from large-scale integrated circuits containing virtual metal fill. Therefore, improving reduction efficiency and reducing memory overhead while maintaining accuracy is a pressing technical problem to be solved in this field. Summary of the Invention

[0007] To address the aforementioned issues, this invention proposes a hierarchical parallel method and apparatus for extracting and reducing parasitic parameters of virtual metal-filled networks. By distinguishing between the signal network and the virtual metal-filled network, and quantifying parasitic capacitance using the physical parameters of the conductive layer, a mathematically precise reduction method based on Schur complement is employed. This achieves lossless extraction accuracy equivalent to the full matrix reduction method, meeting Sign-off acceptance requirements. Spatial partitioning divides the chip design region into multiple non-overlapping tiles and defines buffers, enabling local reduction within tiles and parallel processing between tiles. This reduces computational complexity from exponential to a linearly controllable range, significantly improving extraction efficiency. By merging adjacent tiles level by level to form super tiles and performing multi-level global reduction, all floating nodes are eliminated, outputting a simplified parasitic network without floating nodes. This achieves chip-level parasitic parameter extraction with controllable memory overhead and strong scalability.

[0008] The first aspect of this invention provides a hierarchical parallel method for extracting and reducing parasitic parameters of virtual metal filling, comprising: The original layout file and process technology file of the chip design area are input, and geometric figures are extracted through data parsing and connectivity analysis is performed. Physical parameters and layout data of conductive layers are obtained through logic connection identification and structured processing. Based on the layout data and the physical parameters of the conductive layer, by extracting the geometric information of the conductors and calculating the coupling capacitance between the conductors, the signal network is mapped to signal nodes and the virtual metal filling network is mapped to floating nodes, thus constructing an initial parasitic capacitance network. Based on the spatial data of the chip design area, multiple non-overlapping basic tiles are obtained through recursive segmentation. A buffer with a preset distance threshold is extended outward for each basic tile. The geometric shapes and electrical nodes inside, at the boundary and in the buffer of the basic tile are classified and labeled to obtain the basic tile containing internal elements, boundary elements and neighboring elements and its corresponding boundary node information. Based on the initial parasitic capacitance network, base tiles, and buffers, a parasitic network without floating nodes is obtained by performing local reduction within each base tile in parallel, merging adjacent base tiles into super tiles step by step, and performing multi-level global reduction.

[0009] Preferably, the step of extracting geometric figures through data parsing and performing connectivity analysis further includes: Read the geometry of the chip design area and perform connectivity analysis to output a connectivity map between the geometric shapes. Based on the connectivity graph, the signal network and the virtual metal-filled network are identified, and the network classification result is output. The signal network is a conductive structure used for logical connections between circuit modules, and the virtual metal-filled network is an isolated structure that does not have electrical connection function.

[0010] Preferably, the physical parameters of the conductive layer include at least layer thickness, resistivity, and dielectric constant.

[0011] Preferably, the step of obtaining the initial parasitic capacitance network further includes: Based on the layout data, the location data and hierarchical information of the conductive structures are extracted, and the spatial distance relationship between the conductors is calculated. The parasitic capacitance value is calculated based on the physical parameters of the conductive layer, the signal network nodes are obtained by mapping the signal network, and the floating nodes are obtained by mapping the virtual metal-filled network. An initial parasitic capacitance network is constructed based on the coupling relationships between the network nodes and the coupling relationships between the floating nodes.

[0012] Preferably, the step of constructing the initial parasitic capacitance network further includes: Based on all conductors and the capacitive network between conductors in the layout data, an equation relating charge and voltage is established, and the expression is as follows: In the formula, Q is the node charge vector, U is the node voltage vector, and C is the capacitance matrix; Based on node type, the node charge vector and node voltage vector are updated by partitioning into blocks, and the calculation expression is as follows: In the formula, , These are the voltage vectors of the floating node and the signal node, respectively. , These are the charge vectors of the floating node and the signal node, respectively. The capacitance matrix is ​​divided into submatrices based on the coupling relationship type between nodes, and the calculation expression is as follows: In the formula, , , These are the floating node-to-floating node capacitance, the signal node-to-floating node capacitance, and the capacitance between signal nodes, respectively. The capacitance between signal nodes is calculated based on the relationship equation between charge and voltage, the node charge vector, the node voltage vector, and a submatrix, using an equality relationship constructed from these equations. The expression for this equality relationship is as follows: .

[0013] Preferably, the step of obtaining the basic tile and corresponding boundary node information further includes: Based on the spatial data of the chip design area, the entire chip design area is recursively divided into multiple non-overlapping basic tiles by a preset grid density. Based on each of the basic tiles, a buffer zone is obtained by expanding outwards through a preset distance threshold, wherein the preset distance threshold is determined based on the effective influence radius of the parasitic effect; The geometry located on the base tile is classified and labeled according to the following rules: geometry located inside the base tile is labeled as internal element, geometry that crosses the tile boundary is labeled as boundary element, and geometry located within the buffer and outside the base tile is labeled as neighbor element; electrical nodes that are completely inside the tile are labeled as internal nodes, and electrical nodes that cross the tile boundary or connect to boundary elements are labeled as boundary nodes.

[0014] Preferably, the step of obtaining a parasitic network that does not contain floating nodes further includes: Based on the initial parasitic capacitance network, base tiles, and buffer, a parasitic network without floating nodes is obtained by performing local reduction within each base tile in parallel, merging adjacent base tiles into super tiles step by step, and performing multi-level global reduction. Integrate adjacent basic tiles that have completed local specifications, and form super tiles by merging adjacent basic tiles step by step; At the super-tile level, multi-level global reduction is performed on the newly generated internal floating nodes after merging to eliminate all floating nodes and output a simplified parasitic network that does not contain floating nodes.

[0015] Preferably, the multi-level global reduction process further includes: Based on the physical characteristics of the floating network and the block structure of the capacitance matrix, the voltage vector of the floating node is obtained, and the calculation expression is as follows: In the formula, , These are the voltage vectors of the floating node and the signal node, respectively. For floating node-floating node capacitance; Construct an equivalent capacitance matrix; the calculation expression is as follows: In the formula, The capacitance between signal nodes; Calculate the equivalent capacitance between the signal node with index j and the signal node with index k in the capacitance matrix. The calculation expression is as follows: In the formula, , These are the signal node-floating node capacitors with index value j and index value k, respectively.

[0016] A second aspect of the present invention provides a hierarchical parallel virtual metal-filling parasitic parameter extraction and reduction device, comprising: The layout data acquisition module is used to input the original layout file and process technology file of the chip design area, extract geometric graphics through data parsing and perform connectivity analysis, and obtain the physical parameters of the conductive layer and layout data through logic connection identification and structured processing. The parasitic network construction module is used to construct an initial parasitic capacitance network based on the layout data and the physical parameters of the conductive layer by extracting conductor geometric information and calculating the coupling capacitance between conductors, mapping the signal network to signal nodes and the virtual metal filling network to floating nodes. The spatial partitioning module is used to obtain multiple non-overlapping basic tiles based on the spatial data of the chip design area through recursive partitioning. For each basic tile, a buffer with a preset distance threshold is extended outward. The geometric shapes and electrical nodes inside the basic tile, the boundary, and the buffer are classified and labeled to obtain the basic tile containing internal elements, boundary elements, and neighboring elements and its corresponding boundary node information. The hierarchical parallel reduction processing module is used to obtain a parasitic network without floating nodes based on the initial parasitic capacitance network, base tiles and buffers, by performing local reduction within each base tile in parallel, merging adjacent base tiles into super tiles step by step and performing multi-level global reduction.

[0017] A third aspect of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the hierarchical parallel virtual metal filling parasitic parameter extraction and reduction method described in any of the preceding claims.

[0018] Because the present invention adopts the above technical solution, it has the following advantages and positive effects compared with the prior art: (1) By introducing virtual metal filler, the thickness of the metal layer in the CMP process is ensured to be uniform, avoiding butterfly defects and erosion, achieving uniform heat dissipation and reducing wafer deformation.

[0019] (2) Accurately quantify the parasitic capacitance coupling effect between the virtual metal filler and the signal network, and evaluate its impact on signal integrity, propagation delay and circuit power consumption.

[0020] (3) The mathematical exact reduction method based on Schur complement is adopted, which is equivalent in accuracy to the full matrix reduction method and meets the requirements of sign-off verification and acceptance.

[0021] (4) By partitioning space and parallel computing, the reduction problem of massive floating nodes is decomposed into multiple small-scale sub-problems, which significantly improves the processing speed. Attached Figure Description

[0022] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is the main flowchart of the hierarchical parallel virtual metal filling parasitic parameter extraction and reduction method in this invention; Figure 2 This is a schematic diagram of the signal network and virtual metal filling layout in this invention; Figure 3 This is a schematic diagram of the space division and buffer zone in this invention; Figure 4 This is a diagram illustrating one embodiment of the space partitioning and buffer system in this invention. Detailed Implementation

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0024] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0025] First Embodiment See Figure 1 and Figure 2 The first aspect of the present invention provides a hierarchical parallel method for extracting and reducing parasitic parameters of virtual metal filling, comprising: S100: Input the original layout file and process technology file of the chip design area, extract the geometric pattern through data parsing and perform connectivity analysis, and obtain the physical parameters and layout data of the conductive layer through logic connection identification and structured processing; S200: Based on layout data and physical parameters of the conductive layer, the signal network is mapped to signal nodes and the virtual metal filling network is mapped to floating nodes by extracting conductor geometric information and calculating the coupling capacitance between conductors, thus constructing an initial parasitic capacitance network. S300: Based on the spatial data of the chip design area, multiple non-overlapping basic tiles are obtained through recursive segmentation. A buffer with a preset distance threshold is extended outward for each basic tile. The geometric shapes and electrical nodes inside the basic tile, the boundary and the buffer are classified and marked to obtain the basic tile containing internal elements, boundary elements and neighboring elements and its corresponding boundary node information. S400: Based on the initial parasitic capacitance network, basic tiles and buffers, it obtains a parasitic network that does not contain floating nodes by performing local reduction within each basic tile in parallel, merging adjacent basic tiles into super tiles step by step and performing multi-level global reduction.

[0026] By recursively dividing the chip region into non-overlapping basic tiles and adding buffers, this method breaks the strong dependence of traditional methods on global data of the entire chip. Processing within each basic tile can be performed independently and simultaneously, significantly reducing the extraction time of parasitic parameters for the entire chip, which contains massive amounts of virtual metal filling. By expanding the buffer outwards and finely classifying (internal elements, boundary elements, neighboring elements, boundary nodes), parasitic coupling capacitance information across tile boundaries is captured, avoiding the common problem of overlooking boundary effects in existing spatial partitioning methods. The massive floating node network, which was originally too large to be eliminated all at once, is transformed into a hierarchical dimensionality reduction process involving local reduction, step-by-step merging, and multi-level global reduction. Compared to the exponential memory explosion and computational lag problems faced by traditional full matrix reduction methods, this method keeps computational resource consumption within a manageable range, ultimately outputting a simplified network without floating nodes, reducing the computational burden of circuit simulation.

[0027] S100: Input the original layout file and process technology file of the chip design area. Extract geometric figures through data parsing and perform connectivity analysis. Obtain the physical parameters and layout data of the conductive layer through logic connection identification and structured processing. Specifically, read the geometric figures of the chip design area and perform connectivity analysis, outputting a connectivity graph between the geometric figures. Based on the connectivity graph, identify signal networks and virtual metal-filled networks, and output the network classification results. Signal networks are conductive structures used for logical connections between circuit modules, while virtual metal-filled networks are isolated structures without electrical connection functions. The physical parameters of the conductive layer include layer thickness, resistivity, and dielectric constant.

[0028] S200: Based on layout data and physical parameters of the conductive layer, an initial parasitic capacitance network is constructed by extracting conductor geometric information and calculating inter-conductor coupling capacitance, mapping the signal network to signal nodes, and the virtual metal-filled network to floating nodes. Specifically, based on the layout data, the position data and hierarchical information of the conductive structure are extracted, and the spatial distance relationship between conductors is calculated; parasitic capacitance values ​​are calculated based on the physical parameters of the conductive layer, signal network nodes are obtained by mapping the signal network, and floating nodes are obtained by mapping the virtual metal-filled network; the initial parasitic capacitance network is constructed based on the coupling relationship between network nodes and the coupling relationship between floating nodes. When constructing the initial parasitic capacitance network, based on the capacitive network of all conductors and between conductors in the layout data, the relationship equation between charge and voltage is established, and the calculation expression is: Q=C×U, where Q is the node charge vector, U is the node voltage vector, and C is the capacitance matrix; based on the node type, the node charge vector and node voltage vector are updated by block partitioning, and the calculation expression is: Q=[Q f Q s ], U=[U f ;U s ], where U f U s These are the voltage vectors of the floating node and the signal node, respectively; Q f Q s These are the charge vectors of the floating nodes and the signal nodes, respectively. The capacitance matrix is ​​divided into submatrices based on the coupling relationship type between nodes, and the calculation expression is as follows: In the formula, , , These are the capacitances between floating nodes, between signal nodes, and between signal nodes, respectively. The capacitance between signal nodes is calculated based on the relationship between charge and voltage, node charge vectors, node voltage vectors, and submatrices to construct an equality relationship. The expression for this equality relationship is as follows: In the formula, The capacitance between signal nodes; S300: Based on the spatial data of the chip design area, multiple spatially non-overlapping basic tiles are obtained through recursive segmentation. A buffer with a preset distance threshold is extended outward from each basic tile. Geometric shapes and electrical nodes within the basic tiles, their boundaries, and the buffer are classified and labeled, obtaining basic tiles containing internal elements, boundary elements, and neighboring elements, along with their corresponding boundary node information. Specifically, based on the spatial data of the chip design area, the entire chip design area is recursively segmented into multiple spatially non-overlapping basic tiles using a preset grid density. For each basic tile, a buffer is obtained by extending outwards using a preset distance threshold, which is determined based on the effective influence radius of parasitic effects. Geometric shapes located within the basic tiles are classified and labeled according to the following rules: geometric shapes located inside the basic tile are labeled as internal elements; geometric shapes crossing tile boundaries are labeled as boundary elements; geometric shapes located within the buffer and outside the basic tile are labeled as neighboring elements. Electrical nodes completely inside the tile are labeled as internal nodes; electrical nodes crossing tile boundaries or connecting boundary elements are labeled as boundary nodes.

[0029] S400: Based on the initial parasitic capacitance network, base tiles, and buffers, a parasitic network without floating nodes is obtained by parallelly performing local reduction within each base tile, merging adjacent base tiles into super tiles, and performing multi-level global reduction. Specifically, adjacent base tiles that have completed local reduction are integrated, and super tiles are formed by merging adjacent base tiles step by step. At the super tile level, multi-level global reduction is performed on the newly generated internal floating nodes after merging to eliminate all floating nodes, outputting a simplified parasitic network without floating nodes. During the multi-level global reduction process, the voltage vector of the floating nodes is obtained based on the physical characteristics of the floating network and the block structure of the capacitance matrix. The calculation expression is as follows: ,in, , These are the voltage vectors of the floating node and the signal node, respectively. For floating node-floating node capacitance, construct an equivalent capacitance matrix, and calculate the expression as follows: In the formula, The capacitance between signal nodes is calculated; the equivalent capacitance between the signal node with index j and the signal node with index k in the capacitance matrix is ​​calculated using the following expression: In the formula, , These are the signal node-floating node capacitances with index values ​​j and k, respectively. Using the aforementioned hierarchical parallel method for extracting and reducing parasitic parameters of virtual metal fill, floating nets in the chip layout, such as virtual metal fills, can be processed efficiently and accurately, precisely calculating the parasitic capacitances they introduce. This method achieves parallel processing of parasitic extraction by dividing the entire design region into non-overlapping basic tiles and defining a buffer for each tile. A complete parasitic network model is constructed through classification and labeling of different types of network elements and extraction of coupling capacitances. Finally, through local reduction and multi-level global reduction, all floating nodes are eliminated, outputting a simplified parasitic network without floating nodes, improving the efficiency and accuracy of parasitic parameter extraction.

[0030] Preferably, the step of extracting geometric figures through data parsing and performing connectivity analysis further includes: Read the geometry of the chip design area and perform connectivity analysis to output a connectivity map between the geometric shapes. Based on connectivity graph identification, signal networks and virtual metal-filled networks are identified, and network classification results are output. Signal networks are conductive structures used for logical connections between circuit modules, while virtual metal-filled networks are isolated structures that do not have electrical connection functions.

[0031] The system reads all geometric data within the chip design area and analyzes the physical contact and connection relationships between the geometric shapes using algorithms, outputting a connectivity map reflecting the topological connection status of each geometric shape. Based on the topological features of this map, network determination is performed, identifying and classifying conductive structures with logical connection paths as signal networks, and identifying and classifying isolated structures without any electrical connection paths as virtual metal-filled networks. The final classification results are output, clearly distinguishing between signal networks and virtual metal-filled networks. Signal networks are conductive structures used for logical connections between circuit modules, while virtual metal-filled networks are isolated structures without electrical connection functions. Transforming massive, scattered layout geometric coordinate data into a topological map reduces the computational cost of subsequent data retrieval and matching. Before constructing complex capacitor networks, topological features are used to distinguish between valid signals and invalid floating fills in one step, eliminating unnecessary computation and clearing obstacles for subsequent lightweight modeling and rapid reduction.

[0032] Preferably, the physical parameters of the conductive layer include at least layer thickness, resistivity, and dielectric constant.

[0033] These three parameters, from the three physical dimensions of spatial geometry (layer thickness), electrical loss characteristics (resistivity), and electric field coupling nature (dielectric constant), provide indispensable and accurate data support for the subsequent construction of a high-fidelity initial parasitic capacitance network. They are the prerequisite for ensuring that the final extraction results meet the Sign-off accuracy requirements.

[0034] Preferably, the step of obtaining the initial parasitic capacitance network further includes: Based on the layout data, the location data and hierarchical information of the conductive structure are extracted, and the spatial distance relationship between the conductors is calculated; Parasitic capacitance values ​​are calculated based on the physical parameters of the conductive layer, signal network nodes are obtained by mapping the signal network, and floating nodes are obtained by mapping the virtual metal-filled network. An initial parasitic capacitance network is constructed based on the coupling relationships between network nodes and the coupling relationships between floating nodes.

[0035] The specific coordinates of all conductive structures on the chip and their metal layer information are extracted from the layout data, and the physical distance relationships between different conductors in three-dimensional space are calculated. Combined with the previously obtained physical parameters of the conductive layers, the parasitic capacitance values ​​between each pair of conductors are calculated using physical formulas. Simultaneously, a network-to-node mapping transformation is completed, mapping the signal network to signal network nodes with electrical properties, and mapping the virtual metal-filled network to floating nodes. The calculated capacitance values ​​are used as edge weights, and the coupling relationships between signal nodes and floating nodes, as well as between floating nodes themselves, are combined to construct a complete mesh topology, thus obtaining the initial parasitic capacitance network. This achieves the transformation from a purely geometric shape to an electrical topology network: by extracting position, level, and distance, it is transformed into a circuit node model with clear spatial coupling relationships, providing a valid data structure for subsequent mathematical matrix operations. Through mapping operations, signal nodes and floating nodes are clearly distinguished and assigned different electrical identities, ensuring that floating nodes can be located and eliminated during subsequent reduction. The capacitance value was calculated based on real physical parameters and spatial distance, and the coupling relationship was constructed to restore the real physical electric field environment of the layout, so as to achieve lossless accuracy in subsequent mathematical reduction.

[0036] Preferably, the step of constructing the initial parasitic capacitance network further includes: Based on the capacitive network of all conductors and the interconductors in the layout data, an equation relating charge and voltage is established, and the calculation expression is as follows: In the formula, Q is the node charge vector, U is the node voltage vector, and C is the capacitance matrix; Based on node type, the node charge vector and node voltage vector are updated by partitioning into blocks. The calculation expression is as follows: In the formula, , These are the voltage vectors of the floating node and the signal node, respectively. , These are the charge vectors of the floating node and the signal node, respectively. The capacitance matrix is ​​divided into submatrices based on the coupling relationship type between nodes, and the calculation expression is as follows: In the formula, , , These are the floating node-to-floating node capacitance, the signal node-to-floating node capacitance, and the capacitance between signal nodes, respectively. The capacitance between signal nodes is calculated based on the relationship equation between charge and voltage, node charge vectors, node voltage vectors, and sub-matrices to construct an equality relationship. The expression for the equality relationship calculation is as follows: .

[0037] First, based on the physical capacitor network composed of all conductors and their insulating media in the chip layout, a fundamental matrix equation Q=CU between charge vector Q and voltage vector U is established at the macroscopic electrical level. Second, according to whether nodes have electrical connection functions, the macroscopic node vectors are physically identified and partitioned, precisely separating Q and U into floating node components and signal node components. Third, corresponding to the above node classification, the originally large and messy capacitor matrix C is precisely reduced in dimension and divided into three sub-matrices according to the directionality of coupling relationships: the capacitance inside floating nodes, the cross-network capacitance between signals and floating nodes, and the local network capacitance inside signal nodes. Substituting the partitioned vectors and sub-matrices back into the fundamental equation, an expansion of the equal relationships reflecting the interactions of these three types of capacitors is constructed. This transforms the difficult-to-calculate and messy layout... Figure 3 The parasitic coupling effect is completely equivalent to a rigorous linear algebraic matrix equation, providing the fundamental conditions for large-scale mathematical operations by computers. By dividing the matrix and vector into blocks based on signals and floating nodes, the floating nodes and signal nodes are thoroughly clarified at the mathematical level. This block structure is an absolute prerequisite for subsequent lossless Schur complement transformation and accurate elimination of floating nodes.

[0038] See Figure 4 Preferably, the step of obtaining the basic tile and corresponding boundary node information further includes: Based on the spatial data of the chip design area, the entire chip design area is recursively divided into multiple non-overlapping basic tiles by a preset grid density. Based on each basic tile, a buffer zone is obtained by expanding outward through a preset distance threshold, which is determined based on the effective influence radius of the parasitic effect. The geometry located on the base tile is classified and labeled according to the following rules: geometry located inside the base tile is labeled as internal element, geometry that crosses the tile boundary is labeled as boundary element, and geometry located within the buffer and outside the base tile is labeled as neighbor element; electrical nodes that are completely inside the tile are labeled as internal nodes, and electrical nodes that cross the tile boundary or connect to boundary elements are labeled as boundary nodes.

[0039] Based on a predetermined grid density, the entire chip design area is recursively divided from large to small, discretizing the complete layout space into multiple independent, non-overlapping basic tiles. For each divided basic tile, the effective radius of parasitic effects is used as a distance threshold to expand spatially outward, forming a buffer surrounding the basic tile. Graphics within the tile are marked as internal elements, graphics crossing boundaries are marked as boundary elements, and graphics falling into the outer buffer are marked as neighbor elements. Similarly, at the electrical node level, purely local nodes are marked as internal nodes, and nodes with cross-region connections are marked as boundary nodes. By recursively dividing the originally fully coupled, massive chip region into independent basic tiles, the dependency of global computation is broken, allowing each tile to be assigned to different computation threads for independent and synchronous processing, significantly improving extraction efficiency. The ingenious introduction of the buffer ensures that the signal network inside the tile can capture parasitic capacitance interference from a sufficiently long distance outside, avoiding the risk of long-distance cross-region coupling capacitance being truncated. By strictly separating internal elements / nodes from boundary elements / nodes, the internal and boundary relationships are logically clearly defined. This provides clear operational boundaries for subsequent layered reduction, ensuring that the connectivity of the cross-tile signal network is not disrupted when eliminating internal floating nodes in parallel.

[0040] by Figure 4 For example, the entire design region is divided into a set of non-overlapping base tiles, which form a grid covering the entire design region. Each base tile extends outwards by a buffer (also called a halo or padding). Figure 4The medium green background represents the entire design area, divided into multiple rectangular base tiles (e.g., Tilei,j,Tilei+1,j,Tilei,j+1,Tilent,nt). Each base tile has an outward-expanding dashed frame, which is the padding / haloregion. The width of the buffer is defined by the field solver according to specific technology. When the distance between two networks exceeds this threshold, their coupling capacitance can be considered negligible. This ensures that when performing parasitic extraction within the base tile, only the coupling within the base tile and the buffer needs to be considered, ignoring coupling at greater distances, thus enabling parallel processing. See also... Figure 4 In the diagram, S represents the signal nets of the base tile, f represents the dummy fills / floating nets of the base tile, and ft represents the floating nets of the base tile's padding area. Based on this, the following coupling capacitances need to be extracted: C is the capacitance between the signal network and the floating network within the base tile. ff : Capacitance between floating meshes within the base tile. C s，ft C represents the capacitance between the signal mesh and the floating mesh of the buffer zone within the base tile. f，ft : Capacitance between the floating mesh within the base tile and the floating mesh in the buffer zone.

[0041] See Figure 4 Preferably, the step of obtaining a parasitic network that does not contain floating nodes further includes: Based on the initial parasitic capacitance network, basic tiles and buffers, a parasitic network without floating nodes is obtained by performing local reduction within each basic tile in parallel, merging adjacent basic tiles into super tiles step by step and performing multi-level global reduction. Integrate adjacent basic tiles that have completed local specifications, and form super tiles by merging adjacent basic tiles step by step; At the super-tile level, multi-level global reduction is performed on the newly generated internal floating nodes after merging to eliminate all floating nodes and output a simplified parasitic network that does not contain floating nodes.

[0042] Within the base tile with buffers, since boundary coupling is fully captured, the numerous floating nodes within the tile can be considered relatively independent subsystems. Using mathematical matrix transformations, these internal floating nodes are first eliminated on a local, small-scale matrix, their capacitance effects being equivalently superimposed onto the signal nodes. Since boundary nodes are preserved in the local reduction, these serve as stitching lines to merge adjacent small tiles into a larger super-tile. At this point, the floating nodes originally located at the boundaries of the base tile are transformed into new internal floating nodes from the perspective of the super-tile. The elimination operation is repeated on the larger super-tile matrix. Through this recursive process of local elimination, boundary merging, and further internal elimination, floating nodes at all levels of the entire chip are completely removed from the mathematical equations from the bottom up, ultimately leaving only the pure signal node equivalent capacitance network. The operation that originally required a massive one-time matrix inversion across billions of nodes on the entire chip is now distributed and completed step-by-step within countless small tiles. The scale of each matrix operation is strictly limited to the memory capacity of a single computing node, achieving a low memory consumption reduction for massive numbers of nodes. The local reduction of each basic tile is completely independent and does not interfere with each other. It can be seamlessly mapped to multiple CPU / GPU threads in a computer cluster for synchronous execution, compressing the serial computation time of the entire chip to nearly the processing time of a single tile. See also Figure 4 The local reduction operation is performed on (f,ft), and then a super tile is formed by merging adjacent basic tiles at each level. Multi-level global reduction is performed, and finally all floating nodes are eliminated, outputting a simplified parasitic network that does not contain floating nodes.

[0043] See Figure 2 Preferably, the multi-level global reduction process further includes: Based on the physical characteristics of the floating network and the block structure of the capacitance matrix, the voltage vector of the floating node is obtained, and the calculation expression is as follows: In the formula, , These are the voltage vectors of the floating node and the signal node, respectively. For floating node-floating node capacitance; Construct an equivalent capacitance matrix; the calculation expression is as follows: In the formula, The capacitance between signal nodes; The equivalent capacitance between the signal node with index j and the signal node with index k in the capacitance matrix is ​​calculated using the following expression: In the formula, , These are the signal node-floating node capacitors with index value j and index value k, respectively.

[0044] By deriving from the physical characteristics of floating nodes, the floating voltage is rigorously expressed as a controlled function of the signal node voltage, completely binding the unknown floating variables to known variables, providing an absolutely rigorous mathematical premise for subsequent elimination. By constructing an equivalent capacitance matrix, the massive system of equations containing a huge number of floating nodes is equivalently transformed into a small-scale system of equations containing only signal nodes. This process is a purely analytical mathematical derivation, ensuring that the electrical coupling effect between signal networks remains accurate even after eliminating floating nodes. The calculation of equivalent capacitance values ​​reduces the peak memory access during actual code implementation and is highly compatible with the parallel computing architecture of computers, resulting in a significant increase in the speed of global reduction operations at the super-tile level.

[0045] Second Embodiment A second aspect of the present invention provides a hierarchical parallel virtual metal-filling parasitic parameter extraction and reduction device, comprising: The layout data acquisition module is used to input the original layout file and process technology file of the chip design area, extract geometric graphics through data parsing and perform connectivity analysis, and obtain the physical parameters of the conductive layer and layout data through logic connection identification and structured processing. The parasitic network construction module is used to construct an initial parasitic capacitance network based on layout data and physical parameters of conductive layers by extracting conductor geometric information and calculating the coupling capacitance between conductors, mapping the signal network to signal nodes and the virtual metal filling network to floating nodes. The spatial partitioning module is used to obtain multiple non-overlapping basic tiles based on the spatial data of the chip design area through recursive partitioning. For each basic tile, a buffer with a preset distance threshold is extended outward. The geometric shapes and electrical nodes inside the basic tile, the boundary, and the buffer are classified and labeled to obtain the basic tile containing internal elements, boundary elements, and neighboring elements and its corresponding boundary node information. The hierarchical parallel reduction processing module is used to obtain a parasitic network without floating nodes based on the initial parasitic capacitance network, base tiles and buffers. This is achieved by performing local reduction within each base tile in parallel, merging adjacent base tiles into super tiles step by step and performing multi-level global reduction.

[0046] By decoupling the massive chip design region into multiple independent basic tiles with buffers through a spatial partitioning module, the hierarchical parallel reduction processing module can allocate multiple computing resources to process each tile synchronously, completely breaking the performance bottleneck of traditional full matrix reduction which requires global serial computation. The unique buffer design and refined classification and labeling of internal elements, boundary elements, and neighbor elements in the spatial partitioning module ensure that no parasitic capacitance effects across tiles are missed during spatial partitioning, guaranteeing the lossless accuracy of the original data in subsequent reductions from a physical architecture perspective. Based on the initial network built by the parasitic network construction module, the hierarchical parallel reduction processing module adopts a funnel-shaped architecture that merges local reduction super tiles with multi-level global reduction. The massive matrix operations that would otherwise cause memory overflow are broken down and consumed in various controllable local levels, ultimately outputting a stable, simplified parasitic network without floating nodes, significantly reducing hardware memory overhead. In summary, through the coordinated efforts of various functional modules, the complex spatial cutting and mathematical reduction process is materialized, enabling the extraction and simplification of massive virtual metal-filled parasitic networks across the entire chip in a parallel, fast, and high-precision manner with low hardware memory consumption.

[0047] Third Embodiment A third aspect of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, it implements the steps of a hierarchical parallel virtual metal filling parasitic parameter extraction and reduction method as described above.

[0048] The electronic device can be a computer, a server, or a dedicated integrated circuit design workstation with computing capabilities. The memory can be random access memory (RAM), read-only memory (ROM), flash memory, or other types of storage media. When the computer program is executed by the processor, it implements all the steps of the hierarchical parallel virtual metal-filling parasitic parameter extraction and reduction method described in Embodiment 1, including input data parsing and parameter extraction, construction of the initial parasitic capacitance network, spatial partitioning and buffer definition, and parallel reduction and parasitic network acquisition.

[0049] In the description of this application, it should be noted that the terms "inner" and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0050] It should also be noted that, unless otherwise explicitly specified and limited, the terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0051] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific identification content executed by the system and device described above can be referred to the corresponding process in the foregoing method embodiments.

[0052] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they shall still fall within the protection scope of the present invention.

Claims

1. A hierarchical parallel method for extracting and reducing parasitic parameters of virtual metal filling, characterized in that, include: The original layout file and process technology file of the chip design area are input, and geometric figures are extracted through data parsing and connectivity analysis is performed. Physical parameters and layout data of conductive layers are obtained through logic connection identification and structured processing. Based on the layout data and the physical parameters of the conductive layer, by extracting the geometric information of the conductors and calculating the coupling capacitance between the conductors, the signal network is mapped to signal nodes and the virtual metal filling network is mapped to floating nodes, thus constructing an initial parasitic capacitance network. Based on the spatial data of the chip design area, multiple non-overlapping basic tiles are obtained through recursive segmentation. A buffer with a preset distance threshold is extended outward for each basic tile. The geometric shapes and electrical nodes inside, at the boundary and in the buffer of the basic tile are classified and labeled to obtain the basic tile containing internal elements, boundary elements and neighboring elements and its corresponding boundary node information. Based on the initial parasitic capacitance network, base tiles, and buffers, a parasitic network without floating nodes is obtained by performing local reduction within each base tile in parallel, merging adjacent base tiles into super tiles step by step, and performing multi-level global reduction.

2. The hierarchical parallel method for extracting and reducing parasitic parameters of virtual metal filling according to claim 1, characterized in that, The steps of extracting geometric figures through data parsing and performing connectivity analysis further include: Read the geometry of the chip design area and perform connectivity analysis to output a connectivity map between the geometric shapes. Based on the connectivity graph, the signal network and the virtual metal-filled network are identified, and the network classification result is output. The signal network is a conductive structure used for logical connections between circuit modules, and the virtual metal-filled network is an isolated structure that does not have electrical connection function.

3. The method for extracting and reducing parasitic parameters of virtual metal filling in a hierarchical parallel manner according to claim 1, characterized in that, The physical parameters of the conductive layer include at least layer thickness, resistivity, and dielectric constant.

4. The hierarchical parallel method for extracting and reducing parasitic parameters of virtual metal filling according to claim 1, characterized in that, The steps for obtaining the initial parasitic capacitance network further include: Based on the layout data, the location data and hierarchical information of the conductive structures are extracted, and the spatial distance relationship between the conductors is calculated. The parasitic capacitance value is calculated based on the physical parameters of the conductive layer, the signal network nodes are obtained by mapping the signal network, and the floating nodes are obtained by mapping the virtual metal-filled network. An initial parasitic capacitance network is constructed based on the coupling relationships between the network nodes and the coupling relationships between the floating nodes.

5. The hierarchical parallel method for extracting and reducing parasitic parameters of virtual metal filling according to claim 4, characterized in that, The steps for constructing the initial parasitic capacitance network further include: Based on all conductors and the capacitive network between conductors in the layout data, an equation relating charge and voltage is established, and the expression is as follows: In the formula, Q is the node charge vector, U is the node voltage vector, and C is the capacitance matrix; Based on node type, the node charge vector and node voltage vector are updated by partitioning into blocks, and the calculation expression is as follows: In the formula, , These are the voltage vectors of the floating node and the signal node, respectively. , These are the charge vectors of the floating node and the signal node, respectively. The capacitance matrix is ​​divided into submatrices based on the coupling relationship type between nodes, and the calculation expression is as follows: In the formula, , , These are the floating node-to-floating node capacitance, the signal node-to-floating node capacitance, and the capacitance between signal nodes, respectively. The capacitance between signal nodes is calculated based on the relationship equation between charge and voltage, the node charge vector, the node voltage vector, and a submatrix, using an equality relationship constructed from these equations. The expression for this equality relationship is as follows: 。 6. The hierarchical parallel method for extracting and reducing parasitic parameters of virtual metal filling according to claim 1, characterized in that, The steps for obtaining basic tile and corresponding boundary node information further include: Based on the spatial data of the chip design area, the entire chip design area is recursively divided into multiple non-overlapping basic tiles by a preset grid density. Based on each of the basic tiles, a buffer zone is obtained by expanding outwards through a preset distance threshold, wherein the preset distance threshold is determined based on the effective influence radius of the parasitic effect; The geometry located on the base tile is classified and labeled according to the following rules: geometry located inside the base tile is labeled as internal element, geometry that crosses the tile boundary is labeled as boundary element, and geometry located within the buffer and outside the base tile is labeled as neighbor element; electrical nodes that are completely inside the tile are labeled as internal nodes, and electrical nodes that cross the tile boundary or connect to boundary elements are labeled as boundary nodes.

7. The hierarchical parallel method for extracting and reducing parasitic parameters of virtual metal filling according to claim 1, characterized in that, The steps for obtaining a parasitic network that does not contain floating nodes further include: Based on the initial parasitic capacitance network, base tiles, and buffer, a parasitic network without floating nodes is obtained by performing local reduction within each base tile in parallel, merging adjacent base tiles into super tiles step by step, and performing multi-level global reduction. Integrate adjacent basic tiles that have completed local specifications, and form super tiles by merging adjacent basic tiles step by step; At the super-tile level, multi-level global reduction is performed on the newly generated internal floating nodes after merging to eliminate all floating nodes and output a simplified parasitic network that does not contain floating nodes.

8. The method for extracting and reducing parasitic parameters of virtual metal filling in a hierarchical parallel manner according to claim 7, characterized in that, The steps of multi-level global reduction processing further include: Based on the physical characteristics of the floating network and the block structure of the capacitance matrix, the voltage vector of the floating node is obtained, and the calculation expression is as follows: In the formula, , These are the voltage vectors of the floating node and the signal node, respectively. For floating node-floating node capacitance; Construct an equivalent capacitance matrix; the calculation expression is as follows: In the formula, The capacitance between signal nodes; Calculate the equivalent capacitance between the signal node with index j and the signal node with index k in the capacitance matrix. The calculation expression is as follows: In the formula, , These are the signal node-floating node capacitors with index value j and index value k, respectively.

9. A layered parallel virtual metal-filling parasitic parameter extraction and reduction device, characterized in that, include: The layout data acquisition module is used to input the original layout file and process technology file of the chip design area, extract geometric graphics through data parsing and perform connectivity analysis, and obtain the physical parameters of the conductive layer and layout data through logic connection identification and structured processing. The parasitic network construction module is used to construct an initial parasitic capacitance network based on the layout data and the physical parameters of the conductive layer by extracting conductor geometric information and calculating the coupling capacitance between conductors, mapping the signal network to signal nodes and the virtual metal filling network to floating nodes. The spatial partitioning module is used to obtain multiple non-overlapping basic tiles based on the spatial data of the chip design area through recursive partitioning. For each basic tile, a buffer with a preset distance threshold is extended outward. The geometric shapes and electrical nodes inside the basic tile, the boundary, and the buffer are classified and labeled to obtain the basic tile containing internal elements, boundary elements, and neighboring elements and its corresponding boundary node information. The hierarchical parallel reduction processing module is used to obtain a parasitic network without floating nodes based on the initial parasitic capacitance network, base tiles and buffers, by performing local reduction within each base tile in parallel, merging adjacent base tiles into super tiles step by step and performing multi-level global reduction.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the computer program is executed by the processor, it implements the steps of the hierarchical parallel virtual metal filling parasitic parameter extraction and reduction method as described in any one of claims 1-8.

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