Analog-digital mixed signal verification system and method supporting tolerance comparison and cross-domain communication
By constructing a two-layer system architecture and introducing a proxy interface and mixed-signal bridge based on the UVM-MS specification, the problem of insufficient description of analog circuit characteristics in mixed-signal verification is solved, achieving efficient cross-domain communication and adaptive judgment, and improving the automation level and accuracy of the verification platform.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NORTHWESTERN POLYTECHNICAL UNIV
- Filing Date
- 2026-04-13
- Publication Date
- 2026-07-21
AI Technical Summary
Existing technologies struggle to accurately describe the key electrical characteristics of analog circuits in mixed-signal verification of systems-on-a-chip, leading to false errors in verification platforms when faced with reasonable physical fluctuations, making it difficult to achieve fully automated regression testing.
A two-layer system architecture including a UVM verification environment and a simulation test platform is constructed. By introducing a proxy interface and a mixed signal bridge based on the UVM-MS specification, efficient cross-domain communication and synchronization of digital and analog signals are achieved. A tolerance window mechanism is introduced into the scoring board for adaptive judgment.
It significantly improves the automation level of mixed-signal verification, effectively filters out false errors, and enhances the reliability and efficiency of the verification platform.
Smart Images
Figure CN122433657A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit design verification technology, specifically relating to a mixed-signal verification system and method that supports tolerance comparison and cross-domain communication. Background Technology
[0002] As the integration density of System-on-Chip (SoC) increases, the boundary between digital and analog circuits is becoming increasingly blurred. For example, large-scale pixel array detection chips often integrate analog front-end circuits such as DACs (Digital-to-Analog Converters) and ADCs (Analog-to-Digital Converters). Current mixed-signal functional verification faces significant challenges: on the one hand, the purely digital UVM environment lacks the ability to describe physical quantities such as voltage, current, and impedance, making it difficult to characterize the key electrical characteristics of analog circuits, thus hindering accurate verification of analog-to-digital interaction behavior. On the other hand, although SPICE transistor-level or Verilog-AMS continuous-time simulations offer high accuracy, their extremely low simulation efficiency cannot support automated regression testing of the entire system-level chip.
[0003] To address the challenges of mixed-signal verification, the industry has adopted the UVM-MS architecture based on specifications such as the Accellera UVM-MS draft and the IEEE P2427 standard draft, attempting to solve the problem of co-modeling digital and analog components through a unified methodological framework. Real number modeling (RNM) technology is commonly used in the industry. For example, Texas Instruments' patent (US202318481711A) mentions extracting weights and biases from analog simulation logs to construct a transfer function, ultimately generating a real number-based mathematical simulation model. However, if the RNM model introduces non-ideal factors such as process mismatch and finite output impedance in pursuit of higher physical fidelity, its analog output will exhibit fluctuating continuous real number characteristics, no longer a perfect discrete ideal value, and traditional verification and comparison mechanisms may not be suitable.
[0004] In the "A Method and Apparatus for Mixed-Signal Verification of Nor Flash" (CN111221692B), a Verilog reference model is constructed based on the operating characteristics of the analog circuit to generate the design under test, and data verification and comparison are performed through a UVM verification platform. However, the scoring board of this scheme is still limited by the matching mode of "strict bit-by-bit equality" or "fixed static error" in traditional pure digital verification. In actual full-chip mixed-signal simulation, the nonlinear error caused by the process deviation and voltage fluctuation of the analog circuit will dynamically expand nonlinearly with the change of the input code value. The fixed static tolerance cannot adapt to the reasonable performance drift under multiple process angles, causing the verification platform to throw out a large number of false errors when faced with reasonable physical fluctuations, ultimately making it difficult for fully automated regression testing to achieve closed loop. Summary of the Invention
[0005] To overcome the shortcomings of existing technologies, this invention provides a mixed-signal verification system and method that supports tolerance comparison and cross-domain communication. Addressing the issues that current purely digital verification environments cannot accurately assess non-ideal errors in analog circuits, and that traditional static numerical comparisons lead to numerous false errors in full-chip simulations, this invention constructs a two-layer system architecture comprising a verification environment side and a simulation test platform side. By introducing a proxy interface conforming to the UVM-MS specification and a mixed-signal bridge (MS Bridge), continuous quantities are extracted based on multiple sampling average logic within a steady-state window, achieving efficient cross-domain communication and synchronization of digital and analog signals. Simultaneously, a tolerance window mechanism is introduced into the scoring board, enabling result judgment based on adaptively calculated dynamic deviations. This invention effectively filters false errors caused by reasonable component deviations and impedance loads, significantly improving the automation level of the mixed-signal verification platform.
[0006] The technical solution adopted by this invention to solve its technical problem is as follows: A mixed-signal verification system supporting tolerance comparison and cross-domain communication, including a UVM verification environment and a simulation test platform; The UVM verification environment includes a digital signal generation component, an analog signal measurement component, a reference model, and a scoring board; The digital signal generation component includes a sequence manager and driver for generating configurations, a collector for collecting coverage, and a monitor for monitoring the output values of the reference model; the analog signal measurement component includes a collector for collecting coverage and a monitor for monitoring the output values of the design under test transmitted through a proxy interface in the simulation test platform. The monitor processes the actual values and writes them to the scoring board; the reference model receives the configuration signal from the digital signal generation component and writes the generated expected value to the scoring board. The simulation test platform includes a mixed-signal bridge and a design under test (DUT). The digital interface in the mixed-signal bridge receives configuration signals from the digital signal generation component, extracts DAC codes and writes them to the DUT. The output values are generated by the weighted network of digital logic and analog circuits in the DUT and written back to the mixed-signal bridge. The proxy interface in the mixed-signal bridge receives the output values of the DUT and transmits them to the analog signal measurement component in the UVM verification environment.
[0007] Preferably, the scoring board has a built-in dual-mode judgment logic. After acquiring the actual measured value and calculating the expected value and absolute error, it enters different branches according to the working mode: the tolerance detection mode will perform variable error tolerance comparison; the performance monitoring mode will directly record data for offline analysis.
[0008] A method for verifying mixed-signal signals that supports tolerance comparison and cross-domain communication includes the following steps: Step 1: Component initialization; Establish a UVM verification environment and simulation test platform, connect the design under test to the verification environment through a proxy interface, and configure the port mapping relationship; open the log file and set the log recording format and output path; Step 2: Digital-driven and cross-domain push; In the UVM verification environment, the driver in the digital signal generation component obtains a test transaction containing the current cycle input digital control codeword and module enable signal from the sequence manager within the same component. Subsequently, the driver injects discrete digital signals into the simulation test platform via an interface in a push manner. The mixed-signal bridge of the simulation test platform receives the discrete digital signals and generates DAC digital control codes. After receiving the DAC digital control codes from the mixed-signal bridge, the design under test (DUT) in the simulation test platform completes the register and digital logic configuration. Then, the analog circuit weight network inside the DUT responds and starts the voltage build-up process, causing the node potential to transition from the initial state to the target analog voltage, thereby completing the signal excitation injection from the digital domain to the analog domain. Step 3: Steady-state waiting logic execution; The driver executes the waiting logic according to the preset delay duration in the interface variable to ensure that the analog voltage fully enters the steady-state region and avoids the nondeterministic glitches in the early stage of discrete event triggering; Step 4: Cross-domain sampling triggered; After the delay period ends, the driver immediately sets the sampling control field and sends a cross-domain sampling trigger pulse to the mixed-signal bridge, indicating that the system is ready to perform high-precision continuous quantity extraction. Step 5: Continuous data extraction and averaging of multiple samples; After detecting the rising edge of the sampling control signal, the mixed-signal bridge starts continuous signal extraction. The core of the bridge in the mixed-signal bridge performs multiple step samplings on the analog output node of the design under test within the steady-state window according to the number of sampling points N defined by the interface variable, and eliminates the solution error by calculating the average value. Step 6: Cross-domain state synchronization; The mixed-signal bridge updates the final calculated average voltage value to the output variable of the proxy interface and pulls the handshake synchronization signal high to indicate that the cross-domain data is ready and the state synchronization is complete. Step 7: Monitor pull-up and bus reset; The analog signal measurement component located in the UVM verification environment acts as a passive monitor. It does not actively send stimuli. It only performs a pull operation after detecting that the handshake synchronization signal is pulled high. It reads the stable actual analog measurement value from the agent interface, packages it with the original digital stimulus, and sends it to the scoring board. At the same time, it pulls the signal low to reset the bus state. Step 8: Tolerance comparison and recording; The scoring board's internal reference model calculates the expected value of the gold standard based on the ideal transfer function and executes tolerance comparison logic: If in tolerance detection mode, the system will use an adaptively calculated variable error range to judge the result. If the actual measured value falls within the variable error range, it is judged as passing; otherwise, an error is thrown. If in performance monitoring mode, the system does not directly judge failure, but writes information such as the digital codeword of the current period, the actual measured value, the expected value, and the error to the log file in real time. The system continues to execute normally. The data generated by the performance monitoring mode is used for offline statistical analysis of indicators such as integral nonlinearity and differential nonlinearity after verification.
[0009] Preferably, the scoring board has a built-in reference model, whose gold standard expected value is calculated based on the input digital control code and predefined transmission characteristic parameters.
[0010] Preferably, the transmission characteristic parameters include: least significant bit step, zero-point bias voltage, and system gain error parameters.
[0011] An electronic device includes: a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory to enable the electronic device to perform the above-described mixed-signal verification method.
[0012] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described mixed-signal verification method.
[0013] A chip includes a processor for calling and running a computer program from a memory, causing a device equipped with the chip to perform the above-described mixed-signal verification method.
[0014] A computer program product includes a computer storage medium storing a computer program, the computer program including instructions executable by at least one processor, which, when executed by the at least one processor, implement the above-described mixed-signal verification method.
[0015] The beneficial effects of this invention are as follows: This invention retains the advantages of standard UVM in constrained random excitation and coverage-driven regression, while solving the problem of unstable sampling and verification of analog signals in digital environments through a unified interface and tolerance judgment, significantly improving the automation and reusability of mixed signal verification. Attached Figure Description
[0016] Figure 1 This is a diagram showing the overall architecture of the hybrid signal verification system of the present invention.
[0017] Figure 2 This is a block diagram of the internal comparison logic of the scoring board of the present invention, showing the branches of tolerance detection mode and performance monitoring mode.
[0018] Figure 3 This is a flowchart of the hybrid signal cross-domain interaction and event triggering based on the Push-Sync mechanism of this invention.
[0019] Figure 4 This is a flowchart illustrating the implementation steps of the mixed-signal verification method in this embodiment of the invention. Detailed Implementation
[0020] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0021] The core system of this invention adopts a dual-top-level architecture design, mainly composed of a UVM verification environment and a simulation test platform. The UVM verification environment is connected to the design under test (DUT) via a cross-domain communication module. The UVM verification environment includes a digital signal generation component, an analog signal measurement component, a reference model, and a scoring board. The digital signal generation component includes a sequence manager and driver for generating configurations, a collector for collecting coverage, and a monitor for monitoring the output values of the reference model. The analog signal measurement component includes a collector and a monitor. The collector collects coverage, and the monitor monitors the DUT output values transmitted through the proxy interface in the simulation test platform. The monitor then processes the actual values and writes them to the scoring board. The reference model receives configuration signals from the digital signal generation component and generates expected values, which are then written to the scoring board. The simulation test platform mainly consists of a mixed-signal bridge and the DUT. The digital interface in the mixed-signal bridge receives configuration signals from the digital signal generator, extracts DAC codes, and writes them to the DUT. This input is processed by a weighted network of digital logic and analog circuits in the DUT to generate output values, which are then written back to the mixed-signal bridge. This output value, after processing, is sent to the analog signal measurement component via a proxy interface. It is then written to the scoring board and compared with the expected value generated by the reference signal according to the tolerance comparison mechanism to produce the result. Cross-domain data transmission and control signal interaction are achieved between modules through configuration signals and proxy interfaces.
[0022] Regarding cross-domain interaction, this invention designs a hybrid signal bridge and a proxy component. The UVM-MS proxy interface is used to solve the polymorphic adaptation problem, and a Push-Sync discrete event-triggered sampling mechanism is proposed. By performing multiple samplings within the steady-state window and calculating the average, the glitches caused by time uncertainty between discrete events and continuous-time solutions are effectively overcome.
[0023] Regarding automatic result determination, this invention introduces a reference model and tolerance window mechanism into the UVM scoreboard. Unlike the traditional preset dead zone threshold, the scoreboard of this invention can use the reference model to calculate the expected value of the gold standard. In the tolerance detection mode, the scoreboard will use tolerance comparison to determine whether the verification passes or fails. If the deviation exceeds the variable deviation range calculated adaptively, an error will be thrown. In the performance monitoring mode, it does not directly determine whether it fails or not, but writes the collected data into the log in real time for subsequent offline statistical analysis of nonlinear indicators such as integral nonlinearity and differential nonlinearity.
[0024] Example: like Figure 1 As shown, the verification system of this invention adopts a dual-top-level architecture, mainly composed of a UVM verification environment and a simulation test platform. The UVM verification environment mainly consists of digital signal generation components (including a sequence manager and drivers), analog signal measurement components (including a collector and a monitor), a reference model, and a scoring board. The simulation test platform mainly consists of a mixed-signal bridge (containing a digital interface, a bridge core, and a proxy interface) and the design under test. Cross-domain data transmission and control signal interaction are achieved between the modules through configuration signals and proxy interfaces.
[0025] like Figure 2 As shown, the scoring board module incorporates dual-mode decision logic. After acquiring the actual measured value and calculating the expected value and absolute error, the system enters different branches according to the working mode: the tolerance detection mode performs variable error tolerance comparison; the performance monitoring mode directly records data for offline analysis.
[0026] like Figure 3 With Figure 4 As shown, the verification method of the present invention specifically includes the following implementation steps: S10, Component Initialization. Create the components and mixed-signal bridges included in the test environment, and initialize the configuration information. Establish the UVM verification environment and simulation test platform, connect the design under test to the verification environment through the proxy interface, and configure the port mapping relationship. Open the log file and set the log recording format and output path.
[0027] S20, Digital Drive and Cross-Domain Push. The digital driver on the UVM environment side retrieves a test transaction from the sequence manager, containing the current cycle's input digital control codeword and module enable signal. Subsequently, the driver injects these discrete digital signals into the simulation test platform via an interface using a push method. Upon receiving the digital code value, the design under test (DUT)'s internal analog circuitry responds and initiates a voltage build-up process, causing the node potential to transition from its initial state to the target analog voltage, thus completing the signal excitation injection from the digital domain to the analog domain.
[0028] S30, steady-state wait logic execution. Given the physical settling time in analog circuit responses, the output signal needs to transition from transient to steady state. The driver executes the wait logic according to the preset delay duration in the interface variables, ensuring the analog voltage fully enters the steady-state region and avoiding nondeterministic glitches in the initial stages of discrete event triggering.
[0029] S40, Cross-domain sampling trigger. After the delay period, the driver immediately sets the sampling control field and sends a cross-domain sampling trigger pulse to the mixed-signal bridge, indicating that the system is ready to perform high-precision continuous quantity extraction.
[0030] S50, Continuous Signal Extraction and Multiple Sampling Averaging. The mixed-signal bridge initiates continuous signal extraction upon detecting the rising edge of the sampling control signal. This component performs multiple step samplings of the analog output nodes of the design under test within a steady-state window, based on the number of sampling points N defined by the interface variable, and calculates the average value to eliminate solution errors.
[0031] S60, Cross-domain state synchronization. The bridge updates the finally calculated average voltage value to the output variable of the proxy component and pulls the handshake synchronization signal high, indicating that the cross-domain data is ready and state synchronization is complete.
[0032] S70, Monitor Pull and Bus Reset. The passive monitor located on the UVM environment side, upon detecting a high handshake synchronization signal, performs a pull operation, reads stable actual analog measurement values from the proxy interface, packages them together with the raw digital stimulus, and sends them to the scoring board. Simultaneously, it pulls the signal low to reset the bus state.
[0033] S80, Tolerance Comparison and Recording. The scoring board's internal reference model calculates the expected value of the gold standard based on the ideal transfer function and executes tolerance comparison logic: If in tolerance detection mode, the system will use an adaptively calculated variable error range to judge the result. If the actual measured value falls within this error range, it is judged as passing; otherwise, an error is thrown. If in performance monitoring mode, the system does not directly judge failure, but writes information such as the current period's digital codeword, actual measured value, expected value, and error to the log file in real time, and the system continues to execute normally. The data generated in this mode is used for offline statistical analysis of indicators such as integral nonlinearity and differential nonlinearity after verification.
[0034] In a typical embodiment, for the verification requirements of a 10-bit current-controlled digital-to-analog converter (DAC), the cross-domain control field of the proxy component is defined using a hybrid real and integer definition. The input digital control codeword contains a 10-bit width and supports voltage output identifiers with a maximum of 1024 discrete steps. The steady-state delay time (delay_in) setting needs to consider the physical settling time of the analog circuit under test and load conditions. For basic functional tests with light loads, this delay time is set to 10 to 50 nanoseconds; for complex network scenarios with large capacitive loads, this parameter can be set longer as needed. The number of sampling points (duration_in) within the steady-state window is typically configured to 16 to 64 times to adequately filter out cross-domain transient glitches through averaging multiple samples. In addition, the tolerance threshold settings of the scoring board need to match the verification purpose: in the tolerance detection mode, the reference model sets the nominal LSB voltage to 1.56mV and the tolerance limit is configured to 0.5 times LSB, i.e., 0.78mV; while in the performance monitoring mode with random process mismatch of the device enabled and a relative standard deviation of 0.2% introduced, the tolerance verification constraint will be bypassed, and the system will automatically continuously import the simulated acquisition values in the full code range of 0 to 1023 into the log to support the subsequent complex calculation of INL / DNL indicators.
[0035] In another typical embodiment incorporating non-ideal factors, the scoreboard's dynamic tolerance is calculated. Its decision threshold is composed of both static baseline error and dynamic mismatch error. The system extracts the currently input digital code Din and the process relative standard deviation parameter. The error inflation in the current cycle is dynamically calculated. For example, based on the assumption that the random mismatch of each current source unit in the current-controlled DAC follows a normal distribution, the standard deviation of its error is proportional to the square root of the number of active units. The static reference error is then superimposed to obtain the error range. Through this adaptive mechanism, as long as the actual floating-point analog measurement value falls within the error range dynamically generated with the code value, it is automatically identified by the platform as the expected output, effectively filtering out false errors caused by process characteristics.
Claims
1. A mixed-signal verification system supporting tolerance comparison and cross-domain communication, characterized in that, This includes the UVM verification environment and simulation testing platform; The UVM verification environment includes a digital signal generation component, an analog signal measurement component, a reference model, and a scoring board; The digital signal generation component includes a sequence manager and driver for generating configurations, a collector for collecting coverage, and a monitor for monitoring the output values of the reference model; the analog signal measurement component includes a collector for collecting coverage and a monitor for monitoring the output values of the design under test transmitted through a proxy interface in the simulation test platform. The monitor processes the actual values and writes them to the scoring board; the reference model receives the configuration signal from the digital signal generation component and writes the generated expected value to the scoring board. The simulation test platform includes a mixed-signal bridge and a design under test (DUT). The digital interface in the mixed-signal bridge receives configuration signals from the digital signal generation component, extracts DAC codes and writes them to the DUT. The output values are generated by the weighted network of digital logic and analog circuits in the DUT and written back to the mixed-signal bridge. The proxy interface in the mixed-signal bridge receives the output values of the DUT and transmits them to the analog signal measurement component in the UVM verification environment.
2. The mixed-signal verification system supporting tolerance comparison and cross-domain communication according to claim 1, characterized in that, The scoring board has a built-in dual-mode decision logic. After acquiring the actual measurement value and calculating the expected value and absolute error, it enters different branches according to the working mode: the tolerance detection mode will perform variable error tolerance comparison; the performance monitoring mode will directly record data for offline analysis.
3. A signal verification method for the mixed-signal verification system as described in claim 1, characterized in that, Includes the following steps: Step 1: Component initialization; Establish a UVM verification environment and simulation test platform, connect the design under test to the verification environment through a proxy interface, and configure port mapping relationships; Open the log file and set the log recording format and output path; Step 2: Digital-driven and cross-domain push; In the UVM verification environment, the driver in the digital signal generation component obtains a test transaction containing the current cycle input digital control codeword and the module enable signal from the sequence manager within the same component. Subsequently, the driver injects discrete digital signals into the simulation test platform via an interface in a push manner; The mixed-signal bridge of the simulation test platform receives discrete digital signals and generates DAC digital control codes. After receiving the DAC digital control codes from the mixed-signal bridge, the design under test in the simulation test platform completes the register and digital logic configuration. Subsequently, the analog circuit weight network inside the design under test responds and starts the voltage establishment process, so that the node potential transitions from the initial state to the target analog voltage, thereby completing the signal excitation injection from the digital domain to the analog domain. Step 3: Steady-state waiting logic execution; The driver executes the waiting logic according to the preset delay duration in the interface variable to ensure that the analog voltage fully enters the steady-state region and avoids the nondeterministic glitches in the early stage of discrete event triggering; Step 4: Cross-domain sampling triggered; After the delay period ends, the driver immediately sets the sampling control field and sends a cross-domain sampling trigger pulse to the mixed-signal bridge, indicating that the system is ready to perform high-precision continuous quantity extraction. Step 5: Continuous data extraction and averaging of multiple samples; After detecting the rising edge of the sampling control signal, the mixed-signal bridge starts continuous signal extraction. The core of the bridge in the mixed-signal bridge performs multiple step samplings on the analog output node of the design under test within the steady-state window according to the number of sampling points N defined by the interface variable, and eliminates the solution error by calculating the average value. Step 6: Cross-domain state synchronization; The mixed-signal bridge updates the final calculated average voltage value to the output variable of the proxy interface and pulls the handshake synchronization signal high to indicate that the cross-domain data is ready and the state synchronization is complete. Step 7: Monitor pull-up and bus reset; The analog signal measurement component located in the UVM verification environment acts as a passive monitor. It does not actively send stimuli. It only performs a pull operation after detecting that the handshake synchronization signal is pulled high. It reads the stable actual analog measurement value from the agent interface, packages it with the original digital stimulus, and sends it to the scoring board. At the same time, it pulls the signal low to reset the bus state. Step 8: Tolerance comparison and recording; The internal reference model of the scoreboard calculates the expected value of the gold standard based on the ideal transfer function and executes the tolerance comparison logic: if it is in the tolerance detection mode, the system will use the adaptively calculated variable error range to judge the result. If the actual measured value falls within the variable error range, it is judged as passing; otherwise, an error is thrown. If in performance monitoring mode, the system does not directly determine failure, but writes information such as the current period's digital codeword, actual measured value, expected value, and error to the log file in real time. The system continues to execute normally. The data generated in performance monitoring mode is used for offline statistical analysis of indicators such as integral nonlinearity and differential nonlinearity after verification.
4. The signal verification method according to claim 3, characterized in that, The scoring board has a built-in reference model, and its gold standard expected value is calculated based on the input digital control code and predefined transmission characteristic parameters.
5. The signal verification method according to claim 4, characterized in that, The transmission characteristic parameters include: least significant bit step, zero-point bias voltage, and system gain error parameters.