Compensation parasitic capacitance extraction method, device and equipment for through hole

Abstract

The application relates to the chip manufacturing technical field and discloses a via hole compensation parasitic capacitance extraction method, device and equipment, wherein the chip comprises a target via hole, a first conductor object connected with the target via hole and a second conductor object not directly connected with the target via hole; based on device information of the target via hole, a proportional coefficient of the target via hole is found in a via hole parasitic capacitance library; the proportional coefficient represents the ratio of the first parasitic capacitance between the via hole and the second conductor object to the standard parasitic capacitance between the first conductor object and the second conductor object; the via hole parasitic capacitance library is generated based on device information and the proportional coefficient of a plurality of preset via hole samples; and based on the standard parasitic capacitance between the first conductor object and the second conductor object and the proportional coefficient of the target via hole, a compensation parasitic capacitance between the target via hole and the second conductor object is calculated. The beneficial effect is that the parasitic capacitance extraction accuracy is improved.

Description

Technical Field

[0001] This application relates to the field of chip manufacturing technology, and in particular to a method, apparatus and equipment for extracting the parasitic capacitance of vias. Background Technology

[0002] As chips continue to evolve, Moore's Law continues to extend, and device dimensions continue to shrink. For novel 3D structure devices such as fin field-effect transistors, it is necessary to use 3D pattern matching to extract the parasitic capacitance between each layer.

[0003] However, typical 3D patterns do not include via structures. Therefore, the parasitic capacitance generated by vias cannot be directly obtained, which can easily lead to inaccurate extraction of the chip's parasitic capacitance. Summary of the Invention

[0004] This application provides a method, apparatus, and device for extracting the compensating parasitic capacitance of a through-hole, which solves the technical problem that the parasitic capacitance of a through-hole cannot be extracted in the prior art, and achieves the technical effect of accurately extracting the supplementary parasitic capacitance of the through-hole and using the parasitic capacitance for compensation, thereby improving the accuracy of parasitic capacitance extraction.

[0005] To achieve the above objectives, the main technical solutions adopted in this application include: In a first aspect, embodiments of this application provide a method for extracting the parasitic capacitance compensation of a via, wherein the chip includes a target via, a first conductor object connected to the target via, and a second conductor object not directly connected to the target via; the method includes: Based on the device information of the target via, the scaling factor of the target via is obtained by searching in the via parasitic capacitance library; the scaling factor represents the ratio of the first parasitic capacitance between the via and the second conductor object to the standard parasitic capacitance between the first conductor object and the second conductor object; the via parasitic capacitance library is generated based on the device information and scaling factor of a preset number of via samples; The compensated parasitic capacitance between the first conductor object and the second conductor object is calculated based on the standard parasitic capacitance between the target via and the scaling factor of the target via.

[0006] Secondly, embodiments of this application provide a device for extracting parasitic capacitance through a via. The chip includes a target via, a first conductor object connected to the target via, and a second conductor object not directly connected to the target via; the device includes: The search module is used to search for the scaling factor of the target via in the via parasitic capacitance library based on the device information of the target via; the scaling factor represents the ratio of the first parasitic capacitance between the via and the second conductor object to the standard parasitic capacitance between the first conductor object and the second conductor object; the via parasitic capacitance library is generated based on the device information and scaling factor of a preset number of via samples; The calculation module is used to calculate the compensation parasitic capacitance between the target via and the second conductor object based on the standard parasitic capacitance between the first conductor object and the second conductor object and the scaling factor of the target via.

[0007] Thirdly, embodiments of this application provide a computer device, including: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the method described in any of the above embodiments.

[0008] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer instructions, which are used to cause a computer to perform the method described in any one of the above embodiments.

[0009] Fifthly, embodiments of this application provide a computer program product, including computer instructions, which are used to cause a computer to perform the method described in any of the above embodiments.

[0010] In this embodiment, a scaling factor is obtained by looking up a table in the via parasitic capacitance library based on the device information of the target via. Based on this scaling factor and the standard parasitic capacitance between the first conductor object and the second conductor object, a means of compensating for the parasitic capacitance between the target via and the second conductor object is obtained. This achieves accurate calculation of the compensating parasitic capacitance of the target via, realizes the extraction of the parasitic capacitance of the target via, improves the overall accuracy of the extraction of the parasitic capacitance of the chip, and thus improves the design effect of the subsequent chip. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0012] Figure 1 A flowchart illustrating a method for extracting parasitic capacitance from a device layer via, provided in an embodiment of this application; Figure 2 A flowchart illustrating a method for compensating parasitic capacitance of a device layer via provided in this application embodiment; Figure 3 A front view of a 3D structure device with through holes provided in an embodiment of this application; Figure 4 A top view of a 3D structural device fabrication layout provided in an embodiment of this application; Figure 5 A front view of a 3D structure device without through holes, provided in an embodiment of this application; Figure 6 This is a structural diagram of a through-hole parasitic capacitance compensation device provided in an embodiment of this application; Figure 7 This is a structural diagram of a computer device provided in an embodiment of this application. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0014] With the continuous development of chips, the continuation of Moore's Law, and the continuous miniaturization of device dimensions, three-dimensional structure devices are the development trend. For devices with three-dimensional structures, typical three-dimensional devices include vias. As the parasitic capacitance of vias in integrated circuit layouts accounts for an increasingly larger proportion of the total parasitic capacitance of the device, accurately extracting the parasitic capacitance of vias in the device layer has become a key technical challenge.

[0015] However, existing process documentation typically does not specify which type of device vias can be used to build. Therefore, when constructing a device sample based on a 3D pattern, it is impossible to know which type of vias can be used to form this type of device, resulting in the inability to construct device samples containing vias, and thus the inability to directly extract the parasitic capacitance of the vias in the device layer.

[0016] Furthermore, even knowing which devices vias can be used to build, adding via models to a standard 3D model parasitic parameter library significantly increases the size and build time of the library. This increase in the size and build time of the parasitic capacitance library may be unacceptable to some users. Moreover, the parasitic capacitance extraction process may also increase the capacitance library loading time and program runtime memory usage.

[0017] To address the aforementioned issues, this application proposes a method for extracting the parasitic capacitance of vias in a device layer through parasitic capacitance compensation, and superimposing the via parasitic capacitance onto the upper and lower metal layers to characterize the effect of the via parasitic capacitance.

[0018] This application can indirectly determine the devices that can be formed by a via based on the device type of the device layers connected to it. Subsequently, a proportionality table is established between the parasitic capacitance of the via to other device layers and the parasitic capacitance of the device objects on the connected device layers to other device layers, and this proportionality table is stored in the program according to the process type. Finally, by multiplying the parasitic capacitance of the device objects on the connected device layers to other device layers by the proportionality table, the parasitic capacitance of the via to other device layers is calculated, and this value is then added to the device objects on the connected device layers.

[0019] Building a parasitic capacitance library by directly overlaying different via sizes onto a conventional 3D pattern would significantly increase the size of the 3D pattern's parasitic capacitance library. This application, however, calculates the parasitic capacitance between vias and device objects on other device layers, in addition to the existing 3D pattern, and determines the scaling factor between this capacitance and the parasitic capacitance between device objects on the layers above and below the via and device objects on other device layers. When extracting the via parasitic capacitance, it is only necessary to find the parasitic capacitance between device objects on the layers above and below the via and device objects on other device layers, and then multiply it by the found scaling factor to calculate the parasitic capacitance between the via and device objects on other device layers. Therefore, the method of this application can generate new 3D patterns separately for vias of different types and sizes without increasing the size of the general 3D pattern parasitic capacitance library. Furthermore, the parasitic capacitance between vias and device objects on other device layers extracted by the method of this application is very accurate.

[0020] Furthermore, without restrictions on the size of the 3D pattern parasitic capacitance library, more novel 3D patterns can be generated by superimposing via structures of different device types on top of general 3D patterns. Subsequently, a massive number of device samples are generated based on the sampling points of these newly added patterns, and the parasitic capacitances of vias and device objects on other device layers are directly stored. In the actual parasitic capacitance extraction process, the pre-stored capacitance parameters are directly called to complete the efficient extraction.

[0021] According to an embodiment of this application, a method for compensating parasitic capacitance through a via is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed on a computer device via a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here. The computer device can be a mobile terminal, a personal computer, a server, etc.

[0022] Figure 1 This is a flowchart illustrating a method for extracting compensated parasitic capacitance from vias, provided in an embodiment of this application. This via parasitic capacitance extraction method is applied to a chip. The chip may include multiple vias. Each via is connected to a device layer on both its upper and lower sides. Other device layers may also be disposed outside these device layers, containing device objects connected to the vias; these device objects are components of the device. In current parasitic capacitance extraction methods, the parasitic capacitance between device objects on one device layer and device objects on other device layers is typically extracted. However, this method ignores the parasitic capacitance existing between the via and the device objects on the device layer, leading to inaccurate extracted parasitic capacitance and consequently, inaccurate subsequent calculations. For example, in… Figure 3 and Figure 4 In the chip shown, the device objects on the upper and lower device layers connected by the via are the substrate and the source / drain, respectively. The device objects on other device layers can be gate, field polysilicon, etc.

[0023] The via parasitic capacitance extraction method of this application superimposes the parasitic capacitance of the via onto the parasitic capacitance of other device objects on the same device layer. In this embodiment, the computer device can identify a via to be processed and name the device object on the device layer connected to the via as a first conductor object. Other device objects on other device layers that are not directly connected to the via and are used to calculate parasitic capacitance are named second conductor objects. The second conductor object and the first conductor object have an electrical interaction. Furthermore, the first conductor object, the second conductor object, the via, and the device objects on other device layers connected to the via together constitute a single device.

[0024] Furthermore, in the chip of this application, multiple devices can share a first conductor object, a second conductor object, or a device object on another device layer connected to a via. For example, such as Figure 3 The first gate on the left side, as shown, can be used together with the first and second sources / drains on the left side to form device 1. Similarly, the second source / drain on the left side can be used together with the second gate on the left side and the third source / drain on the left side to form device 2. The second source / drain on the left side is shared by both device 1 and device 2.

[0025] For example, a through hole can be like... Figure 3 The leftmost via shown is represented by the source / drain above it, and the second conductor can be the leftmost gate. The computer device can then compensate for the parasitic capacitance between the leftmost via and the leftmost gate by applying it to the standard parasitic capacitance between the leftmost source / drain and the leftmost gate, thus obtaining the target parasitic capacitance.

[0026] For example, a through hole can be like... Figure 3 The second via shown on the left is the first conductor object, which is the second source / drain on the left above the via. The second conductor object can be the leftmost gate. The computer device can then compensate the parasitic capacitance between the second via and the leftmost gate by applying it to the standard parasitic capacitance between the second source / drain and the leftmost gate to obtain the target parasitic capacitance.

[0027] Optionally, when the computer device needs to calculate and compensate for the parasitic capacitance between the via and the field polysilicon, the computer device can use the field polysilicon as a second conductor object and perform the calculation using the method of this embodiment. The calculation of the compensated parasitic capacitance and target parasitic capacitance between other vias and device objects on other device layers is similar.

[0028] like Figure 1 As shown, with computer equipment as the executing entity, this process includes the following steps: S101. Based on the device information of the target via, the scaling factor of the target via is obtained by searching the via parasitic capacitance library. The scaling factor represents the ratio of the first parasitic capacitance between the via and the second conductor object to the standard parasitic capacitance between the first conductor object and the second conductor object. The via parasitic capacitance library is generated based on the device information and scaling factors of multiple preset via samples.

[0029] In this embodiment, after obtaining the device information of the target via, the computer device can use the device information to search in the pre-generated via parasitic capacitance library to obtain the scaling factor of the target via.

[0030] In one implementation, the via parasitic capacitance library includes a mapping relationship between device information and scaling factors for different via samples. Specifically, the device information for each via sample in the via parasitic capacitance library can be represented by device type and device size.

[0031] In one implementation, when multiple scaling factors matching the device information of the target via are found in the via parasitic capacitance library based on the device information of the target via, the computer device can calculate the scaling factor of the target via corresponding to the device information of the target via based on the multiple scaling factors using interpolation or other methods.

[0032] In one implementation, the scaling factor is used to indicate the ratio of the first parasitic capacitance between the target via and the second conductor object to the standard parasitic capacitance between the first conductor object and the second conductor object.

[0033] Optionally, based on this scaling factor and the standard parasitic capacitance between the first and second conductor objects, the computer device can calculate the compensated parasitic capacitance between the target via and the second conductor object. This compensated parasitic capacitance is an estimate of the first parasitic capacitance between the target via and the second conductor object.

[0034] The first conductor object, the second conductor object, and the via are all device objects that make up the device. Specifically, the first conductor object is a device object on a device layer within the chip, located above and below the target via, and directly connected to the target via. For example, the first conductor object can be as follows: Figure 3 The source / drain device objects shown.

[0035] The second conductor object is a device object in another device layer of the chip that has an electrical interaction with the first conductor object. For example, in... Figure 3 In the chip shown, the second conductor object can be a device object such as a gate or field polysilicon.

[0036] S102. Based on the standard parasitic capacitance between the first conductor object and the second conductor object and the scaling factor of the target via, calculate the compensated parasitic capacitance between the target via and the second conductor object.

[0037] In this embodiment, the computer device calculates and obtains the standard parasitic capacitance between the first conductor object and the second conductor object. Then, the computer device can use this standard parasitic capacitance to multiply by the scaling factor of the target via to calculate the compensated parasitic capacitance between the target via and the second conductor object.

[0038] In one implementation, the standard parasitic capacitance between the first conductor object and the second conductor object can be obtained by looking up a table or by calculation.

[0039] The inherent parasitic capacitance between the first and second conductor objects due to factors such as coupling can be predetermined through theoretical calculations, experimental measurements, or empirical formulas, without considering the influence of vias.

[0040] Optionally, the computer device can obtain the standard parasitic capacitance between the first conductor object and the second conductor object by searching a preset standard parasitic capacitance library. The standard parasitic capacitance library includes the mapping relationship between the first conductor object sample, the second conductor object sample, and the standard parasitic capacitance.

[0041] The preset standard parasitic capacitance library stores data that maps the first and second conductor objects to standard parasitic capacitances. This standard parasitic capacitance library can be stored in a database or in memory.

[0042] In one implementation, the compensating parasitic capacitance is actually an estimated value of the first parasitic capacitance between the target via and the second conductor object.

[0043] In one implementation, the computer equipment can also introduce some correction coefficients related to process deviations, temperature changes, etc., during the calculation of the parasitic compensation capacitance to further adjust the value of the parasitic compensation capacitance and improve the accuracy of the parasitic compensation capacitance.

[0044] For example, the correction factor can be a parameter related to temperature change. The computer device can normalize this parameter to obtain the correction factor. The computer device can then use the product of the standard parasitic capacitance, the proportional coefficient, and the correction factor as the compensation parasitic capacitance.

[0045] In this embodiment, based on the device information of the target via, the proportional coefficient corresponding to the target via is obtained by looking up a table in the via parasitic capacitance library. Based on this proportional coefficient and the standard parasitic capacitance between the first conductor object and the second conductor object, the compensation parasitic capacitance between the target via and the second conductor object is obtained. This embodiment achieves accurate and rapid calculation of the compensation parasitic capacitance of the target via, realizes the extraction of the parasitic capacitance of the target via, improves the accuracy of the overall parasitic capacitance extraction of the chip, and thus improves the design effect of subsequent chips. The construction of the via parasitic capacitance library and the accurate and rapid calculation of the compensation parasitic capacitance of the target via provide an essential foundation.

[0046] In one example, before searching for the scaling factor of the target via in the via parasitic capacitance library in step S101 above, the computer device needs to generate the via parasitic capacitance library first. The construction of this via parasitic capacitance library is actually the construction of a 3D pattern parasitic capacitance library. During this process, based on process design rules and the 3D pattern, a large number of device samples with different structures and sizes can be constructed, and the various parasitic capacitance components in the device samples can be solved and pre-stored. Therefore, before constructing these different types of device samples, it is necessary to know which device layers can form which types of devices. The construction process of this via parasitic capacitance library includes: S201. Generate a via parasitic capacitance library based on device information and scaling factors from multiple preset via samples.

[0047] For example, a computer device can acquire multiple chip samples containing vias. Based on these chip samples, the computer device can obtain device information for the via samples. Further, based on the device information of the via samples, the computer device can calculate the scaling factor for the via sample. Then, the computer device can combine the device information and scaling factor of the via samples from these chip samples into a data pair and write this data pair into a via parasitic capacitance library.

[0048] In this example, the via parasitic capacitance library generated based on via samples facilitates the lookup of scaling factors in subsequent use, based on the device information of the target via. This improves the efficiency of scaling factor acquisition and the extraction efficiency of the target via's compensating parasitic capacitance. Furthermore, by extracting the parasitic capacitance of the target via, the overall accuracy of the chip's parasitic capacitance extraction is further improved, thereby enhancing the design performance of the subsequent chip.

[0049] In one example, step S201 above, generating a via parasitic capacitance library based on device information and scaling factors of multiple preset via samples, includes: S2011. Determine the device information of the via sample corresponding to each preset sampling point.

[0050] For example, a computer device may have multiple preset sampling points. Based on each chip sample, the computer device can form a via sample for each chip sample and sampling point. Different via samples correspond to different device information. Optionally, each sampling point can be a scaling factor. Multiple sampling points have different scaling factors.

[0051] In one implementation, since the first conductor object sample, second conductor object sample, and via sample in the designed chip sample typically have a reference size, a computer device can scale the reference size of the first conductor object sample, second conductor object sample, and via sample in the chip sample based on these multiple sampling points, thereby calculating multiple possible sizes of the first conductor object sample, second conductor object sample, and via sample. Furthermore, the computer device can determine the device information of the via sample based on these possible sizes of the first conductor object sample, second conductor object sample, and via sample.

[0052] In one implementation, a computer device can determine the device information of a first conductor object sample connected to the via sample based on the device information of that sample. The device information of the first conductor object sample can be determined based on information written in the process document and the sampling point.

[0053] Since the device information for via samples is not usually directly defined in the process documentation, computer equipment can indirectly determine which devices the via sample is used to form based on the device information of the first conductor object sample connected to the via sample, thereby determining the device information of the via sample.

[0054] Optionally, the via sample typically belongs to the same device as the connected first conductor object sample. Therefore, after determining the device of the first conductor object sample based on the process document, the computer device can use the device of the first conductor object sample as the device of the via sample, thereby indirectly determining the constituent devices of the via sample. Furthermore, the computer device can determine the device information of the via sample based on the device information of the first conductor object sample.

[0055] For example, the computer device can use the device type of the first conductor object sample as the device type of the via sample. Also, the computer device can use the size of the first conductor object sample as the device size of the via sample.

[0056] In one implementation, the process document may include various process parameters and specifications involved in the manufacturing process. This information determines the physical properties of the first conductor object sample, the second conductor object sample, and the through-hole sample.

[0057] S2012. Based on the device information of the via sample and the device information of the second conductor object sample, the first parasitic capacitance between the via sample and the second conductor object sample corresponding to each sampling point is obtained.

[0058] For example, the computer device can directly obtain the device information of the second conductor object sample from the design file. Then, based on the device information of the via sample and the second conductor object sample, the computer device can use methods such as field solvers or pattern matching to calculate the first parasitic capacitance, and obtain the parasitic capacitance between the via sample and the second conductor object sample corresponding to each sampling point.

[0059] S2013. Calculate the ratio of the first parasitic capacitance between the through-hole sample and the second conductor object sample corresponding to each sampling point to the standard parasitic capacitance between the first conductor object sample and the second conductor object sample, and obtain the proportional coefficient of the through-hole sample corresponding to each sampling point.

[0060] For example, the computer device can calculate the standard parasitic capacitance between the first conductor object sample and the second conductor object sample. Furthermore, the computer device can calculate the ratio of the first parasitic capacitance to the standard parasitic capacitance corresponding to each sampling point, obtaining the scaling factor for the via sample corresponding to each sampling point.

[0061] In one implementation, the computer device can preprocess the two capacitor values ​​before performing the division operation to check for zero or near-zero values, thus avoiding division-to-zero errors or numerical overflow problems.

[0062] S2014. Based on the device information and the scaling factor of multiple via samples, generate a via parasitic capacitance library.

[0063] For example, a computer device can write the device information based on the via sample corresponding to each sampling point and the calculated scaling factor corresponding to each via sample into the via parasitic capacitance library.

[0064] When the via parasitic capacitance library is stored as a data table, each data item represents a via sample. Each data item can have three dimensions of data. These three dimensions can be: the device size of the via sample, the device type of the via sample, and the scale factor of the via sample.

[0065] Because layer operations generate different device samples when the via sample corresponds to different device types, the computer device needs to write the device type of the via sample into the via parasitic capacitance library as a dimension, so as to facilitate the selection of scaling factors based on different device types.

[0066] In one implementation, to avoid the influence of data randomness, the computer device can set multiple via samples for each type of device information. These via samples with the same device information can be recorded in a via parasitic capacitance library.

[0067] In another implementation, to avoid data redundancy, when multiple via samples have the same device information, data fusion can be used to fuse the scaling factors of the multiple via samples with the same device information and record them as a data item in the via parasitic capacitance library.

[0068] In one implementation, the computer device can directly retrieve the proportional coefficient corresponding to the target via from the via parasitic capacitance library during subsequent calculations, based on the device information of the target via, thereby improving the efficiency of obtaining the proportional coefficient.

[0069] In one implementation, the spatial relationship between the via sample and different second conductor object samples will inevitably lead to different scaling factors. Therefore, the computer device can write the device information of the second conductor object sample into the scaling factor table to facilitate the subsequent acquisition of different scaling factors for different second conductor object samples.

[0070] In this example, a via sample is acquired, and the device information of the via sample is determined based on the first conductor object sample connected to it. Then, based on the device information of the sampling points and the second conductor object sample, the first parasitic capacitance of the via sample corresponding to each sampling point is calculated. Based on the ratio of this first parasitic capacitance to the standard capacitance, the scaling factor of the via sample corresponding to each sampling point is determined. Finally, a via parasitic capacitance library is generated based on the sampling points, via samples, and scaling factors. This method enables the generation of the parasitic capacitance library, allowing the scaling factor to be obtained simply by looking up a table, thus improving the efficiency of scaling factor acquisition and the extraction efficiency of the target via's compensating parasitic capacitance. Furthermore, by extracting the parasitic capacitance of the target via, the overall accuracy of the chip's parasitic capacitance extraction is further improved, thereby enhancing the design performance of subsequent chips.

[0071] In one example, the device information may specifically include device type and device size. Therefore, determining the device information of the via sample corresponding to each preset sampling point may specifically include determining the device type and device size of the via sample. Since the computer device can determine the device information of the via sample based on the device information of the first conductor object sample connected to the via sample, the process of determining the device information of the via sample corresponding to each preset sampling point in step S2011 may include at least one of the following steps for the first conductor object sample: Step 111: Determine the device type of the first conductor object sample connected to the via sample as the device type of the via sample.

[0072] For example, since the device type of a via is typically not defined in the process documentation provided by a third party, but the connection relationship between the device object on the device layer and the via is specified, the computer device can assume that the via sample and the first conductor object sample together constitute the corresponding device, based on the fact that the first conductor object sample is a device object on the device layer directly connected to the via sample. That is, the computer device can determine the device type corresponding to the first conductor object sample as the device type corresponding to the via.

[0073] The device types can include metal-oxide-semiconductor field-effect transistors (MOSFETs) with N-channel, P-channel, NPN, and PNP characteristics. Furthermore, for MOSFETs, threshold voltage can be categorized into low threshold voltage (LVT), standard threshold voltage (SVT), and high threshold voltage (HVT) types, resulting in device types such as LVT_NMOS, LVT_PMMOS, SVT_NMOS, SVT_PMMOS, HVT_NMOS, and HVT_PMMOS. Functionally, they can also include MOSFETs with input / output (I / O) terminals, resulting in device types such as IO_NMOS and IO_PMMOS.

[0074] In one implementation, the computer device can further obtain the device type of the second conductor object sample and determine that device type as the device type of the via sample. Generally, the via sample, the first conductor object sample, and the second conductor object sample constitute the same device, therefore their device types are identical.

[0075] In another implementation, the device type of the via sample can be preset, and the device information of the device object on the device layer connected to the via sample can be determined based on the device type of the via sample. The preset device type of the via sample is a device type existing in the standard parasitic capacitance library. Furthermore, the device size of the via sample can be determined based on the device information of the device object on the device layer connected to the via sample.

[0076] In one implementation, the first conductor object sample can be a source / drain. The device type of this first conductor object sample is then the type corresponding to the device constructed from that source / drain.

[0077] Step 112: Determine the reference dimensions of the through-hole sample.

[0078] For example, the dimensions of a via are an important reference for via fabrication and performance analysis. A via sample typically has the same length and width dimensions as a first conductor object sample. For instance, when the first conductor object sample is a source / drain, the via sample has the same length and width dimensions as the source / drain. A computer device can design multiple chip samples containing via samples. The computer device can determine the reference dimensions of the via samples in the chip samples based on the via samples in these chip samples and the first conductor object samples connected to the via samples.

[0079] Optionally, since the design of the chip sample is typically based on a baseline design, the via sample, the first conductor object sample, and the second conductor object sample in the chip sample all have a baseline size.

[0080] In one implementation, the computer device can also directly determine the reference size of the via sample based on a preset value. Then, based on the via sample with the reference size, a first conductor object sample and a second conductor object sample in the chip sample are constructed.

[0081] Step 113: Scale the reference size of the via sample based on each sampling point to obtain the device size of the via sample corresponding to each sampling point.

[0082] For example, first determine the reference size of the via sample in the chip sample, and then scale the reference size based on each sampling point to obtain the device size of the via sample corresponding to each sampling point.

[0083] Each sampling point can correspond to a scaling factor. This scaling factor is used to scale the baseline size of the via samples in the chip sample to obtain the device size of different via samples. The device size of the via sample, together with the device type of the via sample, can serve as the device information of the via sample corresponding to each sampling point.

[0084] Optionally, when scaling the reference size of the via sample in the chip sample based on the sampling point, the device information of the first conductor object sample and the second conductor object sample related to the via sample can also change synchronously, and the scaling ratio, that is, the magnification factor corresponding to the sampling point, can be different.

[0085] For example, these multiple sampling points can be uniformly amplified, such as 0.5x, 1x, 2x, 3x, 4x, etc. Alternatively, these multiple sampling points can be non-uniformly amplified based on capacitance changes, such as 1x, 1.5x, 1.8x, 2x, etc.

[0086] In one implementation, the device dimensions of the via sample may include information such as the length, width, and thickness of the via.

[0087] In one implementation, while scaling the via sample based on its reference size, the device information of the first conductor object sample and the second conductor object sample used to calculate the parasitic capacitance corresponding to the via sample can typically be scaled synchronously. The scaling factors for the first conductor object sample, the second conductor object sample, and the via sample can be the same or different.

[0088] In this example, based on sampling points and the device type and size indicated in the device information of the first conductor object sample, the method of determining the device type and size indicated in the device information of the via sample achieves accurate acquisition of the device information of the via sample. This solves the problem of lacking device information for the via sample in the prior art, providing a data foundation for the subsequent calculation of the first parasitic capacitance, improving the efficiency of obtaining the scaling factor, and improving the extraction efficiency of the parasitic capacitance compensation of the target via. Furthermore, by extracting the parasitic capacitance of the target via, the accuracy of extracting the overall parasitic capacitance of the chip is further improved, thereby improving the design effect of the subsequent chip.

[0089] In one example, step S2012 above, based on preset multiple sampling points, device information of via samples, and device information of second conductor object samples, calculates the first parasitic capacitance between the via sample and the second conductor object sample corresponding to each sampling point, including: Step 121: Determine the device size of the second conductor object sample as indicated in the device information of the second conductor object sample; based on the device size of the via sample corresponding to each sampling point and the device size of the second conductor object sample as indicated in the device information of the second conductor object sample, solve for the first parasitic capacitance between the via sample corresponding to each sampling point and the second conductor object sample.

[0090] For example, a computer device can determine the device size of a second conductor object sample as indicated in the device information of the second conductor object sample from a process parameter file.

[0091] In one implementation, the computer device can further determine the scaling factor of the device size of the second conductor object sample based on the sampling points corresponding to the via sample. Then, the computer device can scale the second conductor object sample to obtain the device size of the second conductor object sample required for calculation in this step, based on the reference size of the second conductor object sample determined from the process parameter file.

[0092] For example, a computer device can solve for the first parasitic capacitance between the via sample and the second conductor object sample based on the device size of the via sample and the device size of the second conductor object sample.

[0093] Among them, the device size of the via sample corresponding to different sampling points can be combined with the device size of different second conductor object samples to form different device samples for calculating parasitic capacitance.

[0094] For example, the computer device can calculate the first parasitic capacitance corresponding to each sampling point based on the device size of the via sample corresponding to each sampling point calculated in step 121, combined with the device size of the second conductor object sample.

[0095] In one implementation, the computer device can use an accurate field solver to solve for the first parasitic capacitance between the via sample and the second conductor object sample. This accurate field solver can first construct a device sample based on the device dimensions of the via sample. The device sample is a virtual model obtained by abstracting and modeling the actual via sample and its surrounding environment; it contains information such as the geometry and material properties of the via sample. Optionally, the device sample can be generated using layer operations.

[0096] In this example, by calculating the sampling dimensions of multiple via samples based on multiple sampling points, and using the device dimensions of the via samples and the device information of the second conductor object sample, the first parasitic capacitance corresponding to each sampling point is calculated. This allows for the estimation of the first parasitic capacitance corresponding to multiple sampling points for each via sample, providing a data foundation for the subsequent calculation of the scaling factor of the via sample at each sampling point. This improves the efficiency of obtaining the scaling factor and the efficiency of extracting the parasitic capacitance compensation of the target via. Furthermore, by extracting the parasitic capacitance of the target via, the accuracy of extracting the overall parasitic capacitance of the chip is further improved, thereby enhancing the design performance of the subsequent chip.

[0097] In one example, where data storage space is sufficient and data loading efficiency is not critical, the via parasitic capacitance library can also include compensating parasitic capacitances corresponding to the via samples. The computer device can directly look up the compensating parasitic capacitance between the via sample and the second conductor sample based on the device information of the target via, the first conductor object sample, and the second conductor object sample. This method can further improve the efficiency of obtaining the compensating parasitic capacitance.

[0098] In step S101 above, based on the device information of the target via, the scaling factor of the target via is obtained by searching the via parasitic capacitance library, including: S1011. Find at least one candidate via sample with the same device type as the target via in the via parasitic capacitance library.

[0099] For example, after obtaining the device information of the target via, the computer device can first obtain the device type contained in the device information. Based on the device type, the computer device can search for at least one candidate via sample with the same device type as the target via in the via parasitic capacitance library.

[0100] In one implementation, if the via parasitic capacitance library contains multiple via samples with the same device type as the target via, the computer device can acquire data items from all via samples with the same device type. The computer device can then record these acquired data items as candidate via samples.

[0101] S1012. Match the device size of the target via with the device size of each candidate via sample to obtain at least one target via sample that matches the target via.

[0102] For example, a computer device can obtain the device size of the target via. Then, the computer device determines at least one candidate via sample that matches the device size of the target via from among the candidate via samples.

[0103] In one implementation, a computer device can determine that among all candidate via samples, the candidate via sample whose device size is closest to that of the target via is the target via sample.

[0104] For example, when the difference between the device size of the target via and the device size of any candidate via sample is less than or equal to a preset error threshold, the candidate via sample can be determined to be the target via sample that matches the target via.

[0105] For example, when the difference between the device size of the target via and the device size of the candidate via samples is greater than a preset error threshold, a preset number of candidate via samples that are closest to the via size of the target via can be identified as the target via samples. This preset number can be one, two, or more.

[0106] S1013. Determine the scale factor of the target through hole based on the scale factor of at least one target through hole sample.

[0107] For example, after determining each target via sample, the computer device can look up the corresponding scaling factor for that target via sample in a via parasitic capacitance library. The computer device can then determine the scaling factor for the target via based on at least one of the retrieved scaling factors.

[0108] In one implementation, when there are multiple target via samples, the computer device can fuse at least one scaling factor based on a preset fusion method to obtain the final scaling factor of the target via. Optionally, the computer device can use the average or weighted sum of multiple scaling factors of multiple target via samples as the scaling factor of the target via.

[0109] In another embodiment, the computer device can also obtain the final target through-hole ratio by interpolating the target through-hole sample.

[0110] In this example, the scaling factor of the target via was accurately obtained by looking up a table, improving the efficiency of obtaining the scaling factor and thus improving the efficiency of extracting the parasitic capacitance of the target via. Furthermore, by extracting the parasitic capacitance of the target via, the accuracy of extracting the overall parasitic capacitance of the chip was further improved, thereby enhancing the design performance of subsequent chips.

[0111] In one example, based on the above embodiment, after calculating the compensated parasitic capacitance between the target via and the second conductor object, the computer device can also superimpose the compensated parasitic capacitance onto the standard parasitic capacitance between the first conductor object and the second conductor object to obtain the compensated target parasitic capacitance.

[0112] In this embodiment, the computer device can superimpose the compensated parasitic capacitance calculated in step S102 with the standard parasitic capacitance between the first conductor object and the second conductor object to obtain the compensated target parasitic capacitance.

[0113] In one implementation, the computer device can add the values ​​of the compensated parasitic capacitance and the standard parasitic capacitance to obtain the target parasitic capacitance.

[0114] In another implementation, the computer device can obtain the target parasitic capacitance by weighted summation of the compensated parasitic capacitance and the standard parasitic capacitance. For example, based on the differences in the influence of vias at different locations or under different process conditions, different weights can be assigned to the compensated parasitic capacitance, and then it can be added to the standard parasitic capacitance to obtain a more accurate target parasitic capacitance.

[0115] For example, based on the target parasitic capacitance, the computer device can perform more accurate calculations on the chip in subsequent calculations, thereby improving the design efficiency of the chip and avoiding the problem of inaccurate calculations caused by the omission of the parasitic capacitance between the via and the second conductor object.

[0116] Figure 2 This is a flowchart illustrating a method for extracting the parasitic capacitance of a via provided in an embodiment of this application. Figure 1 Based on the illustrated embodiments, as Figure 2 As shown, with a computer device as the execution subject, the process includes the following steps: S301. Identify the device type corresponding to the first conductor object sample connected to the through-hole sample, and then determine the device type of the through-hole sample.

[0117] For example, a computer device can identify the device type corresponding to the first conductor object sample connected to the via sample based on layer connection rules. Furthermore, the computer device can determine the device formed by the via sample and the first conductor object sample, and determine the device type corresponding to the via sample.

[0118] Although the process documentation provided by the third party does not directly define the device type corresponding to the via sample, it typically defines the device type corresponding to the first conductor object sample connected to the via sample. Therefore, the computer device can determine the first conductor object sample connected to the via sample based on the layer connection rules defined in the process documentation, and then determine the device type of the first conductor object sample as defined in the process documentation. Furthermore, the computer device can indirectly determine which types of devices the via sample can constitute based on the device type of the first conductor object sample connected to the via sample, thereby determining the device type to which the via sample belongs.

[0119] S302. Determine the device size of the through-hole sample based on the device size and preset sampling points specified in the process document for the first conductor object sample connected to the through-hole sample.

[0120] For example, when selecting sampling points for via samples, a strict Design Rule Check (DRC) must be followed to ensure that the distance between the edge of different types of via samples and the first conductor object sample they are connected to is within the range allowed by the design rules. Simultaneously, multiple sampling points must be determined after comprehensively considering the above factors, taking into account different process types, referring to the standard dimensions of via length and width and the etching process effect table defined in third-party process documents.

[0121] Computer equipment can determine the reference dimensions of vias in a chip sample based on the chip sample and its process documents, and then scale these reference dimensions using the scaling ratio of the sampling point to obtain the device dimensions of multiple chip samples.

[0122] S303. Construct device samples of different device types based on the three-dimensional layout, and use an accurate field solver to solve the first parasitic capacitance between the via sample and the second conductor object sample, and to solve the standard parasitic capacitance between the first conductor object sample connected to the via sample and the second conductor object sample.

[0123] For example, based on a 3D layout, a computer device can generate realistic 3D device samples using layer operations according to via samples of different device types. Furthermore, in this process, based on each sampling point of a via sample of a device type, the computer device can generate its corresponding 3D device sample.

[0124] Subsequently, the computer device can use a precise field solver to solve for the first parasitic capacitance between the via sample and the second conductor object sample. Furthermore, the computer device can also use a precise field solver to solve for the standard parasitic capacitance between the first conductor object sample and the second conductor object sample. Here, the second conductor object sample is a device object on another device layer in the chip. For example, in... Figure 3 and Figure 4 In this context, the second conductor object sample can be a gate or a field polysilicon.

[0125] S304. Solve for the ratio of the first parasitic capacitance to the standard parasitic capacitance of each via sample to obtain the scaling factor of each via sample; store the device type, device size and scaling factor of each via sample in the via parasitic capacitance library.

[0126] For example, a computer device can use the first parasitic capacitance and the standard capacitance obtained from the via samples of various device types at each sampling point, calculate their ratio, and obtain the scaling factor of the via samples of each device type. Then, the computer device stores the scaling factor of each via sample in a via parasitic capacitance library according to device type and sampling point.

[0127] The computer device can load the via parasitic capacitance library the next time the chip is loaded. When extracting the parasitic capacitance of a target via, the computer device can directly obtain the scaling factor for that target via from the via parasitic capacitance library based on the device information of the target via. Furthermore, based on this scaling factor, the computer device can calculate the compensating parasitic capacitance of the target via and use this compensating parasitic capacitance to compensate for the standard parasitic capacitance, thus obtaining the target parasitic capacitance.

[0128] S305. Based on the standard parasitic capacitance library of a general three-dimensional layout, find the standard parasitic capacitance between the first conductor object and the second conductor object corresponding to the target via; and find the scaling factor from the via parasitic capacitance library based on the device information of the target via; calculate the product of the standard parasitic capacitance and the scaling factor to obtain the compensation parasitic capacitance between the target via and the second conductor object.

[0129] For example, a computer device can look up a scaling factor in a via parasitic capacitance library based on the device type and via size of the target via. This scaling factor lookup can be done using linear or non-linear interpolation.

[0130] Furthermore, the computer device can use linear or nonlinear interpolation to find the standard parasitic capacitance between the first conductor object and the second conductor object corresponding to the target via from a general 3D pattern standard parasitic capacitance library.

[0131] The computer equipment can then calculate the product of the scaling factor and the standard parasitic capacitance to estimate the compensated parasitic capacitance between the target via and the second conductor object.

[0132] S306. The compensated parasitic capacitance is superimposed on the standard parasitic capacitance between the first conductor object and the second conductor object corresponding to the target via to obtain the target parasitic capacitance. This target parasitic capacitance can be used to equivalently simulate the parasitic capacitance between the via and the first conductor object and the second conductor object, thereby improving the accuracy of parasitic capacitance extraction.

[0133] In this embodiment, a via parasitic capacitance library is constructed based on the device type, sampling points, and scaling factor of via samples. Based on the device information of the target via, the scaling factor is obtained from the via parasitic capacitance library. Then, the target parasitic capacitance after compensation is calculated based on the standard parasitic capacitance. This method improves the accuracy of parasitic capacitance extraction for the entire chip.

[0134] Figure 3 This is a front view of a 3D structure device with through holes provided in an embodiment of this application. Figure 4 This is a top view of a 3D structural device fabrication layout provided in an embodiment of this application. Figure 5 This is a front view of a 3D structural device without through holes, provided as an embodiment of this application.

[0135] like Figures 3 to 5 As shown, a via is provided between the substrate and the source / drain. The source / drain connected to this via is the first conductor. A large parasitic capacitance exists between this via and the gate or field polysilicon. This gate or field polysilicon can be the second conductor. Because this via structure does not exist in typical 3D layouts, it is impossible to establish a lookup table for the parasitic capacitance between the via and the gate or field polysilicon, resulting in the loss of this parasitic capacitance during the actual extraction process.

[0136] To address the aforementioned problem scenarios, the parasitic capacitance compensation method proposed in this application can be adopted, with the following steps: S401. Based on the process technology documents provided by the third party, identify the device type of the source / drain connected by the through-hole, and confirm the device type of the through-hole accordingly. This source / drain is the first conductor object.

[0137] S402. Due to the significant parasitic capacitance between vias and the gate, field polysilicon, and other adjacent vias, the main environment of these parasitic capacitances must be considered when designing the 3D layout. Furthermore, under DRC design rules, vias typically have the same length and width dimensions as the source / drain they connect to. Therefore, designs such as... Figure 3 and Figure 4 The three-dimensional layout shown includes the width of the via, the width of the gate, the width of the trench contact, the length of the field polysilicon, the length of the shallow trench isolation, and other three-dimensional structural parameters of the device. The maximum variation range is specified in the process documents and design rules, and a sampling point is selected at appropriate intervals.

[0138] S403, according to Figure 3 The three-dimensional layout shown is used to perform layer operation according to the determined device type and sampling points, using the 3D layer in the process file to generate a three-dimensional structure device sample. The precise field solver is used to solve the first parasitic capacitance between the via and the gate, the field polysilicon, and the second parasitic capacitance between the source / drain connected to the via and the gate or the source / drain connected to the field polysilicon.

[0139] S404. Calculate the ratio of the first parasitic capacitance to the second parasitic capacitance to obtain the proportionality coefficient. Then, generate a proportionality coefficient table according to device type and sampling points. Based on this table, the proportionality coefficient can be calculated.

[0140] S405. During the extraction of parasitic capacitance from vias, first locate the source / drain connections of the via. Check if the surrounding environment meets the following requirements: Figure 5 The diagram shows a typical 3D layout. If satisfied, based on the corresponding device type and sampling points, the standard parasitic capacitance between the gate and source / drain, as well as the standard parasitic capacitance between the field polysilicon and source / drain, are retrieved from a general 3D layout capacitance library using linear or nonlinear interpolation. Simultaneously, based on the same device type and sampling points, and combined with the via dimensions, the scaling factor is obtained by looking up the scaling factor table using linear or nonlinear interpolation.

[0141] Multiplying the standard parasitic capacitance between the gate and the source / drain by the corresponding scaling factor yields the compensated parasitic capacitance between the gate and the source / drain. Similarly, multiplying the standard parasitic capacitance between the field polysilicon and the source / drain by the corresponding scaling factor yields the compensated parasitic capacitance between the field polysilicon and the via.

[0142] S406. The compensated parasitic capacitance between the gate and the via obtained in step S405 is superimposed on the standard parasitic capacitance between the gate and the source / drain to obtain the optimized target parasitic capacitance. The compensated parasitic capacitance between the field polysilicon and the via obtained in step S405 is superimposed on the standard parasitic capacitance between the field polysilicon and the source / drain to obtain the optimized target parasitic capacitance.

[0143] In this embodiment, by designing device samples in a 3D layout, the proportional coefficient between vias and other devices is calculated, thereby realizing the calculation of the parasitic capacitance of vias and obtaining the compensated target parasitic capacitance. This improves the accuracy of capacitance extraction and avoids the problem of inaccurate calculations in the chip design process caused by missing the parasitic capacitance of vias.

[0144] In one example, if there are no requirements on the size of the parasitic capacitance library in the 3D layout, vias of different device types can be added to a general 3D layout to generate more new 3D layouts. Then, a large number of new device samples are generated based on the sampling points, and the compensation parasitic capacitance between the vias of different device types and the second conductor object is directly stored. This enables a method to directly find and obtain the corresponding target parasitic capacitance through 3D layout matching during the actual parasitic capacitance extraction process.

[0145] Figure 6 A structural diagram of a through-hole compensation parasitic capacitance extraction device provided in an embodiment of this application is shown below. Figure 6 As shown, the chip includes a target via, a first conductor object connected to the target via, and a second conductor object not directly connected to the target via. The via's parasitic capacitance extraction device 600 includes: The lookup module 601 is used to search for the scaling factor of the target via in the via parasitic capacitance library based on the device information of the target via. The scaling factor represents the ratio of the first parasitic capacitance between the via and the second conductor object to the standard parasitic capacitance between the first conductor object and the second conductor object. The via parasitic capacitance library is generated based on the device information and scaling factors of multiple preset via samples.

[0146] The calculation module 602 is used to calculate the compensation parasitic capacitance between the target via and the second conductor object based on the standard parasitic capacitance between the first conductor object and the second conductor object and the scaling factor of the target via.

[0147] In one example, the via-hole compensation parasitic capacitance extraction device 600 further includes: The generation module 603 is used to generate a via parasitic capacitance library based on device information and scaling factors of multiple preset via samples.

[0148] In one example, module 603 is used for: Determine the device information of the via sample corresponding to each preset sampling point; Based on the device information of the via sample and the device information of the second conductor object sample, the first parasitic capacitance between the via sample and the second conductor object sample corresponding to each sampling point is obtained. Calculate the ratio of the first parasitic capacitance between the via sample and the second conductor object sample corresponding to each sampling point to the standard parasitic capacitance between the first conductor object sample and the second conductor object sample, and obtain the proportional coefficient of the via sample corresponding to each sampling point. Based on the device information and the scaling factor of multiple via samples, a via parasitic capacitance library is generated.

[0149] In one example, the device information includes: device type and device size. Generation module 603 is used for: The device type of the first conductor object connected to the via sample is determined as the device type of the via sample.

[0150] Determine the reference dimensions of the through hole.

[0151] The reference size of the via is scaled based on each sampling point to obtain the device size of the via sample corresponding to each sampling point.

[0152] In one example, module 603 is used for: Determine the device dimensions of the second conductor object sample as indicated in the device information of the second conductor object sample; Based on the device size of the via sample corresponding to each sampling point and the device size of the second conductor object sample indicated in the device information of the second conductor object sample, the first parasitic capacitance between the via sample corresponding to each sampling point and the second conductor object sample is calculated.

[0153] In one example, the lookup module 601 is used for: At least one candidate via sample with the same device type as the target via is found in the via parasitic capacitance library.

[0154] The device size of the target via is matched with the device size of each candidate via sample to obtain at least one target via sample that matches the target via.

[0155] The scaling factor of the target through hole is determined based on the scaling factor of at least one target through hole sample.

[0156] In one example, the calculation module 602 is used for: The compensated parasitic capacitance is superimposed on the standard parasitic capacitance between the first conductor object and the second conductor object to obtain the compensated target parasitic capacitance.

[0157] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0158] In this embodiment, the through-hole parasitic capacitance compensation device is presented in the form of a functional unit. Here, a unit refers to an application-specific integrated circuit (ASIC), a processor and memory that execute one or more software or fixed programs, and / or other modules that can provide the above functions.

[0159] Figure 7 A structural diagram of a computer device provided in an embodiment of this application, such as... Figure 7 As shown, the computer device 700 includes: one or more processors 701, memory 702, and interfaces for connecting the components.

[0160] Processor 701 may be a central processing unit, a network processor, or a combination thereof. Processor 701 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic module (PLM), or a combination thereof. The programmable logic module may be a complex programmable logic module (CPL), a field-programmable gate array (FPGA), a general-purpose array logic (GMAC), or any combination thereof.

[0161] The memory 702 stores instructions executable by at least one processor 701 to cause the at least one processor 701 to perform the method shown in the above embodiments.

[0162] The memory 702 may include a program storage area and a data storage area, wherein the program storage area may store application programs required for operating the device and at least one function; and the data storage area may store data created based on the use of the computer device.

[0163] The computer device also includes a communication interface 703 for communicating with other devices or communication networks.

[0164] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor computer devices, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the methods shown in the above embodiments are implemented.

[0165] This application provides a computer program product including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the method of any embodiment of this application.

[0166] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

[0167] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for extracting the compensating parasitic capacitance of a through-hole, characterized in that, The chip includes a target via, a first conductor object connected to the target via, and a second conductor object not directly connected to the target via; the method includes: Based on the device information of the target via, the scaling factor of the target via is obtained by searching in the via parasitic capacitance library; the scaling factor represents the ratio of the first parasitic capacitance between the target via and the second conductor object to the standard parasitic capacitance between the first conductor object and the second conductor object; the via parasitic capacitance library is generated based on the device information and scaling factor of a preset number of via samples; The compensated parasitic capacitance between the first conductor object and the second conductor object is calculated based on the standard parasitic capacitance between the target via and the scaling factor of the target via.

2. The method for extracting parasitic capacitance according to claim 1, characterized in that, Before finding the scaling factor of the via in the via parasitic capacitance library based on the device information of the via, the method includes: The via parasitic capacitance library is generated based on device information and scaling factors from multiple preset via samples.

3. The method for extracting parasitic capacitance according to claim 2, characterized in that, The via parasitic capacitance library is generated based on device information and scaling factors from multiple preset via samples, including: Determine the device information of the via sample corresponding to each preset sampling point; Based on the device information of the via sample and the device information of the second conductor object sample, the first parasitic capacitance between the via sample and the second conductor object sample corresponding to each sampling point is calculated. Calculate the ratio of the first parasitic capacitance between the via sample and the second conductor object sample corresponding to each sampling point to the standard parasitic capacitance between the first conductor object sample and the second conductor object sample, and obtain the proportional coefficient of the via sample corresponding to each sampling point; The via parasitic capacitance library is generated based on the device information of multiple via samples and the scaling factor of the via samples.

4. The method for extracting parasitic capacitance according to claim 3, characterized in that, The device information includes: device type and device size; determining the device information of the via sample corresponding to each preset sampling point includes: The device type of the first conductor object sample connected to the via sample is determined as the device type of the via sample; Determine the reference dimensions of the through hole; The reference size of the via is scaled based on each sampling point to obtain the device size of the via sample corresponding to each sampling point.

5. The method according to claim 4, characterized in that, Based on multiple preset sampling points, the device information of the via sample, and the device information of the second conductor object sample, the first parasitic capacitance between the via sample and the second conductor object sample corresponding to each sampling point is calculated, including: Determine the device dimensions of the second conductor object sample as indicated in the device information of the second conductor object sample; Based on the device size of the via sample corresponding to each sampling point and the device size of the second conductor object sample indicated in the device information of the second conductor object sample, the first parasitic capacitance between the via sample corresponding to each sampling point and the second conductor object sample is calculated.

6. The method according to claim 1, characterized in that, Based on the device information of the target via, the scaling factor of the target via is obtained by searching the via parasitic capacitance library, including: At least one candidate via sample with the same device type as the target via is found in the via parasitic capacitance library; The device size of the target via is matched with the device size of each candidate via sample to obtain at least one target via sample that matches the target via; The scaling factor of the target through-hole is determined based on the scaling factor of the at least one target through-hole sample.

7. The method for extracting parasitic capacitance according to any one of claims 1-6, characterized in that, The method further includes: The compensated parasitic capacitance is superimposed on the standard parasitic capacitance between the first conductor object and the second conductor object to obtain the compensated target parasitic capacitance.

8. A through-hole compensation parasitic capacitance extraction device, characterized in that, The chip includes a target via, a first conductor object connected to the target via, and a second conductor object not directly connected to the target via; the device includes: The search module is used to search for the scaling factor of the target via in the via parasitic capacitance library based on the device information of the target via; the scaling factor represents the ratio of the first parasitic capacitance between the target via and the second conductor object to the standard parasitic capacitance between the first conductor object and the second conductor object; the via parasitic capacitance library is generated based on the device information and scaling factor of a preset number of via samples; The calculation module is used to calculate the compensation parasitic capacitance between the target via and the second conductor object based on the standard parasitic capacitance between the first conductor object and the second conductor object and the scaling factor of the target via.

9. A computer device, characterized in that, include: A memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, the processor executing the computer instructions to perform the method of any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the method of any one of claims 1 to 7.

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