Space reservation method, device and electronic equipment for chip engineering modification

Abstract

The application relates to the technical field of super large scale integrated circuits, and discloses a space reservation method for chip engineering modification, a device and electronic equipment, which comprises the following steps: candidate reservation positions are generated by analyzing a timing path and a number of fan-outs of a line network; placeholder units are inserted and wiring channels are reserved after multi-factor scoring screening; and the placeholder units are replaced by actual engineering modification units in situ in an engineering modification stage. The application enables the required units to be directly replaced in the original positions during engineering modification, thereby avoiding repair failure caused by insufficient layout space or wiring resources.

Description

Technical Field

[0001] This invention relates to the field of very large-scale integrated circuit technology, and more specifically to methods, apparatuses, and electronic devices for reserving space for chip engineering modifications. Background Technology

[0002] In very large-scale integrated circuit (VLSI) design, after chip placement and routing are completed, the available placement space and routing channels are extremely limited. When engineering modification tools attempt to insert cells to repair timing violations, the target area often fails or yields unsatisfactory results due to insufficient resources. Existing technologies reserve space by uniformly or randomly inserting spare cells, but this method suffers from problems such as blind placement, low resource utilization, and neglecting routing resources while only considering placement space. Consequently, convergence efficiency remains low during engineering modifications due to insufficient resources. Summary of the Invention

[0003] This invention provides a method, apparatus, and electronic device for reserving space for chip engineering modifications, in order to solve the problem that insufficient layout space and wiring channel resources in the existing chip engineering modification stage prevent the insertion of the required cells in situ for timing repair.

[0004] In a first aspect, the present invention provides a method for reserving space for chip engineering modifications, the method comprising: Obtain the timing path from the chip physical design database, analyze the nets that make up the timing path, and generate a set of candidate reserved positions based on the net fan-out number. Evaluate the priority score of each candidate reserved location and select the final set of reserved locations based on the priority scores; Iterate through each reserved location in the final reserved location set, insert a placeholder cell with fixed attributes and prohibited optimization attributes at each reserved location, and expand outward by a specified distance based on the geometric boundary of each placeholder cell, and set a wiring blocking layer in the area formed after expansion. During the engineering modification phase, the coordinate positions specified in the engineering modification script are parsed, and placeholder units that meet the preset distance threshold at the corresponding coordinate positions are searched. The fixed attributes and optimization prohibition attributes of the placeholder units are removed, and the wiring obstruction layer corresponding to the placeholder units is removed. Finally, the placeholder units are directly replaced with actual engineering modification units.

[0005] This invention provides a space reservation method for chip engineering modifications. By analyzing timing paths and their fan-out numbers, it predicts the locations most likely to require engineering modifications and selects the most valuable reservation locations based on priority scores. Placeholder cells are inserted in advance at these locations, and routing channels are reserved. This allows the required cells to be directly replaced in their original locations during engineering modifications, avoiding repair failures due to insufficient layout space or routing resources. This reduces the number of iterations for engineering modifications, improves timing convergence efficiency, and solves the problem that insufficient layout space and routing channel resources in existing chip engineering modification stages prevent the insertion of required cells in their original locations for timing repair.

[0006] In one optional implementation, timing paths are obtained from the chip physical design database, the nets constituting the timing paths are analyzed, and a set of candidate reserved locations is generated based on the net fan-out number, including: Obtain timing paths from the chip physical design database, filter out timing paths with timing margins lower than a preset threshold, and generate a target path set; Traverse each time-series path in the target path set, analyze the nets that make up the time-series path, and generate a set of candidate reserved positions based on the net fan-out number.

[0007] In the above technical solution, by screening out timing paths with timing margins lower than a preset threshold, the range of critical paths that need to be focused on is narrowed down. On this basis, the net is analyzed and candidate reserved positions are generated based on the fan-out number, so that the generation of reserved positions focuses on paths with real timing risks, avoiding blind reservations across the entire chip and improving the targeting and effectiveness of reserved resources.

[0008] In one optional implementation, timing paths with timing margins lower than a preset threshold are selected to generate a target path set, including: When focusing on establishment time repair, all time-series paths with an end-point establishment time margin less than a first preset threshold are filtered out, and a target path set is generated. When focusing on hold-time repair, all time-series paths with a hold-time margin less than a second preset threshold are selected, and a target path set is generated.

[0009] In the above technical solution, by distinguishing between two scenarios, setup time repair and hold time repair, and setting independent time margin thresholds for each, the selection of the target path set can be flexibly adjusted for different types of time violations, thereby improving the accuracy and adaptability of time path selection.

[0010] In one optional implementation, the nets constituting the time-series path are analyzed, and a set of candidate reserved locations is generated based on the net fan-out number, including: Extract each net traversed by the timing path; When the fanout number of the net is a preset value, a candidate reserved position is generated at the midpoint of the physical connection from the drive pin to the load pin of the net. When the fan-out number of the net is greater than a preset value, the key load pins of the net are identified, and candidate reserved positions are generated at the midpoint of the physical connection from the drive pin of the net to each key load pin.

[0011] In the above technical solution, different candidate reserved position generation strategies are adopted by distinguishing between single-fan outgoing network and multi-fan outgoing network: for single-fan outgoing network, candidate positions are directly generated at the midpoint of the physical connection from the driver pin to the load pin; for multi-fan outgoing network, key load pins are first identified, and then candidate positions are generated for each key load pin. This ensures the spatial correspondence between candidate positions and physical connections, and avoids generating too many invalid positions in multi-fan outgoing scenarios, thus improving the accuracy and simplicity of the candidate reserved position set.

[0012] In one alternative implementation, a priority score is evaluated for each candidate reserved location, and a final set of reserved locations is selected based on the priority scores, including: A multi-factor normalized weighted model is used to calculate the priority score of each candidate reserved location. The model includes a timing urgency factor, a load factor, a delay factor, and a congestion factor. The timing urgency factor is calculated based on the timing margin associated with the candidate reserved location, the load factor is calculated based on the fan-out number of the net to which the candidate reserved location belongs, the delay factor is calculated based on the signal delay from the net drive pin to the associated load pin, and the congestion factor is calculated based on the cabling track utilization rate of the local area where the candidate reserved location is located. Each candidate reserved position is sorted from high to low according to its priority score, and a predetermined number of candidate reserved positions with the highest scores are selected to form the final reserved position set.

[0013] In the above technical solution, by integrating four dimensions—timing urgency, load intensity, signal delay, and local congestion—each candidate reserved location is given a normalized weighted score, and the most valuable reserved location is selected based on the score. This allows the final set of reserved locations to comprehensively reflect the urgency of timing repairs and the feasibility of physical implementation, avoiding resource misallocation caused by relying on a single factor, and achieving the best match between reserved resources and future engineering modification needs within a limited area.

[0014] In one optional implementation, placeholder units with fixed attributes and anti-optimization attributes are inserted at each reserved position, including: Insert fill cells as placeholders at each reserved position, and set fixed attributes and disable optimization attributes for the placeholders.

[0015] In the above technical solution, filling units are used as placeholder units and fixed attributes and non-optimization attributes are set for them. This ensures that the placeholder units will not be moved or deleted during the subsequent optimization process of the physical design, thereby ensuring that the reserved positions are always effective and providing a stable and reliable placeholder basis for in-situ replacement during the engineering modification stage.

[0016] In one optional implementation, during the engineering modification phase, the coordinate positions specified in the engineering modification script are parsed, and placeholder units that meet a preset distance threshold at the corresponding coordinate positions are searched, including: Analyze the commands in the engineering modification script that involve cell insertion or cell-driven increase, and extract the coordinate positions specified in the commands; Using each extracted coordinate position as the center, search for placeholder units within a rectangular area of ​​a preset side length.

[0017] In the above technical solution, by parsing the coordinate position carried by the unit insertion or drive enlargement command in the engineering modification script, and directionally searching for placeholder units within a rectangular area centered on the coordinates, the positioning process of placeholder units is naturally connected with the output of the engineering modification tool, avoiding blind global search and improving the efficiency and accuracy of placeholder unit search.

[0018] In one optional implementation, the fixed attribute and the disable optimization attribute of the placeholder unit are removed, and the wiring blocking layer corresponding to the placeholder unit is removed. Finally, the placeholder unit is directly replaced with the actual engineering modification unit, including: Remove the fixed attribute of the placeholder unit to allow it to be moved, and remove the disallow optimization attribute of the placeholder unit to allow it to be optimized. Remove the wiring obstruction layer set within the expansion area of ​​the placeholder unit; Remove the placeholder unit and place the actual project modification unit in the same location.

[0019] In the above technical solution, by first removing the fixed attribute and the prohibited optimization attribute of the placeholder unit to make it operable, then removing the reserved wiring blocking layer to release wiring resources, and finally replacing the actual unit in the same position, the precise connection between reserved resources and engineering modification requirements is achieved, so that the pre-locked layout space and wiring channel can be directly utilized, avoiding engineering modification failures caused by resource conflicts.

[0020] In a second aspect, the present invention provides a space reservation device for chip engineering modifications, the device comprising: The candidate location generation module is used to obtain timing paths from the chip physical design database, analyze the nets that make up the timing paths, and generate a set of candidate reserved locations based on the net fan-out number. The location filtering module is used to evaluate the priority score of each candidate reserved location and filter out the final set of reserved locations based on the priority score; The resource reservation module is used to traverse each reserved position in the final reserved position set, insert placeholders with fixed attributes and prohibited optimization attributes at each reserved position, and expand outward by a specified distance based on the geometric boundary of each placeholder, and set a wiring blocking layer in the area formed after expansion. The engineering modification execution module is used to parse the coordinate positions specified in the engineering modification script during the engineering modification stage, search for placeholder units that meet the preset distance threshold at the corresponding coordinate positions, remove the fixed attributes and optimization prohibition attributes of the placeholder units, remove the wiring blocking layer corresponding to the placeholder units, and finally directly replace the placeholder units with actual engineering modification units.

[0021] Thirdly, the present invention provides an electronic device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the chip engineering modification space reservation method of the first aspect or any corresponding embodiment described above.

[0022] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the space reservation method for chip engineering modifications described in the first aspect or any corresponding embodiment thereof.

[0023] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the space reservation method for chip engineering modifications described in the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0024] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 This is a schematic flowchart of a first method for reserving space for chip engineering modifications according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the second method for reserving space for chip engineering modifications according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the physical design phase workflow according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the workflow of the eco (Engineering Change Order) stage according to an embodiment of the present invention; Figure 5 This is a structural block diagram of a space reservation device for chip engineering modifications according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0028] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0029] Traditional engineering modification (eco) processes have the following drawbacks: (1) Mismatch in design objectives: Spare cells and gate decoupling capacitors are mainly designed for metal layer engineering modifications, and their cell types and locations are not planned with the aim of repairing timing paths. Moreover, if too many spare cells are used during the timing engineering modification phase, the number of spare cells available when metal layer engineering modifications actually occur will be reduced, thus creating risks.

[0030] (2) Blind placement of resources: The backup units are usually evenly distributed or based on simple rules, and lack correlation with the path and physical location of the actual timing violation in the future, resulting in low accuracy of resource placement.

[0031] (3) Low resource utilization: In order to ensure coverage, the two existing technologies mentioned above need to insert a large number of spare units in the whole chip or in some parts, which occupies valuable chip area. However, since it is impossible to accurately associate with the specific timing path, it will still result in insufficient space reservation in some areas when repairing timing, and redundant space reservation in other areas.

[0032] (4) No consideration of cabling resource reservation: The above-mentioned existing technologies usually only consider the reservation of layout space, but do not consider the reservation of cabling resources. In actual engineering, even if the layout space is sufficient, insufficient cabling resources will still lead to the introduction of many design rule violations or cause serious cabling detours. This results in a huge deviation between the timing and the ideal effect after engineering modification and physical implementation, and may even require engineering modification and iteration again, reducing the convergence efficiency of engineering modification.

[0033] This invention provides a method for reserving space for chip engineering modifications. By analyzing timing paths and their net fan-out numbers, candidate reserved positions are generated. After multi-factor scoring and screening, placeholder units are inserted and routing channels are reserved. During the engineering modification stage, the placeholder units are replaced in place with actual engineering modification units to avoid engineering modification failures due to insufficient placement and routing resources and to improve timing convergence efficiency.

[0034] This invention can be executed at one or more selected points in the chip physical design process, including but not limited to after placement optimization, after clock tree synthesis, after global routing, and after detailed routing.

[0035] According to an embodiment of the present invention, a method for reserving space for chip engineering modifications is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0036] This embodiment provides a method for reserving space for chip engineering modifications, which can be used in electronic design automation servers or engineering workstations. Figure 1 This is a flowchart of a space reservation method for chip engineering modifications according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps: Step S101: Obtain the timing path from the chip physical design database, analyze the nets that make up the timing path, and generate a set of candidate reserved positions based on the net fan-out number.

[0037] The chip physical design database refers to all the data generated during the chip physical design phase, which stores data such as chip layout, routing, cell location, and timing information.

[0038] In chip design, a timing path refers to the complete path a signal takes from the clock pin of one timing unit, through combinational logic units and interconnects, to the data input pin of another timing unit.

[0039] A net that makes up a timing path refers to the wires connecting the pins of each unit in the timing path and the collective term for all the pins connected to them. A net represents a signal connection that connects one driver pin and several load pins.

[0040] Candidate reserved locations refer to the physical coordinates of future engineering modification units that may need to be inserted, automatically calculated based on the timing path and network information.

[0041] Specifically, after obtaining the timing paths from the chip physical design database, the timing paths with timing margins lower than a preset threshold are first filtered out to identify the critical paths that need attention. Then, these paths are traversed, and the nets traversed by each path are extracted. The nets are processed according to their fan-out number: for single-fan-out nets, candidate reserved positions are generated at the midpoint of the physical connection from the net driver pin to the load pin; for multi-fan-out nets, the critical load pins are first identified, and then candidate reserved positions are generated at the midpoint of the physical connection from the driver pin to the pin for each critical load pin, thus forming an initial set of candidate reserved positions.

[0042] Step S102: Evaluate the priority score of each candidate reserved location and select the final set of reserved locations based on the priority score.

[0043] The priority score for each candidate reserved location is a value calculated by taking into account timing urgency, load intensity, signal delay, and local congestion. It is used to quantitatively evaluate the reservation value of each candidate reserved location, with a higher score indicating that it is more worthwhile to reserve.

[0044] Specifically, for each initially generated candidate reserved position, the system calculates its timing urgency factor, load factor, delay factor, and congestion factor, and then sums these four factors according to their respective weighting coefficients to obtain a comprehensive score representing the reservation priority of that position. After all candidate positions are sorted from highest to lowest score, a certain number of top-ranked positions are selected based on a preset resource budget. These selected positions constitute the final set of reserved positions used for the actual insertion of placeholder units.

[0045] Step S103: Traverse each reserved position in the final reserved position set, insert a placeholder cell with fixed attributes and prohibited optimization attributes at each reserved position, and extend outward by a specified distance based on the geometric boundary of each placeholder cell, and set a wiring blocking layer in the area formed after the extension.

[0046] Placeholder cells are pre-inserted fill cells at predicted locations. They have fixed and disabled optimization properties and are used to lock layout and routing resources in advance. When the project is modified, they are replaced in place with the actual required modification cells (such as buffers).

[0047] A wiring barrier is a wiring constraint set in a designated area around a placeholder unit. It is used to limit or reduce the occupancy of wiring channels in that area by other signal lines, thereby reserving wiring resources for future engineering modifications.

[0048] Specifically, for each coordinate location that needs to be reserved, a placeholder cell is placed at that location and assigned two attributes: fixed and non-optimization, to prevent it from being moved or deleted during subsequent physical optimization. Based on the geometry of this placeholder cell, a rectangular area is delineated by expanding outwards by a predetermined distance. Within this area, a routing density limit is applied to the signal routing layer, forming a soft routing barrier layer. This effectively locks in the layout space at that location while preserving available routing channels in the surrounding area for future engineering modifications.

[0049] Step S104: In the engineering modification stage, the coordinate positions specified in the engineering modification script are parsed, the placeholder units that meet the preset distance threshold at the corresponding coordinate positions are searched, the fixed attributes and optimization prohibition attributes of the placeholder units are removed, and the wiring blocking layer corresponding to the placeholder units is removed. Finally, the placeholder units are directly replaced with actual engineering modification units.

[0050] The engineering modification phase refers to a local repair phase after the physical design phase is completed. That is, a local modification phase after the chip physical design is completed and before or after chip manufacturing, used to fix timing violations or logic errors that could not be resolved in the physical design phase.

[0051] An engineering modification script is a command file generated by electronic design automation (EDA) tools during physically-aware engineering modifications. It contains instructions for operations such as cell insertion and cell drive enlargement, along with their corresponding coordinate positions. This script is automatically generated by the EDA tools based on timing violation conditions and the physical design database. In this embodiment, the coordinate positions are extracted from the script through parsing for searching and locating pre-inserted placeholder cells.

[0052] Specifically, after the chip design enters the engineering modification stage, the modification command file output by the engineering modification tool is first read, and the physical coordinates associated with all operations involving cell insertion or cell size increase are extracted. For each extracted coordinate, a pre-embedded placeholder cell is searched within a set range centered on that coordinate. If the corresponding placeholder cell is found, its attached fixed markers and optimization prohibition markers are cleared, making it operable. At the same time, the pre-set wiring density constraints around the placeholder cell are deleted, releasing the reserved wiring channels. After completing the above cleanup work, the original placeholder cell is removed from the layout, and the logic cell actually required for the repair is placed in the exact same physical location, thus achieving a seamless connection between reserved resources and actual engineering modifications.

[0053] The space reservation method for chip engineering modifications provided in this embodiment proactively and intelligently predicts the physical locations where standard cells are most likely to be inserted to fix or maintain timing violations during critical stages of the physical design process. A placeholder structure that can be directly replaced in situ by engineering modification tools is pre-positioned at these locations, thus locking in critical placement and routing resources. When the engineering modification phase actually requires operation at these locations, the placeholder structure can be seamlessly replaced with the target cell, avoiding engineering modification failures due to insufficient resources. This provides reliable assurance for the timing convergence process and also avoids timing convergence difficulties caused by resource constraints.

[0054] This embodiment provides a method for reserving space for chip engineering modifications, which can be used in electronic design automation servers or engineering workstations. Figure 2 This is a flowchart of a space reservation method for chip engineering modifications according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps: Step S201: Obtain the timing path from the chip physical design database, analyze the nets that make up the timing path, and generate a set of candidate reserved positions based on the net fan-out number.

[0055] Specifically, such as Figure 3 As shown, this step belongs to the physical design stage, and step S201 includes: Step S2011: Obtain the timing paths in the chip physical design database, filter out timing paths with timing margins lower than a preset threshold, and generate a target path set.

[0056] Based on the timing information in the database during the current design phase, the timing paths of interest are selected. Users can configure the system to perform subsequent calculations for one or more of the setup and hold times as needed.

[0057] In some optional implementations, step S2011 above includes: Step a: When focusing on setup time repair, filter out all time-series paths whose endpoint setup time time margin is less than the first preset threshold, and generate a target path set; when focusing on hold time repair, filter out all time-series paths whose endpoint hold time time margin is less than the second preset threshold, and generate a target path set.

[0058] If attention is set to establish time repair, all paths with an endpoint establishment time margin (slack) less than the first preset threshold (T_setup) are filtered; if attention is set to hold time repair, all paths with an endpoint hold time margin (slack) less than the second preset threshold (T_hold) are filtered.

[0059] The default value for T_setup is a negative number equal to 5% of the clock cycle, and the default value for T_hold is 0. Users can also set the values ​​of T_setup and T_hold as needed. This will ultimately generate a set of target paths, target_paths.

[0060] Step S2012: Traverse each time-series path in the target path set, analyze the nets that make up the time-series path, and generate a candidate reserved location set based on the net fan-out number.

[0061] In some optional implementations, step S2012 above includes: Step b: Extract each net traversed by the timing path; when the fan-out number of the net is a preset value, generate a candidate reserved position at the midpoint of the physical connection from the drive pin to the load pin of the net; when the fan-out number of the net is greater than the preset value, identify the key load pin of the net, and generate candidate reserved positions at the midpoint of the physical connection from the drive pin to each key load pin respectively.

[0062] Candidate location enumeration: Automatically traverse each time-series path in the target path set target_paths, and perform the following operations on each net to generate an initial candidate reserved location set L_candidate: For a net with a fanout of 1: Generate a candidate location at coordinates (X, Y) of the midpoint of the physical connection from the output pin of the net driver unit to the input pin of its unique load unit.

[0063] For nets with a fan-out number greater than 1: a) Critical Load Pin Identification: Obtain the worst-case timing margin (slack) value across all timing paths from the net driver pin to each load pin. Find the minimum worst-case timing margin (slack) among all load pins, denoted as worst_slack. Mark all load pins satisfying slack(pin)∈[worst_slack, worst_slack +Δ] as critical load pins, forming the critical load pin set p_critical. Here, Δ is a configurable parameter; the system default value is 20 ps (20 picoseconds).

[0064] b) Candidate location generation: For each critical load pin p in the critical load pin set p_critical, generate a candidate location at coordinates (Xp, Yp) of the midpoint of the physical connection from the net drive pin to that particular pin p.

[0065] It should be noted that the method of reserving locations based on the selected time-critical paths in this embodiment can be replaced by other reservation methods. For example, after selecting the time-critical paths, physical locations can be reserved evenly or randomly in the regions where these paths are distributed.

[0066] Step S202: Evaluate the priority score of each candidate reserved location and select the final set of reserved locations based on the priority score.

[0067] Specifically, such as Figure 3 As shown, this step belongs to the physical design phase, and step S202 includes: Step S2021: Calculate the priority score of each candidate reserved location using a multi-factor normalized weighted model. The model includes a timing urgency factor, a load factor, a delay factor, and a congestion factor. The timing urgency factor is calculated based on the timing margin associated with the candidate reserved location. The load factor is calculated based on the fan-out number of the net to which the candidate reserved location belongs. The delay factor is calculated based on the signal delay from the net drive pin to the associated load pin. The congestion factor is calculated based on the cabling track utilization rate of the local area where the candidate reserved location is located.

[0068] Specifically, candidate positions are scored based on a multi-factor normalization model: the system automatically assigns a score to each candidate position L in L_candidate. i Calculate a space reservation priority score i The score is obtained through the system's built-in multi-factor normalized weighted model, which comprehensively considers four dimensions: timing urgency, load intensity, path delay, and local congestion.

[0069] The formula for the multi-factor normalized weighted model is as follows: (1); in, , , , Candidate positions L i The corresponding time urgency factor, load factor, delay factor, and congestion factor are all normalized, with values ​​ranging from [0, 1]. A larger value indicates a more urgent need for the reserved space at that location. w1, w2, w3, and w4 are the weighting coefficients of each factor, satisfying w1 + w2 + w3 + w4 = 1.

[0070] Different weighting coefficients are set according to the different stages of the database, and users can also modify the settings as needed.

[0071] If the database is in the pre-wiring stage, the system default weight values ​​are w1=0.5, w2=0.2, w3=0.2, and w4=0.1.

[0072] If the database is in the post-wiring stage, the system default weight values ​​are w1=0.4, w2=0.2, w3=0.2, and w4=0.2.

[0073] The specific normalization calculation methods for each factor are as follows: Time urgency factor : (2); in, It is candidate position L i Associated timing margin slack, It is the maximum value of the time margin slack associated with all candidate locations. It is the minimum value of the time-series path slack associated with all candidate locations.

[0074] Loading factor : (3); in, It is candidate position L i The fan-out number of the net. and These are the maximum and minimum fan-out numbers of the net to which all candidate positions belong, respectively.

[0075] Delay factor : (4); in, From the net driver pin to the candidate position L iThe timing arc delay of the associated load pin, which can be calculated using a line load model or based on resistor and capacitor values ​​extracted from the current wiring state, at the current database stage. and These are the maximum and minimum delays of the time-series arcs corresponding to all candidate positions, respectively.

[0076] Congestion factor : (5); in, It is candidate position L i Utilization rate of cabling tracks in the local area and These represent the maximum and minimum routing track utilization rates within the regions containing all candidate locations. The local region containing a candidate location is a rectangle 50µm x 50µm in size, centered at the candidate location's coordinates. Routing track utilization rate is the total length of all occupied routing tracks within this rectangular region for signal routing divided by the total length of routing tracks within that region.

[0077] It should be noted that the model for calculating the reserved position score can be replaced by other models or formulas. For example, different normalization algorithms, different weights, or different factors can be introduced.

[0078] Step S2022: Sort each candidate reserved position according to its priority score from high to low, and select a preset number of candidate reserved positions that are ranked first to form the final reserved position set.

[0079] Specifically, candidate positions are filtered and finally determined based on the calculated priority scores. All positions in the candidate position set L_candidate are ranked according to their priority scores. i The values ​​are sorted in descending order. Based on the user-preset maximum number of allowed insertable placeholder units N, the first N positions are selected from the sorted list to form the final reserved position set L_final.

[0080] Step S203: Traverse each reserved position in the final reserved position set, insert a placeholder cell with fixed attributes and prohibited optimization attributes at each reserved position, and extend outward by a specified distance based on the geometric boundary of each placeholder cell, and set a wiring blocking layer in the area formed after the extension.

[0081] Specifically, such as Figure 3 As shown, this step belongs to the physical design phase, and step S203 includes: Step c: Insert fill cells as placeholders at each reserved position, and set fixed attributes and disable optimization attributes for the placeholders.

[0082] A timing eco cell is automatically inserted at each target reserved location coordinate (X, Y) in the final reserved location set L_final. The area of ​​the inserted eco cell can be preset by the user or use the system's internal default value. The user can preset a standard cell as an area reference, and the system will automatically calculate the area of ​​the preset standard cell and then insert a filler cell of the same size at each target coordinate. When placing these eco cells, if the system detects that there is not enough space to insert a eco cell in the target location area that meets the preset distance threshold, the system will automatically abandon the insertion of that eco cell. The target location area that meets the preset distance threshold refers to a rectangular area of ​​a certain size centered on the target location coordinates. The system default value is a rectangular area of ​​20um × 20um, and the user can also preset the size of this rectangular area as needed. To prevent these eco cells from being optimized away in subsequent optimization processes, the system will set the dont_touch disabling attribute and the fixed attribute for these eco cells to ensure the effectiveness of the eco cells.

[0083] After the placeholder cells are laid out, the system automatically adds a routing blockage layer within a certain area around each placeholder cell. The routing blockage layer constrains the layers that allow signal routing in the design, and its constrained routing density can be preset by the user or use the system default value (70%). The certain area around the placeholder cell refers to a rectangular area formed by extending outward a certain distance based on the geometry of the placeholder cell. The system default extension distance is 3µm, but the user can also preset it as needed.

[0084] It should be noted that this embodiment uses a filler cell as a placeholder cell, but other cell types can also be used instead. The reason for using a filler cell is that traditional engineering eco-modification tools can treat the filler cell as available space during physical eco-modification, making it easier to implement in engineering. For example, if a buffer is used as a placeholder, subsequent eco-modification in engineering will involve in-situ replacement and net reconnection.

[0085] Step S204: In the engineering modification stage, the coordinate positions specified in the engineering modification script are parsed, the placeholder units that meet the preset distance threshold at the corresponding coordinate positions are searched, the fixed attributes and optimization prohibition attributes of the placeholder units are removed, and the wiring blocking layer corresponding to the placeholder units is removed. Finally, the placeholder units are directly replaced with actual engineering modification units.

[0086] Specifically, this step is part of the workflow during the engineering modification phase, such as... Figure 4 As shown, step S204 above includes: Step S2041: Analyze the commands in the engineering modification script that involve cell insertion or cell-driven enlargement, and extract the coordinate positions specified in the commands; with each extracted coordinate position as the center, search for placeholder cells within a rectangular area of ​​a preset side length.

[0087] The specific steps are as follows: Perform the physical aware eco modification and generate the eco script.

[0088] Parse coordinates in the project modification eco script: Automatically parse the coordinates involved in the commands that involve cell insertion or cell drive increase in the project modification eco script, and form a set of project modification eco coordinates.

[0089] Search placeholder units: Based on the modified eco coordinate set of the project, search placeholder units in a specified area that meets a preset distance threshold at each coordinate. The specified area that meets the preset distance threshold refers to a rectangular area of ​​a certain size centered at that coordinate. The system defaults to searching a rectangular area of ​​20um × 20um at each coordinate, but users can also preset a search area of ​​a specified size as needed.

[0090] Step S2042: Remove the fixed attribute of the placeholder unit to allow the placeholder unit to be moved, and remove the prohibited optimization attribute of the placeholder unit to allow the placeholder unit to be optimized; remove the wiring blocking layer set in the extended area of ​​the placeholder unit; remove the placeholder unit and place the actual engineering modification unit in the same position.

[0091] The specific steps are as follows: Unlock placeholders: If a placeholder is found, it will be automatically unlocked. The unlocking action includes removing the pre-defined dont_touch and fixed attributes of the placeholder, and removing the routing blockage layer covering it.

[0092] Execute the project modification eco script and complete the subsequent project modification eco steps.

[0093] The space reservation method for chip engineering modifications provided in this embodiment has the following beneficial effects: (1) The multi-factor normalized weighted model integrates information from four dimensions: timing, load, delay and congestion. It can quantitatively evaluate the reservation value of each candidate location, so that the reserved layout space resources can be modified and used by subsequent projects with a high probability, thereby improving resource utilization efficiency.

[0094] (2) By coordinating the insertion of placeholder units and setting local cabling blocking layers, the layout space and cabling channel resources are simultaneously and quantitatively reserved. While reserving sufficient cabling channels in key locations, the cabling blocking layer allows for partial cabling, reducing interference with global cabling optimization and achieving a balance between ensuring the feasibility of engineering modifications and maintaining design quality.

[0095] (3) By locking the key locations that are most likely to need resources in advance during the physical design phase, we can ensure that there are available layout and wiring resources when the preset distance threshold needs to be met at these locations during the engineering modification phase, thereby avoiding engineering modification failures due to insufficient resources and improving the success rate of engineering modification.

[0096] (4) Avoid complex layout and routing adjustments and re-iterations triggered by engineering modification failures, shorten the engineering modification cycle, accelerate chip timing convergence, and reduce design costs.

[0097] (5) Compared to inserting a large number of spare cells, the precise reservation method ensures timing convergence with a smaller area overhead. Under the same chip area budget, more resources can be reserved for the performance critical path, which helps to achieve a higher operating frequency.

[0098] (6) The reservation and replacement mechanism matches the working mode of existing engineering modification tools without requiring modification of the tool kernel. The pre-built process can be integrated into the existing physical design and engineering modification process.

[0099] This embodiment also provides a space reservation device for chip engineering modifications. This device is used to implement the above embodiments and preferred embodiments, and details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0100] This embodiment provides a space reservation device for chip engineering modifications, such as... Figure 5 As shown, it includes: The candidate location generation module 501 is used to obtain the timing path in the chip physical design database, analyze the nets that make up the timing path, and generate a set of candidate reserved locations based on the net fan-out number.

[0101] The location filtering module 502 is used to evaluate the priority score of each candidate reserved location and filter out the final set of reserved locations based on the priority score.

[0102] The resource reservation module 503 is used to traverse each reserved position in the final reserved position set, insert placeholders with fixed attributes and prohibited optimization attributes at each reserved position, and extend outward by a specified distance based on the geometric boundary of each placeholder, and set a wiring blocking layer in the area formed after the extension.

[0103] The engineering modification execution module 504 is used to parse the coordinate positions specified in the engineering modification script during the engineering modification stage, search for placeholder units that meet the preset distance threshold at the corresponding coordinate positions, remove the fixed attributes and optimization prohibition attributes of the placeholder units, remove the wiring blocking layer corresponding to the placeholder units, and finally directly replace the placeholder units with actual engineering modification units.

[0104] In some optional implementations, the candidate location generation module 501 includes: The target path set generation unit is used to obtain timing paths from the chip physical design database, filter out timing paths with timing margins lower than a preset threshold, and generate a target path set.

[0105] The candidate reserved location filtering unit is used to traverse each time-series path in the target path set, analyze the net that makes up the time-series path, and generate a candidate reserved location set based on the net fan-out number.

[0106] In some optional implementations, the target path set generation unit includes: The path filtering subunit is used to filter out all time-series paths whose endpoint establishment time time margin is less than a first preset threshold when the focus establishment time is repaired, and generate a target path set; when the focus retention time is repaired, it filters out all time-series paths whose endpoint retention time time margin is less than a second preset threshold, and generates a target path set.

[0107] In some optional implementations, the candidate reserved position filtering unit includes: A candidate position generation subunit is used to extract each net traversed by the timing path. When the fan-out number of the net is a preset value, a candidate reserved position is generated at the midpoint of the physical connection from the drive pin to the load pin of the net. When the fan-out number of the net is greater than the preset value, the key load pin of the net is identified, and candidate reserved positions are generated at the midpoint of the physical connection from the drive pin to each key load pin.

[0108] In some alternative implementations, the location filtering module 502 includes: The priority score calculation unit is used to calculate the priority score of each candidate reserved position using a multi-factor normalized weighted model. The model includes a timing urgency factor, a load factor, a delay factor, and a congestion factor. The timing urgency factor is calculated based on the timing margin associated with the candidate reserved position, the load factor is calculated based on the fan-out number of the net to which the candidate reserved position belongs, the delay factor is calculated based on the signal delay from the net drive pin to the associated load pin, and the congestion factor is calculated based on the cabling track utilization rate of the local area where the candidate reserved position is located.

[0109] The final reserved position selection unit is used to sort each candidate reserved position from high to low according to the priority score, and select a preset number of candidate reserved positions with the highest priority to form the final reserved position set.

[0110] In some alternative implementations, the resource reservation module 503 includes: Placeholder cell insertion cells are used to insert fill cells as placeholder cells at each reserved position, and to set fixed attributes and disable optimization attributes for the placeholder cells.

[0111] In some alternative implementations, the engineering modification execution module 504 includes: The script parsing and search unit is used to parse commands in the engineering modification script that involve unit insertion or unit-driven enlargement, and extract the coordinate positions specified in the commands; with each extracted coordinate position as the center, it searches for placeholder units within a rectangular area of ​​a preset side length.

[0112] Placeholder unit unlock and replacement unit is used to remove the fixed attribute of the placeholder unit to allow it to be moved, and to remove the prohibited optimization attribute of the placeholder unit to allow it to be optimized; remove the wiring blocking layer set in the extended area of ​​the placeholder unit; remove the placeholder unit and place the actual engineering modification unit in the same position.

[0113] The space reservation device for chip engineering modification provided in this embodiment of the invention can execute the space reservation method for chip engineering modification provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects for executing the method. Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0114] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0115] The following is a detailed reference. Figure 6This diagram illustrates a suitable structural design for implementing an electronic device according to embodiments of the present invention. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 601, which can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) 602 or a program loaded from memory 608 into random access memory (RAM) 603. RAM 603 also stores various programs and data required for the operation of the electronic device. The processor 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0116] Typically, the following devices can be connected to I / O interface 605: input devices 606 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 608 including, for example, magnetic tapes, hard disks, etc.; and communication devices 609. Communication device 609 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 6 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0117] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 609, or installed from a memory 608, or installed from a ROM 602. When the computer program is executed by the processor 601, it performs the functions defined in the space reservation method for chip engineering modifications according to embodiments of the present invention.

[0118] Figure 6 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0119] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium after being downloaded via a network. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the space reservation method for chip engineering modifications shown in the above embodiments is implemented.

[0120] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0121] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for reserving space for chip engineering modifications, characterized in that, The method includes: Obtain the timing path from the chip physical design database, analyze the nets that make up the timing path, and generate a set of candidate reserved positions based on the net fan-out number. Evaluate the priority score of each candidate reserved location, and select the final set of reserved locations based on the priority score; Traverse each reserved position in the final reserved position set, insert a placeholder unit with fixed attributes and prohibited optimization attributes at each reserved position, and expand outward by a specified distance based on the geometric boundary of each placeholder unit, and set a wiring blocking layer in the area formed after expansion. During the engineering modification phase, the coordinate positions specified in the engineering modification script are parsed, and placeholder units that meet the preset distance threshold at the corresponding coordinate positions are searched. The fixed attributes and optimization prohibition attributes of the placeholder units are removed, and the wiring blocking layer corresponding to the placeholder units is removed. Finally, the placeholder units are directly replaced with actual engineering modification units.

2. The method according to claim 1, characterized in that, The process of acquiring timing paths from the chip physical design database, analyzing the nets that make up the timing paths, and generating a set of candidate reserved locations based on the net fan-out number includes: Obtain timing paths from the chip physical design database, filter out timing paths with timing margins lower than a preset threshold, and generate a target path set; Traverse each time-series path in the target path set, analyze the nets that make up the time-series path, and generate a candidate reserved location set based on the net fan-out number.

3. The method according to claim 2, characterized in that, Filter out timing paths with timing margins below a preset threshold, and generate a target path set, including: When focusing on establishment time repair, all time-series paths with an end-point establishment time margin less than a first preset threshold are filtered out, and a target path set is generated. When focusing on hold-time repair, all time-series paths with a hold-time margin less than a second preset threshold are selected, and a target path set is generated.

4. The method according to claim 2, characterized in that, Analyze the nets that make up the time-series path, and generate a set of candidate reserved locations based on the net fan-out number, including: Extract each net traversed by the time-series path; When the fanout number of the net is a preset value, a candidate reserved position is generated at the midpoint of the physical connection from the drive pin to the load pin of the net. When the fan-out number of the net is greater than a preset value, the key load pins of the net are identified, and candidate reserved positions are generated at the midpoint of the physical connection from the drive pin of the net to each key load pin.

5. The method according to claim 1, characterized in that, The process of evaluating the priority score of each candidate reserved location and selecting the final set of reserved locations based on the priority scores includes: A multi-factor normalized weighted model is used to calculate the priority score of each candidate reserved location. The model includes a timing urgency factor, a load factor, a delay factor, and a congestion factor. The timing urgency factor is calculated based on the timing margin associated with the candidate reserved location. The load factor is calculated based on the fan-out number of the net to which the candidate reserved location belongs. The delay factor is calculated based on the signal delay from the net drive pin to the associated load pin. The congestion factor is calculated based on the cabling track utilization rate of the local area where the candidate reserved location is located. Each candidate reserved position is sorted from high to low according to its priority score, and a predetermined number of candidate reserved positions with the highest scores are selected to form the final reserved position set.

6. The method according to claim 1, characterized in that, The insertion of placeholder units with fixed attributes and prohibited optimization attributes at each reserved position includes: Insert filler units as placeholders at each reserved position, and set fixed attributes and disable optimization attributes for the placeholders.

7. The method according to claim 1, characterized in that, During the engineering modification phase, the coordinate positions specified in the engineering modification script are parsed, and placeholder units that meet the preset distance threshold at the corresponding coordinate positions are searched, including: The commands involving cell insertion or cell-driven increase in the engineering modification script are analyzed, and the coordinate positions specified in the commands are extracted. Using each extracted coordinate position as the center, search for placeholder units within a rectangular area of ​​a preset side length.

8. The method according to claim 1, characterized in that, Remove the fixed and disabled optimization attributes of the placeholder unit, remove the wiring blocking layer corresponding to the placeholder unit, and finally replace the placeholder unit directly with the actual engineering modification unit, including: Remove the fixed attribute of the placeholder unit to allow the placeholder unit to be moved, and remove the disallow optimization attribute of the placeholder unit to allow the placeholder unit to be optimized; Remove the wiring blocking layer disposed within the extended area of ​​the occupant unit; Remove the placeholder unit and place the actual engineering modification unit in the same position.

9. A space reservation device for chip engineering modifications, characterized in that, The device includes: The candidate location generation module is used to obtain timing paths from the chip physical design database, analyze the nets that make up the timing paths, and generate a set of candidate reserved locations based on the net fan-out number. The location filtering module is used to evaluate the priority score of each candidate reserved location and filter out the final set of reserved locations based on the priority score; The resource reservation module is used to traverse each reserved position in the final reserved position set, insert a placeholder unit with fixed attributes and prohibited optimization attributes at each reserved position, and extend outward by a specified distance based on the geometric boundary of each placeholder unit, and set a wiring blocking layer in the area formed after the extension. The engineering modification execution module is used to parse the coordinate positions specified in the engineering modification script during the engineering modification stage, search for placeholder units that meet the preset distance threshold at the corresponding coordinate positions, remove the fixed attributes and optimization prohibition attributes of the placeholder units, remove the wiring blocking layer corresponding to the placeholder units, and finally directly replace the placeholder units with actual engineering modification units.

10. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the space reservation method for chip engineering modifications as described in any one of claims 1 to 8.

Images