Hardware backend design error correction method, device, equipment, medium and product
By using large language models to automatically identify and resolve errors in EDA tools, the efficiency of error correction in the chip back-end design process has been improved, solving the problem of time-consuming manual error correction and achieving a more efficient design process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NATIONAL CENTER OF TECHNOLOGY INNOVATION FOR EDA
- Filing Date
- 2025-09-22
- Publication Date
- 2026-07-21
AI Technical Summary
In traditional chip back-end design processes, error correction using EDA tools relies on multiple manual iterations, which is time-consuming and leads to low design efficiency.
By using large language models to automatically identify processes that malfunction in EDA tools, extract key information, determine the cause of the error, and generate solutions, manual intervention is reduced.
It improves the error correction efficiency of the chip back-end design process, reduces manual analysis time, and improves the accuracy and speed of design.
Smart Images
Figure CN122433673A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip back-end design, and in particular to a hardware back-end design error correction method, apparatus, device, medium and product. Background Technology
[0002] With the increasing complexity of modern chip design, traditional back-end design flows pose an efficiency challenge to the rapid implementation of chips. Chip back-end design flows rely on Electronic Design Automation (EDA) tools to complete the physical synthesis from hardware design description language to layout. A typical back-end design flow involves synthesis, logic equivalence checking, placement planning, clock tree synthesis, routing, parasitic parameter extraction, layout and schematic diagrams. Figure 1 The process includes sub-processes such as consistency checks, design rule checks, and approvals, each with numerous tool parameters requiring adjustment. The approved layout depends on configuring the correct subset of parameters. Inappropriate parameters or file settings can lead to EDA errors, necessitating debugging and error correction.
[0003] Currently, error correction in EDA runtime relies on multiple rounds of manual iteration, each round taking several days or even months. Manually analyzing the large number of complex log files generated across multiple workflow stages consumes significant time and effort, resulting in low efficiency in chip backend design error correction. Summary of the Invention
[0004] The hardware back-end design error correction method, apparatus, device, medium, and product provided in this application are used to improve the accuracy of hardware back-end design error correction results.
[0005] In a first aspect, embodiments of this application provide a hardware backend design error correction method, comprising: determining a target flow; the target flow characterizing the flow in which electronic design automation tools malfunction;
[0006] Obtain the process file of the target process and the process files of each first process; the first process represents each process that has finished running before the target process.
[0007] Based on the process file, key information is extracted through file parsing and a large language model; the key information includes error data of the target process, and process files of each first process associated with the error data;
[0008] Based on the key information, the sub-processes where errors occurred and the corresponding causes of errors were identified through error analysis using a large language model and based on an electronic design automation database.
[0009] Based on the sub-processes where errors occurred and their corresponding causes, a large language model is generated through the solution, and a first solution is generated based on the electronic design automation database; the electronic design automation database includes electronic design automation tool design documents, error case datasets, correct case datasets, and correct case solutions.
[0010] In one possible implementation, the method further includes:
[0011] Based on the first solution, the correctness of the first solution is verified by comparing and checking the large language model.
[0012] If the first solution is correct, then input the first solution into the electronic design automation tool, run it, and generate the design result;
[0013] If the first solution is incorrect, a second solution is generated based on the error message, until a correct solution is obtained.
[0014] In one possible implementation, based on the first solution, verifying the correctness of the first solution by comparing and checking a large language model includes:
[0015] Verify that the format of the first solution conforms to the preset format;
[0016] Verify whether the syntax of the first solution conforms to the preset syntax rules;
[0017] In addition, verify whether the content of the first solution conforms to the design input file;
[0018] If all the above tests are met, the first solution is deemed correct; if at least one test is not met, the first solution is deemed incorrect.
[0019] In one possible implementation, the method further includes:
[0020] If the first solution is correct, it is input into the electronic design automation tool for execution. If an error occurs, the third solution is regenerated according to the error process file, and the first solution is stored in the electronic data automation database.
[0021] In one possible implementation, the method further includes:
[0022] The subprocess that has been identified as having an error, the corresponding error cause, the corresponding error solution, and the corresponding correct solution are stored in the electronic design automation database.
[0023] In one possible implementation, the sub-process that determined the error, the corresponding error cause, the corresponding error solution, and the corresponding correct solution are stored in the electronic design automation database, including:
[0024] Based on the large language model for text formatting, based on the determined sub-process where the error occurred, the corresponding error cause, and the corresponding error solution, an error example is generated; and based on the determined sub-process where the error occurred, the corresponding error cause, and the corresponding correct solution, a correct example is generated.
[0025] The error samples and the correct samples are stored in the electronic design automation database.
[0026] In one possible implementation, the first solution includes target parameters; the method further includes:
[0027] Based on a heuristic algorithm, the parameters to be adjusted are adjusted to determine the target parameters.
[0028] Secondly, embodiments of this application provide a hardware backend design error correction device, comprising:
[0029] The determination module is used to determine the target process; the target process characterizes the process in which the electronic design automation tool malfunctions.
[0030] The acquisition module is used to acquire the process file of the target process and the process files of each first process; the first process represents each process that has finished running before the target process.
[0031] The parsing module is used to extract key information based on the process file by parsing a large language model; the key information includes error data of the target process and process files of each first process associated with the error data;
[0032] The analysis module is used to determine the sub-processes where errors occurred and the corresponding error causes based on the key information, through the error analysis big language model and the electronic design automation database.
[0033] The generation module is used to generate a large language model based on the sub-process where the error occurred and the corresponding error cause, and to generate a first solution based on the electronic design automation database; the electronic design automation database includes electronic design automation tool design documents, error case datasets, correct case datasets, and correct case solutions.
[0034] Thirdly, embodiments of this application provide an electronic device, including: a memory and a processor;
[0035] The memory stores computer-executed instructions;
[0036] The processor executes computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.
[0037] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.
[0038] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.
[0039] The hardware backend design error correction method, apparatus, device, medium, and product provided in this application's embodiments involve: determining a target flow; wherein the target flow represents the process in which the electronic design automation (EDA) tool malfunctions; acquiring the flow file of the target flow and the flow files of each first flow; each first flow represents the completed processes preceding the target flow; extracting key information based on the flow files and design input files using a file parsing model (large language model); the key information includes error data of the target flow and the flow files of each first flow associated with the error data; and extracting the error information and related information from each flow file using the file parsing model (large language model). Based on the key information, and using the error analysis model (large language model) and an EDA database, determining the erroneous sub-flows and their corresponding error causes; and generating a first solution based on the solution generation model (large language model) and the EDA database (electronic design automation database includes EDA tool design documents, error case datasets, correct case datasets, and correct case solutions). This application's solution, based on the large language model, automatically identifies errors in the EDA process and generates corresponding solutions, thus improving the efficiency of hardware backend design process error correction. Attached Figure Description
[0040] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0041] Figure 1 An exemplary flowchart of a hardware backend design error correction method is shown.
[0042] Figure 2An exemplary flowchart of a hardware backend design error correction method is shown.
[0043] Figure 3 A schematic diagram illustrating the hardware backend design process as an example;
[0044] Figure 4 An exemplary schematic diagram of a hardware back-end design error correction device is shown.
[0045] Figure 5 An exemplary schematic diagram of an electronic device is shown.
[0046] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0047] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0048] The following is an explanation of the terms used in this application:
[0049] EDA (Electronic Design Automation): A collection of software tools used for designing and verifying electronic systems, such as integrated circuits and printed circuit boards. EDA tools help engineers automate the process from circuit design and simulation to physical implementation.
[0050] RAG (Retrieval-Augmented Generation): A natural language processing technique that combines information retrieval and generative models. The core idea is to enhance the capabilities of generative models by retrieving relevant information from external knowledge bases.
[0051] Register Transfer Level (RTL): An abstract model used to describe digital circuits, primarily for hardware design. RTL describes the transfer of data between registers and the behavior of control signals, forming the basis for logic synthesis and subsequent back-end physical design processes.
[0052] GDS (Graphic Data System): A binary data format used to describe the final layout of an integrated circuit design. A GDS file contains physical layout information of the chip, including detailed design data such as devices, metal layers, and interconnects. It is a crucial data file used in the chip manufacturing process to generate photomasks.
[0053] CTS (Clock Tree Synthesis): An important step in chip back-end physical design, used to generate a clock distribution network. The goal of CTS is to ensure that clock signals arrive synchronously across all parts of the chip, thereby meeting timing requirements.
[0054] DRC (Design Rule Check): A critical verification step in the back-end physical design of a chip, used to check whether the layout design conforms to the design rules of the manufacturing process. The goal of DRC is to ensure that the geometry, spacing, and hierarchy in the layout meet the process requirements, thereby ensuring that the chip can be successfully manufactured and function properly.
[0055] LVS (Layout and Principles) Figure 1 Layout Versus Schematic (LVS) is a verification process used to check whether the chip layout matches the circuit schematic design. LVS ensures the functional consistency between the physical implementation and the logic design.
[0056] PDK (Process Design Kit): A toolkit provided to designers during the chip design process. It contains design rules, device models and layouts for specific process nodes, and is used to connect the abstract design of a chip to its specific physical implementation.
[0057] With the increasing complexity of modern chip design, traditional back-end design flows pose an efficiency challenge to the rapid implementation of chips. Chip back-end design flows rely on electronic design automation (EDA) tools to complete the physical synthesis from hardware design description language to layout. A typical back-end design flow involves synthesis, logic equivalence checking, placement planning, clock tree synthesis, routing, parasitic parameter extraction, layout and schematic diagrams. Figure 1 The process includes sub-processes such as consistency checks, design rule checks, and approvals, each with numerous tool parameters requiring adjustment. The approved layout depends on configuring the correct subset of parameters. Inappropriate parameters or file settings can lead to EDA errors, necessitating debugging and error correction.
[0058] Currently, error correction in EDA runtime relies on engineers with engineering experience and requires multiple iterations, each taking days or even months. Engineers manually analyze the large number of complex log files generated across multiple workflow stages, consuming significant time and effort. This lengthy response time further increases the time cost of the hardware design workflow, failing to meet the demands of agile design.
[0059] The methods, apparatus, devices, media, and products provided in this application aim to solve the aforementioned technical problems of the prior art. The methods, apparatus, devices, media, and products provided in this application involve: determining a target process; wherein the target process represents the process in which an electronic design automation (EDA) tool malfunctions; acquiring the process files of the target process and the process files of each first process; each first process representing the completed processes preceding the target process; extracting key information from the process files using a file parsing model and a large language model; the key information includes error data of the target process and the process files of each first process associated with the error data; and extracting the error information and related information from each process file using the large language model of file parsing. Based on the key information, and using an error analysis large language model and an EDA database, determining the erroneous sub-processes and their corresponding error causes; and generating a first solution using a solution generation large language model based on the EDA database, based on the EDA database; the EDA database includes EDA tool design documents, error case datasets, correct case datasets, and correct case solutions. The solution proposed in this application automatically identifies errors in the EDA process and generates corresponding solutions based on a large language model, thereby improving the efficiency of error correction in the hardware backend design process.
[0060] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.
[0061] Example 1
[0062] Figure 1 An exemplary flowchart of a hardware backend design error correction method is shown, such as... Figure 1 As shown, the method includes:
[0063] Step 101: Determine the target process; the target process represents the process by which electronic design automation tools malfunction.
[0064] Step 102: Obtain the process file of the target process and the process files of each first process; the first process represents each process that has finished running before the target process;
[0065] Step 103: Based on the process document, extract key information by parsing the large language model of the document; the key information includes the error data of the target process, and the process documents of each first process associated with the error data;
[0066] Step 104: Based on the key information, through the error analysis big language model and the electronic design automation database, determine the sub-processes where errors occurred and the corresponding error causes.
[0067] Step 105: Based on the sub-processes where errors occurred and the corresponding error causes, generate a large language model through the solution, and generate the first solution based on the electronic design automation database; the electronic design automation database includes electronic design automation tool design documents, error case datasets, correct case datasets, and correct case solutions.
[0068] Optionally, the solution of this application is applicable to various backend EDA toolchains that support Tool Command Language (TCL), and the backend design flow and its sub-flows. For example, the solution of this application can also be applied to other languages and backend EDA toolchains that support the corresponding languages, and the backend design flow and its sub-flows, such as Python and C; this application does not impose any limitations on this. The EDA toolchain is an end-to-end implementation toolchain from RTL to GDS layout. This tool is used to implement the entire backend flow from RTL code synthesis, layout, placement, routing, CTS, all the way to the final DRC and LVS. This solution supports all EDA tools that support the TCL language, and is not limited to open-source academic EDA or specific versions of EDA tools.
[0069] For example, EDA chip back-end design typically includes synthesis, logic equivalence checking, placement planning, placement, clock tree synthesis, routing, parasitic parameter extraction, layout and schematic design. Figure 1 The processes, including consistency checks, design rule checks, and approvals, each require adjustments to numerous tool parameters. First, the target process must be defined; this target process represents the stage where errors occur during the execution of the EDA tool.
[0070] Obtain the process files for the target process and the first process; the first process represents all processes that have completed execution before the target process. For example, when errors occur in certain processes during EDA execution, it is not necessarily due to unreasonable design of the current process parameters or unreasonable RTL code in the circuit design; it may be due to unreasonable EDA parameter settings in the previously completed first processes, or unreasonable RTL code in the circuit design. EDA tool parameters can include global control parameters: running mode, multi-threading settings, memory limits; timing-related parameters: clock constraints, path grouping, timing exceptions; physical design parameters: placement density, number of routing layers, power networks; power and area parameters: dynamic power optimization, leakage power optimization, area limits; design rules: spacing rules, antenna effects, metal fill; debugging and logging parameters: log level, error tolerance, checkpoint saving. The corresponding design specifications and design description files differ for different chips.
[0071] For example, design input files for electronic design automation can also be obtained; these design input files include design specification files and design description files. The design description files provide a brief description of the current design, while the design specification files provide design specifications for each design process.
[0072] Based on the process documents and design input documents, key information can be extracted through file parsing and a large language model. The key information includes error data of the target process and process documents of each first process associated with the error data. For example, the file input includes modal files such as GDS format layout, LEF, DEF, and netlist. Compared with plain text, the error correction capability has been further improved. It can locate the problem more accurately by aligning, processing and analyzing information from multiple modalities.
[0073] The process files include various logs, reports, configurations, design names, and runtime conditions (error outputs such as layouts, LEFs, DEFs, or netlists) generated during the EDA tool's operation. Information is extracted and parsed from the process files in conjunction with the design input files. Key and useful information is extracted from each file, removing a large amount of useless redundancy, and transforming it into a standardized key-value pair format that is easy for the model to understand. This overcomes the characteristics of EDA files, such as intertwined structured and unstructured data, high information redundancy, and sparse key information. For example, key error information may include specific error codes (ERROR-XXX), the physical coordinates of the error (x, y), hierarchical paths u_top / u_sub / reg, parameter key-value pairs (-max_cap=0.15, etc.), and key natural language description fragments (including error explanations and descriptions). By using built-in rules and semantic understanding, it automatically filters out massive amounts of redundant information (such as duplicate status reports and irrelevant INFO logs), focusing on errors, warnings, key parameters, and progress milestones; at the same time, it constructs error association contexts (related to information, error stages, and error messages of the same design object), and finally outputs a structured, standardized, and highly condensed problem summary.
[0074] Based on key information, the error analysis big language model, using an electronic design automation (EDA) database, identifies the sub-processes where errors occurred and their corresponding causes. For example, the error analysis big language model further diagnoses the key information; using the EDA database, specifically the Retrieval-Augmented Generation (RAG) vector database, it locates the problematic sub-processes and related parameter configurations, ultimately identifying and diagnosing the cause of errors in the current design within the EDA workflow under given parameter configurations, and providing a corresponding standardized description. This standardized description is in a language understandable by the model.
[0075] Based on the identified error processes and their causes, and using knowledge retrieved from the local RAG vector database, specific and actionable solutions and improvement suggestions are generated through deep thinking chains. Generally, this involves adjusting parameters, configuring EDA commands, and modifying the design.
[0076] Optionally, the first solution includes the target parameters; the method also includes:
[0077] Based on heuristic algorithms, the parameters to be adjusted are adjusted to determine the target parameters.
[0078] For example, for problems related to parameter tuning, a heuristic algorithm can be introduced for rapid parameter tuning while using a balancing strategy to prevent the agent from getting bogged down in infinite error correction attempts. The generated solution includes parameters, instructions, and RTL code generated after inference. For example, the heuristic algorithm defines the parameters to be tuned as a multi-dimensional solution space. Based on a random seed initial solution, it simulates intelligent optimization behavior, performs rapid local evaluation in each iteration, selectively reproduces / updates parameter combinations based on feedback, and utilizes intelligent random perturbation mechanisms (mutation / random steps) and dynamic balancing control (adaptive strategy) to break deadlocks and escape local optima. Ultimately, within a controllable computational overhead, it finds a set of proven and effective parameter combinations that balance repair quality and efficiency, achieving rapid parameter selection while avoiding excessive parameter search loops.
[0079] The N parameters to be optimized (such as the learning rate, number of layers, number of nodes, etc. of a machine learning model) are mapped to a point in an N-dimensional space. Each parameter corresponds to a dimension. The specific value of each parameter corresponds to the coordinates in that dimension. The solution is a complete combination of parameters, which is a point in this space, or a candidate solution.
[0080] By intelligently optimizing behavior, a refined search is performed within the currently discovered, relatively good regions to find even better solutions. Further exploration of unknown spaces beyond the current region is undertaken to discover new regions with greater potential. Examples of optimization algorithms include: evolutionary computation, genetic algorithms, evolutionary strategies, particle swarm optimization, ant colony optimization, etc.
[0081] When the algorithm reaches its maximum number of iterations, or the fitness does not significantly improve within N consecutive generations, or a solution that meets the requirements has been found, the final output is a verified, high-performance, and practical combination of parameters, which is the target parameter.
[0082] The Electronic Design Automation (EDA) database includes EDA tool design documents, error case datasets, correct case datasets, and correct case solutions. For example, it can include a dedicated database of EDA tools, EDA debugging resources, expert experience, EDA guidelines, and related technical documents, empowering LLM (Elastic Design Management) tools for high-quality analysis. Automated analysis through LLM bridges the knowledge gap between designers, LLM tools, and EDA tools, reducing over-reliance on human expertise, significantly lowering the barrier to entry for users and enhancing usability.
[0083] The Electronic Design Automation (EDA) database stores new error-related data generated during the iterative problem-solving process. This data is then used to develop standardized solutions and update the RAG vector database. The RAG vector database is a knowledge base compiled to enable the system to possess domain-specific knowledge for effective problem-solving. It includes technical documents, user manuals, standards and specifications related to one or more EDA tools, error case datasets (design - EDA tool parameter configuration - runtime errors under this configuration - human engineer solutions to the error, one data point), correct example datasets (design - EDA tool parameter configuration - correct runtime results under this configuration, one data point), and real-world problem solutions from users (e.g., collected through internet platforms or other legitimate means).
[0084] The method provided in this application involves determining a target process, whereby the target process represents the process in which an electronic design automation (EDA) tool malfunctions. The method acquires the process files for the target process and each first process, as well as design input files. The design input files include EDA design specifications and design description files. Each first process represents a process that has completed its execution before the target process. Based on the process files and design input files, key information is extracted using a file parsing model (large language model). The key information includes error data for the target process and the process files for each first process associated with the error data. Using the file parsing model, the error information and related information are extracted from each process file. Based on the key information, and using an error analysis model (large language model), and based on an EDA database, the method identifies the malfunctioning sub-processes and their corresponding error causes. Based on the malfunctioning sub-processes and their corresponding error causes, a solution generation model (large language model) is used to generate a first solution, based on the EDA database. The EDA database includes EDA tool design documents, error case datasets, correct case datasets, and correct case solutions. The solution proposed in this application automatically identifies errors in the EDA process and generates corresponding solutions based on a large language model, thereby improving the efficiency of error correction in the hardware backend design process.
[0085] Optionally, the method also includes:
[0086] Based on the first solution, the correctness of the first solution is verified by comparing and checking the large language model.
[0087] If the first solution is correct, then input the first solution into the electronic design automation tool, run it, and generate the design results;
[0088] If the first solution is incorrect, a second solution is generated based on the error message, and so on, until the correct solution is obtained.
[0089] Optionally, after producing the first solution, the correctness of the first solution is verified by comparing it with the large language model. For example, if the first solution is verified to be correct, it is input into the EDA tool and run to obtain the final design result; if the current flow is not the chip back-end design flow, the EDA flow continues to be corrected until the correct solution is obtained.
[0090] When the first solution is incorrect, a second solution can be generated based on the error information until a correct solution is obtained. For example, if the solution generated by the large language model is incorrect, the error-related information is returned to the error analysis large language model to re-determine the process that caused the error and analyze the cause of the error, generate a new solution, and then check the solution until a correct solution is obtained. In this example, the efficiency and accuracy of error correction in the chip back-end design process are improved.
[0091] Optionally, based on the first solution, the correctness of the first solution is verified by comparing and checking the large language model, including:
[0092] Verify that the format of the first solution conforms to the preset format;
[0093] Verify that the syntax of the first solution conforms to the preset syntax rules;
[0094] In addition, verify whether the content of the first solution conforms to the design input documents;
[0095] If all the above tests are met, the first solution is considered correct; if at least one test is not met, the first solution is considered incorrect.
[0096] Optionally, the system verifies whether the format of the first solution conforms to a preset format; whether the syntax of the first solution conforms to preset syntax rules; and whether the content of the first solution conforms to the design input file. For example, it verifies whether the output solution's format matches the original input process file, whether the output syntax rules match the input syntax rules, and whether the generated solution conforms to the content of the input rule file. For instance, if the EDA design is for an automotive chip, it verifies whether the output solution is indeed an automotive chip design solution.
[0097] If all the above checks are met, the validation is considered successful. If at least one check fails, the generated solution is deemed incorrect, and a new solution needs to be generated.
[0098] The solution generated from the large language model is checked and compared with the solution before modification. The range and rationality of adjustment commands and parameters are checked to avoid over-adjustment. If the check is incorrect (e.g., the parameter adjustment of the process after the error-causing process was introduced in the modified solution, which is an unreasonable adjustment and cannot solve the problem of the error-causing process), the problem is reported to the error cause analysis and the large language model is regenerated; if the modification is effective, the modified result is output to the EDA toolchain.
[0099] Verification checks are performed on format, syntax, and content relevance. The changes are also compared with the original design to confirm their reasonableness, thereby minimizing the illusion of a model and ensuring the reliability of the solution.
[0100] Optionally, the method also includes:
[0101] If the first solution is correct, it is input into the electronic design automation tool for execution. If an error occurs, the third solution is regenerated according to the error process file, and the first solution is stored in the electronic data automation database.
[0102] If the first solution is verified correctly, it is then input into the EDA design tool for execution. If an error occurs again during execution, a third solution must be regenerated based on the error process document. Simultaneously, the first solution must be stored in the EDA database. For example, storing the first solution as an error example in the EDA database allows the model to output a more accurate solution, improving the accuracy of error correction in the hardware design process.
[0103] Optionally, the method also includes:
[0104] The subprocesses where errors occurred, the corresponding error causes, the corresponding error solutions, and the corresponding correct solutions are identified and stored in the electronic design automation database.
[0105] Optionally, the subprocess that malfunctioned, the corresponding error cause, the corresponding error solution, and the corresponding correct solution can be stored in the electronic design automation database to enrich the database's sample data.
[0106] Optional, Figure 2 An exemplary flowchart of a hardware backend design error correction method is shown; the sub-processes that determine the occurrence of errors, the corresponding error causes, the corresponding error solutions, and the corresponding correct solutions are stored in an electronic design automation database, including:
[0107] Step 201: Based on the large language model for text formatting, generate error examples according to the sub-processes where errors occurred, the corresponding error causes, and the corresponding error solutions; and generate correct examples according to the sub-processes where errors occurred, the corresponding error causes, and the corresponding correct solutions.
[0108] Step 202: Store the error samples and correct samples in the electronic design automation database.
[0109] Optionally, a large text-formatted language model can be used to generate error examples based on the identified sub-process that erred, its corresponding error cause, and its corresponding error solution; and to generate correct examples based on the identified sub-process that erred, its corresponding error cause, and its corresponding correct solution. For example, the large text-formatted language model can tag and categorize the positive or negative feedback into correct or incorrect examples, and input these data entries into a RAG vector database to update the content of the local knowledge database. Optionally, the electronic design automation database can use RAG, retrieval methods based on RAG as the core approach, and retrieval methods based on traditional relational databases or graph databases.
[0110] Error and correct examples are stored in the electronic design automation database. Each user-approved solution is automatically updated to the knowledge base, continuously enhancing the system's knowledge level and intelligence during problem-solving.
[0111] This model collects timely user feedback and organizes real-world problems and solutions from a solution repository to achieve formatted output, which is then used to update the local knowledge database.
[0112] In one example Figure 3 A schematic diagram illustrating the hardware backend design process for example; such as Figure 3As shown, firstly, the system files of the target process and the first process are input into the file parsing large language model, which generates key information. The key information is then input into the error analysis large language model, and based on the electronic design automation (EDA) database, the sub-processes where problems occur and their corresponding causes are identified. The causes of the problem analysis are input into the solution generation model, and based on the EDA database, a corresponding solution is generated. Next, the solution is input into the comparison and checking large language model to determine if the generated solution is effective. If invalid, the error information is fed back to the error analysis large language model to generate a new solution. If effective, the solution is output to the EDA toolchain for program execution. The process execution is then checked for errors. If error-free, the corresponding GDS layout is output. If errors are found, the corresponding process files are re-input into the file parsing large language model, and the process of key information extraction, cause analysis, and solution generation is re-executed.
[0113] The hardware backend design error correction method provided in this application involves: determining a target flow; wherein the target flow represents the process in which the electronic design automation (EDA) tool malfunctions; obtaining the flow file of the target flow and the flow files of each first flow; each first flow representing the completed processes preceding the target flow; extracting key information based on the flow files using a file parsing model and a large language model; the key information includes error data of the target flow and the flow files of each first flow associated with the error data; and extracting the error information and related information based on each flow file using the file parsing model. Based on the key information, the sub-flows that malfunction and their corresponding error causes are determined using an error analysis model and an EDA database; based on the malfunctioning sub-flows and their corresponding error causes, a solution generation model is used to generate a first solution using the EDA database; the EDA database includes EDA tool design documents, error case datasets, correct case datasets, and correct case solutions. This application's solution, based on a large language model, automatically identifies errors in the EDA process and generates corresponding solutions, improving the efficiency of hardware backend design process error correction.
[0114] Example 2
[0115] Figure 4 An exemplary schematic diagram of a hardware backend design error correction device is shown; such as Figure 4 As shown, the device includes:
[0116] Module 21 is used to determine the target flow; the target flow characterizes the process in which the electronic design automation tool malfunctions.
[0117] The acquisition module 22 is used to acquire the process file of the target process and the process files of each first process; the first process represents each process that has finished running before the target process.
[0118] The parsing module 23 is used to extract key information based on the process file and through the file parsing model and the large language model. The key information includes the error data of the target process and the process files of each first process associated with the error data.
[0119] Analysis module 24 is used to determine the sub-processes where errors occurred and the corresponding error causes based on key information, through error analysis big language model, and based on the electronic design automation database.
[0120] The generation module 25 is used to generate a large language model based on the sub-processes where errors occurred and the corresponding error causes, and to generate a first solution based on the electronic design automation database. The electronic design automation database includes electronic design automation tool design documents, error case datasets, correct case datasets, and correct case solutions.
[0121] The image text description generation device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.
[0122] Example 3
[0123] Figure 5 An exemplary schematic diagram of an electronic device is shown. The device includes:
[0124] The device includes a processor 291 and a memory 292; it may also include a communication interface 293 and a bus 294. The processor 291, memory 292, and communication interface 293 can communicate with each other via the bus 294. The communication interface 293 can be used for information transmission. The processor 291 can invoke logical instructions stored in the memory 292 to execute the methods described in the example above.
[0125] Furthermore, the logic instructions in the aforementioned memory 292 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.
[0126] The memory 292, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this application. The processor 291 executes functional applications and data processing by running the software programs, instructions, and modules stored in the memory 292, that is, it implements the methods in the above method examples.
[0127] The memory 292 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 292 may include high-speed random access memory and may also include non-volatile memory.
[0128] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the method in any of the embodiments.
[0129] This application also provides a computer program product, including a computer program that, when executed by a processor, is used to implement the method in any of the embodiments.
[0130] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.
[0131] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.
[0132] It should be understood that the above-described device embodiments are merely illustrative, and the device of this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units, modules, or components may be combined, or integrated into another system, or some features may be ignored or not executed.
[0133] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this application can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.
[0134] When integrated units / modules are implemented in hardware, the hardware can be digital circuits, analog circuits, etc. The physical implementation of the hardware structure includes, but is not limited to, transistors, memristors, etc. Unless otherwise specified, the processor can be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC, etc. Unless otherwise specified, the storage unit can be any suitable magnetic or magneto-optical storage medium, such as Resistive Random Access Memory (RRAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Enhanced Dynamic Random Access Memory (EDRAM), High-Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), etc.
[0135] If the integrated unit / module is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.
[0136] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.
[0137] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.
[0138] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A hardware backend design error correction method, characterized in that, include: Define the target process; The target process characterizes the process by which electronic design automation tools malfunction. Obtain the process file of the target process and the process files of each first process; The first process represents each process that has completed its execution before the target process; Based on the process file, key information is extracted by parsing the large language model; the key information includes the error data of the target process, and the process files of each first process associated with the error data; Based on the key information, the sub-processes where errors occurred and the corresponding causes of errors were identified through error analysis using a large language model and based on an electronic design automation database. Based on the sub-processes where errors occurred and their corresponding causes, a large language model is generated through the solution, and a first solution is generated based on the electronic design automation database. The electronic design automation (EDA) database includes EDA tool design documents, error case datasets, correct case datasets, and correct case solutions.
2. The method according to claim 1, characterized in that, The method further includes: Based on the first solution, the correctness of the first solution is verified by comparing and checking the large language model. If the first solution is correct, then input the first solution into the electronic design automation tool, run it, and generate the design result; If the first solution is incorrect, a second solution is generated based on the error message, until a correct solution is obtained.
3. The method according to claim 2, characterized in that, The step of verifying the correctness of the first solution by comparing and checking the large language model includes: Verify that the format of the first solution conforms to the preset format; Verify whether the syntax of the first solution conforms to the preset syntax rules; In addition, verify whether the content of the first solution conforms to the design input file; If all the above tests are met, the first solution is deemed correct; if at least one test is not met, the first solution is deemed incorrect.
4. The method according to claim 2, characterized in that, The method further includes: If the first solution is correct, it is input into the electronic design automation tool for execution. If an error occurs, the third solution is regenerated according to the error process file, and the first solution is stored in the electronic data automation database.
5. The method according to any one of claims 1-4, characterized in that, The method further includes: The subprocess that has been identified as having an error, the corresponding error cause, the corresponding error solution, and the corresponding correct solution are stored in the electronic design automation database.
6. The method according to claim 5, characterized in that, The step of storing the identified error sub-process, the corresponding error cause, the corresponding error solution, and the corresponding correct solution in the electronic design automation database includes: Based on the large language model for text formatting, based on the determined sub-process where the error occurred, the corresponding error cause, and the corresponding error solution, an error example is generated; and based on the determined sub-process where the error occurred, the corresponding error cause, and the corresponding correct solution, a correct example is generated. The error samples and the correct samples are stored in the electronic design automation database.
7. The method according to any one of claims 1-4, characterized in that, The first solution includes target parameters; the method further includes: Based on a heuristic algorithm, the parameters to be adjusted are adjusted to determine the target parameters.
8. A hardware backend design error correction device, characterized in that, include: The determination module is used to determine the target process; The target process characterizes the process by which electronic design automation tools malfunction. The acquisition module is used to acquire the process file of the target process and the process files of each first process; The first process represents each process that has completed its execution before the target process; The parsing module is used to extract key information from the process file using a file parsing model and a large language model. The key information includes error data of the target process, and process files of each first process associated with the error data; The analysis module is used to determine the sub-processes where errors occurred and the corresponding error causes based on the key information, through the error analysis big language model and the electronic design automation database. The generation module is used to generate a large language model based on the sub-process where the error occurred and the corresponding error cause, and to generate a first solution based on the electronic design automation database. The electronic design automation (EDA) database includes EDA tool design documents, error case datasets, correct case datasets, and correct case solutions.
9. An electronic device, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method as described in any one of claims 1-7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-7.
11. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method described in any one of claims 1-7.