A method for automatically generating timed logical invariants for software requirements verification in aviation

Abstract

The application discloses a kind of timing logic regulation automatic generation method for aviation software demand verification, its characteristics are to identify target timing logic category, in the deconstruction phase, synthesis phase and verification phase respectively according to logic category and processing phase call corresponding example resource and historical error correction resource, generate structured semantic sketch, and complete closed-loop iterative timing logic regulation automatic generation by back-translation heuristic comparison, verification phase sub-library backwriting, presequence phase local rollback and threshold control.Compared with the prior art, the present application accurately calls the most relevant reference information for the current logic category and the current processing phase, while considering multiple timing logic scenarios such as MTL, STL, and CTL. It effectively solves problems such as object recognition errors, time boundary deviations, path quantifier misconfigurations, or incomplete formula combinations. The application is particularly suitable for natural language demand verification tasks in aviation software scenarios such as flight control software, track control software, communication navigation, and fault diagnosis and recovery.

Description

Technical Field

[0001] This invention relates to the interdisciplinary fields of formal verification and natural language processing, and in particular to an automatic generation method for converting natural language requirements of aerospace software into temporal logic specifications, which can then be used for requirement verification, model checking, rule analysis, and simulation analysis. Background Technology

[0002] Aviation software is typically used in safety-critical scenarios, and its requirements documents are mostly written in natural language. While natural language is easy for designers, testers, and domain experts to understand and review, it is generally prone to problems such as ambiguity, numerous implicit constraints, inconsistent expression of time boundaries, and inconsistent object naming. Therefore, it is difficult to use it directly for subsequent formal verification, specification checks, and consistency analysis.

[0003] Currently, the technical approaches to converting natural language requirements into temporal logic specifications are as follows: 1) Based on constrained natural language, syntax trees, or template rules, convert the requirement text into linear temporal logic or branching temporal logic formulas; 2) Based on domain terminology, semantic intermediate representation, or semantic clause trees, map objects, actions, and constraints in natural language into atomic propositions and then combine them into formulas; 3) With the help of large language models, few-sample examples, or interactive correction mechanisms, generate temporal logic expressions directly or step by step. However, the existing technologies mentioned above still have the following problems when applying them to the verification of aviation software requirements: 1) Most solutions only target a single logic type and lack a mechanism for identifying and processing different requirement characteristics according to their logic categories, making it difficult to simultaneously accommodate multiple temporal logic scenarios such as MTL, STL, and CTL; 2) Although existing solutions introduce domain vocabularies, template libraries, or sample data, these resources are usually not organized in a two-dimensional manner according to "logic category + processing stage," making it difficult to accurately call the most relevant reference information for the current logic category and processing stage in actual processing; 3) The error correction mechanisms in existing solutions mostly remain at the level of manual rewriting, overall rerun, or simple result filtering, lacking a mechanism for structured accumulation, targeted rewriting, and subsequent reuse of historical errors and their correction results; 4) Existing solutions focus more on "generating a temporal logic formula," but lack an effective closed loop on whether the generated result maintains semantic consistency with the original natural language requirement, easily leading to the problem that the formula can be generated in form but deviates from the original requirement in semantics; 5) In aviation software requirement scenarios, the same requirement often includes object constraints, state constraints, continuous signal constraints, time window constraints, and path constraints simultaneously. If a structured semantic sketch matching the target logical category cannot be formed before generation, subsequent reduction generation is prone to problems such as object recognition errors, time boundary deviations, path quantifier mismatches, or incomplete formula combinations.

[0004] In summary, existing technologies for converting natural language requirements into temporal logic specifications still lack an automatic generation method that addresses the natural language requirements of aviation software. This method should first identify the target temporal logic category, then, in the deconstruction, synthesis, and verification stages, respectively, invoke corresponding example resources and historical error correction resources based on the logic category and processing stage to generate a structured semantic sketch. Finally, it should complete a closed-loop iteration of temporal logic specification generation through back-translation heuristic comparison, sub-library back-writing in the verification stage, local back-back in the preceding stage, and threshold control. The key technical problems to be solved are: 1) How to automatically identify the appropriate target temporal logic category based on the semantic features of different aviation software requirements; 2) How to organize example resources and error correction resources in a two-dimensional manner according to "temporal logic category + processing stage" and call them in a targeted manner at different stages; 3) How to form a structured semantic sketch that matches the target logic category before the specification is generated, so as to reduce object recognition bias, time boundary bias and path quantifier mismatch; 4) How to establish an iterative generation and correction closed loop through candidate specification back-translation, heuristic comparison, verification stage sub-library back-writing and preliminary stage local rollback; 5) How to configure a unified extension interface for the access of other temporal logic categories without changing the existing identification, deconstruction, synthesis, verification and back-writing process. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of existing technologies by providing an automatic generation method for temporal logic specifications for aerospace software requirements verification. This method identifies the target temporal logic category and, in the deconstruction, synthesis, and verification stages, invokes corresponding example resources and historical error correction resources based on the logic category and processing stage, respectively, to generate a structured semantic sketch. Through back-translation heuristic comparison, verification stage sub-library write-back, previous stage local backtracking, and threshold control, a closed-loop iterative automatic generation of temporal logic specifications is achieved. This method accurately invokes the most relevant reference information for the current logic category and current processing stage. It also accommodates multiple temporal logic scenarios such as MTL, STL, and CTL, effectively solving problems such as formulas that can be generated in form but deviate from the original requirements semantically, as well as object recognition errors, time boundary deviations, path quantifier mismatches, or incomplete formula combinations. It is particularly suitable for natural language requirements verification tasks in aerospace software scenarios such as flight control software, trajectory control software, energy management software, communication and navigation software, thermal management software, and fault diagnosis and recovery software, and has promising application prospects.

[0006] The specific technical solution for achieving the objective of this invention is: an automatic generation method for timing logic specifications for aerospace software requirements verification, characterized by the following steps:

[0007] An automatic generation method for timing logic specifications for aerospace software requirements verification is characterized by the following steps:

[0008] Step 1: Receive the aviation software natural language request text to be processed;

[0009] Step 2: Based on the time expression, object type, state change, continuous signal constraints and path semantics in the natural language requirement text, determine the target temporal logic category corresponding to the natural language requirement text. The target temporal logic category includes at least one of MTL, STL and CTL.

[0010] Step 3: Call the example resource library and historical error correction resource library, which are organized in two dimensions: "sequential logical category + processing stage";

[0011] Step 4: In the deconstruction, synthesis, and verification stages, retrieve relevant example records and error correction records from the sub-libraries corresponding to the target temporal logic category and the current processing stage, and form the enhanced processing context for the corresponding stage.

[0012] Step 5: Utilize the enhanced processing context of the deconstruction phase to perform semantic deconstruction and generate a structured semantic sketch corresponding to the target temporal logic category;

[0013] Step 6: Perform synthesis processing based on the pre-set object mapping table, the enhanced processing context of the synthesis stage, and the structured semantic sketch to generate candidate temporal logic reductions;

[0014] Step 7: Utilize the enhanced processing context of the verification phase to back-translate the candidate temporal logic specification into a natural language description, and generate error correction information based on the heuristic comparison between the back-translation result and the original requirement text;

[0015] Step 8: Write the error correction information into the historical error correction resource sub-library corresponding to the target temporal logic category and verification stage. If the number of error correction information writes does not reach the preset threshold, convert the error correction information into the previous stage constraint term to trigger the re-execution of deconstruction processing or re-execution of synthesis processing. When the preset threshold is reached, stop continuing to automatically roll back and output the current candidate temporal logic reduction and its heuristic comparison result.

[0016] Each example record in the example resource library contains at least a logical category field, a processing stage field, an input text field, a target output field, and a reasoning description field.

[0017] A single error correction record in the historical error correction resource library includes at least a logical category field, a processing stage field, a problem input field, an error output field, a correction output field, and an error type field.

[0018] The structured semantic sketch uses different field templates according to different target temporal logic categories.

[0019] The pre-set object mapping table maps object names, component names, signal names, state names, and action names in the natural language requirement text of aviation software to standard object symbols, atomic proposition symbols, or state predicate symbols.

[0020] The heuristic comparison in the verification phase is used for iterative correction. One error correction information writing is performed on the same requirement text in the verification phase and is recorded as one iteration. When the error correction information is converted into a previous stage constraint, it is mapped to a field-level constraint and triggers the destructuring process or reduction fragment synthesis process corresponding to the field-level constraint.

[0021] The enhanced processing context is constructed as a field-level enhanced processing context according to the field type.

[0022] In the deconstruction phase, multiple models generate candidate values ​​for at least one field in the structured semantic sketch. When there is a conflict between the candidate values, field-level consensus processing is performed. In the synthesis phase, multiple models generate candidate reduction fragments for at least one of the following: atomic formula construction, timing operator selection, and formula combination relationship. When there is a conflict between the candidate reduction fragments, fragment-level consensus processing is performed.

[0023] The target temporal logic category can be expanded to other temporal logic categories. For a new temporal logic category, a semantic sketch template, rule mapping relationship, example resource sub-library, and historical error correction resource sub-library corresponding to the logic category are configured, and the new temporal logic category is connected to the target logic category recognition, semantic deconstruction, reduction synthesis, and verification write-back process.

[0024] Compared with the prior art, the present invention has the following beneficial technical effects and significant technical progress:

[0025] 1) By identifying the target sequential logic category before processing and directing it to the corresponding processing path of MTL, STL or CTL respectively, different types of aerospace software requirements such as discrete event constraints, continuous signal constraints and branch path constraints can be processed respectively.

[0026] 2) By organizing the example resource library and the historical error correction resource library in a two-dimensional manner according to "sequential logic category + processing stage", the system can call the most relevant example and error correction information in the current logical domain in the deconstruction stage, synthesis stage and verification stage respectively, thereby improving the relevance of reference information calling.

[0027] 3) By generating a structured semantic sketch corresponding to the target logical category during the deconstruction stage, the objects, events, states, time windows, continuous signal conditions and path relationships in the requirements are explicitly expressed before the specification is generated, thereby reducing object recognition bias, time boundary bias and path quantifier mismatch.

[0028] 4) By setting up a pre-defined object mapping table, a unified mapping of object names, state names, and action names in aviation software requirements text to standard object symbols, atomic proposition symbols, or state predicate symbols is achieved, which helps to improve the consistency of specification generation and the traceability of subsequent verification.

[0029] 5) By back-translating candidate specifications and heuristic comparison, an iterative correction loop is established from the original requirements to the candidate specifications and then to the natural language description. After reaching the preset threshold, the current candidate specifications and comparison results are output for manual review or external verification.

[0030] 6) By writing back the error correction information generated in the verification phase to the historical error correction resource sub-library of the verification phase, and converting it into a constraint item of the preceding phase when the preset threshold is not reached, so as to trigger the re-execution of deconstruction processing or re-execution of synthesis processing, the structured accumulation and targeted reuse of error correction information are realized.

[0031] 7) By enhancing the processing context at the field level, performing joint retrieval at the field level, generating multiple model candidates at the field level and processing consensus at the field level, as well as generating multiple model candidates at the reduction fragment level and processing consensus at the fragment level, the impact of field attribution conflicts and reduction fragment conflicts on subsequent processing results can be reduced.

[0032] 8) By organizing logical category identification, semantic sketch templates, rule mapping, and example and historical error correction resources into an extensible structure, new time-related logical categories can be accessed without altering the main process. Attached Figure Description

[0033] Figure 1 This is a system schematic diagram of the architecture of the present invention;

[0034] Figure 2 This is a flowchart illustrating the deconstruction phase.

[0035] Figure 3 This is a flowchart illustrating the synthesis stage;

[0036] Figure 4 This is a flowchart illustrating the verification phase. Detailed Implementation

[0037] This invention includes the following steps:

[0038] Step 1: Receive the natural language request text for the aviation software to be processed;

[0039] Step 2: Based on the time expression, object type, state change, continuous signal constraints and path semantics in the natural language requirement text, determine the target temporal logic category corresponding to the natural language requirement text. The target temporal logic category includes at least one of MTL, STL and CTL.

[0040] Step 3: Call the example resource library and historical error correction resource library, which are organized in two dimensions: "sequential logical category + processing stage";

[0041] Step 4: In the deconstruction, synthesis, and verification stages, retrieve relevant example records and error correction records from the sub-libraries corresponding to the target temporal logic category and the current processing stage, and form the enhanced processing context for the corresponding stage.

[0042] Step 5: Utilize the enhanced processing context of the deconstruction phase to perform semantic deconstruction and generate a structured semantic sketch corresponding to the target temporal logic category;

[0043] Step 6: Perform synthesis processing based on the pre-set object mapping table, the enhanced processing context of the synthesis stage, and the structured semantic sketch to generate candidate temporal logic reductions;

[0044] Step 7: Utilize the enhanced processing context of the verification phase to back-translate the candidate temporal logic specification into a natural language description, and generate error correction information based on the heuristic comparison between the back-translation result and the original requirement text;

[0045] Step 8: Write the error correction information into the historical error correction resource sub-library corresponding to the target temporal logic category and verification stage. If the number of error correction information writes does not reach the preset threshold, convert the error correction information into the previous stage constraint term to trigger the re-execution of deconstruction processing or re-execution of synthesis processing. When the preset threshold is reached, stop continuing to automatically roll back and output the current candidate temporal logic reduction and its heuristic comparison result.

[0046] The specific processing steps of this invention are as follows:

[0047] (1) Identification of demand input and target logical category

[0048] The system receives the natural language requirement text for aviation software to be processed, and identifies the corresponding target temporal logic category based on the time expression, object type, state change, continuous signal constraint, and path semantics in the requirement. The target temporal logic category includes at least: metric temporal logic (MTL), signal temporal logic (STL), and branch temporal logic (CTL). The target temporal logic category is determined by the system calculating the matching score of the requirement text on the time constraint feature, continuous signal feature, and path branch feature, respectively, and based on the comprehensive score. For requirements that have multiple semantic features, multiple candidate temporal logic categories can be retained and further confirmed in subsequent processing.

[0049] (2) Resource organization methods

[0050] The system build or call includes: a collection of resources such as an example resource repository, a historical error correction resource repository, and a pre-built object mapping table.

[0051] The example resource library and the historical error correction resource library are both organized in a two-dimensional manner of "time-sequence logical category + processing stage". The processing stage includes at least the following: deconstruction stage, synthesis stage and verification stage. Each example record in the example resource library includes at least the following fields: logical category field, processing stage field, input text field, target output field and reasoning description field. Each error correction record in the historical error correction resource library includes at least the following fields: logical category field, processing stage field, problem input field, error output field, correction output field and error type field.

[0052] (3) Phase-enhanced processing context construction

[0053] During the deconstruction, synthesis, and verification phases, the system retrieves relevant records from the example resource sub-library and historical error correction resource sub-library corresponding to the current target logic category and the current processing stage, respectively. The retrieval results are combined with the input information of the current stage to form the enhanced processing context of the corresponding stage. When the task has been located to a specific field, the system can further construct a field-level enhanced processing context. The field-level enhanced processing context is based at least on: the target logic category, the current processing stage, and the current field type. The field type includes at least object fields, event fields, time interval fields, time window fields, trigger condition fields, path quantifier fields, atomic formula fields, timing operator fields, and formula combination fields.

[0054] (4) Semantic deconstruction and generation of structured semantic sketches

[0055] The system utilizes the enhanced processing context of the deconstruction phase to perform semantic deconstruction, generating a structured semantic sketch corresponding to the target logic category. Different target logic categories can adopt the following different field templates: 1) Semantic sketches for MTL include at least object fields, event fields, time interval fields, trigger condition fields, and timing relationship fields; 2) Semantic sketches for STL include at least signal object fields, signal variable fields, comparison relationship fields, threshold fields, time window fields, and sampling context fields; 3) Semantic sketches for CTL include at least state proposition fields, path quantifier fields, branch timing relationship fields, target state fields, and branch constraint fields.

[0056] At least one field in the semantic sketch can be generated by multiple models to produce field candidate values. When there is a conflict between field candidate values, the system performs field-level consensus processing. The field-level consensus processing determines the final field result based on at least one or more of the following: field candidate consistency, retrieval evidence support, object mapping constraints, target logical category constraints, and inter-field dependency constraints.

[0057] (5) Specification synthesis

[0058] The system performs reduction synthesis based on structured semantic sketches, enhanced processing context during the synthesis phase, and a pre-defined object mapping table to generate candidate temporal logic specifications. The reduction synthesis includes at least the following: 1) standardizing and mapping object names, component names, signal names, state names, and action names in the requirements according to the pre-defined object mapping table; 2) constructing atomic formulas or state predicates based on the constraints in the structured semantic sketches; 3) selecting the corresponding timing operators according to the target temporal logic category and applying time intervals, continuous signal constraints, or path quantifiers; 4) combining multiple atomic formulas or specification fragments into candidate temporal logic specifications based on logical connection relationships.

[0059] Multiple models can generate candidate reduction fragments for atomic formula construction, timing operator selection, and formula combination relationships, respectively. When there are conflicts among the candidate reduction fragments, the system performs fragment-level consensus processing to determine the target reduction fragment.

[0060] (6) Result verification, error correction and write-back and local rollback

[0061] During the verification phase, the system retrieves relevant example records and error correction records from the sub-library corresponding to the current target logic category and verification phase, translates the candidate temporal logic specification back into a natural language description, and then generates error correction information based on the heuristic comparison between the back translation result and the original requirement text.

[0062] The heuristic comparison can employ at least one of semantic similarity calculation, rule comparison, or manual-assisted analysis to generate error correction criteria, rather than to make a definitive judgment on the strict semantic consistency between the original requirement text and the candidate specification. The error correction information generated includes at least: 1) deviation location; 2) deviation type; 3) correction suggestions; and 4) corresponding processing stage identifier.

[0063] The deviation types include at least one of the following: object recognition deviation, time boundary deviation, logical category deviation, path quantifier deviation, and formula combination deviation.

[0064] Subsequently, the system writes the error correction information into the historical error correction resource sub-library corresponding to the target logical category and verification stage. Each time error correction information is written for the same requirement text during the verification stage, it is counted as one iteration. When the number of error correction information writes does not reach the preset threshold, the system reads the error correction information corresponding to the current requirement text from the sub-library corresponding to the verification stage, converts it into a constraint item of the preceding stage, and then triggers the re-execution of deconstruction processing or re-execution of synthesis processing according to the deviation type, as follows: 1) When the error correction information corresponds to object recognition, time boundary, path semantics, or logical category judgment, the re-execution of deconstruction processing is triggered; 2) When the error correction information corresponds to atomic formula construction, timing operator selection, or formula combination relationship, the re-execution of synthesis processing is triggered.

[0065] Furthermore, the preceding stage constraints can be mapped to field-level constraints, and only the deconstruction processing or reduction fragment synthesis processing corresponding to the field-level constraints is triggered to narrow the scope of reprocessing. When the number of times the error correction information is written reaches a preset threshold, the system stops automatically rolling back and outputs the current candidate sequential logic reduction and its heuristic comparison results. At the same time, it outputs the object mapping results, the example record identifier used, and the error correction record identifier used, for subsequent manual review or external verification processing.

[0066] (7) Extend to other time logic categories

[0067] This invention can be extended to other temporal logic categories. For a new logic category, the following needs to be configured: 1) a semantic sketch template for the corresponding logic category; 2) operator mapping rules and formula combination rules for the corresponding logic category; 3) an example resource sub-library and a historical error correction resource sub-library for the corresponding logic category; 4) identification rules for the corresponding logic category and necessary object or proposition mapping relationships. For example, it can be extended to other temporal logic categories such as MITL and PPTL. After the extension, the main process of "logic category identification -> phased resource call -> semantic deconstruction -> reduction synthesis -> back-translation heuristic comparison -> verification stage write-back and rollback control" is still followed.

[0068] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0069] Example 1

[0070] (I) Overall Implementation Architecture

[0071] See Figure 1This invention employs a system architecture comprising a text deconstruction module, a contract generation module, and a formula verification module to achieve automatic generation of temporal logic specifications. The text deconstruction module processes the input natural language requirements through a multi-model check and execution module, a multi-model consensus and debate module, and an expert review and evaluation module to obtain a new structured sketch. If, after discussion by the expert model and other models in the multi-model consensus stage, some opinions (including those for and against) from the multi-model check stage still cannot reach a consensus, the expert model will conduct a separate review and evaluation with reference to the discussion records of the consensus stage. Finally, if there are inconsistent opinions in the expert model's evaluation before and after, the opinion is assumed to be reasonable, but it is not added to the historical error correction sub-library of the deconstruction module. Instead, it is added to the backup error correction sub-library of the deconstruction module (whose content is the same as the historical error correction sub-library of the deconstruction module), and the multi-model check and execution module generates another candidate semantic sketch. The purpose is to allow both semantic sketches to enter the contract generation module and the formula verification module, compare the final formulas generated by the two, and select the optimal one. To prevent any useful opinions from being overlooked when there is uncertainty, the contract generation module inputs them. The contract generation model processes the input structured sketch (if there are candidate structured sketches, the candidate structured sketch is input again after the first one passes through the contract generation module for a second contract generation) through the multi-model check execution module, the multi-model consensus and debate module, and the expert review and evaluation module to obtain the temporal logic reduction formula. If, after discussion by the expert model and other models in the multi-model consensus stage, there are still some opinions (including for and against) from the multi-model check stage that cannot reach a consensus, they will be transferred to the expert model for separate review and evaluation with reference to the discussion records of the consensus stage. Finally, if there are opinions that are inconsistent in the evaluation of the expert model before and after, the opinion is assumed to be reasonable, but it is not added to the historical error correction sub-library of the contract module. Instead, it is added to the backup error correction sub-library of the contract module (whose content is the same as the historical error correction sub-library of the contract module), and the multi-model check execution module generates another candidate temporal logic reduction formula. The purpose is to allow both temporal logic reduction formulas to enter the formula verification module, compare the two, and select the optimal one. When there is uncertainty, to prevent any useful opinions from being overlooked (the same applies if there are candidate sketches), input them into the formula verification module; the formula verification module verifies one or more input time logic specifications against the original natural language requirements, using back translation and similarity calculation. If it passes, it is converted into multiple time logic formulas (TL) for output; if it fails, it is handed over to experts for manual processing, and relevant examples are fed back to the text deconstruction module example library or the formula synthesis module example library.

[0072] See Figure 1This workflow consists of a forward processing link and a lower-level verification and feedback link. First, the natural language requirement input text deconstruction module breaks down the objects, events, time constraints, and related semantic relationships in the requirement, forming a structured semantic sketch for subsequent processing. Second, during text deconstruction, the processing results further enter the multi-model checking and execution module for candidate checking, and then enter the multi-model consensus and debate module to compare and filter the judgments given by different models. When there are still opinions that are difficult to reach a consensus, the results are then submitted to the expert review and evaluation module for review and evaluation. The evaluation results are sent back to the upper-level module to correct the current deconstruction results. Subsequently, the corrected structured semantic sketch is sent to the formula synthesis module to generate a temporal logic reduction. The formula synthesis module, together with the multi-model checking and execution module, the multi-model consensus and debate module, and the expert review and evaluation module, forms a closed loop of downward checking, discussion consensus, and feedback correction to improve the completeness and consistency of candidate formulas. Finally, the temporal logic reduction is entered into the formula verification module for verification and comparison with the original natural language requirements. After the verification is successful, the corresponding multiple temporal logic formulas TL are output. If problems are found during the verification, the relevant correction information is fed back to the aforementioned processing stage, thus forming a closed-loop working process that gradually advances around text deconstruction, formula synthesis and formula verification.

[0073] The overall processing flow of this invention includes the following steps: requirement input, logical category identification, phased resource allocation, semantic deconstruction, specification synthesis, result verification, and error correction and write-back.

[0074] (II) Implementation Method of Resource Organization and Target Logical Category Identification

[0075] The system constructs a resource set corresponding to the target task. This set includes at least an example resource library, a historical error correction resource library, and object mapping information. Both the example resource library and the historical error correction resource library adopt a two-dimensional organization method. The first dimension is divided into three categories according to logical categories: MTL, STL, and CTL. The second dimension is divided into three categories according to processing stages: deconstruction stage, synthesis stage, and verification stage. Through this organization method, when the system processes a new task, it can directly locate the resource subset corresponding to "current logical category + current processing stage".

[0076] After receiving a natural language request for aviation software, the system performs sentence segmentation, terminology recognition, constraint fragment localization, and semantic feature extraction on the text. Based on this, and combining the time expression, object type, state changes, continuous signal conditions, and path semantics in the request, it determines the appropriate logical category for the current request.

[0077] (III) Semantic Deconstruction Implementation Method

[0078] Based on the target logical category and the current processing stage, the system retrieves relevant example records and relevant error correction records from the corresponding sub-databases, and combines the basic processing information, the retrieved set of example records, the retrieved set of error correction records, and the current stage input information to form an enhanced processing context.

[0079] See Figure 2 During the deconstruction phase, different structured semantic sketches are output based on different logical categories: 1) MTL-Sketch = (Object, Event, TimeInterval, TriggerCondition, TemporalRelation); 2) STL-Sketch = (SignalObject, SignalVar, Comparator, Threshold, TimeWindow, SampleContext); 3) CTL-Sketch = (StateProp, PathQuantifier, BranchRelatio)

[0080] n, TargetState, BranchConstraint).

[0081] For the requirement "the flight control mode switches to safety mode within 2 seconds after the flight attitude deviation exceeds the limit", the following intermediate results can be obtained in the deconstruction stage: 1) Object = Flight control mode; 2) Event = Switch to safety mode; 3) TimeInterval = [0,2s]; 4) TriggerCondition = Flight attitude deviation exceeds the limit; 5) TemporalRelation = Eventually occurs.

[0082] If different models output TimeInterval = [0,2s], TimeWindow = [0,2s] respectively, or there is a disagreement on the field belonging to “within 2 seconds”, the system will retrieve relevant example records and error correction records based on the target logic category, deconstruction stage and time field type, and determine the time interval field to be written into the MTL semantic sketch by combining the consistency between the trigger condition field and the time sequence relationship field.

[0083] (iv) Specification Synthesis Implementation Method

[0084] The system maps object names, component names, signal names, status names, and action names in aviation software requirements text to standard object symbols, atomic proposition symbols, or status predicate symbols based on a pre-defined object mapping table. For example: 1) "Flight control mode" can be mapped to flight_control_mode; 2) "Safe mode" can be mapped to safe_mode; 3) "Flight attitude deviation overlimit" can be mapped to attitude_error_overlimit; 4) "Combustion chamber pressure" can be mapped to combustion_pressure.

[0085] See Figure 3 The synthesis phase is executed in the following sub-steps: 1) Standardize terminology based on a pre-defined object mapping table; 2) Construct atomic formulas or state predicates based on structured semantic sketches; 3) Apply corresponding timing operators, time window constraints, or path quantifiers according to the target logical category; 4) Combine multiple fragments into candidate specifications based on logical connection relationships. For example: 1) For the requirement "the flight attitude deviation should enter the safe mode within 2 seconds after exceeding the limit", the candidate MTL formula can be generated: G(attitude_error_overlimit -> F_[0,2] safe_mode); 2) For the requirement "the combustion chamber pressure is always not lower than 0.8MPa within 0 to 5 seconds", the candidate STL formula can be generated: G_0,5; 3) For the requirement "there is a path that eventually restores the flight control computer to normal mode after a failure", the candidate CTL formula can be generated: EF normal_mode.

[0086] (V) Implementation of Result Verification and Error Correction Writeback

[0087] See Figure 4The system translates the candidate temporal logic reduction back into a natural language description, and then heuristically compares the translation result with the original requirement text. In this embodiment, a comparison score of score_ver = cos(e_req, e_back) can be calculated between the semantic vector e_req of the original requirement text and the semantic vector e_back of the translated text, and error correction basis can be generated by combining rule verification or manual confirmation. After the comparison is completed, the system generates corresponding error correction information based on the differences and writes the error correction information into the historical error correction resource sub-library of the verification stage. One error correction information writing for the same requirement text in the verification stage is counted as one iteration. If the error correction information corresponds to an error in object recognition, time boundary, path semantics, or logical category judgment, the deconstruction process is re-executed; if the error correction information corresponds to an error in atomic formula construction, temporal operator selection, or formula combination relationship, the synthesis process is re-executed. When the error correction information is converted into a preceding stage constraint, the system further maps it to a field-level constraint. If the field-level constraint corresponds to an object field, time interval field, time window field, or path quantifier field, then only the destructuring process associated with that field is triggered; if the field-level constraint corresponds to an atomic formula field, timing operator field, or formula combination field, then only the candidate reduction fragment synthesis process associated with that field constraint is triggered.

[0088] (vi) Extended Implementation Methods

[0089] In extended scenarios of this implementation, if support for other time-related logical categories is required, the system can add processing branches for the corresponding logical categories based on the existing set of logical categories. For newly added time-related logical categories, after completing the definition of corresponding semantic features, configuration of logical category recognition rules, construction of example resource sub-libraries, and construction of historical error correction resource sub-libraries, the system can integrate the logical category into the existing recognition process. For example, when the target time-series logical category is expanded to MITL, corresponding field templates can be constructed around interval constraints, event triggering windows, and bounded time-series relationships; when the target time-series logical category is expanded to PPTL, corresponding field templates can be constructed around propositional interval relationships, projection relationships, and interval combination relationships.

[0090] The above is merely a preferred implementation of the present invention and is not intended to limit the present invention in any way. Therefore, any simple modifications, equivalent changes, and alterations made to the above implementation methods based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall be included within the scope of the claims of this patent as equivalent implementations of the present invention.

Claims

1. A method for automatically generating timing logic specifications for aerospace software requirements verification, characterized in that, The method includes the following steps: Step 1: Receive the aviation software natural language request text to be processed; Step 2: Based on the time expression, object type, state change, continuous signal constraints and path semantics in the natural language requirement text, determine the target temporal logic category corresponding to the natural language requirement text. The target temporal logic category includes at least one of MTL, STL and CTL. Step 3: Call the example resource library and historical error correction resource library, which are organized in two dimensions: "sequential logical category + processing stage"; Step 4: In the deconstruction, synthesis, and verification stages, retrieve relevant example records and error correction records from the sub-libraries corresponding to the target temporal logic category and the current processing stage, and form the enhanced processing context for the corresponding stage. Step 5: Utilize the enhanced processing context of the deconstruction phase to perform semantic deconstruction and generate a structured semantic sketch corresponding to the target temporal logic category; Step 6: Perform synthesis processing based on the pre-set object mapping table, the enhanced processing context of the synthesis stage, and the structured semantic sketch to generate candidate temporal logic reductions; Step 7: Utilize the enhanced processing context of the verification phase to back-translate the candidate temporal logic specification into a natural language description, and generate error correction information based on the heuristic comparison between the back-translation result and the original requirement text; Step 8: Write the error correction information into the historical error correction resource sub-library corresponding to the target time-series logic category and verification stage. If the number of error correction information writes does not reach the preset threshold, convert the error correction information into a previous stage constraint item to trigger the re-execution of deconstruction processing or re-execution of synthesis processing. When the preset threshold is reached, the automatic rollback stops and the current candidate timing logic reduction and its heuristic comparison result are output.

2. The method for automatically generating timing logic specifications for aerospace software requirements verification according to claim 1, characterized in that, Each example record in the example resource library contains at least a logical category field, a processing stage field, an input text field, a target output field, and a reasoning description field.

3. The method for automatically generating timing logic specifications for aerospace software requirements verification according to claim 1, characterized in that, A single error correction record in the historical error correction resource library includes at least a logical category field, a processing stage field, a problem input field, an error output field, a correction output field, and an error type field.

4. The method for automatically generating timing logic specifications for aerospace software requirements verification according to claim 1, characterized in that, The structured semantic sketch uses different field templates according to different target temporal logic categories.

5. The method for automatically generating timing logic specifications for aerospace software requirements verification according to claim 1, characterized in that, The pre-set object mapping table maps object names, component names, signal names, state names, and action names in the natural language requirement text of aviation software to standard object symbols, atomic proposition symbols, or state predicate symbols.

6. The method for automatically generating timing logic specifications for aerospace software requirements verification according to claim 1, characterized in that, The heuristic comparison in the verification phase is used for iterative correction. One error correction information writing is performed on the same natural language requirement text in the verification phase and is recorded as one iteration. When the error correction information is converted into a previous stage constraint, it is mapped to a field-level constraint and triggers the deconstruction processing or reduction fragment synthesis processing corresponding to the field-level constraint.

7. The method for automatically generating timing logic specifications for aerospace software requirements verification according to claim 1, characterized in that, The enhanced processing context is constructed as a field-level enhanced processing context according to the field type.

8. The method for automatically generating timing logic specifications for aerospace software requirements verification according to claim 1, characterized in that, In the deconstruction phase, multiple models generate candidate values ​​for at least one field in the structured semantic sketch. When there is a conflict between the candidate values, field-level consensus processing is performed. In the synthesis phase, multiple models generate candidate reduction fragments for at least one of the following: atomic formula construction, timing operator selection, and formula combination relationship. When there is a conflict between the candidate reduction fragments, fragment-level consensus processing is performed.

9. The method for automatically generating timing logic specifications for aerospace software requirements verification according to claim 1, characterized in that, The target temporal logic category can be expanded to other temporal logic categories. For a new temporal logic category, a semantic sketch template, rule mapping relationship, example resource sub-library, and historical error correction resource sub-library corresponding to the logic category are configured, and the new temporal logic category is connected to the target logic category recognition, semantic deconstruction, reduction synthesis, and verification write-back process.

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