Neuromorphic processor system and data processing method

Abstract

Embodiments of the present application provide a neuromorphic processor system and a data processing method. The neuromorphic processor system comprises: at least one central routing and interface chiplet; and a plurality of computing chiplets; wherein the central routing and interface chiplet and the plurality of computing chiplets are integrated in the same package; each computing chiplet comprises: a plurality of processing cores, each processing core being configured to support spiking neural network (SNN) inference, artificial neural network (ANN) inference, and / or spike-timing-dependent plasticity (STDP) online learning tasks; and a local communication network for realizing communication between different processing cores within the corresponding computing chiplet; the central routing and interface chiplet comprises: a global routing engine for realizing packet forwarding across the computing chiplets; and / or a weight version management unit for conflict arbitration of weight change amounts from different computing chiplets and global weight broadcasting to maintain weight consistency across chiplets for STDP learning.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence technology, and more specifically, the embodiments of this application relate to a neuromorphic processor system and a data processing method. Background Technology

[0002] With the increasing demand for high energy efficiency and low latency in edge computing for artificial intelligence, neuromorphic processors have become a research hotspot due to their event-driven, in-memory computing, or brain-like computing characteristics. To support complex neural network models, related technologies tend to design neuromorphic processors as large-scale single-chip systems integrating massive numbers of neurons and synapses.

[0003] For example, a publicly available technology presents a monolithically integrated digital neuromorphic processor called "PAICORE," which integrates 1024 processing cores, over 1.919 million neurons, and 4.773 billion synapses on a single chip (with an area of ​​up to 537.98 mm²), and employs a five-layer fat quadtree on-chip network (NoC) for communication between processing cores. This type of design aims to uniformly support spiking neural networks (SNNs), artificial neural networks (ANNs), and on-chip online learning based on spike-timing-dependent plasticity (STDP). Furthermore, Intel's Loihi 2 and IBM's TrueNorth also employ monolithic integration solutions, concentrating a large number of neural computing cores, routers, and memory onto a single chip.

[0004] The above-mentioned monolithic integration solution has the following significant drawbacks:

[0005] Excessive chip size (typically >300 mm²) leads to low yield (usually below 20%), high manufacturing costs, and hinders large-scale commercialization. Fixed chip architecture prevents flexible adjustment of computing resource composition and configuration based on application scenarios (e.g., the number of cores for online learning, inference / learning ratio). While expansion is possible through board-level multi-chip interconnects, inter-chip communication bandwidth (<50 GB / s) and latency (>100 ns) are significantly worse than on-chip communication, limiting the linear scalability of the system. Concentrating all computing units on a single die results in high power supply and heat dissipation density, making localized hotspots prone to triggering frequency throttling and impacting peak performance.

[0006] While related technologies offer the technical concept of breaking down large monolithic chips into multiple smaller chiplets and integrating them, these technical solutions cannot meet the specific requirements of the related technical solutions. For example, none of them can maintain the stability of the online learning process based on the pulse timing-dependent plasticity rule under the chiplet architecture. Summary of the Invention

[0007] The purpose of this application is to provide a neuromorphic processor system and a data processing method. The neuromorphic processor system of this application decouples the traditional monolithic large-scale chip into multiple computing chips and a central routing and interface chip, improving manufacturing yield, reducing manufacturing costs, and supporting flexible configuration of computing chips with different functional focuses as needed. At the same time, the central routing and interface chip has a built-in weight version management unit, which centrally arbitrates STDP learning weight conflicts across chips and broadcasts globally consistent updates. For the first time, it solves the distributed learning consistency problem under a chip-based architecture, achieving learning accuracy comparable to monolithic solutions. Moreover, the system scale can be linearly expanded, and the cross-chip communication latency is low, providing a high-energy-efficiency and commercially viable hardware foundation for ultra-large-scale neuromorphic computing systems.

[0008] In a first aspect, embodiments of this application provide a neuromorphic processor system, the neuromorphic processor system comprising: at least one central routing and interface core; and multiple computing cores; wherein the central routing and interface core and the multiple computing cores are integrated within the same package; each computing core comprises: multiple processing cores, each processing core being configured to support spiking neural network (SNN) inference, artificial neural network (ANN) inference, and / or spiking time-dependent plasticity (STDP) online learning tasks; and a local communication network for enabling communication between different processing cores within the corresponding computing core; the central routing and interface core comprises: a global routing engine for enabling packet forwarding across computing cores; and / or a weight version management unit for conflict arbitration and global weight broadcasting of weight changes from different computing cores to maintain weight consistency in cross-core STDP learning.

[0009] The neuromorphic processor system provided in the embodiments of this application decouples the traditional monolithic large-scale chip into multiple computing chips and a central routing chip, improving manufacturing yield, reducing manufacturing costs, and supporting flexible configuration of computing chips with different functional focuses as needed. At the same time, the central routing and interface chip has a built-in weight version management unit, which centrally arbitrates STDP learning weight conflicts across chips and broadcasts globally consistent updates. For the first time, the distributed learning consistency problem is solved under the chip-based architecture, achieving learning accuracy comparable to monolithic solutions. Moreover, the system scale can be linearly expanded, and the cross-chip communication latency is low, providing a high-energy-efficiency and commercially viable hardware foundation for ultra-large-scale neuromorphic computing systems.

[0010] In some embodiments, the central routing and interface chip is connected to any computing chip via an inter-chip interface circuit; the inter-chip interface circuit includes: a source synchronous clock transmitter, located in the transmitting chip, for outputting a local clock along with the data to be transmitted; a dual-edge sampling receiver, located in the receiving chip, for sampling data according to the rising and falling edges of the received clock; a credit counter, located in the transmitting chip, for recording the currently available credits and pausing data transmission when credits are exhausted; a credit return signal generator, located in the receiving chip, for generating a credit return signal and sending it back to the corresponding transmitting chip when the receiving end successfully receives a data chip and the receiving buffer is not full, thereby increasing the credit value of the corresponding credit counter; and a retransmission buffer, located in the transmitting chip, wherein the depth of the retransmission buffer is a preset fixed length.

[0011] The source-synchronous clock transmission and dual-edge sampling reception in this embodiment allow the receiving chip to sample directly without relying on a global clock tree or phase-locked loop, avoiding the complexity and additional latency caused by cross-chip clock synchronization. Simultaneously, dual-edge sampling doubles the bandwidth for the same number of lines. The credit flow control logic records the available credits using a credit counter in the transmitting chip and pauses transmission when credits are exhausted. The credit return signal generator in the receiving chip returns credits when a data slice is successfully received and the buffer is not full, forming a closed-loop flow control that eliminates the need for complex link-layer handshake mechanisms, reducing flow control latency. The retransmission buffer has only a fixed depth and does not enable complex link-layer retransmission windows, minimizing error recovery overhead. These lightweight asynchronous transmission protocols collectively reduce the unidirectional minimum latency of cross-chip communication, making the communication performance between chips approach the level of native on-chip networks, thereby supporting efficient collaborative computing of large-scale chip-based neuromorphic processors.

[0012] In some embodiments, the weight version management unit includes: a global weight version mapping table for storing the correspondence between synapse identifiers, version numbers, and currently valid weight values; a conflict arbitrator for determining a target global weight value according to preset rules and assigning an updated version number to the target global weight value when receiving weight changes from different computing kernels for the same synapse; and a broadcast controller for sending the updated version number and the target global weight to the relevant computing kernels via multicast or broadcast.

[0013] The weight version management unit provided in the embodiments of this application records the latest weight and version number of each synapse through a centralized global mapping table, solving the problem of multiple copy conflicts caused by weight updates of the same synapse in multiple granules after granulation. The conflict arbitrator adjudicates the weight changes reported by different granules according to different preset rules such as timestamps or preset priorities, ensuring convergence to a definite global weight value and avoiding learning divergence; the broadcast controller synchronously distributes the new weights and version numbers to all relevant computing granules, so that the weight tables of each granule are eventually consistent. This mechanism replaces frequent global synchronization with incremental weight change exchange and loose synchronous updates, which not only ensures the accuracy comparable to single-chip STDP learning (error less than 0.5%), but also controls the cross-granule learning communication overhead within a small threshold of the total inter-chip bandwidth, thereby realizing scalable distributed online learning in granulated neuromorphic processors.

[0014] In some embodiments, each computing chip further includes: a local sovereign recalculation table; a shadow register for temporarily storing weight changes generated by locally executing STDP rules; and a control circuit coupled to the local sovereign recalculation table and the shadow register, wherein the control circuit is configured to: periodically or when the number of accumulated learning events in the corresponding computing chip reaches a preset threshold, send the weight changes in the corresponding shadow register to the central routing and interface chip through the inter-chip interface circuit; and update the local sovereign recalculation table and clear the shadow register upon receiving a global weight update instruction from the central routing and interface chip.

[0015] The embodiments of this application physically separate the stable storage and temporary updates of synaptic weights: the local sovereign weight table is a static memory array that provides stable weight values ​​for inference tasks; the shadow register is an independent temporary storage area that records the increments generated by local STDP events. The control circuit, acting as the scheduling core, periodically or based on event counts triggers batch transmissions, aggregating scattered small updates into messages, significantly reducing the number of cross-chip communication calls, thereby reducing the load on the central arbitrator and inter-chip bandwidth consumption. Upon receiving a global broadcast, the control circuit atomically writes the new weights to the sovereign weight table and clears the shadow register, ensuring that the weight versions of each computed chip are synchronized. This physical separation and batch synchronization mechanism allows inference and learning to be executed in parallel without blocking each other, while ensuring the eventual consistency of distributed learning, providing scalable, low-overhead online learning capabilities for chip-based architectures.

[0016] In some embodiments, the central routing and interface chip and the plurality of computing chips are integrated in the same package via 2.5D silicon interposer packaging or 3D stacked packaging.

[0017] In some embodiments, each computing chip further includes a local SRAM for storing local data required by the processing core within the respective computing chip.

[0018] In some embodiments, the local communication network corresponds to the L1 to L4 layer routers of the fat quadtree network, and the global routing engine corresponds to the L5 layer of the fat quadtree network.

[0019] The embodiments of this application logically decouple and physically reconstruct the original fat quadtree, enabling each computing core to implement L1-L4 layer routers, while the central routing and interface cores centrally implement L5 layer and cross-core routing tables. The advantages of this split are: First, the computing cores do not need to integrate complex L5 routing logic, saving computing core area and allowing a single computing core to integrate more processing cores; second, the centralization of the L5 layer avoids multi-level inter-chip routing forwarding, and any cross-core communication only needs to pass through the central routing and interface core relay once, with a fixed and predictable path length, which is beneficial for timing convergence. Therefore, this split scheme maintains the advantages of the original network architecture while reducing the design complexity and area overhead of the computing cores, providing hierarchical boundaries for linear system expansion.

[0020] In some embodiments, the global routing engine further includes: a cross-core routing table for storing the mapping relationship between target address ranges and output port numbers; wherein, the global routing engine is configured to look up the cross-core routing table based on the target address in the received data packet, determine the output port connected to the target computing core, and forward the data packet to the corresponding output port.

[0021] Some embodiments of this application require certain data packets to travel from a source computational kernel to a target computational kernel. The cross-kernel routing table within the global routing engine provides a mapping between target address segments and output ports, enabling the central routing kernel and interface kernels to make single-cycle table lookup decisions based on the target neuron address in the data packet, without the need for hierarchical routing or software intervention. This lookup-and-forward mechanism fixes the number of hops for cross-kernel communication to 1 (from the source kernel to the central routing kernel and then to the target kernel), avoiding the uncertain delays caused by multi-level inter-chip routing. Simultaneously, the routing table uses address segment matching (rather than exact address matching), and the number of entries is proportional only to the number of kernels (e.g., 8 to 64), not to the number of neurons, thus minimizing hardware overhead and supporting fast parallel lookups.

[0022] In some embodiments, the credit return signal generator includes: a subtractor, with the minuend input connected to the write pointer signal line output by the write address counter and the subtrahend input connected to the read pointer signal line output by the read address counter, for calculating the number of currently occupied positions in the receive buffer; a numerical comparator, with a first input connected to the output of the subtractor and a second input connected to a hardwired fixed value, and the output used to generate an incomplete signal; wherein the fixed value is equal to the total depth of the receive buffer; and an AND gate, with a first input connected to the receive valid flag signal line output by the dual-edge sampling register, a second input connected to the output of the comparator, and the output connected to the credit return signal line, wherein the credit return signal line is connected to the output acknowledge pin of the corresponding receiver chip.

[0023] The credit return signal generator in some embodiments of this application is implemented using pure combinational logic circuits. A subtractor calculates the occupied amount of the receive buffer in real time, a comparator compares it with the total buffer depth to obtain an incomplete flag, and an AND gate performs a logical AND operation on this flag with a valid receive flag, immediately outputting the credit return signal. The entire path does not contain any clock triggers or registers; the signal propagation delay is only the three-stage gate delay of the subtractor, comparator, and AND gate, far faster than traditional credit return mechanisms that require clock synchronization. The credit return signal is sent directly to the transmitting chip via a dedicated acknowledge line, enabling the transmitting end to receive credit release information almost in real time, thereby maintaining continuous transmission at high throughput.

[0024] Secondly, some embodiments of this application provide a data processing method running on the neuromorphic processor system described in the first aspect. The data processing method includes: an i-th computational core independently executes local STDP rules and stores the generated weight change in a local shadow register, where i is an integer greater than or equal to 1; if a weight update trigger condition is met, a weight update message is generated and sent to the central routing and interface core; in response to receiving a weight update message from multiple computational cores including the i-th computational core, the central routing and interface core performs conflict resolution on the weight change for the same synapse based on preset rules to determine a target global weight value; the central routing and interface core broadcasts the target global weight value to the multiple computational cores so that the multiple computational cores update their respective local sovereignty tables and clear their shadow registers.

[0025] In some embodiments, the data processing method further includes: the transmitting chip sending a local clock and the data to be transmitted together to the receiving chip via an inter-chip link, wherein the receiving chip is the central routing and interface chip or another computing chip; the receiving chip using the local clock to perform dual-edge sampling on the data to be transmitted. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is one of the architecture diagrams of a neuromorphic processor system provided in an embodiment of this application.

[0028] Figure 2 This is a second architectural diagram of a neuromorphic processor system according to an embodiment of this application.

[0029] Figure 3 The timing diagram of the lightweight asynchronous transport protocol provided in the embodiments of this application is shown.

[0030] Figure 4 A flowchart illustrating the data processing method provided in this application embodiment. Detailed Implementation

[0031] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0032] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0033] The following describes the full Chinese and English names of some of the English abbreviations used in the embodiments of this application.

[0034] ACK: Acknowledgment. ANN: Artificial Neural Network. ASIC: Application Specific Integrated Circuit. BGA: Ball Grid Array. BIST: Built-in Self Test. CCD: Core Complex Die (AMD terminology). CMOS: Complementary Metal Oxide Semiconductor. CoWoS: Chip on Wafer on Substrate (TSMC advanced packaging technology). CPU: Central Processing Unit. CRC: Cyclic Redundancy Check. DDR: Double Data Rate. DFT: Design for Testability. DLL: Delay Locked Loop. DRAM: Dynamic Random Access Memory. DVFS: Dynamic Voltage and Frequency Scaling. DVS: Dynamic Vision Sensor. ECC: Error Correcting Code. EDA: Electronic Design Automation. EMI: Electromagnetic Interference. EMIB: Embedded Multi-die Interconnect Bridge (Intel technology). FIFO: First In First Out. FPGA: Field Programmable Gate Array. GALS: Globally Asynchronous Locally Synchronous. Gbps: Gigabits per second. GHz: Gigahertz. GPIO: General Purpose Input Output.GPU: Graphics Processing Unit. GSOPS: Giga Synaptic Operations Per Second. HBM: High Bandwidth Memory. I2C: Inter Integrated Circuit. IOD: IO Die (AMD terminology). JTAG: Joint Test Action Group (Boundary Scan Standard). KGD: Known Good Die. LAT: Lightweight Asynchronous Transport. LIF: Leaky Integrate and Fire (Neuron Model). MCM: Multi-Chip Module. MIM: Metal Insulator Metal. MIPI: Mobile Industry Processor Interface. MRAM: Magnetoresistive Random Access Memory. NoC: Network on Chip. PCB: Printed Circuit Board. PCIe: Peripheral Component Interconnect Express. PHY: Physical Layer. PLL: Phase Locked Loop. RAM: Random Access Memory. RDY: Ready. RF: Radio Frequency. RISC V: Reduced Instruction Set Computer Five. RRAM: Resistive Random Access Memory. RTL: Register Transfer Level. SiP: System in Package. SNN: Spiking Neural Network. SoC: System on Chip. SoW: System on Wafer.SPI: Serial Peripheral Interface. SRAM: Static Random Access Memory. STDP: Spike Timing Dependent Plasticity. TDP: Thermal Design Power. TLB: Translation Lookaside Buffer. Tbps: Terabits per second. TSOPS: Tera Synaptic Operations Per Second. TSV: Through Silicon Via. UCIe: Universal Chipplet Interconnect Express. V / f: Voltage over Frequency.

[0035] The inventors of this application discovered that in the field of semiconductor design, breaking down a large monolithic chip into multiple smaller chiplets and integrating them for use in neuromorphic processors presents unique technical obstacles. One of the core mechanisms of neuromorphic computing is pulse timing-dependent plasticity (STDP) online learning, where weight updates depend on local observations of the pulse timing of presynaptic and postsynaptic neurons. When presynaptic and postsynaptic neurons of the same synapse are distributed across different computational chiplets, the independent execution of STDP rules by each chiplet generates multiple weight changes for the same synapse, leading to weight copy conflicts. Simply using conventional distributed consensus algorithms (such as majority voting or global lockstep synchronization) either introduces excessively high communication latency or undermines the biological realism of STDP. Existing chipletization schemes lack effective solutions to the aforementioned distributed learning consensus problem. Furthermore, related technologies, while breaking down a single chip into chiplets, significantly increase data transmission latency between different chiplets, affecting communication speed.

[0036] To address the aforementioned technical problems, embodiments of this application decompose the neuromorphic processor into a neuromorphic processor system comprising multiple computational cores and at least one central routing and interface core. In this system, the central routing and interface core centrally collects the weight changes of each core and, through conflict arbitration and version management, broadcasts the resolved global weight values ​​back to all relevant cores. This mechanism of local asynchronous learning combined with global loose synchronization avoids the high-frequency communication overhead caused by direct weight synchronization across cores and resolves multi-copy conflicts through centralized arbitration, thereby ensuring stable convergence of the STDP learning process under the core-based architecture while maintaining learning accuracy.

[0037] Some embodiments of this application aim to overcome the problems of low yield, rigid architecture, limited scalability, and difficult thermal management inherent in existing large-scale monolithic neuromorphic processors. Simultaneously, they address two major technical obstacles: increased cross-chip communication latency after chip-leveling and inconsistent learning weights in distributed STDP. Some embodiments of this application provide a chip-based modular, reconfigurable integration scheme, along with a supporting lightweight asynchronous transmission protocol and loosely synchronized weight consistency mechanism. This achieves optimized manufacturing costs, flexible system configuration, and near-infinite scalability while maintaining a high-performance unified computing paradigm.

[0038] For example, embodiments of this application provide a neuromorphic processor system, comprising: at least one central routing and interface core and multiple computing cores; wherein the central routing and interface core and the multiple computing cores are integrated within the same package; each computing core includes: multiple processing cores, each processing core being configured to support spiking neural network (SNN) inference, artificial neural network (ANN) inference, and / or spiking time-dependent plasticity (STDP) online learning tasks; and a local communication network for enabling communication between different processing cores within the computing core; the central routing and interface core includes: a global routing engine for enabling packet forwarding across computing cores; and / or a weight version management unit for conflict arbitration and global weight broadcasting of weight changes from different computing cores to maintain weight consistency in cross-core STDP learning.

[0039] In some embodiments of this application, the global routing engine further includes: a cross-core routing table for storing the mapping relationship between target address ranges and output port numbers; wherein, the global routing engine is configured to look up the cross-core routing table based on the target address in the received data packet, determine the output port connected to the target computing core, and forward the data packet to the corresponding output port.

[0040] Some embodiments of this application provide a neuromorphic processor system that decouples and reconstructs a traditional monolithic large-scale architecture into multiple functionally defined chips, and integrates them at high density using advanced 2.5D / 3D packaging technology. The overall architecture is as follows: Figure 1 As shown.

[0041] Please refer to Figure 1 , Figure 1 A neuromorphic processor system provided for some embodiments of this application includes: a central routing and interface core 110 and eight computing cores 120.

[0042] Figure 1 This diagram shows a top-view layout of a neuromorphic processor system according to this application. A central routing and interface chip (approximately 6mm × 6mm) is positioned at the center, surrounded by eight computing chips (each approximately 4mm × 4mm). All chips are interconnected via a bottom silicon interposer. A through-silicon via (TSV) is located beneath the central routing and interface chip, connecting to the package substrate and BGA solder balls.

[0043] The central routing and interface core is located at the encapsulation center and is responsible for global routing, cross-core communication arbitration, distributed learning consistency maintenance, and external interface control. In some embodiments of this application, the central routing domain interface core also includes a global routing engine 111 and a weight version management unit 112.

[0044] It should be noted that, in some embodiments of this application, the central routing and interface core is used to implement packet forwarding across computing cores, logically corresponding to the L5 layer (root router) of the original fat quadtree network. The central routing and interface core in some embodiments of this application has a weight version management unit, which is used to solve the cross-core weight consistency problem in distributed STDP learning (see below for details). The central routing and interface core in some embodiments of this application has an inter-chip interface controller, which is based on a lightweight asynchronous transport protocol (see...). Figure 3 It manages communication between all computing chips and controls external interfaces such as UCIe-IO, PCIe, and HBM.

[0045] Figure 1 The computing cores are distributed around a central routing and interface core. Each computing core integrates a processing core (e.g., ...). Figure 1The i-th processing core supports SNN / ANN / STDP, local SRAM (used to store local data required by the processing core within the corresponding computing core, including local weights and membrane potential data required by the corresponding processing core), and local on-chip network (i.e., local communication network, for example, in some embodiments of this application, the local on-chip network corresponds to layers L1 to L4 of a fat quadtree). In other embodiments of this application, each computing core also includes a shadow register or a local sovereignty table, etc. The computing cores in some embodiments of this application maintain a unified computing paradigm: each processing core can support SNN inference, ANN inference, and STDP online learning tasks through hardware reconfiguration; the computing cores adopt a globally asynchronous locally synchronous (GALS) clock scheme and have an independent power management domain.

[0046] Figure 1 All chips are integrated into a single package using 2.5D silicon interposer or 3D hybrid bonding technology. The data link between the computing chip and the central routing and interface chips employs a lightweight asynchronous transmission protocol (e.g., ...). Figure 3 As shown, instead of the standard UCIe full-featured protocol, it minimizes cross-chip communication overhead. The packet format follows and is compatible with the original design's Address Event Representation (AER) format.

[0047] Figure 1 The silicon interposer 130 is located beneath all the chips and employs 2.5D packaging technology, containing a high-density redistribution layer (RDL). Different chips are flip-chip bonded to the silicon interposer via microbumps, and the interconnections between chips are achieved through metal lines within the interposer, making cross-chip communication latency close to on-chip levels.

[0048] Through-silicon via (TSV) Figure 1 (Not shown) Located below the central routing and interface chip, it passes vertically through the silicon interposer and the package substrate, leading the internal signals of the chip (such as power, ground, and external interfaces) to the BGA solder balls at the bottom of the package, and then connecting to the system PCB. Figure 1 An example shows that any i-th computing chip includes: an i-th processing core 121, a local communication network 122, and a local SRAM 123. The i-th processing core represents any processing core, and the value of i is an integer greater than or equal to 1. Figure 1 Silicon via 140 is also shown.

[0049] Unlike related technologies, the embodiments of this application reconstruct the traditional monolithic large chip into multiple computing chips plus a central routing and interface chip, utilizing 2.5D packaging to achieve high-density and low-latency integration. This simultaneously addresses the yield, cost, and thermal management issues of monolithic solutions and provides a physical foundation for the distributed STDP learning consensus mechanism. It is understood that some embodiments of this application can... Figure 1 The number of computing cores has been expanded from 8 to more than 64.

[0050] The following is combined with Figure 2 The architecture of the central routing and interface core and computing core of some embodiments of this application is illustrated by way of example.

[0051] like Figure 2 As shown in some embodiments of this application, Figure 1 The weight version management unit 112 includes: a global weight version mapping table 112-1, a conflict arbitrator 112-2, and a broadcast controller 112-3.

[0052] The global weight version mapping table 112-1 is used to store the correspondence between synapse identifiers, version numbers, and currently valid weight values.

[0053] The conflict arbitrator 112-2 is used to determine the target global weight value according to preset rules and assign an update version number to the target global weight value when it receives weight changes from different computational cores for the same synapse.

[0054] The following examples illustrate the preset rules adopted by the conflict arbitrator 112-2 in this application.

[0055] Example 1: Conflict arbitration based on global logical timestamps (timestamp scheme)

[0056] Each computing core maintains a local learning event counter. Every fixed time interval (e.g., every 64 learning events), the accumulated weight variable Δw is encapsulated together with the current local timestamp and sent to the central routing and interface core.

[0057] After receiving multiple weight variables Δw for the same synapse, the conflict arbiter between the central router and the interface core receives them. It then compares the timestamps attached to each weight variable Δw and selects the Δw with the largest timestamp (i.e., the most recent one) as the valid update. If the timestamps are the same, it further compares the preset core priority.

[0058] It should be noted that in the embodiments of this application, the timestamps are generated independently by each computing core and do not require global clock synchronization (i.e., the embodiments of this application adopt the following loose synchronization method: the initial timestamp of each computing core is set to zero, and it increments by 1 for each local learning event generated; the central router and the interface core only compare relative order, and absolute consistency is not required). The specific hardware implementation includes: adding an N-bit counter (N=8~16) in each computing core, which increments by 1 for each STDP event completed; the conflict arbiter of the central router and the interface core includes a comparator array for comparing multiple timestamps of the same synapse.

[0059] It is easy to understand that Example 1 ensures that the most recent learning results take precedence, which is consistent with the biological rationale of STDP (synaptic weights should be more influenced by recent impulse activity), while avoiding the problem of old updates overwriting new updates due to communication delays.

[0060] Example 2: Hierarchical arbitration (priority scheme) based on the priority of the core part where the posterior membrane neuron is located.

[0061] The weight variable Δw of the computational core containing the posterior membrane neuron takes precedence. This embodiment concretizes this into a hardware-executable priority encoding rule.

[0062] Rule definition:

[0063] Each synapse is defined by an anterior membrane neuron (located in computational core A) and a posterior membrane neuron (located in computational core B). When computational core A and computational core B independently detect the STDP event and generate a weighted variable Δw, the weighted variable Δw generated by the computational core where the posterior membrane neuron is located (i.e., the core that receives the pulse) has the highest priority, and the weighted variable Δw generated by the computational core where the anterior membrane neuron is located has the second highest priority.

[0064] If two weight variables Δw come from the same computational core (e.g., pre- and post-membrane neurons are in the same computational core), they are directly merged locally without cross-core conflicts.

[0065] Arbitrator implementation:

[0066] The conflict arbitrator internally uses a priority mapping table: for each synapse identifier, it records the ID of its post-membrane attribution calculation core. When multiple weight variables Δw are received, the post-membrane attribution calculation core for that synapse is searched, and the weight variable Δw from that calculation core is selected as the arbitration result; the rest are discarded. The priority table in this embodiment can be enumerated upon power-on or statically configured by the compiler.

[0067] It is easy to understand that, through the priority rule in Example 2, the change in synaptic weights in STDP mainly depends on the post-synaptic spike of the postmembrane neuron, thus the weight variable Δw observed on the postmembrane side is more accurate. Hardware-wise, it can be implemented using only a lookup table, requiring minimal additional hardware resources.

[0068] Example 3: Adaptive Dynamic Prioritization Based on Learning Activity Popularity

[0069] Some synapses in some embodiments of this application may learn events sparsely on the posterior endoplasmic reticulum side and very frequently on the anterior endoplasmic reticulum side, so a fixed priority may result in effective updates being ignored for a long time.

[0070] rule:

[0071] Each computational core sends a learning heat value (i.e., the number of STDP events that occur at that synapse during the current cycle) along with the weight variable Δw.

[0072] The conflict arbiter between the central router and the interface core selects the weight variable Δw of the calculation core with the highest "hotness" value as the valid update for multiple weight variables Δw of the same synapse. If the "hotness" values ​​are the same, the timestamps are compared.

[0073] The popularity value is implicitly counted by the local shadow register (the popularity counter is incremented by 1 for each weight variable Δw generated, and cleared to zero after being packaged and sent).

[0074] It is easy to understand that Embodiment 3 can automatically adapt to the distribution of learning activities on each computing chip, preventing updates of active computing chips from being overwritten by outdated updates of inactive computing chips. In these embodiments, the hardware adds a heat comparator, requiring fewer hardware resources. Embodiment 3 is suitable for asymmetric neural network mappings (e.g., some chips undertake more online learning tasks).

[0075] Example 4: Hybrid Arbitration Strategy (Timestamp, Priority, and Weight Variation)

[0076] The conflict arbitrator employs a three-level comparison:

[0077] First, compare the absolute values ​​of the weight variables Δw: select the Δw with the largest change in weight (indicating that the learning event occurring in that core is more significant).

[0078] If the magnitudes are the same, then compare the timestamps (newer timestamps take precedence).

[0079] If they are still the same, compare the preset core particle priority (prioritize the back membrane side or the one with the higher learning heat value).

[0080] It is easy to understand that by incorporating the strength of the learning signal into the arbitration criterion in Example 4, the learning results that have the greatest impact on network behavior take precedence, which may accelerate convergence. This strategy requires adding an amplitude field to the Δw message (Δw itself implicitly contains the amplitude), and only an absolute value comparator is needed in hardware.

[0081] The broadcast controller 112-3 is used to send the updated version number and the target global weight value to the relevant computing core via multicast or broadcast.

[0082] In some embodiments of this application, the central routing and interface chip is connected to any computing chip via an inter-chip interface circuit (not shown in the figure), which includes:

[0083] A source synchronous clock transmitter (not shown in the figure) is located in the transmitting chip and is used to output the local clock along with the data to be transmitted.

[0084] A dual-edge sampling receiver (not shown in the figure) is located in the receiving chip and is used to sample data according to the rising and falling edges of the received clock.

[0085] The credit flow control logic includes a credit counter set in the transmitting chip and a credit return signal generator set in the receiving chip. The credit counter is used to record the number of currently available credits and to pause data transmission in the transmitting chip when the credits are exhausted. The credit return signal generator is used to generate a credit return signal and send it back to the transmitting chip when the receiving chip successfully receives a data slice and the receive buffer is not full, so as to increase the credit value of the corresponding credit counter.

[0086] A retransmission buffer is set in the transmitting chip, wherein the depth of the retransmission buffer is a preset fixed length.

[0087] It should be noted that in some embodiments of this application, the transmitting chip can be a computing chip or a central routing and interface chip, depending on the direction of data transmission; the receiving chip is similar. It is understood that the transmitting and receiving chips are determined for a specific communication process.

[0088] The following is combined Figure 3 This application provides an exemplary illustration of a lightweight asynchronous transmission protocol used by the inter-chip interface circuits provided in some embodiments to solve the problem of inter-chip delay.

[0089] Figure 3 In this architecture, the transmitting chip outputs the data signal D[0:31] and the accompanying clock CLK_src (i.e., the source synchronization clock). The receiving chip directly samples using the source synchronization clock transmitted by the transmitting chip, without needing to go through a phase-locked loop (PLL). It also uses a two-wire handshake mechanism of Ready / Acknowledge (RDY / ACK) and employs credit counting for flow control. The retransmission window contains only 4 data slices.

[0090] The lightweight asynchronous transport protocol provided in this application includes the following features:

[0091] Source Synchronous Clock: The transmitting chip sends its local clock along with the data to be transmitted, and the receiving chip directly uses this clock for sampling, avoiding the global clock tree being distributed across chips.

[0092] Dual-edge sampling: Data is transmitted on both the rising and falling edges of the clock. The data rate = clock frequency × 2, doubling the bandwidth for the same number of lines. Similarly, dual sampling is performed on both the rising and falling edges at the receiving end chip.

[0093] Micro-retransmission mechanism: Only erroneous data packets are retransmitted. The retransmission window is fixed at 4 flits. The link layer retransmission window is not enabled.

[0094] Credit flow control: A fixed number of credits is maintained in each direction (e.g., 8 credits). Transmission is paused when credits are exhausted. The control logic is implemented using pure combinational circuitry. It should be noted that pure combinational circuitry is used to implement the above credit flow control logic (not shown in the figure). In some embodiments of this application, the strategy for implementing credit flow control includes: a credit counter, set in the transmitting chip, used to record the currently available number of credits and pause data transmission when credits are exhausted; and a credit return signal generator, set in the receiving chip, used to generate a credit return signal and send it back to the corresponding transmitting chip when the receiving end successfully receives a data slice and the receive buffer is not full, thereby increasing the credit value of the corresponding credit counter.

[0095] For example, in some embodiments of this application, the credit return signal generator includes: a subtractor, with its minuend input connected to the write pointer signal line output by the write address counter, its subtrahend input connected to the read pointer signal line output by the read address counter, and its output connected to the first input of a numerical comparator, the subtractor being used to calculate the number of currently occupied positions in the receive buffer; and a numerical comparator, with its first input connected to the output of the subtractor, its second input connected to a fixed-value hardwired line, and its output used to generate an incomplete signal, specifically, when the occupied number is less than the total depth, the numerical comparator... The not-full signal is high, otherwise it is low. This numerical comparator is used to determine whether the receive buffer is full. The fixed value is equal to the total depth of the receive buffer. The AND gate has its first input connected to the receive valid flag signal line output by the dual-edge sampling register, its second input connected to the output of the comparator, and its output connected to the credit return signal line. This AND gate is used to perform a logical AND operation between the data receive valid signal and the buffer not-full signal and output a credit return signal. The credit return signal line is connected to the output acknowledgment pin of the corresponding receiver chip and is sent to the corresponding transmitter chip through the inter-chip link.

[0096] For example, in some embodiments of this application, a write address counter outputs a write pointer signal connected to the minuend input of a subtractor; the write address counter increments when the dual-edge sampling register group outputs a valid receive flag and the data slice FIFO is not full. A read address counter outputs a read pointer signal connected to the subtrahend input of a subtractor; the read address counter increments when the data slice is read by the local processing core. A subtractor calculates the difference between the write pointer and the read pointer to obtain the number of currently occupied positions in the data slice FIFO. A numerical comparator compares the output of the subtractor with a fixed value (equal to the total depth of the data slice FIFO), outputting a "not full" signal when the occupied number is less than the total depth. An AND gate performs a logical AND operation between the "valid receive flag" output by the dual-edge sampling register group and the "not full" signal, outputting a credit return signal. The credit return signal is sent to the credit counter of the transmitting chip via a dedicated acknowledgment line in the inter-chip physical link.

[0097] Unlike related technologies, it adopts Figure 3 Compared to the standard UCIe protocol, this data transmission protocol can reduce the fixed overhead per packet and decrease the minimum one-way latency while improving the bandwidth utilization of small packets.

[0098] In some embodiments of this application, each of the computing kernels further includes: a local sovereign recalculation table; a shadow register for temporarily storing the weight changes generated by the local execution of STDP rules; and a control circuit coupled to the local sovereign recalculation table and the shadow register, wherein the control circuit is configured to: periodically or when the number of accumulated learning events in the corresponding computing kernel reaches a preset threshold, send the weight changes in the shadow register to the central routing and interface kernel through the inter-chip interface circuit; and update the local sovereign recalculation table and clear the shadow register after receiving a global weight update from the central routing and interface kernel.

[0099] For example, in some embodiments of this application, the local sovereign recalculation table is used to store currently valid synaptic weight values ​​that have been agreed upon globally. Specifically, the local sovereign recalculation table of each computational core records the identifiers of the synapses that the core is responsible for (such as source neuron ID and target neuron ID) and their corresponding latest weight values ​​(typically with 4-8 bit precision). These weight values ​​are updated after conflict arbitration between the central routing and interface cores and global broadcasting, and are the version commonly recognized by all relevant computational cores, used for weight lookup in SNN / ANN inference and STDP learning. The shadow register temporarily stores locally generated weight changes (Δw) that have not yet been globally confirmed, while the sovereign recalculation table stores confirmed stable weights.

[0100] The following is combined with Figure 2Taking two computing cores as an example, this application illustrates the loosely synchronized incremental weight update and cross-core consistency mechanism (solving the distributed learning consistency problem) provided in some embodiments.

[0101] Figure 2 This demonstrates the process by which computational core 121-7 (containing anterior membrane neurons) and computational core 121-8 (containing posterior membrane neurons) exchange weight increments via a central routing and interface core. The central routing and interface core maintains a global weight version table and performs conflict arbitration and broadcasting. The i-th computational core includes anterior cluster neurons 121-1, a first shadow register 121-2, and a first sovereign re-table 121-3; the j-th computational core includes posterior cluster neurons 121-4, a second shadow register 121-5, and a second sovereign re-table 121-6.

[0102] Figure 2 Weight variable synchronization methods include:

[0103] The i-th computational core performs local STDP learning, generating a weight variable Δw which is stored in the first shadow register. Periodically (or triggered every N learning events), the weight variable Δw stored in the first shadow register is packaged and sent to the central router and interface core. The central router and interface core performs conflict arbitration and version management to obtain the weight variable to be synchronized (i.e., the target global weight value). Through broadcast update, the weight variable to be synchronized is synchronized to the second sovereign weight table and the data stored in the first shadow register is cleared.

[0104] In other words, in some embodiments of this application, each computational core independently executes local STDP rules, and the generated weight change Δw (e.g., 4-8 bits) is temporarily stored in a local shadow register without directly modifying the sovereign weight table; periodic exchange or exchange every N learning events (N is configurable, typically 64) occurs, and the computational core packages all weight variables Δw generated in the current period into a weight update message and sends it to the central routing and interface core; central arbitration and version management are implemented, and the weight version management unit of the central routing and interface core maintains a mapping table (synaptic identifier, latest version number, and mapping relationship to the current valid weight value). When a weight variable Δw is received from a different computational core, conflict resolution is performed based on the timestamp or a preset priority (e.g., Δw of the core containing the posterior membrane neuron has priority), and the resolved target global weight value is assigned a new version number and multicast to all relevant computational cores; core synchronization occurs, each computational core receives the broadcast, updates its local sovereign weight table, and clears the shadow register.

[0105] The weight variable data synchronization strategy adopted in this application can achieve weight convergence accuracy comparable to that of a single-chip solution. The cross-core learning communication overhead accounts for a low proportion of the total D2D bandwidth, and the system scale can be linearly expanded to more than 64 computing cores.

[0106] like Figure 3 As shown in the figure, the following content is illustrated:

[0107] In the embodiments of this application, a source-synchronized clock refers to a clock where the sending end sends its own local clock along with the data to the receiving end, rather than relying on a system-wide global clock. Figure 3 In this configuration, the source synchronization clock signal is a separate line that is transmitted from the transmitter to the receiver along with the data. The receiver directly uses this clock to sample the data, avoiding the power consumption and timing convergence problems caused by long-distance global clock distribution. Typically, the frequency of the source synchronization clock is configurable, such as 1.25 GHz, and dual-edge sampling (sampling once on the rising edge and once on the falling edge) can be used to improve bandwidth.

[0108] Credit counting is a flow control mechanism used to prevent receiver buffer overflow. The transmitter maintains a credit counter, initially equal to the number of available buffer units at the receiver (e.g., if the receiver has 8 chip buffers, the initial credit count is 8). The credit counter is decremented by 1 for each chip transmitted. When the credit count reaches 0, the transmitter must stop transmitting and wait for the receiver to increment the credit count by returning a credit update (e.g., sending a credit increment signal). Figure 3 In this code, decrementing by 1 for each sent flit explicitly indicates this operation. Compared to a simple ready / acknowledgment handshake, the credit mechanism can reduce the acknowledgment overhead per packet and improve link utilization.

[0109] The data bus width is 32 bits, meaning that 32 bits (4 bytes) of data are transmitted each time. Figure 3 The labels “Data (D[0:31])” and the “D0 D1 D2 D3” below indicate four data units transmitted consecutively. One data item is driven on each edge (or cycle) of the source synchronous clock. If dual-edge sampling is used, two 32-bit data items can be transmitted in one clock cycle. These data are typically part of a flit, or multiple flits are transmitted consecutively.

[0110] Ready (RDY) and Acknowledge (ACK) are two-wire handshake signals. RDY is driven by the receiver, indicating that the receiver is ready to receive new data; ACK is driven by the receiver, indicating that a data item has been successfully received. In the four-way handshake protocol, after the transmitter waits for RDY to be valid, it puts the data on the bus and pulls the write enable (or valid flag) high. The receiver samples the data and pulls ACK high, and then both sides reset the signals. Figure 3The RDY / ACK handshake is associated with "time (t)," characterizing how these signals change over time. This handshake method can operate across clock domains without requiring a global clock. In high-speed links, it can be used in conjunction with credit-based flow control: credits are used for long-term flow control, and RDY / ACK is used for acknowledgment of each chip.

[0111] Figure 3 Below the voltage indicator are four waveform markers "D0 D1 D2 D3", representing the voltage change on the data line over time, transmitting four data units sequentially. The time (t) axis also indicates the timing relationship of the signals. The waveforms of the source synchronization clock, data, and RDY / ACK are time-aligned. For example, at the edge of the source synchronization clock, the data must be stable; the RDY and ACK signals should maintain appropriate levels during the data validity period.

[0112] The following is based on Figure 3 The inter-chip transmission process of source synchronization clock, credit flow control, and RDY / ACK handshake:

[0113] Step 1: During system initialization, the sender and receiver negotiate the initial credit value (e.g., the receiver has 8 micro-chip buffers, so credit = 8). The sender's credit counter is set to 8.

[0114] Step 2: When the sending end has data to send, it checks the credit counter. If it is greater than 0, it prepares to send.

[0115] Step 3: The transmitting end checks the RDY signal of the receiving end. If RDY is valid, the transmitting end drives the first data (D0) onto the 32-bit data bus and simultaneously drives the source synchronization clock.

[0116] Step 4: The receiving end samples the data at the edge of the source synchronization clock and checks the validity of the data. If the reception is successful, the receiving end pulls the ACK signal high for one clock cycle.

[0117] Step 5: After receiving the ACK, the sender decrements the credit counter by 1 (corresponding to "decrement by 1 for each flit sent" in the diagram), and then prepares to send the next data (D1).

[0118] Repeat steps 3 to 5, sending D2 and D3 in sequence.

[0119] When the credit counter reaches 0, the sender stops sending until the receiver returns a credit increment signal (e.g., after processing the data in the buffer, the receiver sends a credit update through a dedicated channel). Credit updates can be performed in batches, for example, returning a credit +4 message after processing every 4 micro-pieces.

[0120] Figure 3The time (t) axis displayed in the middle shows that D0, D1, D2, and D3 appear sequentially on the data bus. Each data item corresponds to one source synchronization clock cycle (or half a cycle). The RDY and ACK signals are pulled high or low at appropriate time points.

[0121] Figure 3 This combined mechanism enables low-latency, high-reliability data transmission between cores, avoids global clocks, and reduces handshake overhead through credit flow control. It is suitable for pulse event communication between the central routing core and the computing core in a neuromorphic processor.

[0122] The following describes the data processing method performed by the neuromorphic processor system provided in the embodiments of this application.

[0123] like Figure 4 As shown, some embodiments of this application provide a data processing method that runs on the aforementioned neuromorphic processor system. The data processing method includes:

[0124] The first step is the system initialization phase.

[0125] S110: System power-on

[0126] The entire package is powered on, and all cores (central routing and interface cores and individual computing cores) begin to reset and enter the working state.

[0127] S111: Central routing and interface core discovery and enumeration of all compute cores

[0128] The central routing and interface cores communicate via inter-chip interfaces (lightweight asynchronous protocol links, and...) Figure 3 The data transmission process shown corresponds to a transmission protocol that sends an enumeration command to each possible port to be connected.

[0129] Each computing core responds to its own identifier (ID), address range (e.g., the ID range of the neurons it is responsible for), and capability information (e.g., the number of processing cores and storage size).

[0130] S112: Constructing the global topology graph (core address space)

[0131] Based on the received responses, the central routing core and interface particles establish a global topology mapping table to determine the correspondence between the address range and the corresponding port of each computing core particle. This topology map is used for subsequent static route configuration and task mapping.

[0132] S113: Compiler toolchain performs topology-aware task mapping

[0133] An external compilation toolchain (which supports topology awareness) reads the above physical topology information.

[0134] The neural network model (SNN / ANN) of the user is divided into groups of neurons and synaptic connections, so that neurons that communicate frequently with each other are mapped to the same computational core as much as possible (for example, in some embodiments of this application, this strategy includes: representing the neural network model as a graph, with neurons as nodes and synaptic connections as edges, using a multi-level partitioning algorithm (such as Metis) to divide the graph into subgraphs with an equal number of cores, so as to minimize the sum of the weights of the cutting edges; then assigning each subgraph to a computational core and generating an address mapping), thereby minimizing cross-core communication.

[0135] Generate the local configuration (routing table, initial values ​​of the local sovereignty table) for each compute core, as well as the cross-core routing tables for the central routing and interface cores.

[0136] After initialization, the system enters the runtime phase, where the inference data stream and the learning stream are executed in parallel.

[0137] The second step is data flow (inference) and learning flow (STDP).

[0138] For the data flow (inference) path: the processing core performs inference based on the task mapping and generates event data packets (AER format).

[0139] S114: Processing core-generated AER data packets

[0140] When a neuron generates a pulse (event), the processing core generates an AER data packet, which contains information such as the source address, the destination address (the ID of the target neuron), and the event type.

[0141] S117: Determine if the target address is within this computing core.

[0142] The control logic inside the computing core checks whether the destination address of the data packet belongs to the address range that the current computing core is responsible for.

[0143] Branch 1: Target address within this computing core

[0144] S118: Processed directly by the local communication network

[0145] Data packets are directly sent to the local on-chip network of this computing chip (corresponding to L1~L4 layer routers).

[0146] The local network forwards data packets to the target processing core based on the address, completing the event transmission. The entire process does not leave the current computing core, resulting in extremely low latency.

[0147] Branch 2: The target address is not within this computational core (cross-core).

[0148] S119 is sent to the central routing and interface core via a lightweight protocol.

[0149] Figure 3 The data packet is sent to the central routing chip using the Lightweight Asynchronous Transfer Protocol (LATP) shown. The data packet is then sent to the inter-chip interface circuitry of the computing chip, encapsulated according to the LTP protocol (source synchronous clock, dual-edge sampling, credit flow control, and micro-retransmission), and sent to the central routing and interface chip.

[0150] S120, Central Router and Interface Core Query Global Routing Table

[0151] The global routing engine of the central routing core extracts the destination address from the data packet.

[0152] Look up the cross-core routing table (which stores the mapping between address ranges and output ports) to determine the port number of the target computing core where the target neuron is located.

[0153] S121, forward to target computing chip

[0154] The central routing and interface chip will re-use the data packets through the corresponding inter-chip interface port. Figure 3 The lightweight asynchronous transport protocol shown is sent to the target computing chip.

[0155] S123, continues to be processed by the local communication network of the target core.

[0156] After receiving the data packet, the target computing chip sends it to its local on-chip network and finally delivers it to the target processing core.

[0157] The data flow path ends here.

[0158] For the learning flow (STDP) path: each computational core performs online learning independently, and weight updates adopt a loose synchronization mechanism of local accumulation, centralized arbitration, and global broadcast.

[0159] S115, each core independently performs local STDP learning.

[0160] Each processing core within the computational core continuously monitors the time difference between presynaptic and postsynaptic pulse events.

[0161] The weight variable Δw (which can be positive or negative, and is usually 4 to 8 digits precise) is calculated based on the STDP rule function.

[0162] S116, the local weight variable Δw is stored in the shadow register and the count is accumulated.

[0163] The calculated weight variable Δw does not directly modify the local sovereign table, but is temporarily stored in the corresponding shadow register.

[0164] Meanwhile, a learning event counter is maintained inside the computation core to record the total number of STDP events (or the number of events per synapse) that occur within the computation core, which can be simplified to cumulative counting.

[0165] S124, Determine whether the count has reached the preset threshold N (e.g., N=64).

[0166] The control logic checks whether the cumulative count of learning events has reached a threshold (e.g., 64 events).

[0167] If the threshold is not reached, the accumulation continues (i.e., the continued accumulation process of S128 is executed, waiting for more learning events).

[0168] If the threshold is reached, proceed to the packaging and sending step.

[0169] S125 encapsulates the weight change into an update message, that is, packages the weight variable Δw into an update message.

[0170] The control logic packages all non-zero weight variables Δw in the shadow register together with their corresponding synapse identifiers (SynapseID) into a weight update message.

[0171] S126, the update message is sent to the central routing and interface core, which then makes an arbitration decision and broadcasts it.

[0172] It is sent to the central routing and interface chip via the inter-chip interface circuit (lightweight asynchronous transmission protocol).

[0173] After sending, the shadow register can be left unresolved, marked as pending confirmation, and then cleared after a broadcast update.

[0174] The central routing core performs conflict arbitration and version management. The weight version management unit of the central routing and interface cores receives weight update messages from multiple computing cores.

[0175] Conflict arbitration: For multiple weighted variables Δw of the same synaptic identifier (which may come from different computational cores), the arbitrator selects one of them as the valid increment according to preset rules (such as timestamps and preset priorities).

[0176] Version management: The selected weight variable Δw is superimposed on the current valid weight value stored in the global weight version mapping table to obtain a new global weight value, and a new version number (monotonically increasing) is assigned.

[0177] This step resolves the multi-replica weight conflict issue caused by computational granulation.

[0178] Multicast global weight update: The broadcast engine sends the new global weight value and version number to all relevant computational cores (at least those cores containing the presynaptic / postsynaptic membrane neurons) via multicast or broadcast.

[0179] S127, each computing chip updates its sovereignty table and clears the shadow register.

[0180] After each relevant computing chip receives the broadcast:

[0181] The corresponding synapse entry is found in the local sovereignty table, and the weight value is updated to the new value in the broadcast.

[0182] Clearing the shadow register corresponding to the synapse to zero (or marking it as confirmed) indicates that Δw has been globally adopted.

[0183] After that, we will continue with the next round of local learning and accumulation.

[0184] It should be noted that the data flow (inference) in this embodiment is an event-driven real-time path, prioritizing low latency; the learning flow is a background path triggered by periodic / event counting, prioritizing weight consistency. In this embodiment, both achieve parallel operation through the separation of the shadow register and the sovereign weight table: inference always reads the confirmed master weight table, while learning only modifies the shadow register, without blocking each other. The central routing and interface core is responsible for both packet routing and forwarding, as well as arbitration and synchronization of learning increments, serving as the hub of system integration.

[0185] In other words, some embodiments of this application provide a data processing method running on the neuromorphic processor system described in the first aspect. The data processing method includes: an i-th computational core independently executes local STDP rules and stores the generated weight changes in a local shadow register (without immediately modifying the local sovereign recalculation table); if a weight update triggering condition is met (e.g., the number of learning events reaches a preset threshold), a weight update message is generated and sent to the central routing and interface core; in response to receiving weight update messages from multiple computational cores including the i-th computational core, the central routing and interface core performs conflict resolution on weight changes for the same synapse based on preset rules to determine a target global weight value; the central routing and interface core broadcasts the target global weight value to the multiple computational cores so that the multiple computational cores update their respective local sovereign recalculation tables and clear their shadow registers.

[0186] In some embodiments of this application, the data processing method further includes: the transmitting chip sending a local clock and the data to be transmitted together to the receiving chip via an inter-chip link, wherein the receiving chip is the central routing and interface chip or another computing chip; the receiving chip using the local clock to perform dual-edge sampling on the data to be transmitted.

[0187] In some embodiments, the data processing method further includes: the receiving end chip manages data transmission through a flow control mechanism based on credit counting; if an error occurs when receiving the data to be sent, the corresponding sending end chip only retransmits the data packets to be sent within a preset fixed window.

[0188] The following example illustrates a specific neuromorphic processor system and its working process.

[0189] Some embodiments of this application determine the number of computing cores based on the target application as 8, with each core containing 128 processing cores. The total number of cores to be managed by the central routing and interface core, and the external interfaces, include: 1 HBM2e interface and 1 PCIe Gen4 interface. Computing core design: 128 processing cores, local SRAM (2MB), and corresponding L1~L4 subnet routers are integrated into a single core, using a 12nm process with an area of ​​4.2mm × 4.2mm. A lightweight D2D interface module is integrated (supporting source-synchronized clock, credit flow control, and micro-retransmission). Central routing and interface core design: A global routing table (supporting up to 64 computing cores), a multi-port switching structure (8 D2D ports + 2 off-chip ports), and an integrated weighted version management unit (including CAM + SRAM, supporting 8192 parallel entries) are designed. Interconnection and packaging design: A silicon interposer is designed, and an ultra-high density redistribution layer with a linewidth / spacing ≤2μm is deployed to connect the D2D interfaces of each chip. Chips are fixed to the silicon interposer via micro-bump flip-chip bonding. The overall structure is led out to the system PCB through a packaging substrate and a ball grid array (BGA). TSMC CoWoS-S packaging technology is used. The startup and operation of the corresponding neuromorphic processor system includes: power-on discovery; the central routing and interface chip enumerates all computing chips through D2D links to construct a global topology map; task mapping; the upgraded compiler toolchain (topology-aware) reads the physical topology, mapping frequently communicating neuron groups to the same computing chip as much as possible to minimize cross-chip communication; runtime data flow; if the destination address of AER packets generated by the processing core is within the local computing chip, it is processed directly by the local network; if cross-chip communication is required, it is handled through the D2D interface. Figure 3The lightweight asynchronous data protocol is sent to the central router and interface core, which forwards it by looking up a table; during runtime, the learning stream is learned, each computing core independently accumulates Δw, and a report is triggered every 64 learning events; after the central router and interface core resolve the conflict, it broadcasts an update.

[0190] It should be noted that, in the embodiments of this application, the global topology refers to the information set constructed by the central routing and interface core during the power-on enumeration phase, which describes the physical layout, address space allocation, and interconnection relationships of all computing cores in the entire core-based neuromorphic processor system. Specifically, the global topology includes: core identifier, a unique identification number (ID) for each computing core; address range, the range of neuron IDs (or more broadly, the address space) that each computing core is responsible for; physical port mapping, which D2D port (i.e., input / output port number) of the central routing core to which each computing core is connected; interconnection relationships, the connection relationships between the central routing and interface core and each computing core, and the connections between different central routing and interface cores if multiple central routing and interface cores exist. The global topology graph is stored in the central routing and interface core, used to initialize the cross-core routing table, and to provide the topology-aware task mapping basis for the compilation toolchain (mapping frequently communicating neuron groups within the same computing core as much as possible). The global topology is a static configuration view of the system hardware resources and is the basis for all subsequent cross-core communication routing and task partitioning.

[0191] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0192] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0193] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0194] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0195] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0196] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A neuromorphic processor system, characterized in that, The neuromorphic processor system includes: At least one central routing and interface core; and Multiple computing chips; The central routing and interface core and the multiple computing cores are integrated into the same package. Each computing core includes: Multiple processing cores, each configured to support spiking neural network (SNN) inference, artificial neural network (ANN) inference, and / or spiking time-dependent plasticity (STDP) online learning tasks; and a local communication network for enabling communication between different processing cores within the respective computing kernels. The central routing and interface core includes: A global routing engine is used to implement packet forwarding across computing kernels; and / or a weight version management unit is used to arbitrate conflicts and broadcast global weights for weight changes from different computing kernels in order to maintain weight consistency in STDP learning across kernels. The central routing and interface chip is connected to any computing chip via an inter-chip interface circuit. The inter-chip interface circuit includes: The source synchronous clock transmitter, located in the transmitting chip, is used to output the local clock along with the data to be transmitted. A dual-edge sampling receiver, located in the receiving chip, is used to sample data based on the rising and falling edges of the received clock. A credit counter, set in the transmitting chip, is used to record the current amount of available credit and to pause data transmission when the credit is exhausted. A credit return signal generator is set in the receiving chip. It is used to generate a credit return signal and send it back to the corresponding transmitting chip when the receiving chip successfully receives a data slice and the receiving buffer is not full, so as to increase the credit value of the corresponding credit counter. A retransmission buffer is set in the transmitting end chip, wherein the depth of the retransmission buffer is a preset fixed length; The weighted version management unit includes: A global weight version mapping table is used to store the correspondence between synapse identifiers, version numbers, and currently valid weight values; A conflict arbitrator is used to determine a target global weight value according to preset rules and assign an update version number to the target global weight value when it receives weight changes from different computing cores for the same synapse. A broadcast controller is used to send the updated version number and the target global weight value to the relevant computing cores via multicast or broadcast.

2. The neuromorphic processor system according to claim 1, characterized in that, Each computing chip also includes: Local sovereignty is redefined; The shadow register is used to temporarily store the weight changes generated by the local execution of STDP rules; The control circuit, coupled to the local sovereign recalculation table and the shadow register respectively, is configured as follows: Periodically, or when the number of accumulated learning events in the corresponding computing chip reaches a preset threshold, the weight change in the shadow register is sent to the central routing and interface chip through the inter-chip interface circuit. Upon receiving a global weight update instruction from the central routing and interface core, the local sovereignty table is updated and the shadow register is cleared.

3. The neuromorphic processor system according to claim 1, characterized in that, The central routing and interface chip and the multiple computing chips are integrated into the same package via 2.5D silicon interposer packaging or 3D stacked packaging.

4. The neuromorphic processor system according to claim 1, characterized in that, Each computing core also includes: Local SRAM is used to store local data required by the processing core within the corresponding computing chip.

5. The neuromorphic processor system as described in any one of claims 1-4, characterized in that, The local communication network corresponds to the L1 to L4 layer routers of the fat quadtree network, and the global routing engine corresponds to the L5 layer of the fat quadtree network.

6. The neuromorphic processor system as described in claim 5, characterized in that, The global routing engine also includes: A cross-core routing table is used to store the mapping relationship between destination address ranges and output port numbers; The global routing engine is configured to look up the cross-core routing table based on the target address in the received data packet, determine the output port connected to the target computing core, and forward the data packet to the corresponding output port.

7. The neuromorphic processor system as described in claim 1, characterized in that, The credit return signal generator includes: The subtractor has its minuend input connected to the write pointer signal line output by the write address counter and its subtrahend input connected to the read pointer signal line output by the read address counter. It is used to calculate the number of positions currently occupied in the receive buffer. The numerical comparator has a first input connected to the output of the subtractor, a second input connected to a fixed-value hardwire, and an output used to generate a not-full signal; wherein the fixed value is equal to the total depth of the receive buffer. The AND gate has its first input connected to the receive valid flag signal line output by the dual-edge sampling register, its second input connected to the output of the comparator, and its output connected to the credit return signal line, wherein the credit return signal line is connected to the output acknowledgment pin of the corresponding receiver chip.

8. A data processing method, operating on a neuromorphic processor system as described in any one of claims 1-7, the data processing method comprising: The i-th computational core independently executes the local STDP rule and stores the generated weight change in the local shadow register, where i is an integer greater than or equal to 1; If the weight update triggering condition is confirmed to be met, a weight update message is generated and sent to the central routing and interface core. The central routing and interface core responds to receiving weight update messages from multiple computing cores, including the i-th computing core, and resolves conflicts of weight changes for the same synapse based on preset rules to determine the target global weight value. The central routing and interface core broadcasts the target global weight value to the multiple computing cores, so that the multiple computing cores update their respective local sovereignty tables and clear shadow registers.

9. The data processing method as described in claim 8, characterized in that, The data processing method further includes: The transmitting chip sends its local clock and the data to be transmitted together to the receiving chip via the inter-chip link, wherein the receiving chip is the central routing and interface chip or another computing chip; The receiving chip uses the local clock to perform dual-edge sampling of the data to be transmitted.

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