A brain-like chip adopting a protein network architecture and a navigation path planning method

Abstract

The application provides a brain-like chip adopting a protein network architecture and a navigation path planning method, the brain-like chip comprising: a PFN neuron calculation array based on a protein folding energy landscape, a Complex-STDP synapse weight storage based on a protein complex mechanism, a hub processing unit, a SignalCascade routing network based on signal transduction inspiration, and a configuration controller supporting dynamic reconstruction. The application draws on the topological characteristics and dynamic mechanism of a protein interaction network, constructs a brain-like chip with higher biological rationality and calculation efficiency, and realizes a robust and efficient robot autonomous navigation system based on the same.

Description

Technical Field

[0002] This invention relates to the technical field of semiconductor memory integration, and more specifically to a neuromorphic chip employing a protein network architecture and a navigation path planning method. Background Technology

[0004] With the rapid development of artificial intelligence technology, traditional computers based on the von Neumann architecture face bottlenecks such as the "memory wall" and "power wall" when processing complex cognitive tasks. Brain-inspired computing, as a computing paradigm that mimics the structure and function of the biological brain, has become an important research direction in the field of artificial intelligence chips due to its advantages in energy efficiency, parallel processing capabilities, and fault tolerance.

[0005] Existing neuromorphic chips mainly adopt the following technical routes: (1) neuromorphic chips based on spiking neural networks (SNN), such as IBM's TrueNorth and Intel's Loihi; (2) in-memory computing chips based on memristors; and (3) digital neuromorphic processors based on traditional CMOS technology. However, these technical routes have limitations in the following aspects:

[0006] The neuron model is too simplified: Most existing SNNs use the simplified Leaky Integrate-and-Fire (LIF) model, which cannot fully simulate the complex dynamic characteristics of biological neurons, resulting in limited information encoding efficiency and computational accuracy.

[0007] Fixed network topology: Traditional neural networks adopt a regular layered connection structure, which lacks the complex topological characteristics such as modularity, small world and scale-free that are common in biological neural networks, making it difficult to achieve efficient distributed information processing.

[0008] The learning mechanism is singular: most existing neuromorphic chips adopt local learning rules based on pulse time-dependent plasticity (STDP), which lacks global optimization capabilities and makes it difficult to complete complex reinforcement learning tasks.

[0009] Therefore, current neuromorphic chips suffer from problems such as overly simplified neuron models, fixed network topologies, and a single learning mechanism.

[0010] Furthermore, current autonomous navigation of robots requires the robots to acquire environmental information solely through their own sensors in unknown or dynamic environments, and to autonomously complete localization, mapping, and path planning. Therefore, the neuromorphic chips used still have the following shortcomings: (1) high computational complexity, making it difficult to run in real time on resource-constrained embedded platforms; (2) lack of rapid adaptability to dynamic environments; (3) low efficiency of multi-sensor information fusion; and (4) insufficient robustness of decision-making in complex scenarios.

[0011] In summary, there is a need for a dedicated chip that can simulate the efficient information processing mechanism of biology. Summary of the Invention

[0013] To address the problems existing in the prior art, this invention provides a neuromorphic chip and navigation path planning method using a protein network architecture, in order to solve the technical problem of the lack of a dedicated chip capable of simulating the efficient information processing mechanism of biology.

[0014] This invention provides a neuromorphic chip employing a protein network architecture. The neuromorphic chip includes a neuronal computing array, a synaptic weight memory, a hub processing unit, a signal transduction module, and a configuration controller. The neuronal computing array includes at least two PFN neuronal processing units based on protein folding energy landscapes. The signal output terminal of the neuronal computing array is connected to the signal input terminal of the synaptic weight memory through the signal transduction module. The signal output terminal of the synaptic weight memory is connected to the signal input terminal of the hub processing unit through the signal transduction module. The signal output terminal of the hub processing unit is connected to the signal input terminal of the configuration controller through the signal transduction module.

[0015] Optionally, the PFN neuron processing unit employs a mixed-signal design and includes at least:

[0016] An integrator circuit for simulating the membrane potential accumulation process, a comparator array for detecting whether the membrane potential has reached the threshold of each metastable state, a state machine for determining the state transition based on the threshold comparison result and the input signal, and a pulse generator for generating output pulses during the state transition are provided. The integrator circuit is electrically connected in sequence to the comparator array, the state machine, and the pulse generator.

[0017] Optionally, the synaptic weight memory adopts a 1T1R structure, which consists of a transistor and a memristor, wherein the conductance value of the memristor is used to represent the synaptic weight and supports continuous storage and in-situ updates of the analog value.

[0018] Optionally, the signal transduction module adopts the SignalCascade communication protocol, which uses cascaded pulse coding to propagate information in the form of pulse sequences. Each time the signal passes through a processing node, it is amplified or modulated.

[0019] Optionally, the SignalCascade communication protocol also employs a multi-channel cross-dialogue mechanism, which enables information exchange between different functional modules by sharing signal molecules, supporting multi-task collaborative processing and multi-modal information fusion.

[0020] Optionally, the neuromorphic chip further includes a spatial coding module, which is connected to the PFN neuron processing unit. The spatial coding module draws on the coding mechanisms of hippocampal position cells and entorhinal cortex grid cells in rodents to construct a spatial recognition map based on the PFN neuron processing unit.

[0021] Optionally, the neuromorphic chip further includes an action selection module, which is connected to the PFN neuron processing unit. The action selection module draws on the direct-indirect pathway model of the basal ganglia to construct an action selection network.

[0022] Optionally, the neuromorphic chip further includes a planning and reasoning module, which is connected to the PFN neuron processing unit. The planning and reasoning module adopts an Actor-Critic architecture based on the PFN neuron processing unit, where the Actor network is responsible for generating action policies and the Critic network is responsible for evaluating state values.

[0023] Optionally, the neuromorphic chip further includes a threat detection module, which is connected to the PFN neuron processing unit. The threat detection module adopts a dual-pathway architecture with fast and slow pathways running in parallel. The fast pathway directly maps sensor input to threat response, while the slow pathway performs fine analysis through feature extraction and classification.

[0024] This invention also provides a navigation path planning method for a neuromorphic chip employing a protein network architecture, implemented using the aforementioned neuromorphic chip employing a protein network architecture, comprising the following steps:

[0025] S1. Collect environmental information through the robot's multimodal sensors, including at least lidar point cloud data, visual image data, and inertial measurement data;

[0026] S2. The spatial coding module uses the collected environmental information to construct an environmental cognitive map based on a continuous attractor network, thereby achieving real-time positioning and path integration.

[0027] S3. The action selection network generates at least two candidate navigation actions based on the real-time positioning and path integral, and selects the optimal action from the candidate navigation actions.

[0028] S4. The planning and reasoning module performs forward path planning based on the candidate navigation actions to handle navigation tasks that require long-term strategies.

[0029] S5. The threat detection module quickly identifies obstacles and dangerous areas in the environment based on the environmental information, triggers an immediate avoidance response, and outputs control commands.

[0030] S6. The output control command is based on the neuromorphic chip configuration controller to drive the robot actuator and realize autonomous navigation.

[0031] Compared with the prior art, the present invention:

[0032] This invention draws upon the topological properties and dynamic mechanisms of protein-protein interaction networks to construct a neuromorphic chip with higher biological rationality and computational efficiency, and possesses the following characteristics:

[0033] 1. Greater biological rationality: By drawing on the topological characteristics and dynamic mechanisms of protein networks, the neuromorphic chip of this invention has greater biological rationality in terms of neuron model, synaptic plasticity and network architecture, and can better simulate the information processing mode of the brain.

[0034] 2. Enhanced computing power: The multi-stable characteristics and variability regulation mechanism of the PFN model enable individual neurons to have stronger information processing capabilities; the modular architecture and hub node design improve the parallel processing efficiency of the network; and the dynamic reconfiguration capability allows the chip to adapt to different task requirements.

[0035] 3. Higher energy efficiency: The pulse-based event-driven computing method consumes energy only when neurons are activated; the in-memory computing design reduces data transfer overhead; the hierarchical modular architecture supports local computing and sparse communication, further reducing power consumption.

[0036] 4. Better robustness: The noise suppression mechanism inspired by chaperone proteins improves the fault tolerance of the system; the competitive-cooperative balance of synaptic plasticity promotes the self-organization of the network; and the dynamic reconfiguration capability enables the system to cope with hardware failures and environmental changes. Attached Figure Description

[0038] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the neuromorphic chip structure of the present invention;

[0041] Figure 2 This is a schematic diagram of the topology connecting modular clusters and hub nodes in the protein network of this invention;

[0042] Figure 3 This is a schematic diagram illustrating the dynamic characteristics of the PFN neuron model in this invention;

[0043] Figure 4 This is a schematic diagram illustrating the synaptic plasticity mechanism of the Complex-STDP model in this invention.

[0044] Figure 5 This is a schematic diagram of the communication protocol cascade structure of the signal transduction module in this invention;

[0045] Figure 6 This is a functional module architecture diagram of the PNN navigation method in this invention;

[0046] Figure 7 This is a diagram showing the interface architecture between the chip and the external system in this invention;

[0047] Figure 8 This is a diagram of the chip physical implementation architecture in this invention;

[0048] Figure 9 This is a state transition diagram of the dynamic reconfiguration mechanism in this invention;

[0049] Figure 10 This is a schematic diagram of the continuous attractor network of the spatial coding module in this invention;

[0050] Figure 11 This is a schematic diagram of the basal ganglia model of the action selection module in this invention;

[0051] Figure 12 This is a schematic diagram of the rapid response mechanism of the threat detection module in this invention;

[0052] Figure 13 This is a diagram of the hardware and software collaborative architecture of the robot navigation system in this invention;

[0053] Figure 14 This is a flowchart of the robot path planning algorithm in this invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other implementation cases obtained by those skilled in the art without creative effort are within the scope of protection of this application. Functional units with the same reference numerals in the examples of this invention have the same and similar structures and functions.

[0056] See Figure 1 This invention provides a neuromorphic chip employing a protein network architecture. The neuromorphic chip comprises a neuronal computing array, a synaptic weight memory, a hub processing unit, a signal transduction module, and a configuration controller. The neuronal computing array includes at least two PFN neuronal processing units based on protein folding energy landscapes. The signal output of the neuronal computing array is connected to the signal input of the synaptic weight memory via the signal transduction module. The signal output of the synaptic weight memory is connected to the signal input of the hub processing unit via the signal transduction module. The signal output of the hub processing unit is connected to the signal input of the configuration controller via the signal transduction module.

[0057] In this embodiment, the application maps the topological characteristics of protein-protein interaction networks to the hardware architecture design of a neuromorphic chip, constructing a neural network processor with modularity, hierarchy, and dynamic reconfiguration capabilities. This processor employs a neuron model inspired by protein folding, a synaptic plasticity mechanism based on protein complex formation, and a network communication protocol based on signal transduction pathways.

[0058] See Figure 2 First, the neuromorphic decision chip of this application adopts a hierarchical modular architecture, the design concept of which originates from the analysis of the topological characteristics of protein-protein interaction networks:

[0059] (1) Modular Cluster: The chip consists of multiple functional modules. Each module uses high-density local connections, corresponding to the functional modules in the protein network. The modules communicate with each other through sparse long-range connections.

[0060] (2) Hub Node: Drawing inspiration from the concept of "hub proteins" in protein networks, a dedicated hub processing unit is set up in the chip to be responsible for cross-module information integration and global status monitoring. Hub nodes have higher connectivity and computing power.

[0061] (3) Dynamic reconfiguration capability: Protein networks can dynamically adjust their interactions based on cell state. This chip supports runtime reconfiguration, including reconfiguration of neuron connections, dynamic adjustment of module boundaries, and on-demand allocation of computing resources.

[0062] See Figure 3 Secondly, the PFN neuron processing unit in the neuron computation array of this application is a neuronal dynamics model based on the protein folding energy landscape, called the ProteinFold-Neuron (PFN) model. This model analogizes the changes in neuronal membrane potential to the energy state transitions during protein folding, specifically including the following characteristics:

[0063] (1) Multistable dynamics: Unlike the monostable state of the traditional LIF model, the PFN model has multiple metastable states, corresponding to intermediate states in protein folding. This multistable characteristic enables neurons to encode richer information and supports multivalued logic operations.

[0064] (2) Allosteric regulation mechanism: Drawing on the protein allosteric effect, the PFN model introduces a remote regulation mechanism. When a part of a neuron receives an input signal, it can affect the functional sites at a distance through conformational changes, thereby achieving cross-layer information modulation.

[0065] (3) Chaperone protein-inspired noise suppression: In the PFN model, a chaperone protein auxiliary unit is introduced. When the neuron is in a misfolded state (i.e. abnormal activation mode), the chaperone unit intervenes and helps to restore normal dynamic behavior, thereby improving the fault tolerance of the system.

[0066] See Figure 4 Furthermore, the synaptic weight memory of this application is a synaptic plasticity model based on protein complex assembly / disassembly, called Complex-STDP. In living organisms, the realization of protein function often depends on the formation of multi-subunit complexes, and the assembly and disassembly of these complexes are key steps in dynamic regulation. The Complex-STDP model analogizes changes in synaptic weights to the assembly process of protein complexes, with the specific mechanism as follows:

[0067] (1) Multi-protein component model: Each synapse is composed of multiple "protein components", and different components correspond to different types of receptors and signaling molecules. The change in synaptic weight depends on the relative concentration and interaction strength of each component.

[0068] (2) Phosphorylation / dephosphorylation dynamics: Drawing on the mechanism of protein post-translational modification, Complex-STDP introduces the "phosphorylation level" variable. High-frequency stimulation leads to increased phosphorylation level (long-term enhanced LTP), while low-frequency stimulation leads to dephosphorylation (long-term inhibited LTD).

[0069] (3) Competition and cooperation: There is competition for limited “protein resources” between different synapses, while functionally related synapses achieve synergistic enhancement through sharing signaling pathways. This competition-cooperation balance promotes the self-organization of the network structure.

[0070] See Figure 5 Then, the signal transduction module in this application is a set of on-chip communication protocols similar to signal transduction, called SignalCascade Protocol (SCP), which has features such as cascaded amplification, crosstalk, and feedback control, specifically including:

[0071] (1) Cascaded pulse coding: Information is propagated in the form of pulse sequences. Each time the signal passes through a processing node, it can be amplified or modulated. The cascaded structure allows the weak initial signal to be amplified step by step, improving detection sensitivity.

[0072] (2) Multi-path crossover: Different functional modules achieve information crossover by sharing "signal molecules" (i.e., common data channels). This crossover dialogue mechanism supports multi-task collaborative processing and multi-modal information fusion.

[0073] (3) Feedback regulation loop: Drawing on the negative and positive feedback mechanisms in signal transduction, SCP supports feedforward and feedback connections, enabling the network to achieve advanced cognitive functions such as predictive coding and attention regulation.

[0074] See Figure 6 The neuromorphic decision-making chip also includes the following core components:

[0075] (1) Spatial coding module inspired by hippocampus-entorhinal cortex: By drawing on the coding mechanisms of place cells in the hippocampus and grid cells in the entorhinal cortex of rodents, a spatial cognitive map based on PFN neurons is constructed. This map has continuous attractor dynamics and supports path integration and position updates.

[0076] (2) Basal Ganglion-Inspired Action Selection Module: Drawing on the direct / indirect pathway model of the basal ganglia, an action selection network is constructed. This network can generate multiple candidate actions based on the current state and target task, combined with external environmental information such as lidar, camera, IMU, and location information, as well as real-time localization and path integration from the spatial coding module, and select the optimal solution from multiple candidate actions.

[0077] (3) Prefrontal cortex-inspired planning and reasoning module: Drawing on the working memory and planning functions of the prefrontal cortex, a sequence decision network based on reinforcement learning is constructed. This network can perform multi-step prospective planning and handle navigation tasks that require long-term strategies.

[0078] (4) Amygdala-inspired threat detection module: Drawing on the rapid threat assessment function of the amygdala, an anomaly detection network based on PFN neurons is constructed. This network can quickly identify negative stimuli such as obstacles and dangerous areas in the environment, triggering avoidance responses.

[0079] In another embodiment, see Figure 1 and Figure 7 The hardware implementation of the neuromorphic chip in this application is described. The application adopts a hierarchical modular architecture, which mainly includes the following components: (1) Neuron computing array - composed of multiple PFN neuron processing units, responsible for performing neuron dynamics calculations; (2) Synaptic weight memory - implemented using a memristor array, storing the connection weights between neurons; (3) Hub processing unit - responsible for cross-module information integration and global state monitoring; (4) Routing network - based on the SCP protocol to realize inter-module communication; (5) Configuration controller - supports dynamic reconfiguration at runtime; The sensing interface of the neuromorphic chip includes, but is not limited to, LiDAR, Camera, etc., and the control / communication interface includes, but is not limited to, the debugging interface and the storage interface.

[0080] The PFN neuron processing unit circuit is implemented using a mixed-signal design. The membrane potential variable is represented by the charge on the capacitor, and the multistable dynamics are realized through a nonlinear feedback circuit. The specific circuit includes: (1) an integrator circuit—simulating the accumulation process of the membrane potential; (2) a comparator array—detecting whether the membrane potential has reached the threshold of each metastable state; (3) a state machine—determining the state transition based on the current state and the input signal; and (4) a pulse generator—generating the output pulse during the state transition. In addition, the PFN neuron processing unit also has an allosteric regulation mechanism, which is realized through a simulated switch network. When a certain input signal is activated, the switch network adjusts the gain coefficient of other input pathways according to the preset allosteric mapping table. The chaperone protein function is realized by an auxiliary monitoring circuit. When an abnormal activation mode of a neuron is detected, a reset signal is triggered to restore the neuron to a normal state.

[0081] See Figure 8 The synaptic weight memory adopts a 1T1R (1 transistor + 1 memristor) structure. The conductance value of the memristor represents the synaptic weight and supports continuous storage of analog values. The hardware implementation of the Complex-STDP learning rule includes: (1) an anterior synaptic trace tracking circuit - recording the pulse history of the anterior neuron; (2) a posterior synaptic trace tracking circuit - recording the pulse history of the posterior neuron; (3) an update controller - generating corresponding SET / RESET pulses to update the memristor state according to the temporal relationship between the anterior and posterior synaptic traces.

[0082] See Figure 9 The chip in this application supports three levels of dynamic reconfiguration: (1) Connection-level reconfiguration - changing the connection relationship between neurons by reconfiguring the routing network; (2) Module-level reconfiguration - adjusting module boundaries and merging or splitting functional modules; (3) System-level reconfiguration - activating or deactivating some computing resources according to task requirements.

[0083] The reconfiguration configuration data is stored in on-chip SRAM. The configuration controller completes the reconfiguration operation within microseconds based on the instructions of the task scheduler. The reconfiguration process uses "shadow configuration" technology, where the new configuration is prepared in the background, enabling a seamless transition during switching.

[0084] In another embodiment, the functional modules of the software portion of the neuromorphic chip are described as follows:

[0085] See Figure 10 First, there is the spatial encoding module, which employs a continuous attractor network (CAN) structure. The network consists of a circular array of multiple PFN neurons, with the connection weights between neurons distributed using the Mexican Hat function, i.e., nearest-neighbor excitation and far-neighbor inhibition. This connection pattern enables the network to exhibit a stable "bump" activity state, with the position of the bump corresponding to the robot's position in the environment.

[0086] The path integration function is implemented through velocity input modulation. As the robot moves, velocity signals (including linear and angular velocities) are input to the network, driving the active bumps to move in the corresponding directions. The mesh cell layer adopts a similar CAN structure, but with multiple periodic active bumps to encode multi-scale information in the space.

[0087] See Figure 11Secondly, there is the action selection module, which draws on the direct-indirect pathway model of the basal ganglia. The module includes: (1) the striatum – receiving candidate action signals from the cortex; (2) the lateral part of the globus pallidus (GPe) and the subthalamic nucleus (STN) – forming an indirect pathway to inhibit unwanted actions; (3) the medial part of the globus pallidus (GPi) and the substantia nigra reticularis (SNr) – output nuclei that inhibit all actions until selection is completed; and (4) the thalamus – feeding back the selected action signal to the cortex.

[0088] The multi-stable nature of PFN neurons gives action selection a "winner-takes-all" competitive effect. When multiple candidate actions are activated simultaneously, the competitive dynamics lead to the selection of the action corresponding to the strongest input, while other actions are suppressed. This selection mechanism is characterized by low latency and high robustness.

[0089] Next is the planning and reasoning module, which adopts an Actor-Critic architecture based on PFN neurons. The Actor network is responsible for generating action policies, and the Critic network is responsible for evaluating state values. The two networks share the state representation provided by the spatial encoding module and are learned end-to-end through Complex-STDP rules.

[0090] To support multi-step planning, the module introduces a working memory mechanism. Working memory consists of a group of self-connected and mutually inhibiting PFN neurons, which can temporarily store planning-related information such as target location and obstacle location. A prefrontal cortex-inspired gating mechanism controls the reading and writing operations of the working memory.

[0091] See Figure 12 Finally, there is the threat detection module, which employs a dual-path architecture with a fast and a slow path running in parallel, borrowing from the processing mechanism of the amygdala. The fast path directly maps sensor input to threat response, resulting in low latency but limited accuracy; the slow path performs feature extraction and classification, achieving high accuracy but with greater latency. When the fast path detects a potential threat, it triggers an immediate avoidance response; simultaneously, the slow path performs detailed analysis and adjusts the response strategy as needed.

[0092] In another embodiment, see Figure 13 The robot navigation system employs a hardware-software co-processing architecture. Sensor data (LiDAR, camera, IMU, etc.) is preprocessed and then input into the hub processing unit within the neuromorphic decision chip. The spatial encoding module on the chip updates the position estimate in real time, constructing a cognitive map. When a navigation decision needs to be made, the planning and reasoning module generates candidate paths, the action selection module selects the optimal action from these, and the result is output to the configuration controller for execution.

[0093] The threat detection module continuously monitors the environment. Once a dangerous situation is detected, it immediately triggers a high-priority interrupt response, bypassing the normal decision-making process and directly controlling the actuators. This design ensures the system's security.

[0094] The neuromorphic chip of this application was deployed on an indoor mobile robot equipped with a 2D LiDAR and an RGB-D camera, operating in an office building corridor. Experimental results show that the robot can autonomously explore, build maps, and plan the optimal path to the target location in an unknown environment. The average navigation speed reached 0.8 m / s, and the obstacle avoidance success rate exceeded 99%. Compared with traditional SLAM-based methods, the system of this invention has lower computational latency (average 20ms vs 150ms) and higher energy efficiency. Furthermore, during navigation, an obstacle could be suddenly placed in front of the robot by an experimenter. The threat detection module detected the obstacle within 50ms and triggered an avoidance response. Subsequently, the planning and reasoning module recalculated the path, bypassing the obstacle to reach the target. The entire response process was completed within 200ms, demonstrating the system's rapid adaptability to dynamic environments. Simultaneously, the chip dynamically switches between navigation and object recognition tasks. When the robot reaches the target area, the configuration controller completes functional reconfiguration within 10 microseconds, switching computing resources from the navigation module to the recognition module. After recognition is completed, it reconfigures back to navigation mode to continue executing the next task. This dynamic reconfiguration capability enables a single chip to support the flexible scheduling of multiple cognitive functions.

[0095] See Figure 14 The present invention also provides a navigation path planning method for a neuromorphic chip employing a protein network architecture, implemented using the aforementioned neuromorphic chip employing a protein network architecture, comprising the following steps:

[0096] S1. Collect environmental information through the robot's multimodal sensors, including at least lidar point cloud data, visual image data, and inertial measurement data;

[0097] S2. The spatial coding module uses the collected environmental information to construct an environmental cognitive map based on a continuous attractor network, thereby achieving real-time positioning and path integration.

[0098] S3. The action selection network generates at least two candidate navigation actions based on the real-time positioning and path integral, and selects the optimal action from the candidate navigation actions.

[0099] S4. The planning and reasoning module performs forward path planning based on the candidate navigation actions to handle navigation tasks that require long-term strategies.

[0100] S5. The threat detection module quickly identifies obstacles and dangerous areas in the environment based on the environmental information, triggers an immediate avoidance response, and outputs control commands.

[0101] S6. The output control command is based on the neuromorphic chip configuration controller to drive the robot actuator and realize autonomous navigation.

[0102] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0103] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A neuromorphic chip employing a protein network architecture, characterized in that, The neuromorphic chip includes a neuronal computing array, a synaptic weight memory, a hub processing unit, a signal transduction module, and a configuration controller. The neuronal computing array includes at least two PFN neuronal processing units based on protein folding energy landscapes. The signal output terminal of the neuronal computing array is connected to the signal input terminal of the synaptic weight memory through the signal transduction module. The signal output terminal of the synaptic weight memory is connected to the signal input terminal of the hub processing unit through the signal transduction module. The signal output terminal of the hub processing unit is connected to the signal input terminal of the configuration controller through the signal transduction module.

2. The neuromorphic chip employing a protein network architecture as described in claim 1, characterized in that, The PFN neuron processing unit employs a mixed-signal design and includes at least: An integrator circuit for simulating the membrane potential accumulation process, a comparator array for detecting whether the membrane potential has reached the threshold of each metastable state, a state machine for determining the state transition based on the threshold comparison result and the input signal, and a pulse generator for generating output pulses during the state transition are provided. The integrator circuit is electrically connected in sequence to the comparator array, the state machine, and the pulse generator.

3. The neuromorphic chip employing a protein network architecture as described in claim 1, characterized in that, The synaptic weight memory adopts a 1T1R structure, which consists of a transistor and a memristor. The conductance of the memristor is used to represent the synaptic weight and supports continuous storage and in-situ updates of the analog value.

4. The neuromorphic chip employing a protein network architecture as described in claim 1, characterized in that, The signal transduction module adopts the SignalCascade communication protocol, which uses cascaded pulse coding to propagate information in the form of pulse sequences. Each time the signal passes through a processing node, it is amplified or modulated.

5. The neuromorphic chip employing a protein network architecture as described in claim 4, characterized in that, The SignalCascade communication protocol also employs a multi-channel cross-dialogue mechanism, which enables information exchange between different functional modules by sharing signal molecules, supporting multi-task collaborative processing and multi-modal information fusion.

6. The neuromorphic chip employing a protein network architecture as described in claim 1, characterized in that, The neuromorphic chip also includes a spatial coding module, which is connected to the PFN neuron processing unit. The spatial coding module draws on the coding mechanisms of hippocampal position cells and entorhinal cortex grid cells in rodents to construct a spatial recognition map based on the PFN neuron processing unit.

7. The neuromorphic chip employing a protein network architecture as described in claim 6, characterized in that, The neuromorphic chip also includes an action selection module, which is connected to the PFN neuron processing unit. The action selection module draws on the direct-indirect pathway model of the basal ganglia to construct an action selection network.

8. The neuromorphic chip employing a protein network architecture as described in claim 7, characterized in that, The neuromorphic chip also includes a planning and reasoning module, which is connected to the PFN neuron processing unit. The planning and reasoning module adopts an Actor-Critic architecture based on the PFN neuron processing unit, where the Actor network is responsible for generating action policies and the Critic network is responsible for evaluating state values.

9. The neuromorphic chip employing a protein network architecture as described in claim 8, characterized in that, The neuromorphic chip also includes a threat detection module, which is connected to the PFN neuron processing unit. The threat detection module adopts a dual-pathway architecture with fast and slow pathways running in parallel. The fast pathway directly maps sensor input to threat response, while the slow pathway performs fine analysis through feature extraction and classification.

10. A navigation path planning method for a neuromorphic chip employing a protein network architecture, characterized in that, The implementation using the neuromorphic chip with a protein network architecture as described in claim 9 includes the following steps: S1. Collect environmental information through the robot's multimodal sensors, including at least lidar point cloud data, visual image data, and inertial measurement data; S2. The spatial coding module uses the collected environmental information to construct an environmental cognitive map based on a continuous attractor network, thereby achieving real-time positioning and path integration. S3. The action selection network generates at least two candidate navigation actions based on the real-time positioning and path integral, and selects the optimal action from the candidate navigation actions. S4. The planning and reasoning module performs forward path planning based on the candidate navigation actions to handle navigation tasks that require long-term strategies. S5. The threat detection module quickly identifies obstacles and dangerous areas in the environment based on the environmental information, triggers an immediate avoidance response, and outputs control commands. S6. The output control command is based on the neuromorphic chip configuration controller to drive the robot actuator and realize autonomous navigation.

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