Multi-bit superconducting quantum chip and quantum computer

Abstract

The application discloses a multi-bit superconducting quantum chip and a quantum computer, and relates to the technical field of quantum computers.The multi-bit superconducting quantum chip comprises a plurality of surface code lattices, the plurality of surface code lattices form a two-dimensional torus structure, and the plurality of surface code lattices are coupled and connected through high-fidelity cross-chip quantum interconnection.The surface code lattices are divided into a plurality of sub-lattice modules along two orthogonal directions, the plurality of sub-lattice modules are coupled and connected, and each sub-lattice module is independently integrated on a sub-chip.The application solves the technical problem that a single-chip integration scheme cannot realize a large code distance torus code.

Description

Technical Field

[0001] This invention relates to the field of quantum chips, and more particularly to a multi-qubit superconducting quantum chip and a quantum computer. Background Technology

[0002] Quantum error correction is a core technological support for realizing large-scale universal fault-tolerant quantum computing. Current superconducting quantum computing technology has achieved chip integration at the hundred-qubit level, but qubits are inherently sensitive to environmental noise, and the error rate of physical qubits is much higher than that of classical semiconductor qubits. Therefore, quantum error correction is necessary to reduce the logical error rate to a level suitable for fault-tolerant computing. The core theoretical foundation of fault-tolerant quantum computing is quantum error-correcting codes, whose core idea is to encode the information of a single logical qubit into the quantum states of multiple physical qubits. Surface codes, because they only require close-neighbor coupling of physical qubits, have high compatibility with quantum chip hardware and a high threshold error rate, and are currently the most widely used and mature quantum error correction scheme, representing the mainstream candidate route for large-scale fault-tolerant quantum computing.

[0003] In the initial theoretical framework of topological quantum codes, the core design idea for constructing the prototype was to close the coding lattice into a two-dimensional torus topology with periodic boundary conditions to obtain a fourfold degenerate ground state under topological protection. However, surface codes with two-dimensional torus topology have long faced engineering bottlenecks: the periodic boundary conditions require coupling the two sets of opposite edges of the system separately. This operation is limited by the single-chip integration framework. When the code distance is extended to a large extent, it leads to intractable engineering problems such as insufficient single-chip area, crosstalk introduced by long-distance wiring, and decreased fabrication yield. Due to the limitations of single-chip integration capabilities, the surface code error correction experiments that have been completed so far all adopt planar surface code schemes with open boundary conditions. These schemes arrange the coding lattice on an open plane, eliminating the need for opposite edge coupling, and are easier to implement in engineering. In open-boundary planar surface codes, the core defect stems from their non-closed topological structure, essentially sacrificing the topological protection advantages of toroidal structures. This results in the following inherent defects: 1) Edge effects exist at the open boundary, inducing non-uniform topological protection: Due to the presence of underweighted non-holonomic stableons at the open edge, the translational invariance of topological order is violated, leading to a significantly higher decoherence rate in the edge region compared to the bulk region. Overall fault tolerance is degraded compared to two-dimensional toroidal surface codes (toroidal codes). 2) The coding space dimension is halved, and resource overhead is doubled: The coding dimension of open-boundary planar surface codes is 1, supporting only one independent logical qubit. The coding rate is only half that of toroidal codes of the same physical bit size, and the physical resource overhead per logical bit is doubled compared to toroidal codes, failing to meet the development requirements of low-overhead fault-tolerant quantum computing. 3) Open boundary induces logical operator truncation degradation: The length of the shortest logical operator in the open plane is limited by boundary truncation. Under the same lattice dimensions, the minimum code distance is strictly smaller than that of toroidal codes, resulting in a lower error correction threshold than toroidal codes of the same size, leading to a fundamental difference in fault tolerance performance. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide a multi-qubit superconducting quantum chip and a quantum computer to solve the technical problem that single-chip integration schemes cannot realize large-gap toroidal codes.

[0005] The technical solution of the present invention is as follows: A multi-qubit superconducting quantum chip, comprising: Multiple surface code lattices, which constitute a two-dimensional toroidal structure, are coupled and connected to each other through high-fidelity cross-chip quantum interconnects. The surface code lattice is divided into multiple sub-lattice modules along two orthogonal directions. The multiple sub-lattice modules are coupled and connected to each other, and each sub-lattice module is integrated on a sub-chip.

[0006] Optionally, the edges of the surface code lattice are provided with interconnect ports, and multiple surface code lattices are coupled together through the interconnect ports.

[0007] Optionally, any two adjacent surface code lattices can connect two qubits coupled across the chip to independent impedance-matched coplanar waveguide transmission lines via tunable couplers, and achieve cross-chip connection of the surface code lattices through bonding or three-dimensional vertical leads.

[0008] Optionally, the multi-qubit superconducting quantum chip also includes: A coupling strength tuning calibration structure is used to calibrate the coupling parameters and modulation pulse shape between surface code lattices.

[0009] Optionally, the surface code lattice is divided into two sub-lattice modules, one above the other or one to the left and right, and the two sub-lattice modules are interconnected across the chip.

[0010] Optionally, the surface code lattice is divided into multiple sub-lattice modules, which are located vertically and horizontally, and these multiple sub-lattice modules are interconnected across multiple chips.

[0011] Optionally, the surface code lattice is divided into M×N rectangular sub-lattice modules along two orthogonal directions, where M and N are both positive integers greater than 1; multiple sub-lattice modules are coupled together through on-chip fixed coupling or couplers.

[0012] Optionally, the multi-qubit superconducting quantum chip also includes: A clock device is connected to multiple sublattice modules, and the clock device is used to output timing signals to multiple sublattice modules.

[0013] Optionally, the clock device is used to control the synchronous triggering of measurements by multiple sublattice modules, and the clock device is connected to each sublattice module through an independent microwave distribution line.

[0014] The present invention also proposes a quantum computer, comprising the multi-qubit superconducting quantum chip described above.

[0015] This invention presents a multi-qubit superconducting quantum chip constructed from multiple surface code lattices. These lattices form a two-dimensional toroidal structure, coupled together via high-fidelity cross-chip quantum interconnects. Each surface code lattice is further divided into multiple sub-lattice modules along two orthogonal directions, with these modules coupled together and each integrated onto a single sub-chip. This multi-qubit superconducting quantum chip decomposes the square-scale qubits that would otherwise require large-size single-chip integration into multiple sub-chips. Because sub-chips are easier to fabricate and have a lower defect rate, the overall yield is significantly higher than that of large-size single-chips with the same qubit count. This effectively reduces the fabrication cost of large-gap toroidal codes, overcomes the single-chip area limitation, and enables the construction of toroidal topological surface codes with arbitrary code spacing. It retains the inherent theoretical advantages of toroidal codes, such as uniform topological protection, doubled coding rate, and larger code spacing at the same scale, while simultaneously reducing the fabrication difficulty of large-size lattices and improving chip yield. This provides a feasible engineering solution for low-overhead, high-performance, fault-tolerant quantum computing. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the surface code lattice cutting scheme in the multi-qubit superconducting quantum chip of the present invention.

[0018] Figure 2 This is a schematic diagram illustrating the boundary bit coupling between different superconducting quantum chips achieved through chip interconnection in the multi-qubit superconducting quantum chip of this invention.

[0019] Figure 3 This is a three-dimensional structural schematic diagram of the cross-chip interconnection implementation scheme in the multi-qubit superconducting quantum chip of the present invention.

[0020] Figure 4 This is a schematic diagram of the functional modules of an embodiment of the multi-qubit superconducting quantum chip of the present invention.

[0021] Explanation of reference numerals in the attached figures: 10, surface code lattice; 11, sublattice module; 20, coupling strength tuning and calibration structure. Detailed Implementation

[0022] To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0023] In the implementation methods and claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of the present invention involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0024] It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements present. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any unit and all combinations of one or more associated listed items.

[0025] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0026] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0027] Quantum error correction is a core technological support for realizing large-scale universal fault-tolerant quantum computing. Current superconducting quantum computing technology has achieved chip integration at the hundred-qubit level, but qubits are inherently sensitive to environmental noise, and the error rate of physical qubits is much higher than that of classical semiconductor qubits. Therefore, quantum error correction is necessary to reduce the logical error rate to a level suitable for fault-tolerant computing. The core theoretical foundation of fault-tolerant quantum computing is quantum error-correcting codes, whose core idea is to encode the information of a single logical qubit into the quantum states of multiple physical qubits. Surface codes, because they only require close-neighbor coupling of physical qubits, have high compatibility with quantum chip hardware and a high threshold error rate, and are currently the most widely used and mature quantum error correction scheme, representing the mainstream candidate route for large-scale fault-tolerant quantum computing.

[0028] In the initial theoretical framework of topological quantum codes, the core design idea for constructing the prototype was to close the coding lattice into a two-dimensional torus topology with periodic boundary conditions to obtain a fourfold degenerate ground state under topological protection. However, surface codes with two-dimensional torus topology have long faced engineering bottlenecks: the periodic boundary conditions require coupling the two sets of opposite edges of the system separately. This operation is limited by the single-chip integration framework. When the code distance is extended to a large extent, it leads to intractable engineering problems such as insufficient single-chip area, crosstalk introduced by long-distance wiring, and decreased fabrication yield. Due to the limitations of single-chip integration capabilities, the surface code error correction experiments that have been completed so far all adopt planar surface code schemes with open boundary conditions. These schemes arrange the coding lattice on an open plane, eliminating the need for opposite edge coupling, and are easier to implement in engineering. In open-boundary planar surface codes, the core defect stems from their non-closed topological structure, essentially sacrificing the topological protection advantages of toroidal structures. This results in the following inherent defects: 1) Edge effects exist at the open boundary, inducing non-uniform topological protection: Due to the presence of underweighted non-holonomic stableons at the open edge, the translational invariance of topological order is violated, leading to a significantly higher decoherence rate in the edge region compared to the bulk region. Overall fault tolerance is degraded compared to two-dimensional toroidal surface codes (toroidal codes). 2) The coding space dimension is halved, and resource overhead is doubled: The coding dimension of open-boundary planar surface codes is 1, supporting only one independent logical qubit. The coding rate is only half that of toroidal codes of the same physical bit size, and the physical resource overhead per logical bit is doubled compared to toroidal codes, failing to meet the development requirements of low-overhead fault-tolerant quantum computing. 3) Open boundary induces logical operator truncation degradation: The length of the shortest logical operator in the open plane is limited by boundary truncation. Under the same lattice dimensions, the minimum code distance is strictly smaller than that of toroidal codes, resulting in a lower error correction threshold than toroidal codes of the same size, leading to a fundamental difference in fault tolerance performance.

[0029] To address the aforementioned problems, this invention proposes a multi-qubit superconducting quantum chip.

[0030] Reference Figure 1 In one embodiment, the multi-qubit superconducting quantum chip includes: Multiple surface code lattices 10 constitute a two-dimensional toroidal structure, and the multiple surface code lattices 10 are coupled and connected to each other through high-fidelity cross-chip quantum interconnect. The surface code lattice 10 is divided into multiple sub-lattice modules 11 along two orthogonal directions. The multiple sub-lattice modules 11 are coupled and connected to each other, and each sub-lattice module 11 is integrated on a sub-chip.

[0031] In this embodiment, the two-dimensional toroidal structure composed of multiple surface code lattices 10 can be viewed as multiple planar surface codes spliced ​​and closed to form a toroidal structure. In this embodiment, each surface code lattice 10 of the toroidal structure is divided into multiple sub-lattice modules 11, and these sub-lattice modules 11 are then integrated onto independent sub-chips. Furthermore, high-fidelity cross-chip interconnect technology is used to complete the adjacency coupling of the multiple surface code lattices 10, thereby ensuring the complete closure of the two-dimensional toroidal structure. The periodic boundary coupling of opposite edges required for a complete toroidal topology can also be achieved through multi-chip synchronous control. In this embodiment, the multi-qubit superconducting quantum chip decomposes the square-scale qubits that originally required large-size single-chip integration into multiple sub-chips. Because the sub-chips are easier to fabricate and have a lower defect rate, the overall yield is significantly higher than that of large-size single-chips with the same number of qubits. Therefore, it effectively reduces the fabrication cost of large-gap toroidal codes, breaks through the single-chip area limitation, and enables the construction of toroidal topological surface codes with arbitrary code spacing. It retains the inherent theoretical advantages of toroidal codes, such as fully uniform topological protection, doubled coding rate, and larger code spacing at the same scale. At the same time, it reduces the fabrication difficulty of large-size lattices and improves chip yield, providing a feasible engineering solution for low-overhead, high-performance, fault-tolerant quantum computing.

[0032] This invention utilizes multiple surface code lattices 10 to construct a multi-qubit superconducting quantum chip. These lattices form a two-dimensional toroidal structure and are coupled together via high-fidelity cross-chip quantum interconnects. Each surface code lattice 10 is further divided into multiple sub-lattice modules 11 along two orthogonal directions, and these sub-lattice modules are coupled together. Each sub-lattice module 11 is integrated onto a single sub-chip. This multi-qubit superconducting quantum chip effectively reduces the fabrication cost of large-gap toroidal codes, overcomes the limitations of single-chip area, and enables the construction of toroidal topological surface codes with arbitrary code pitches. It retains the inherent theoretical advantages of toroidal codes, such as uniform topological protection, doubled coding rate, and larger code pitch at the same scale. Simultaneously, it reduces the fabrication difficulty of large-size lattices and improves chip yield, providing a feasible engineering solution for low-overhead, high-performance, fault-tolerant quantum computing and solving the technical problem that single-chip integration schemes cannot realize large-gap toroidal codes.

[0033] In one embodiment, the edges of the surface code lattice 10 are provided with interconnect ports, and multiple surface code lattices 10 are coupled and connected through the interconnect ports.

[0034] In this embodiment, to form a two-dimensional toroidal structure, multiple surface code lattices 10 need to have interconnect ports set on the edges of each surface code lattice 10, allowing multiple surface code lattices 10 to be coupled and connected through the interconnect ports. The interconnect ports are dedicated physical / logical interfaces for lattice splicing / lattice manipulation, logic gate operations, qubit expansion, and external signal / control access. Essentially, they are specific connection points between boundary stabilizers and data bits, ensuring topology protection, error measurability, and logic operator continuity after splicing. In this embodiment, the interconnect ports are only located at the edges (not corner-priority), and do not occupy internal stabilizers / data bits, ensuring complete internal error correction. It should be noted that when splicing two surface code lattices 10, X-boundary to X-boundary and Z-boundary to Z-boundary (same-type interconnection); otherwise, topology incompatibility, logic operator breakage, and uncorrectable errors will occur. The coupling connection can specifically be achieved by marking all edges as X or Z boundaries (usually top and bottom X, left and right Z, or alternating) to form a compatible splicing surface. Then, in the central region of each target interconnection edge, select a set of continuous data bits (length ≥ 2, ensuring fault tolerance); mark the corresponding edge stabilizers (X / Z) as the measurement anchor points for the ports. The port connections are then configured: physically, the edge data bits are directly coupled to the same-type edge data bits of adjacent lattices (nearest neighbor gates); auxiliaryly, the stabilizer auxiliary bits at the ports are connected to dedicated readout / control lines for stabilizer verification and error monitoring during splicing. Fault tolerance verification can also be performed: verifying the stabilizer weights at the ports (3 weights for edges, 2 weights for corners) to ensure that errors are measurable. Verifying the continuity and lack of breaks in the logical operators (X / Z) after splicing allows for lossless movement of any operator between spliced ​​lattices. Additionally, expansion ports can be reserved on non-interconnection edges to support subsequent lattice expansion and multi-logic-bit array networking. If compatibility with variable code distance or error correction performance calibration is required, the cross-chip coupling can be designed as tunable coupling (coupling strength is controlled by magnetic flux). This allows for calibration of boundary coupling parameters without re-fabricating the chip, adapting to different error correction process requirements.

[0035] For specific details regarding the coupling settings of the surface code lattice 10, please refer to the following: Figure 2 Chip A and chip B are connected by a red line, which ensures the topological protection characteristics of the entire lattice of the two-dimensional toroidal structure, avoids the edge effect of open boundaries, and restores the original theoretical error correction performance of the toroidal code. Only two pairs of edges need to be coupled across chips, and the number of interconnect ports is much smaller than the total number of bits in the lattice, without introducing significant additional resource overhead.

[0036] In one embodiment, any two adjacent surface code lattices 10 connect two cross-chip coupled qubits to independent impedance-matched coplanar waveguide transmission lines via tunable couplers, and the cross-chip connection of the surface code lattices 10 is achieved by bonding or three-dimensional vertical leads.

[0037] In this embodiment, for the cross-chip interconnect layer implementation scheme between surface code lattices 10, one edge port qubit of surface code lattice 10 can be arranged on each of the two surface code lattice 10 chips. These two bits constitute a pair of cross-chip coupled bits, serving as the topological interface between the two lattices. The tunable coupler + independent impedance-matched coplanar waveguide transmission line means that each edge port qubit is connected to an independent impedance-matched coplanar waveguide transmission line through a tunable coupler. The tunable coupler can be used to control the coupling strength between the bit and the transmission line, realizing switch-type interconnection (coupling / decoupling), suppressing crosstalk, and reducing cavity loss and phase noise; the impedance-matched transmission line can realize low-loss transmission of microwave signals between chips, ensuring coherent transmission of arbitrary substates / quantum information in the cross-chip link, and matching the impedance of on-chip qubits and inter-chip bonding / vertical leads. Cross-chip physical connections involve connecting two chips via bonding wires or three-dimensional vertical interconnects (3D TSVs / microbumps). The physical connection directly interfaces with the aforementioned impedance-matched coplanar waveguide transmission lines, thereby achieving stable sub-measurement links between the two surface code lattices. Logic arbitrary units can move between cross-chip lattices, supporting lattice manipulation and fault-tolerant logic gates. For higher integration requirements, three-dimensional vertical stacking interconnects can replace planar splicing. Different sub-chips are vertically stacked and coupled across chips via through-silicon vias (TSVs), further reducing the overall footprint and increasing integration density. The three-dimensional structure of the cross-chip interconnect implementation scheme can be referenced. Figure 3 .

[0038] Reference Figure 4 In one embodiment, the multi-qubit superconducting quantum chip further includes: The coupling strength tuning calibration structure 20 is used to calibrate the coupling parameters and modulation pulse shape between the surface code lattices 10.

[0039] In this embodiment, the coupling strength tuning and calibration structure 20 can be composed of an adjustable coupler, an on-chip calibration auxiliary branch, a pulse waveform modulation module, and an inter-chip interconnection feedback path. The adjustable coupler is positioned between the edge-port qubit and the impedance-matched coplanar waveguide transmission line, and the coupling strength is continuously adjustable through bias voltage / magnetic flux bias. The on-chip calibration auxiliary branch can include a calibration resonator, a phase adjustment unit, and an attenuation adjustment unit, used to extract coupling amplitude and phase information. The pulse waveform modulation module is integrated with the microwave drive line and can perform real-time shaping of the pulse amplitude, pulse width, rise time, phase, and envelope shape. The inter-chip interconnection feedback path introduces a reference signal through bonding leads or three-dimensional vertical leads to achieve synchronous calibration of coupling parameters between the two chips. This coupling strength tuning and calibration structure 20 can measure and correct inherent coupling deviations between qubits, transmission line loss differences, and process discreteness, precisely setting the target coupling strength to ensure stable and controllable coherent coupling between surface code lattices 10 across the chip. It suppresses crosstalk and avoids topological errors and decoherence caused by over-coupling or under-coupling. It can also perform Gaussian / square wave / apodization shaping on the driving pulses to suppress spectral leakage, dynamically adjust pulse timing and waveform, adapt to lattice manipulation, logic gate operations, and stabilizer measurement timing requirements, reduce non-computational errors caused by pulses, and improve the fidelity of cross-chip fault-tolerant quantum operations. Furthermore, it can combine with the readout signal to form a feedback loop, achieving on-orbit real-time calibration of coupling strength and pulse waveform, supporting large-scale surface code array expansion.

[0040] In one embodiment, the surface code lattice 10 is divided into two sub-lattice modules 11, either vertically or horizontally, and the two sub-lattice modules 11 are interconnected across the chip.

[0041] In this embodiment, under special circumstances, such as for the surface code lattice 10 of a small-to-medium code pitch ring, the surface code lattice 10 can be divided into two sub-lattice modules 11, one above the other or one to the left and right, and integrated on two sub-chips. In this way, only one pair of cross-chip interconnects is needed to realize the periodic boundary, the structure is simpler, and it is suitable for the principle verification experiment of surface codes with toroidal topology.

[0042] In one embodiment, the surface code lattice 10 is divided into multiple sub-lattice modules 11, which are located vertically and horizontally, and the multiple sub-lattice modules 11 are interconnected across multiple chips.

[0043] In this embodiment, for the complete toroidal topology of the surface code lattice 10 of the large code pitch ring, the surface code lattice 10 can be divided into multiple sub-lattice modules 11 in the upper and lower and left and right directions, and integrated on multiple sub-chips, so as to realize the periodic boundary conditions for the closure of the two-dimensional toroidal structure without the need for additional redundant bits.

[0044] Therefore, this scheme can use different methods to divide the surface code lattice 10 for different code distance rings to adapt to different situations.

[0045] In one embodiment, the surface code lattice 10 is divided into M×N rectangular sub-lattice modules 11 along two orthogonal directions, where M and N are both positive integers greater than 1; the multiple sub-lattice modules 11 are coupled together by on-chip fixed coupling or couplers.

[0046] In this embodiment, the surface code lattice 10 is divided into M×N rectangular sub-lattice modules 11 along two orthogonal directions, where M and N are both positive integers greater than 1. The M×N sub-lattice modules 11 are spliced ​​together through edge interconnect ports to form a complete surface code lattice 10 array. Each sub-lattice module 11 serves as the basic functional unit of the array and can independently perform stable sub-measurements and logic bit operations. The entire array achieves global synchronous calibration of coupling parameters through a coupling strength tuning calibration structure 20, and large-scale expansion is achieved through a cross-chip interconnect structure. This solves the lattice size bottleneck caused by single-chip size limitations and reduces the complexity of manufacturing, calibration, and maintenance through modular design. Furthermore, each sub-lattice module 11 has uniform specifications and a complete topology, retaining independent X / Z boundaries and compatible edge interconnect ports. Modules are connected through homogeneous boundary alignment, adjustable couplers, and impedance-matched coplanar waveguide transmission lines, achieving collaborative operation in conjunction with the coupling strength tuning calibration structure 20. Cross-chip sub-lattice modules 11 can be connected and expanded through bonding or three-dimensional vertical leads, balancing large-scale integration and fault tolerance.

[0047] In one embodiment, the multi-qubit superconducting quantum chip further includes: A clock device is connected to a plurality of the sublattice modules 11, and the clock device is used to output timing signals to the plurality of the sublattice modules 11.

[0048] Furthermore, in one embodiment, the clock device is used to control the synchronous triggering of measurements by multiple sublattice modules 11, and the clock device is connected to each sublattice module 11 through an independent microwave distribution line.

[0049] In this embodiment, a clock device is incorporated into the multi-qubit superconducting quantum chip, employing a globally synchronized clock-triggered architecture. Control signals for all sub-chips integrated into the sub-lattice module 11 are distributed from the same clock source within the clock device. Timing calibration ensures the synchronization of all stable sub-measurements: the logic operations within the sub-chips are executed in complete parallel, with the global clock only responsible for the synchronous triggering of boundary stable sub-measurements; control signals are distributed to each sub-chip via independent microwave wiring, with clock jitter controlled to less than 1 ps, meeting the synchronization requirements of quantum gate operations and measurements. This scheme leverages the inherent parallel control advantages of a distributed architecture to guarantee the parallelism of all stable sub-measurements of the error correction code, avoiding additional measurement time overhead due to multi-chip splitting; the synchronization accuracy meets the requirements of the error correction process, avoiding additional measurement errors introduced by asynchronous operations, and ensuring overall error correction performance.

[0050] Overall, compared to existing technologies such as single-chip integrated surface codes and open-boundary planar surface codes, this solution achieves periodic boundary conditions for toroidal topological surface codes through a modular multi-chip architecture and low-loss cross-chip interconnects. Existing technologies are limited by single-chip area / yield constraints, making it impossible to fabricate large-pitch toroidal codes. This solution, however, breaks through the limitations of single-chip area and fabrication processes by dividing the two-dimensional lattice of the toroidal code into multiple sub-modules and integrating them into independent superconducting quantum chips. This allows for the construction of toroidal codes with arbitrary pitches by expanding the number of sub-chips, eliminating the upper limit on the scale of single-chip integration. Simultaneously, the sub-chip yield is higher, reducing the overall fabrication cost compared to single-chip solutions, with a more significant improvement in yield for large-size lattices.

[0051] Furthermore, existing open-boundary planar surface codes sacrifice periodic boundaries and lose the inherent advantages of toroidal codes. This scheme achieves adjacency coupling of block lattices through high-fidelity, low-loss cross-chip quantum interconnects and completes the periodic boundary splicing of toroidal topology edges, fully preserving the theoretical advantages of toroidal codes such as uniform topology protection, doubled coding rate, and higher error correction threshold, thus solving the performance loss problem of open-boundary schemes.

[0052] In addition, existing cross-chip interconnect technologies generally suffer from high loss and low fidelity, which cannot meet the requirements of surface code error correction. This solution adopts a boundary homogenization low-loss interconnect design to ensure the consistency of cross-chip coupling parameters with on-chip coupling. Combined with low-loss transmission lines and coupling calibration processes, the loss of cross-chip interconnects is controlled within 0.5dB, and the coupling fidelity is higher than 99%, which meets the noise performance requirements of toroidal code stabilizer measurement.

[0053] With the same physical bit size, toroidal codes can encode twice the number of logical qubits as open-boundary schemes, doubling the encoding rate and reducing resource overhead per logical bit. At the same lattice dimensions, the minimum code distance of toroidal codes is one unit greater than that of open-boundary schemes, and the error correction threshold is higher than that of open-boundary planar surface codes of the same size, significantly improving overall fault tolerance and correction performance. This scheme also retains the parallel operation advantages of a multi-chip distributed architecture; the overall execution time of the error correction process is comparable to that of a single-chip solution, without introducing additional time overhead due to multi-chip splitting.

[0054] The present invention also proposes a quantum computer.

[0055] In one embodiment, the quantum computer includes the multi-qubit superconducting quantum chip described above. It is understood that, since the multi-qubit superconducting quantum chip described above is used in the quantum computer of this invention, the embodiments of the quantum computer of this invention include all the technical solutions of all embodiments of the multi-qubit superconducting quantum chip described above, and the achieved technical effects are exactly the same, and will not be repeated here.

[0056] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A multi-qubit superconducting quantum chip, characterized in that, include: Multiple surface code lattices, which constitute a two-dimensional toroidal structure, are coupled and connected to each other through high-fidelity cross-chip quantum interconnects. The surface code lattice is divided into multiple sub-lattice modules along two orthogonal directions. The multiple sub-lattice modules are coupled and connected to each other, and each sub-lattice module is integrated on a sub-chip.

2. The multi-qubit superconducting quantum chip as described in claim 1, characterized in that, The edges of the surface code lattice are provided with interconnect ports, and multiple surface code lattices are coupled and connected through the interconnect ports.

3. The multi-qubit superconducting quantum chip as described in claim 2, characterized in that, Any two adjacent surface code lattices connect two qubits coupled across the chip to independent impedance-matched coplanar waveguide transmission lines via tunable couplers, and achieve cross-chip connection of the surface code lattices through bonding or three-dimensional vertical leads.

4. The multi-qubit superconducting quantum chip as described in claim 3, characterized in that, Also includes: A coupling strength tuning calibration structure is used to calibrate the coupling parameters and modulation pulse shape between surface code lattices.

5. The multi-qubit superconducting quantum chip as described in claim 1, characterized in that, The surface code lattice is divided into two sub-lattice modules, either top and bottom or left and right, and the two sub-lattice modules are interconnected across chips.

6. The multi-qubit superconducting quantum chip as described in claim 1, characterized in that, The surface code lattice is divided into multiple sub-lattice modules, which are located vertically and horizontally. These multiple sub-lattice modules are interconnected across multiple chips.

7. The multi-qubit superconducting quantum chip as described in claim 1, characterized in that, The surface code lattice is divided into M×N rectangular sub-lattice modules along two orthogonal directions, where M and N are both positive integers greater than 1; multiple sub-lattice modules are coupled together through on-chip fixed coupling or couplers.

8. The multi-qubit superconducting quantum chip according to any one of claims 1-7, characterized in that, Also includes: A clock device is connected to multiple sublattice modules, and the clock device is used to output timing signals to multiple sublattice modules.

9. The multi-qubit superconducting quantum chip as described in claim 8, characterized in that, The clock device is used to control the synchronous triggering of measurements by multiple sublattice modules, and the clock device is connected to each sublattice module through an independent microwave distribution line.

10. A quantum computer, characterized in that, Including the multi-qubit superconducting quantum chip as described in any one of claims 1-9.

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