A PCB bare board defect detection method and device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ARMY ENG UNIV OF PLA
- Filing Date
- 2026-04-07
- Publication Date
- 2026-07-21
AI Technical Summary
Existing technologies for PCB defect detection suffer from insufficient accuracy and high false positive rates, especially when dealing with ultra-high density circuits, complex multi-layer structures, and various micro-holes and micro-blind vias.
An improved YOLOv10 neural network is adopted. By adding a feature fusion attention network module to the backbone network, replacing the convolutional modules in the backbone and neck network, and introducing an expanded residual fusion module, a new depthwise separable weighted residual segmentation module is formed, which enhances the network's ability to recognize complex structures.
It improves the accuracy and recall rate of PCB bare board defect detection, solves the problems of insufficient identification accuracy and high false positive rate, and is suitable for defect detection of ultra-high density circuits and complex multilayer structures.
Smart Images
Figure CN122434836A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method and apparatus for detecting defects in bare PCB boards, belonging to the field of PCB defect detection technology. Background Technology
[0002] Printed Circuit Boards (PCBs) are fundamental components of the modern electronics industry. As electronic components have evolved from discrete, low-density assembly to high-density, multi-functional miniaturized forms, the role of PCBs has become increasingly important. Based on an insulating substrate, PCBs etch copper foil into precise wire patterns, providing orderly and reliable electrical interconnections and mechanical support for various components such as chips, resistors, capacitors, and connectors. Through decades of technological advancements, PCBs have expanded from simple single-layer boards to double-layer, multi-layer, and even high-density interconnect (HDI) structures, providing high performance, stability, and reliability support for increasingly complex electronic products.
[0003] At the manufacturing level, PCB manufacturing involves multiple complex processes such as photolithography, etching, drilling, metallization, and lamination, requiring multi-layer stacking, fine wiring, and stringent tolerance control. These manufacturing processes not only necessitate accurate material selection (such as FR-4, polyimide, and special high-speed, high-frequency dielectrics) but also rely on sophisticated processing equipment and quality control technologies to ensure that the final product meets the requirements for high-speed signal transmission, low electrical loss, and excellent heat dissipation and electromagnetic compatibility (EMC) performance. With the increasing demands for PCB quality and performance from 5G, automotive electronics, medical, and industrial control sectors, manufacturers are continuously investing in R&D and process optimization to constantly raise the performance ceiling of PCBs.
[0004] However, even with increasingly sophisticated manufacturing processes, PCB defect detection still faces numerous challenges. Traditional manual visual inspection is time-consuming and struggles to guarantee high consistency due to human eye fatigue and subjective judgment errors. While automated inspection technologies (such as AOI and AXI) significantly improve inspection speed and accuracy, they still suffer from insufficient recognition accuracy and a high false positive rate when dealing with ultra-high density circuitry, complex multi-layer structures, and various micro-holes and micro-blind vias. Furthermore, the hardware and software costs required for some inspection systems are quite high, placing higher demands on the return on investment for small and medium-sized manufacturers in an increasingly competitive market. Summary of the Invention
[0005] The purpose of this invention is to provide a method and apparatus for detecting defects in bare PCB boards. By improving the traditional YOLOv10 neural network, the method enhances the neural network's ability to identify ultra-high density lines, complex multilayer structures, and minute details, thereby improving the accuracy and regression rate of bare PCB board defect detection. This method is suitable for defect detection and classification of bare PCB boards.
[0006] To achieve the above objectives / to solve the above technical problems, the present invention is implemented using the following technical solution:
[0007] In a first aspect, the present invention provides a method for detecting defects in bare PCB boards, comprising:
[0008] Preprocess the bare PCB data;
[0009] The pre-built PCB bare board defect detection model is used to detect and classify the pre-processed PCB bare board data to obtain PCB bare board defect detection results;
[0010] The PCB bare board defect detection model adopts an improved YOLOv10 neural network. The improvement method of the improved YOLOv10 neural network includes: adding a feature fusion attention network module at the first position of the backbone network, replacing the second and third convolutional modules of the backbone network with a diversified branch module, replacing the first convolutional module of the neck network with a diversified branch module, and replacing the cross-stage local fusion module used for downsampling in the neck network with an expanded residual fusion module. The expanded residual fusion module includes a depth-separable weighted residual segmentation module and a cross-stage local fusion module.
[0011] In conjunction with the first aspect, the backbone network further comprises, in sequence, a feature fusion attention network module, a first convolutional layer, a first diversified branch module, a first cross-stage local fusion module, a second diversified branch module, a second cross-stage local fusion module, a first spatial-channel downsampling module, a third cross-stage local fusion module, a second spatial-channel downsampling module, a cross-stage local fusion-context embedding block module, a fast spatial pyramid pooling module, and a parallel spatial attention module.
[0012] In conjunction with the first aspect, the feature fusion attention network module further includes a shallow feature extraction unit, several cascaded feature fusion groups, a global fusion unit, and an image reconstruction unit.
[0013] In conjunction with the first aspect, the further diversified branch modules include, in sequence, a convolution module, a batch normalization module, a convolution-normalization-activation module, a dilated convolution module, a depthwise convolution-pointwise convolution-normalization module, a pooling-convolution module, a convolution-normalization module, and a fifth concatenation module.
[0014] In conjunction with the first aspect, the neck network further includes a first upsampling module, a first stitching module, a first extended residual fusion module, a second upsampling module, a second stitching module, a second extended residual fusion module, a third diversified branching module, a third stitching module, a third extended residual fusion module, a third spatial-channel downsampling module, a fourth stitching module, and a cross-stage fast partial connection-context embedding block module.
[0015] The parallel spatial attention module of the backbone network is connected to the first upsampling module. The first stitching module stitches the features output by the first upsampling module with the features output by the third cross-stage local fusion module and inputs them into the first extended residual fusion module. The features output by the first extended residual fusion module are upsampled by the second upsampling module. The second stitching module stitches the features output by the second upsampling module with the features output by the second cross-stage local fusion module and inputs them into the second extended residual fusion module and the third diversified branch module. The features output by the third diversified branch module and the features output by the first extended residual fusion module are stitched together by the third stitching module and input into the third extended residual fusion module and the third spatial-channel downsampling module. The features output by the third spatial-channel downsampling module and the features output by the parallel spatial attention module are stitched together by the fourth stitching module and input into the cross-stage fast partial connection-context embedding module.
[0016] In conjunction with the first aspect, the cross-stage local fusion-context-inline block module further includes a first 1×1 convolutional layer, a context-inline block, a splicing layer, and a second 1×1 convolutional layer;
[0017] The context-in-context block includes a first 3×3 depth-separable convolutional layer, a first 1×1 convolutional layer, a second 3×3 depth-separable convolutional layer, a second 1×1 convolutional layer, and a third 3×3 depth-separable convolutional layer, which are connected in series.
[0018] Building upon the first aspect, the extended residual fusion module is further represented by the following model:
[0019]
[0020] in, This represents the pixel position extracted by depthwise separable convolution in the dilated residual fusion module. The output characteristics, Indicates input features Figure X Perform depthwise convolution operations. This represents a pointwise convolution operation;
[0021]
[0022] in, This represents the output feature map of the extended residual fusion module. This represents the features extracted through depthwise separable convolution, and X represents the input feature map of the expanded residual fusion module.
[0023] In conjunction with the first aspect, the model training loss function of the PCB bare board defect detection model is as follows:
[0024] ;
[0025] in, This represents the total loss of the model. For cross-entropy loss, For boundary loss, For cross-entropy loss weights, Weights for boundary loss;
[0026] ;
[0027] Where N is the total number of pixels in the feature map, and C is the total number of categories. The true label for pixel i belonging to category c. Predict the probability that pixel i belongs to category c for the model.
[0028] Secondly, the present invention provides a PCB bare board defect detection device, comprising:
[0029] The preprocessing module is used to preprocess the bare PCB data.
[0030] The defect detection module is used to detect and classify the pre-processed PCB bare board data using a pre-built PCB bare board defect detection model, and obtain the PCB bare board defect detection results.
[0031] The PCB bare board defect detection model adopts an improved YOLOv10 neural network. The improvement method of the improved YOLOv10 neural network includes: adding a feature fusion attention network module at the first position of the backbone network, replacing the second and third convolutional modules of the backbone network with a diversified branch module, replacing the first convolutional module of the neck network with a diversified branch module, and replacing the cross-stage local fusion module used for downsampling in the neck network with an expanded residual fusion module. The expanded residual fusion module includes a depth-separable weighted residual segmentation module and a cross-stage local fusion module.
[0032] Thirdly, the present invention provides a computer-readable storage medium having a computer program / instructions stored thereon, which, when executed by a processor, implements the steps of the PCB bare board defect detection method provided in the first aspect.
[0033] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:
[0034] This invention proposes a method and apparatus for detecting defects on bare PCB boards. It employs a feature fusion attention network module suitable for image dehazing, added to the first position of the backbone network to reduce visual interference caused by imaging environment, lighting conditions, or dust. A diversified branching module replaces the second and third convolutional modules in the original backbone network and the first convolutional module in the neck network. This helps the network better capture subtle differences in PCB texture and subtle changes between multi-layer structures, providing more accurate recognition support for defects of various shapes, sizes, and locations. Furthermore, a branching structure is introduced in the neck network to form a new depth-separable weighted residual segmentation module, replacing the downsampling cross-stage local fusion module, which is renamed the expanded residual fusion module, making the improved network more robust. This invention improves both the accuracy and recall of PCB bare board defect detection, solving the problems of insufficient recognition accuracy and high false positive rate in existing technologies when dealing with ultra-high density circuits, complex multi-layer structures, and various micro-holes and micro-blind vias. Attached Figure Description
[0035] Figure 1 The diagram shows the steps of a PCB bare board defect detection method provided by an embodiment of the present invention.
[0036] Figure 2 The diagram shown is a schematic representation of the improved YOLOv10 neural network in an embodiment of the present invention.
[0037] Figure 3 The diagram shown is a structural schematic of the cross-stage local fusion module in an embodiment of the present invention.
[0038] Figure 4 The diagram shown is a structural schematic of the diversified branch module in an embodiment of the present invention;
[0039] Figure 5 The diagram shown is a structural schematic of the fast spatial pyramid pooling module in an embodiment of the present invention;
[0040] Figure 6 The diagram shown is a structural schematic of the parallel spatial attention module in an embodiment of the present invention.
[0041] Figure 7 The diagram shown is a structural schematic of the cross-stage local fusion-context embedding block module in an embodiment of the present invention.
[0042] Figure 8 The diagram shown is a schematic representation of the structure of a context-inline block in an embodiment of the present invention.
[0043] Figure 9 The diagram shown is a schematic representation of the detection head network in an embodiment of the present invention.
[0044] Figure 10 The diagram shown is a schematic representation of the depth-separable weighted residual segmentation module in an embodiment of the present invention.
[0045] Figure 11 The diagram shown is a schematic diagram of the PCB bare board defect detection results of the method of the present invention in an embodiment of the present invention;
[0046] Figure 12 The diagram shown is a structural schematic of a PCB bare board defect detection device provided in an embodiment of the present invention. Detailed Implementation
[0047] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations thereof. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.
[0048] Example 1
[0049] This embodiment describes a method for detecting defects in bare PCB boards, such as... Figure 1 As shown, the specific steps include the following:
[0050] Step A: Obtain PCB bare board data and preprocess the PCB bare board data.
[0051] The PCB bare board data mainly consists of PCB bare board images. To facilitate inspection, this invention will standardize the size of the acquired PCB bare board images, specifically adjusting the size to 1153×864 pixels.
[0052] Step B: Use a pre-built PCB bare board defect detection model to detect and classify the pre-processed PCB bare board data to obtain the PCB bare board defect detection results. The PCB bare board defect detection model uses an improved YOLOv10 neural network.
[0053] This invention improves upon the traditional YOLOv10 neural network, and the improved YOLOv10 neural network structure is as follows: Figure 2As shown, the main components include a backbone network, a neck network, and a detection head network. This invention incorporates a feature fusion attention network module suitable for image dehazing into the first position of the backbone network. It replaces the second and third convolutional modules in the original backbone network and the first convolutional module in the neck network with a diversified branching module (DBB). A branch structure is introduced into the neck network to form a new depthwise separable weighted residual segmentation module (DWRSeg). The original downsampling cross-stage local fusion module (C2f) is replaced by a combination of the depthwise separable weighted residual segmentation module and the cross-stage local fusion module, and renamed as the expanded residual fusion module (C2f_DWRSeg). By improving the neural network structure, this invention adapts to the more complex structural requirements and higher accuracy requirements of current PCB bare board inspection, thereby improving the accuracy and regression rate of PCB bare board defect detection.
[0054] The backbone network comprises, in sequence, a feature fusion attention network module, a first convolutional layer, a first diversified branch module (DBB), a first cross-stage local fusion module (C2f), a second diversified branch module (DBB), a second cross-stage local fusion module (C2f), a first spatial-channel downsampling module, a third cross-stage local fusion module (C2f), a second spatial-channel downsampling module, a cross-stage local fusion-contextual inlay block module, a fast spatial pyramid pooling module, and a parallel spatial attention module. The feature fusion attention network module significantly improves image contrast and detail rendering, allowing downstream detection networks to perform tasks based on higher-quality feature inputs. The diversified branch module enriches the feature extraction process through a multi-branch structure, thereby enhancing the network's ability to model complex input scenes and diverse target features.
[0055] The feature fusion attention network module adopts the existing module structure, which mainly includes a shallow feature extraction unit, several cascaded feature fusion groups, a global fusion unit, and an image reconstruction unit.
[0056] In this embodiment of the invention, the structure of the cross-stage local fusion module is as follows: Figure 3 As shown, it includes a first convolutional batch normalization activation component, a feature channel segmentation component, a bottleneck component, a feature concatenation component, and a second convolutional batch normalization activation component.
[0057] In this embodiment of the invention, the feature fusion of the spatial-channel downsampling module can be expressed as:
[0058] ;
[0059] in, This represents the weighted fusion of feature maps, which incorporates features from multiple scales. This represents a weighted summation of features across all layers, where l represents the index of the current feature layer, and L represents the total number of feature layers. is the weight of the feature at layer l, representing the importance of the feature at layer l in the fusion process. This represents the feature map of the l-th layer.
[0060] In this embodiment of the invention, the structure of the diversified branch module is as follows: Figure 4 As shown, the diversified branching module processes the input features through multiple parallel branch paths, and then fuses the outputs of these branches to achieve multi-dimensional mining and integration of image features. The diversified branching module includes a convolution module, a batch normalization module, a convolution-normalization-activation module, a dilated convolution module, a depthwise convolution-pointwise convolution-normalization module, a pooling-convolution module, a convolution-normalization module, and a fifth stitching module, all connected in sequence. Furthermore, the diversified branching module introduces multi-scale, multi-parameter branching structures to adapt to feature representations of different scales, shapes, and textures.
[0061] In the diversified branching module, the input features are first decomposed into several components, which are then processed separately through multiple parallel branches. Each branch employs convolutional kernels of different sizes, different types of convolutional operators, or different dilation rates to extract and represent features from various perspectives, including local details, global structure, and mesoscale information. Each parallel branch outputs a feature map after processing through its own multiple convolution-normalization-activation modules. These feature maps are then concatenated in the feature fusion module. Through this feature decomposition and parallel processing, combined with subsequent concatenation and fusion steps, the diversified branching module effectively integrates multi-dimensional feature information, resulting in richer and higher-quality feature representations.
[0062] In this embodiment of the invention, the structure of the fast spatial pyramid pooling module is as follows: Figure 5 As shown, it includes a first convolutional batch normalized activation layer, a first max pooling 2D layer, a second max pooling 2D layer, a third max pooling 2D layer, a splicing layer, and a second convolutional batch normalized activation layer; wherein, the outputs of the first convolutional batch normalized activation layer, the first max pooling 2D layer, and the second max pooling 2D layer are all connected in parallel to the splicing layer.
[0063] The structure of the parallel spatial attention module is as follows: Figure 6 As shown, it includes a 1×1 convolutional layer, a feature segmentation unit, and a splicing layer. The feature segmentation unit consists of a multi-head self-attention layer and a feedforward neural network layer.
[0064] The parallel spatial attention module can be represented as:
[0065] ;
[0066] in, Spatial attention weights representing positions (x, y) are used to adjust the importance of specific positions. The activation function is Sigmoid, with weights restricted to [0,1]. The weight matrix of the convolution kernel is used to extract spatial information from the input features. This represents the convolution operation. The representation involves feature concatenation and global average pooling. and global max pooling The results are spliced together along the channel dimension.
[0067] like Figure 2 As shown, the neck network includes a first upsampling module, a first stitching module, a first extended residual fusion module (C2f_DWRSeg), a second upsampling module, a second stitching module, a second extended residual fusion module (C2f_DWRSeg), a third diversified branch module (DBB), a third stitching module, a third extended residual fusion module (C2f_DWRSeg), a third spatial-channel downsampling module, a fourth stitching module, and a cross-stage fast partial connection-context inline block module (C2fCIB). In this architecture, the parallel spatial attention module of the backbone network is connected to the first upsampling module. The first concatenation module concatenates the features output by the first upsampling module with the features output by the third cross-stage local fusion module (C2f) and then inputs the concatenation into the first extended residual fusion module (C2f_DWRSeg). The features output by the first extended residual fusion module (C2f_DWRSeg) are then upsampled by the second upsampling module. The second concatenation module concatenates the features output by the second upsampling module with the features output by the second cross-stage local fusion module (C2f) and then inputs the concatenation into the second extended residual fusion module. (C2f_DWRSeg) and the third diversification branch module (DBB); the features output by the third diversification branch module (DBB) and the features output by the first extended residual fusion module (C2f_DWRSeg) are concatenated by the third concatenation module and then input into the third extended residual fusion module (C2f_DWRSeg) and the third spatial-channel downsampling module. The features output by the third spatial-channel downsampling module and the features output by the parallel spatial attention module are concatenated by the fourth concatenation module and then input into the cross-stage fast partial connection-context inlay module (C2fCIB).
[0068] like Figure 7 , Figure 8As shown, the cross-stage fast partial connection-context inline block module includes a first 1×1 convolutional layer, a context inline block, a splicing layer, and a second 1×1 convolutional layer. The context inline block comprises a first 3×3 depthwise separable convolutional layer, a first 1×1 convolutional layer, a second 3×3 depthwise separable convolutional layer, a second 1×1 convolutional layer, and a third 3×3 depthwise separable convolutional layer, all sequentially connected in series.
[0069] The detection head network consists of three detection heads. The features output by the second extended residual fusion module, the third extended residual fusion module, and the cross-stage fast partial connection-context embedding block module are respectively output to the three detection heads, such as... Figure 9 As shown, the detection head adopts a one-to-many detection head with regression and classification functions. The three detection heads detect defects of different sizes respectively, corresponding to small, medium and large defects in sequence. Finally, the detection head network will integrate the detection results of the three detection heads to output the final PCB bare board defect detection result.
[0070] In the feature extraction stage, this invention replaces the fourteenth, seventeenth, and twentieth layers of the neck network with a designed extended residual fusion module. Structurally, the extended residual fusion module includes a depthwise separable weighted residual segmentation module and a cross-stage local fusion module. The structure of the depthwise separable weighted residual segmentation module is as follows: Figure 10 As shown.
[0071] The model of the extended residual fusion module can be represented as follows:
[0072]
[0073] in, Represents the pixel position extracted by depthwise separable convolution. The output characteristics, This represents a depthwise convolution operation, which performs independent spatial convolution on each channel of the input X. This indicates a pointwise convolution operation, using a 1×1 convolution kernel to achieve feature fusion between channels.
[0074]
[0075] in, This represents the output feature map of the extended residual fusion module. This represents the features extracted through depthwise separable convolution, and X represents the input feature map of the expanded residual fusion module.
[0076] In this embodiment of the invention, an improved YOLOv10 neural network is trained to obtain a trained PCB bare board defect detection model, which is then used to detect PCB bare board defects. The training method is as follows:
[0077] Step 1: Obtain a PCB bare board dataset containing multiple categories of PCB bare board data. The defect categories include six types: missing holes, rodent bites, open circuits, short circuits, stray copper, and branch lines.
[0078] Step 2: Preprocess the PCB bare board images in the PCB bare board dataset. The preprocessing operations include: unifying the size of the original PCB bare board images using image scaling and adaptive scaling techniques, performing data augmentation operations on the images, including horizontal flipping, contrast enhancement, and noise reduction, and then using the LabelImg annotation tool to annotate the defects of the enhanced images in the radar images. Finally, the annotated images are divided into training and validation sets at an 8:2 ratio and converted into a YOLO format dataset.
[0079] Because the number of bare PCB samples is limited, this embodiment uses small-sized bare PCB images to create training and testing datasets, and trains and improves the YOLOv10 neural network through small-sized bare PCB images and their defect detection.
[0080] Step 3: Input the YOLO format training set into the improved YOLOv10 neural network for PCB bare board defect detection and classification. Calculate the total model loss based on the deviation between the detection results and the true labels. Then optimize the model parameters based on the total model loss until the total model loss meets the preset requirements to obtain the optimal model parameters. The trained improved YOLOv10 neural network is obtained based on the optimal model parameters, which is the trained PCB bare board defect detection model.
[0081] In this embodiment of the invention, the formula for calculating the total model loss is as follows:
[0082] ;
[0083] in, This represents the total loss of the model. Cross-entropy loss is used for pixel-level classification and measures the difference between the model's predicted class probability distribution and the true label. Boundary loss is used to optimize the segmentation accuracy of object boundaries; For cross-entropy loss weights, The boundary loss weights are used.
[0084] ;
[0085] Where N is the total number of pixels in the feature map, and C is the total number of categories. The true label for pixel i belonging to category c. Predict the probability that pixel i belongs to category c for the model.
[0086] Step 4: After training is complete, put the validation set into the optimal model to detect the type and location of defects in the bare PCB board and obtain the recognition results.
[0087] To verify the defect detection effect of the method of the present invention, this embodiment of the invention compares the method of the present invention with the traditional YOLOv neural network for defect detection on bare PCB boards. The experiment uses a camera to acquire images of bare PCB boards, with an acquisition size of size = 640 pixels × 640 pixels; the PCB image resolution is 1153 × 864 pixels; the LabelImg annotation tool is used to annotate the data of bare PCB boards, annotating 6 types of defects: missing hole, mouse bite, open circuit, short circuit, branch line, and spurious copper, with corresponding category labels of 0, 1, 2, 3, 4, and 5, and corresponding names of missing_hole, mouse_bite, open_circuit, short, spur, and spurious_copper. The ratio of training set to validation set is 8:2, and the dataset is saved in YOLO format.
[0088] The present invention is compared with the current mainstream one-stage object detection YOLO algorithm network model on the established dataset. The network settings parameters are shown in Table 1.
[0089] Table 1
[0090] 640×640 150 16 SGD 0.01
[0091] The equipment parameters used in the experiment are as follows: CPU: Intel(R) Xeon(R) Gold 5418Y; GPU: NVIDIA RTX4090; Operating system: Ubuntu 22.04; Python interpreter information: Python 3.12, PyTorch 2.3.1, CUDA12.1; The network detection results were evaluated using precision, recall, mAP50, and mAP50-95, and the comparison of the experimental results is shown in Table 2.
[0092] Table 2
[0093] YOLOv5 1772035 0.933 0.680 0.738 0.405 YOLOv6 4238738 0.920 0.694 0.750 0.454 YOLOv8 3012018 0.987 0.719 0.793 0.500 Model in this embodiment 2866560 0.929 0.724 0.823 0.532
[0094] As shown in Table 2, the method of this invention improves the mAP50 by 8.5%, 7.3%, and 3% respectively compared to YOLOv5, YOLOv6, and YOLOv8, proving that the improved YOLOv10 neural network of this invention has improved the accuracy of PCB bare board defect detection. The PCB bare board defect detection results of this embodiment are as follows: Figure 11 As shown.
[0095] Example 2
[0096] Based on the same inventive concept as Embodiment 1, this embodiment introduces a PCB bare board defect detection device, such as... Figure 12 As shown, it includes:
[0097] The preprocessing module is used to preprocess the bare PCB data.
[0098] The defect detection module is used to detect and classify pre-processed PCB bare board data using a pre-built PCB bare board defect detection model, and obtain PCB bare board defect detection results.
[0099] The PCB bare board defect detection model adopts an improved YOLOv10 neural network. The improvement method of the improved YOLOv10 neural network includes: adding a feature fusion attention network module at the first position of the backbone network, replacing the second and third convolutional modules of the backbone network with a diversified branch module, replacing the first convolutional module of the neck network with a diversified branch module, and replacing the cross-stage local fusion module used for downsampling in the neck network with an expanded residual fusion module.
[0100] The specific functions of each module described above are explained in the relevant content of the method in Embodiment 1, and will not be repeated here.
[0101] Example 3
[0102] Based on the same inventive concept as other embodiments, this embodiment introduces a computer-readable storage medium storing a computer program / instructions thereon, which, when executed by a processor, implements the steps of the PCB bare board defect detection method described in Embodiment 1.
[0103] In summary, this invention employs a feature fusion attention network module suitable for image dehazing, added to the first position of the backbone network. This reduces visual interference caused by imaging environment, lighting conditions, or dust. Diverse branch modules replace the second and third convolutional modules in the original backbone network and the first convolutional module in the neck network. This helps the network better capture subtle differences in PCB texture and subtle changes between multi-layer structures, providing more accurate recognition support for defects of various shapes, sizes, and locations. Furthermore, a branch structure is introduced in the neck network to form a new depth-separable weighted residual segmentation module, replacing the downsampling cross-stage local fusion module and renaming it the extended residual fusion module. This makes the improved network more robust. This invention improves both the accuracy and recall rate of PCB bare board defect detection, solving the problems of insufficient recognition accuracy and high false positive rate in existing technologies when facing ultra-high density lines, complex multi-layer structures, and various micro-holes and micro-blind vias.
[0104] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0105] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0106] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0107] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0108] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.
Claims
1. A method for detecting defects in bare PCB boards, characterized in that, include: Preprocess the bare PCB data; The pre-built PCB bare board defect detection model is used to detect and classify the pre-processed PCB bare board data to obtain PCB bare board defect detection results; The PCB bare board defect detection model adopts an improved YOLOv10 neural network. The improvement method of the improved YOLOv10 neural network includes: adding a feature fusion attention network module at the first position of the backbone network, replacing the second and third convolutional modules of the backbone network with a diversified branch module, replacing the first convolutional module of the neck network with a diversified branch module, and replacing the cross-stage local fusion module used for downsampling in the neck network with an expanded residual fusion module. The expanded residual fusion module includes a depth-separable weighted residual segmentation module and a cross-stage local fusion module.
2. The PCB bare board defect detection method according to claim 1, characterized in that, The backbone network comprises, in sequence, a feature fusion attention network module, a first convolutional layer, a first diversified branch module, a first cross-stage local fusion module, a second diversified branch module, a second cross-stage local fusion module, a first spatial-channel downsampling module, a third cross-stage local fusion module, a second spatial-channel downsampling module, a cross-stage local fusion-contextual inline block module, a fast spatial pyramid pooling module, and a parallel spatial attention module.
3. The PCB bare board defect detection method according to claim 2, characterized in that, The feature fusion attention network module includes a shallow feature extraction unit, several cascaded feature fusion groups, a global fusion unit, and an image reconstruction unit.
4. The PCB bare board defect detection method according to claim 2, characterized in that, The diverse branch modules include, in sequence, a convolution module, a batch normalization module, a convolution-normalization-activation module, a dilated convolution module, a depthwise convolution-pointwise convolution-normalization module, a pooling-convolution module, a convolution-normalization module, and a fifth concatenation module.
5. The PCB bare board defect detection method according to claim 2, characterized in that, The neck network includes a first upsampling module, a first stitching module, a first extended residual fusion module, a second upsampling module, a second stitching module, a second extended residual fusion module, a third diversified branching module, a third stitching module, a third extended residual fusion module, a third spatial-channel downsampling module, a fourth stitching module, and a cross-stage fast partial connection-context embedding module. The parallel spatial attention module of the backbone network is connected to the first upsampling module. The first stitching module stitches the features output by the first upsampling module with the features output by the third cross-stage local fusion module and inputs them into the first extended residual fusion module. The features output by the first extended residual fusion module are upsampled by the second upsampling module. The second stitching module stitches the features output by the second upsampling module with the features output by the second cross-stage local fusion module and inputs them into the second extended residual fusion module and the third diversified branch module. The features output by the third diversified branch module and the features output by the first extended residual fusion module are stitched together by the third stitching module and input into the third extended residual fusion module and the third spatial-channel downsampling module. The features output by the third spatial-channel downsampling module and the features output by the parallel spatial attention module are stitched together by the fourth stitching module and input into the cross-stage fast partial connection-context embedding module.
6. The PCB bare board defect detection method according to claim 5, characterized in that, The cross-stage local fusion-context-in-block module includes a first 1×1 convolutional layer, a context-in-block, a splicing layer, and a second 1×1 convolutional layer; The context-in-context block includes a first 3×3 depth-separable convolutional layer, a first 1×1 convolutional layer, a second 3×3 depth-separable convolutional layer, a second 1×1 convolutional layer, and a third 3×3 depth-separable convolutional layer, which are connected in series.
7. The PCB bare board defect detection method according to claim 5, characterized in that, The model representation of the extended residual fusion module is as follows: ； in, This represents the pixel position extracted by depthwise separable convolution in the dilated residual fusion module. The output characteristics, This indicates that a depthwise convolution operation is performed on the input feature map X. This represents a pointwise convolution operation; ； in, This represents the output feature map of the extended residual fusion module. This represents the features extracted through depthwise separable convolution, and X represents the input feature map of the expanded residual fusion module.
8. The PCB bare board defect detection method according to claim 1, characterized in that, The model training loss function of the PCB bare board defect detection model is as follows: ； in, This represents the total loss of the model. For cross-entropy loss, For boundary loss, For cross-entropy loss weights, Weights for boundary loss; ； Where N is the total number of pixels in the feature map, and C is the total number of categories. The true label for pixel i belonging to category c. Predict the probability that pixel i belongs to category c for the model.
9. A PCB bare board defect detection device, characterized in that, include: The preprocessing module is used to preprocess the bare PCB data. The defect detection module is used to detect and classify the pre-processed PCB bare board data using a pre-built PCB bare board defect detection model, and obtain the PCB bare board defect detection results. The PCB bare board defect detection model adopts an improved YOLOv10 neural network. The improvement method of the improved YOLOv10 neural network includes: adding a feature fusion attention network module at the first position of the backbone network, replacing the second and third convolutional modules of the backbone network with a diversified branch module, replacing the first convolutional module of the neck network with a diversified branch module, and replacing the cross-stage local fusion module used for downsampling in the neck network with an expanded residual fusion module. The expanded residual fusion module includes a depth-separable weighted residual segmentation module and a cross-stage local fusion module.
10. A computer-readable storage medium having a computer program / instructions stored thereon, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the PCB bare board defect detection method according to any one of claims 1-8.