A circuit board quality state evaluation method and system based on edge computing

Abstract

This invention relates to the field of intelligent sensor technology, specifically to a method and system for assessing the quality status of circuit boards based on edge computing. The method includes first performing distortion correction and radiosity compensation on the raw photoelectric signal, reconstructing it into a multispectral brightness response map and grayscale distribution data. Then, prior slicing is performed using a component netlist to decouple and extract physical contours and surface textures. Through topology tracing and low-bit sparse quantization, core deformation features are preserved while significantly reducing edge computing memory consumption. Based on local fitting and spatial integration, wetting angle, three-dimensional envelope volume, and pin coplanarity deviation are calculated to construct a multi-dimensional physical feature vector. Risk classification is performed using a static lookup table embedded in the underlying layer, and graph search is used to locate electrical network link bottlenecks, generating a low-level industrial bus message containing failure semantics. This invention achieves global risk interception through physical space mapping and electrical topology linkage.

Description

Technical Field

[0001] This invention relates to the field of intelligent sensor technology, specifically to a method and system for evaluating the quality status of circuit boards based on edge computing. Background Technology

[0002] As the electronics manufacturing industry moves towards higher density and miniaturization, the package size of components in surface mount technology continues to shrink, leading to a dramatic increase in the assembly density of circuit boards. Solder joints, as the physical and electrical bridge connecting electronic components and the circuit board, directly determine the long-term fatigue resistance and operational reliability of the entire electronic system through their microscopic geometry and wetting quality. Therefore, utilizing automated optical inspection technology for non-contact measurement and quality assessment of the physical state of circuit board solder joints has become an indispensable part of modern electronic assembly processes.

[0003] In existing automated optical inspection technologies, multi-angle, multi-spectral array illumination systems are typically used to strobe-expose circuit boards to obtain photoelectric response images reflecting different physical aspects of the solder joints. Subsequently, computer vision or deep learning algorithms are used to extract features and classify the images. In recent years, to reduce production line network latency and improve system integration, the industry has increasingly favored moving image processing and analysis models down to front-end smart cameras or edge computing nodes, employing an "edge computing" architecture to perform real-time quality assessment.

[0004] However, when combining high-precision optical measurement with edge computing, a fundamental technical bottleneck is encountered: after solder solidifies, it exhibits typical high-brightness metallic specular reflection characteristics. In order to accurately reconstruct this microscopic three-dimensional morphology, existing high-precision detection models usually need to perform global deep convolution operations or point cloud fitting on high-dimensional multispectral image tensors in order to extract the real physical geometric contours from the complex diffuse reflection and specular specular noise.

[0005] This processing method often involves massive floating-point operations and extremely high memory bus bandwidth usage. While this method can run smoothly on centralized industrial control computers with ample computing power, it is highly susceptible to excessively high processing latency or memory overflow when directly deploying such high-dimensional image processing and physical measurement models on edge computing nodes (such as integrated smart sensors) where power consumption, memory bandwidth, and underlying computing power are strictly limited. Conversely, if conventional image scaling or general lightweight networks are used for simple dimensionality reduction, the loss of microscopic physical edge features will prevent the high-precision measurement of geometric and physical properties such as pin coplanarity and three-dimensional envelope volume.

[0006] In summary, how to achieve high-precision measurement and condition assessment of the microscopic three-dimensional morphology and physical geometric properties of solder joints while meeting the requirements of real-time edge computing is a technical problem that urgently needs to be solved in this field.

[0007] To address this, a method and system for evaluating the quality status of circuit boards based on edge computing is proposed. Summary of the Invention

[0008] The purpose of this invention is to provide a method and system for evaluating the quality status of circuit boards based on edge computing. This method achieves global risk interception through physical space mapping and electrical topology linkage. The process includes first performing distortion correction and radiosity compensation on the original photoelectric signal, reconstructing it into a multispectral brightness response map and grayscale distribution data. Then, prior slicing is performed using the component netlist to decouple and extract physical contours and surface textures. Through topology tracing and low-bit sparse quantization, core deformation characteristics are preserved while significantly reducing edge computing memory consumption. Based on local fitting and spatial integration, wetting angle, three-dimensional envelope volume, and pin coplanarity deviation are calculated to construct a multi-dimensional physical feature vector. Risk classification is performed using a static lookup table embedded in the underlying layer, and graph search is used to locate electrical network link bottlenecks, generating a low-level industrial bus message containing failure semantics.

[0009] To achieve the above objectives, the present invention provides the following technical solution: A circuit board quality status assessment method based on edge computing includes: The system acquires the component package coordinate map, solder joint physical geometric constraint parameters, and underlying optical calibration parameters of the smart sensor on the circuit board to be tested. The smart sensor captures the original photoelectric conversion signal on the surface of the circuit board under a preset illumination sequence, and the smart sensor reconstructs the original photoelectric conversion signal into a multispectral brightness response map and spatial domain grayscale distribution data using the underlying optical calibration parameters. The lightweight analysis model is invoked, and the region is extracted using the multispectral brightness response map. The topological features of the solder climbing surface at the connection between the component pin and the pad are identified. The local surface texture contrast data and the edge displacement vector field relative to the component package coordinate map are calculated based on the spatial domain grayscale distribution data. By utilizing the topological features of the solder climb surface, local surface texture contrast data, and edge displacement vector field, the physical edge wetting angle, the three-dimensional envelope volume of the solder joint, and the pin coplanarity deviation value are calculated, and a multi-dimensional feature vector is constructed. The multidimensional feature vector is input into the state mapping model, and the output is a quantitative evaluation score of the physical health of a single solder joint; the quantitative evaluation scores of all solder joints on the circuit board to be inspected are summarized and output to an external monitoring terminal.

[0010] Preferably, the process of acquiring various data of the circuit board to be tested includes: parsing the electronic design automation file of the circuit board to be tested, extracting the physical center coordinates, rotation angles, and matching two-dimensional contour boundaries of each component, and constructing the component package coordinate map; retrieving a preset industrial electronic assembly acceptance standard database, extracting the standard solder climb height ratio, theoretical solder paste deposition volume, and pin coplanarity physical tolerance corresponding to each component package type, as the physical geometric constraint parameters of the solder joint; and reading the lens distortion mapping matrix, single-pixel physical spatial equivalent size, and white balance gain coefficient of the multispectral channel pre-stored in the non-volatile memory inside the smart sensor, as the underlying optical calibration parameters.

[0011] Preferably, the conversion process of the photoelectric conversion raw signal includes: using the clock interrupt signal of the edge computing node to synchronously trigger the multi-band array light source to alternately flash illumination according to the set spatial incident angle and wavelength timing; within each flash illumination cycle of the multi-band array light source, controlling the photoelectric coupling array inside the smart sensor to perform independent exposure, and collecting array level data including the high light reflection component and diffuse reflection component of the circuit board surface as the photoelectric conversion raw signal.

[0012] Preferably, the process of reconstructing the original photoelectric conversion signal into a multispectral brightness response map and spatial domain grayscale distribution data includes: performing pixel-level spatial coordinate interpolation correction on the original photoelectric conversion signal using the lens distortion mapping matrix in the underlying optical calibration parameters; performing radiance compensation and illuminance normalization processing on the corrected signal using the white balance gain coefficient in the underlying optical calibration parameters, and extracting the monochromatic brightness component to generate the spatial domain grayscale distribution data; and performing orthogonal splicing calculation on the feature channel dimension of multiple corrected signals obtained under different spatial incident angles and wavelength time sequences to generate the multispectral brightness response map characterizing the reflectivity gradient of the physical surface.

[0013] Preferably, the lightweight analysis model includes: a priori slicing layer: receiving the multispectral brightness response map and the spatial domain grayscale distribution data, generating physical bounding boxes corresponding to each pad using the component package coordinate map, and performing synchronous slicing extraction within the physical bounding boxes to construct local multispectral feature blocks and local grayscale feature blocks respectively; Decoupling mapping layer: The local multispectral feature blocks are separated into feature channels, and low-frequency signal channels that characterize the surface geometric undulations are extracted as physical contour feature maps; at the same time, the local grayscale feature blocks are used to perform pixel gradient statistics to generate the local surface texture contrast data. Contour Topology Tracking Layer: Obtain the physical contour feature map, perform geometric edge tracking with the pixel gradient extreme points in the region as the tracking starting point, generate closed topology line features representing the boundary of the solder climbing surface; and simultaneously use the local grayscale feature blocks to perform gradient interpolation calculation to generate the edge displacement vector field; Sparse quantization layer: Extract the closed topology features, local surface texture contrast data and non-zero effective nodes in the edge displacement vector field to construct a sparse feature matrix, and perform low bit precision compression mapping on the sparse feature matrix to reconstruct and output the solder climb surface topology features, local surface texture contrast data and edge displacement vector field in compressed data format.

[0014] Preferably, the process of calculating the physical edge wetting angle, the three-dimensional envelope volume of the solder joint, and the coplanarity deviation of the pins, and constructing a multi-dimensional feature vector, includes: using the curvature change gradient of the solder climb surface topology and the edge displacement vector field, calculating the spatial tangent equation at the interface between the solder and the pad, and solving for the dihedral angle between the spatial tangent and the physical plane of the substrate, as the physical edge wetting angle; constructing a microscopic three-dimensional envelope surface based on the solder climb surface topology, and combining the single-pixel physical spatial equivalent size in the underlying optical calibration parameters, calculating the effective pixel set under the microscopic three-dimensional envelope surface by performing spatial discrete integration. The three-dimensional envelope volume of the solder joint is calculated; the vertical height offset component in the edge displacement vector field corresponding to each pin of the component to be tested is extracted, and the reference coplanar physical plane of the component is fitted using the least squares method. The maximum orthogonal distance of each pin from the reference coplanar physical plane is calculated as the pin coplanarity deviation value; the physical edge wetting angle, the three-dimensional envelope volume of the solder joint, the pin coplanarity deviation value, and the local surface texture contrast data characterizing cold solder defects are normalized in terms of dimensions, and tensor splicing is performed on the feature dimension to construct the multi-dimensional feature vector characterizing the comprehensive physical health of a single solder joint.

[0015] Preferably, the process of outputting a quantitative assessment score for the physical health of a single solder joint includes: inputting the multidimensional feature vector into the state mapping model, wherein the state mapping model is a multidimensional physical tolerance envelope based on industrial acceptance standards; calculating the spatial deviation Euclidean distance of the multidimensional feature vector from the multidimensional physical tolerance envelope in the feature space; outputting a discrete level value representing the risk of mechanical fracture or cold solder joint at a single solder joint based on a preset danger step interval of the spatial deviation Euclidean distance, as the quantitative assessment score for the physical health of a single solder joint; and parsing the electronic design netlist file of the circuit board to be tested to extract each solder joint. The electrical series-parallel topology in the underlying circuit logic network is used for link retrieval. The quantitative evaluation scores of all solder joints on each electrical logic link are compared, and the maximum limit deviation value representing the highest open circuit risk on each link is extracted as the short-board evaluation extreme value that determines the overall physical conduction state of the link. The short-board evaluation extreme values ​​of all electrical logic links, the two-dimensional physical coordinates of the defective solder joints that generate the extreme values, and the failure feature classification codes are encapsulated in a data structure to generate an evaluation result feature vector. The evaluation result feature vector is then sent to the external monitoring terminal via the industrial fieldbus protocol of the edge computing node to execute corresponding actions.

[0016] An edge computing-based circuit board quality status assessment system includes: The system acquires the component package coordinate map, solder joint physical geometric constraint parameters, and underlying optical calibration parameters of the smart sensor on the circuit board to be tested. The smart sensor captures the original photoelectric conversion signal on the surface of the circuit board under a preset illumination sequence, and the smart sensor reconstructs the original photoelectric conversion signal into a multispectral brightness response map and spatial domain grayscale distribution data using the underlying optical calibration parameters. The edge computing module calls a lightweight analysis model, uses multispectral brightness response maps to extract regions, identifies the solder climbing surface topology features at the connection between component pins and pads, and calculates local surface texture contrast data and edge displacement vector field relative to the component package coordinate map based on spatial domain grayscale distribution data. By utilizing the topological features of the solder climb surface, local surface texture contrast data, and edge displacement vector field, the physical edge wetting angle, the three-dimensional envelope volume of the solder joint, and the pin coplanarity deviation value are calculated, and a multi-dimensional feature vector is constructed. The multidimensional feature vector is input into the state mapping model, and the output is a quantitative evaluation score of the physical health of a single solder joint; the quantitative evaluation scores of all solder joints on the circuit board to be inspected are summarized and output to an external monitoring terminal.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. By using a cascaded architecture of prior slicing of the map, illuminance decoupling and dimensionality reduction, topology tracing and sparse matrix quantization, the massive raster pixel stream is dimensionality reduced and purified into extremely lightweight closed topology lines and sparse feature matrices. This mechanism tightly maps the data stripping action of machine vision with the heterogeneous computing power of the edge chip (such as CPU truncation and NPU quantization), ensuring high-speed flow and lossless bit-width compression of micro-geometric features in a low-computing-power environment.

[0018] 2. By performing spatial tangent equation solving, envelope discrete integration, and orthogonal deviation fitting calculation on topological features and displacement vector fields, the pixel gradient features of the two-dimensional plane are transformed into a geometric measurement process in three-dimensional space. Combined with the spatial equivalent dimensions in the underlying optical calibration parameters, three specific numerical indicators reflecting the solder morphology—edge wetting angle, absolute volume, and pin coplanarity—are directly derived. This enables the state mapping model to obtain data input with real physical dimensions, avoiding the problem of blurred judgment boundaries that may occur when simply relying on abstract image textures for classification.

[0019] 3. By introducing a multi-dimensional physical tolerance envelope and an extreme value retrieval mechanism for the electrical series-parallel topology of the underlying circuit, the evaluation criteria are expanded from the appearance of a single solder joint to the entire circuit logic link. After obtaining the quantified deviation of each solder joint, the system extracts the short board extreme value that determines the link conduction state based on the netlist file, which serves as the basis for generating the final interception command. The circuit conduction logic of electronic engineering is used as the constraint condition for visual judgment, avoiding false alarms of the entire board caused by local defects of non-current-carrying critical pins, and reducing the invalid interception rate of the back end of the production line from the process perspective. Attached Figure Description

[0020] Fig. 1 A schematic diagram of a circuit board quality status assessment method based on edge computing provided by the present invention; Fig. 2 A schematic diagram of a circuit board quality status assessment system based on edge computing provided by the present invention; Fig. 3 This is a schematic diagram illustrating the process of calculating the pin coplanarity deviation value provided by the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Please see Figs. 1 to 3This invention provides a method and system for evaluating the quality status of circuit boards based on edge computing. The technical solution is as follows: A circuit board quality status assessment method based on edge computing, specifically as follows: Fig. 1 and Fig. 2 As shown, it includes: The system acquires the component package coordinate map, solder joint physical geometric constraint parameters, and underlying optical calibration parameters of the smart sensor on the circuit board to be tested. The smart sensor captures the original photoelectric conversion signal on the surface of the circuit board under a preset illumination sequence, and the smart sensor reconstructs the original photoelectric conversion signal into a multispectral brightness response map and spatial domain grayscale distribution data using the underlying optical calibration parameters. The lightweight analysis model is invoked, and the region is extracted using the multispectral brightness response map. The topological features of the solder climbing surface at the connection between the component pin and the pad are identified. The local surface texture contrast data and the edge displacement vector field relative to the component package coordinate map are calculated based on the spatial domain grayscale distribution data. By utilizing the topological features of the solder climb surface, local surface texture contrast data, and edge displacement vector field, the physical edge wetting angle, the three-dimensional envelope volume of the solder joint, and the pin coplanarity deviation value are calculated, and a multi-dimensional feature vector is constructed. The multidimensional feature vector is input into the state mapping model, and the output is a quantitative evaluation score of the physical health of a single solder joint; the quantitative evaluation scores of all solder joints on the circuit board to be inspected are summarized and output to an external monitoring terminal.

[0023] Example 1: Furthermore, the process of acquiring various data of the circuit board under test includes: parsing the electronic design automation file of the circuit board under test, extracting the physical center coordinates, rotation angles, and matching two-dimensional contour boundaries of each component, and constructing the component package coordinate map; retrieving the preset industrial electronic assembly acceptance standard database, extracting the standard solder climb height ratio, theoretical solder paste deposition volume, and pin coplanarity physical tolerance corresponding to each component package type, as the physical geometric constraint parameters of the solder joint; and reading the lens distortion mapping matrix, single pixel physical space equivalent size, and white balance gain coefficient of the multispectral channel pre-stored in the non-volatile memory inside the smart sensor, as the underlying optical calibration parameters.

[0024] Specifically, the imported PCB design automation (DAI) file (such as ODB++ or Gerber format) is first parsed. The package layer and pad stack layer nodes within the file are traversed to extract the unique identifier of the component under test and its physical center coordinates and rotation angle in the global coordinate system. Then, using the physical center coordinates as the calculation reference and combining the rotation angle parameter, spatial translation and rotation matrix transformations are performed on the local two-dimensional contour boundaries of each pad of the component. Specifically, based on the relative coordinates of the pads in the local coordinate system of the component, a two-dimensional rotation matrix containing the rotation angle parameter is constructed to complete the rotation operation of the two-dimensional contour of the pads. Subsequently, using the physical center coordinates as the translation vector, a two-dimensional translation affine transformation is performed to unify the coordinate system of all pads to the global physical coordinate system of the PCB. Finally, the two-dimensional contours of the pads after coordinate transformation are topologically associated with the corresponding component identifiers to construct and output the component package coordinate map.

[0025] Subsequently, the component package type obtained from the above steps is extracted as a comparison keyword, and a search and matching is performed in the preset industrial electronic assembly acceptance standard database. According to the matched package type record, the system sequentially extracts the lower limit of the target solder climb height ratio corresponding to the type, reads the theoretical solder paste deposition volume reference value calculated based on the standard stencil aperture parameters, and extracts the maximum vertical height difference threshold allowed for adjacent pins of the package type. Specifically, the calculation process is as follows: extract the length and width dimensions of the stencil aperture in the electronic design automation file, calculate the initial solder paste printing volume in combination with the preset stencil thickness parameters, and multiply the initial solder paste printing volume by the preset solder paste alloy powder volume ratio coefficient (e.g., 50% volume shrinkage rate) to calculate the theoretical solder paste deposition volume reference value after reflow solidification; and extract the package type, and perform structured packaging of the three types of tolerance values ​​obtained above to generate the physical geometric constraint parameters of the solder joint specific to the component.

[0026] Simultaneously, the system reads the lens radial and tangential distortion mapping matrix data generated during the factory testing using a standard calibration board, obtains the equivalent scaling factor used to convert the single-pixel side length of the digital image to the actual physical micrometer-level size, and extracts the multispectral channel relative white balance gain coefficients pre-determined for the multi-band array stroboscopic light source. The system performs array parsing and dimension alignment on the above-mentioned independent optical calibration data, and reassembles them into unified underlying optical calibration parameters for subsequent optical image distortion correction and physical size conversion steps. Specifically, the dimension alignment and reassembly process includes: performing tensor flattening on the high-dimensional lens distortion mapping matrix and the multispectral channel relative white balance gain coefficients to convert them into a one-dimensional data vector; then, using the equivalent scaling factor as an independent feature channel, performing channel-level concatenation with the flattened one-dimensional data vector to construct a one-dimensional structured parameter sequence, which serves as the unified underlying optical calibration parameters.

[0027] By analyzing electronic design documents, extracting industrial assembly acceptance standards, and reading underlying optical calibration data, a physical mapping path between digital pixels and microscopic entities was constructed. This provides a measurement benchmark with absolute physical dimensions and an objective industry theoretical tolerance boundary for subsequent model topology calculations. Thus, without human intervention, the automated flow and traceability of the entire microscopic physical measurement process were ensured.

[0028] Furthermore, the conversion process of the original photoelectric conversion signal includes: using the clock interrupt signal of the edge computing node to synchronously trigger the multi-band array light source to alternately flash illumination according to the set spatial incident angle and wavelength sequence; within each flash illumination cycle of the multi-band array light source, controlling the photoelectric coupling array inside the smart sensor to perform independent exposure, and collecting array level data including the high light reflection component and diffuse reflection component of the circuit board surface as the original photoelectric conversion signal.

[0029] The microcontroller or field-programmable gate array at the bottom of the edge computing node generates a fixed-period clock interrupt signal by configuring an internal hardware timer. In the response routine triggered by each clock interrupt, the system sends multiple high and low level trigger pulses to the external constant current light source controller through general-purpose input / output pins. After receiving the trigger pulses, the light source controller sequentially lights up multi-band light-emitting diodes arranged in a ring or hemispherical array according to the timing logic pre-programmed in the register. During this process, light sources of different wavelengths (such as red, green, and blue light) are allocated to different spatial incident elevation angles (such as high-angle coaxial light, medium-angle ring light, and low-angle dark field light), realizing a strict timing alternation of spatial angle and spectral wavelength.

[0030] Within the same hardware clock cycle of the output light source trigger pulse, the edge computing node sends a synchronization exposure level signal to the external trigger pin of the optocoupler array (such as a global shutter CMOS image sensor) inside the smart sensor via another pin with a fixed delay setting. Specifically, the set duration of the fixed delay is greater than the rise time of the array light source reaching its steady-state emission peak, and the pulse width of the synchronization exposure level signal is limited to the duration of the array light source being in its rated brightness flat-top period, to ensure that the CMOS image sensor completes charge integration within the range where the light source brightness is absolutely stable. After receiving the synchronization signal, the optocoupler array forcibly clears the residual charge of the previous frame and starts the integration exposure stage of the global pixel array. This exposure integration time window is strictly limited by the hardware firmware to the flicker illumination cycle of the current single-band array light source, to ensure that each exposure captures only a specific combination of wavelength and spatial incident angle for the reflective properties.

[0031] At the end of each integration exposure cycle, the analog-to-digital converter inside the optocoupler array converts the accumulated photogenerated charge on each pixel into discrete digital voltage values. For high-elevation-angle stroboscopic illumination cycles, this voltage value mainly characterizes the specular reflection component of flat areas and smooth curved surfaces of the solder; for low-elevation-angle stroboscopic illumination cycles, this voltage value mainly characterizes the diffuse reflection component of pad edges and rough pin contours. Subsequently, the optocoupler array packages these discrete digital voltage values ​​into a standard image data stream, which is then transmitted to the dynamic random access memory of the edge computing node in a continuous multi-frame interleaved manner via a mobile industrial processor interface or direct memory access channel. Specifically, during the transmission process, the underlying driver of the edge computing node triggers an interrupt through the falling edge of the hardware field synchronization signal, injecting the corresponding light source wavelength and spatial elevation angle state encoding identifier into the row concealment period or data header of each frame of image data, establishing a frame sequence index dictionary of image frames and physical lighting states, and splicing them to construct a multi-channel array level data matrix containing temporal and spectral dimensions, which serves as the original signal of the optocoupler conversion for subsequent analysis. Specifically, the construction process of the multi-channel array level data matrix is ​​as follows: the frame sequence index dictionary is parsed, and two-dimensional single-channel grayscale data frames with N different incident elevation angles and M different spectral wavelengths obtained under the same physical coordinates to be detected are orthogonally stacked in the feature channel dimension to generate a three-dimensional structured original signal tensor with tensor dimensions of H×W×(N×M), where H and W are the number of effective physical pixel rows and columns of the optocoupler array, respectively.

[0032] By linking the hardware timing interrupt of the edge computing node with the multi-band array light source and optocoupler array, forced physical synchronization between the optical illumination sequence and the image acquisition window is achieved. This eliminates the interference of ambient stray light and dynamic fluctuations in metal reflection on signal acquisition, ensuring that each frame of raw level data can accurately carry high-dimensional optical components at a specific incident angle and wavelength. This completes the initial decoupling of physical spatial features at the underlying hardware level, providing a high signal-to-noise ratio raw data source with spatiotemporal alignment for subsequent topology reconstruction.

[0033] Furthermore, the process of reconstructing the original photoelectric conversion signal into a multispectral brightness response map and spatial domain grayscale distribution data includes: using the lens distortion mapping matrix in the underlying optical calibration parameters to perform pixel-level spatial coordinate interpolation correction on the original photoelectric conversion signal; using the white balance gain coefficient in the underlying optical calibration parameters to perform radiance compensation and illuminance normalization processing on the corrected signal, and extracting the monochromatic brightness component to generate the spatial domain grayscale distribution data; and performing orthogonal splicing calculation on the feature channel dimension of multiple corrected signals obtained under different spatial incident angles and wavelength time sequences to generate the multispectral brightness response map characterizing the reflectivity gradient of the physical surface.

[0034] For each frame of the acquired photoelectric conversion raw signal, the system first extracts the lens distortion mapping matrix from the underlying optical calibration parameters to establish a nonlinear mapping relationship between the raw distortion coordinate system and the standard physical imaging coordinate system. Specifically, the system iterates through each pixel position in the standard physical imaging coordinate system, using the radial and tangential distortion coefficients in the distortion mapping matrix to inversely calculate the corresponding source coordinate point in the raw signal matrix. Since the calculated source coordinates are usually non-integer, the system employs a bilinear interpolation algorithm to extract the level values ​​of the four adjacent pixels around the source coordinates and perform weighted calculations to obtain accurate resampled pixel values. Through this process, the raw level matrix, which contains barrel or pincushion distortion, is reconstructed into a corrected signal frame that conforms to the linear perspective projection law.

[0035] After completing spatial coordinate correction, the system extracts the white balance gain coefficient from the underlying optical calibration parameters and performs radiance compensation on the corrected signal. The system multiplies the signal intensity under different spectral wavelength channels by the corresponding gain coefficient to compensate for energy deviations caused by inhomogeneities in the light source emission spectrum and differences in the quantum efficiency of the photosensitive element. Based on the gain compensation, the system performs illuminance normalization processing, scaling the pixel grayscale values ​​to the preset nominal dynamic range. Subsequently, the system extracts the luminance component of a specific monochromatic band from the multi-channel data, or performs luminance weight aggregation on multiple spectral channels to generate a single-channel two-dimensional feature matrix. Specifically, the luminance weight aggregation process includes: extracting the preset luminance contribution ratio coefficient corresponding to each spectral channel, and weighting and summing the corrected channel signals to simulate a luminance distribution that conforms to human visual perception, thereby eliminating the color bias caused by a single narrow-band light source and generating the spatial domain grayscale distribution data. The process of determining the preset luminance contribution ratio coefficient includes: acquiring the multispectral raw signal of a standard 18% neutral gray card using the intelligent sensor described in this application under a standard light source environment; extracting the average response amplitude of the color card under different spectral channels; and using the constraint that the total luminance after weighted summation of each channel equals the standard luminance of neutral gray, calculating the luminance contribution ratio coefficient corresponding to each spectral channel by least squares method or by integral calculation based on the spectral sensitivity curve of the sensor's photosensitive element.

[0036] Finally, the system orthogonally stitches multiple signal frames acquired under different spatial incident angles and wavelengths, after the aforementioned correction and compensation processes, along the feature channel dimension according to the physical topological order of the light source. This orthogonal stitching refers to stacking signal frames at different illumination elevation angles and wavelengths as independent feature dimensions along the channel axis while maintaining complete spatial resolution alignment for each signal frame. This constructs a multidimensional tensor of shape (H, W, C), where C represents the total number of different illumination schemes. This process ensures that the multidirectional reflectivity features of the same physical spatial coordinate point have a strict physical mapping relationship in the tensor depth direction. Each independent two-dimensional image matrix is ​​considered a specific depth feature layer. Through tensor stacking operations, a multidimensional tensor containing height, width, and illumination dimension information is constructed. In this tensor, the vector sequence of each pixel in the depth direction completely records the reflection response intensity of the solder joint surface under illumination from different directions. By correlating the numerical gradients between channels within the tensor, a multispectral brightness response map is generated that characterizes the reflectivity gradient and micro-geometric undulations of the physical surface. Specifically, the calculation process of the numerical gradient correlation includes: calculating the grayscale change rate between adjacent illumination dimensions in the depth direction of the multidimensional tensor, or calculating the numerical ratio between a specific high elevation angle channel and a low elevation angle channel. This numerical difference is used to quantify the degree of deflection of each pixel on the solder surface relative to the normal direction, thereby transforming the multidimensional reflective intensity characteristics into the multispectral brightness response map that reflects the micro-slope undulations of the surface.

[0037] Furthermore, the lens distortion mapping matrix adopts the Brown-Conrady model, specifically including radial distortion coefficients and tangential distortion coefficients; the pixel-level spatial coordinate interpolation correction adopts a bilinear interpolation algorithm, which performs weighted operations on the four adjacent pixels around the corrected coordinates to obtain the resampled pixel value; the illumination normalization scales the pixel grayscale value to the standard 8-bit dynamic range of 0 to 255; the orthogonal stitching calculation stacks the corrected signal frames with different incident angles and wavelengths along the channel axis to construct a multidimensional tensor of shape (H, W, C), where C is the total number of different illumination schemes.

[0038] By correcting lens distortion and compensating for multi-band radiometry, the nonlinear original level signal is transformed into a set of physical features with spatial linearity and energy consistency. This eliminates the geometric distortion and illuminance bias introduced by the imaging system, ensuring that grayscale data and multispectral response maps can objectively reflect the true reflectivity gradient and curvature changes of the solder joint surface. This provides a standardized input source with physical dimension reference for subsequent lightweight analysis models.

[0039] Furthermore, the lightweight analysis model includes: a priori slicing layer: receiving the multispectral brightness response map and the spatial domain grayscale distribution data, generating physical bounding boxes corresponding to each pad using the component package coordinate map, and performing synchronous slicing extraction within the physical bounding boxes to construct local multispectral feature blocks and local grayscale feature blocks respectively; Decoupling mapping layer: The local multispectral feature blocks are separated into feature channels, and low-frequency signal channels that characterize the surface geometric undulations are extracted as physical contour feature maps; at the same time, the local grayscale feature blocks are used to perform pixel gradient statistics to generate the local surface texture contrast data. Contour Topology Tracking Layer: Obtain the physical contour feature map, perform geometric edge tracking with the pixel gradient extreme points in the region as the tracking starting point, generate closed topology line features representing the boundary of the solder climbing surface; and simultaneously use the local grayscale feature blocks to perform gradient interpolation calculation to generate the edge displacement vector field; Sparse quantization layer: Extract the closed topology features, local surface texture contrast data and non-zero effective nodes in the edge displacement vector field to construct a sparse feature matrix, and perform low bit precision compression mapping on the sparse feature matrix to reconstruct and output the solder climb surface topology features, local surface texture contrast data and edge displacement vector field in compressed data format.

[0040] The prior slicing layer first obtains the component package coordinate map, extracts the center physical coordinates and geometric dimensions of each pad, and converts the physical coordinates of each pad into pixel coordinates in the corresponding image space through a coordinate mapping algorithm. Using the center of each pad as the anchor point, combined with the geometric dimensions and reserving a specific proportion of edge redundant pixels, a rectangular physical bounding box covering the entire solder crawling area is generated. Specifically, the proportion of edge redundant pixels is determined according to the physical mounting tolerance of the component and the preset maximum width of solder wetting and spreading, usually set to 10% to 20% of the length and width of the pad, to ensure that the edge features of solder crawling can still be completely preserved within the slicing area when the component experiences a small probability of positional displacement. Subsequently, using the physical bounding box, a region truncation operation is performed on the synchronously input global multispectral brightness response map and global spatial domain grayscale distribution data. Independent data pointer addresses are allocated in memory to construct and store local multispectral feature blocks and local grayscale feature blocks for each independent solder joint.

[0041] The decoupling mapping layer decomposes the local multispectral feature block into multiple independent spectral channel feature maps through tensor dimension separation instructions. The system calls a preset edge-preserving smoothing operator (such as a bilateral filter or guided filter operator) to perform spatial domain convolution operations on the decomposed multi-channel features. While filtering out high-frequency noise textures that characterize surface crystal roughness, it retains the gradient abrupt change features of the solder climbing boundary, extracts signal channels that take into account both macroscopic curvature changes and physical boundary step responses, and reassembles them into the physical contour feature map. Specifically, the reassembly process includes: extracting the spectral channel corresponding to the high-angle incident light source as the main reference layer, and using the low-pass filter operator to filter out the grainy texture in this layer. Then, the low-frequency components of other angle channels are fused at the pixel level maximum value to obtain a single-channel physical contour feature map that reflects the overall geometric envelope of the solder. Simultaneously, the system performs pixel-level gradient statistics on the local grayscale feature block, uses a first-order differential operator to calculate the grayscale change rate of each pixel in the region, extracts statistical features that reflect the microscopic crystallization state or cold solder defects on the solder surface, and generates the local surface texture contrast data.

[0042] The contour topology tracing layer traverses the physical contour feature map to find the discrete point with the largest gradient change rate as the tracing starting point. Using this starting point as a reference, the system performs edge connectivity retrieval according to the orthogonal direction of the pixel gradient vectors, logically associating edge points that meet curvature continuity constraints. Specifically, the curvature continuity constraint means that when retrieving the next edge point, the angle between the current tracing vector and the candidate point vector is calculated. When this angle is less than a preset threshold (e.g., 15 to 30 degrees) and the pixel gradient magnitude remains above 50% of the global mean, it is determined to be a logically associated point. This ensures that the generated topology line is smooth and conforms to the physical morphology of solder fluid, generating a closed topology line feature representing the boundary of the solder climbing surface. During the tracing process, the system simultaneously extracts the local grayscale feature blocks and performs bilinear gradient interpolation calculations within the neighborhood of the topology line, optimizing the integer pixel-level edge positions into coordinate offsets, thereby generating the edge displacement vector field representing the micro-deformation trend of the edges.

[0043] The sparse quantization layer extracts the coordinates and attribute values ​​of valid nodes with non-zero values ​​in the closed topology features, local surface texture contrast data, and edge displacement vector field through a threshold filtering mechanism. The system rearranges these valid nodes into a sparse feature matrix using a coordinate list format or compressed sparse row format, discarding redundant zero-value regions in the matrix. Subsequently, the system performs low-bit-precision compression mapping, mapping the original floating-point data to integer data of a preset bit width (such as INT8 or INT4 format). Numerical normalization is achieved through truncation operators and scaling factors. Specifically, the scaling factor determination process includes: pre-calibrating the model statically using a set of standard solder joint sample data, statistically analyzing the distribution histogram of each feature layer's values, determining the saturation truncation threshold using KL divergence or maximum absolute value mapping methods, and calculating a fixed scaling factor to map floating-point numbers to integers to ensure that key gradient distribution details are preserved during compression. Finally, a data packet containing the solder climb surface topology features, local surface texture contrast data, and edge displacement vector field is reconstructed and output in compressed binary stream format.

[0044] Furthermore, in the prior slice layer, the generation process of the physical bounding box includes: using the center of each pad as an anchor point, expanding by a preset number of pixels in the horizontal and vertical directions as a boundary redundancy, wherein the expansion range of the boundary redundancy is 10% to 20% of the length and width of the pad, and the specific value is determined according to the physical mounting tolerance level of the component; preferably, for the IPC-A-610 Class 2 standard, the expansion ratio is 15%, and for the Class 3 high reliability requirement, the expansion ratio is 20%.

[0045] Furthermore, in the decoupling mapping layer, extracting the low-frequency signal channel specifically includes: performing spatial domain convolution operation on the local multispectral feature block using a bilateral filtering operator, wherein the spatial domain standard deviation is 2 to 5 pixels, and the value domain standard deviation is 10% to 15% of the corresponding channel's gray-scale dynamic range; separating the low-frequency components through a low-pass filter with a preset cutoff frequency, and retaining the signal channel characterizing the macroscopic curvature change of the solder climb boundary as a physical contour feature map.

[0046] Furthermore, in the contour topology tracking layer, discrete points with pixel gradient magnitudes greater than twice the standard deviation of the local neighborhood mean are used as tracking starting points. Edge connectivity is retrieved along the orthogonal gradient direction. When the angle between the tracking vectors of adjacent edge points is less than 25 degrees and the gradient magnitude remains above 50% of the global mean, they are determined to be logically related points. The gradient interpolation calculation adopts the bilinear interpolation method to optimize the integer pixel-level edge position into coordinate offset.

[0047] Through prior slicing, signal decoupling, topology tracing, and sparse quantization, a step-wise data compression from global massive pixels to local core features was achieved. Redundant backgrounds were removed using physical maps, and surface contours were stripped from optical reflection noise. Combined with low-bit quantization, the memory usage and computational load of edge nodes were significantly reduced. This ensured that the topological structure reflecting the physical evolution of solder joints could still be efficiently extracted even under limited computing power, thus providing structured feature vectors with clear physical meaning for the backend evaluation model.

[0048] Further, the process of calculating the physical edge wetting angle, the three-dimensional envelope volume of the solder joint, and the coplanarity deviation of the pins, and constructing a multi-dimensional feature vector, includes: using the curvature change gradient of the solder climbing surface topology and the edge displacement vector field, calculating the spatial tangent equation at the interface between the solder and the pad, and solving for the dihedral angle between the spatial tangent and the physical plane of the substrate, as the physical edge wetting angle; constructing a microscopic three-dimensional envelope surface based on the solder climbing surface topology, and combining the single-pixel physical spatial equivalent size in the underlying optical calibration parameters, calculating the physical edge wetting angle by performing spatial discrete integration on the effective pixel set under the microscopic three-dimensional envelope surface. The three-dimensional envelope volume of the solder joint is calculated; the vertical height offset component in the edge displacement vector field corresponding to each pin of the component under test is extracted, and the reference coplanar physical plane of the component is fitted using the least squares method. The maximum orthogonal distance of each pin from the reference coplanar physical plane is calculated as the pin coplanarity deviation value; the physical edge wetting angle, the three-dimensional envelope volume of the solder joint, the pin coplanarity deviation value, and the local surface texture contrast data characterizing cold solder defects are normalized in terms of dimensions, and tensor splicing is performed on the feature dimension to construct the multi-dimensional feature vector characterizing the comprehensive physical health of a single solder joint. The specific process is as follows: Fig. 3 As shown.

[0049] To calculate the physical edge wetting angle, the system first extracts the trajectory line with the highest rate of curvature change in the topological features of the solder climbing surface, using it as the physical boundary line between the solder and the pad surface. The system then uses each pixel on this physical boundary line as the center, combined with the offset value provided by the edge displacement vector field, to fit the spatial tangent equation of the solder surface at the boundary by calculating the distribution trend of the surface normal vector. Specifically, the construction process of the spatial tangent equation includes: extracting a 3×3 or 5×5 local neighborhood window centered on the pixel on the physical boundary line, and calculating the height gradient value of each pixel within this window in the X and Y axis directions. Specifically, the calculation of the height gradient value is based on: extracting the photoelectric response values ​​of different spatial incident elevation angle channels in the multispectral brightness response map, combined with the underlying calibration... Given the known incident spatial vectors of the light sources (i.e., the elevation and azimuth angles of each stroboscopic light source), the relative tilt angle and gradient parameters (p, q) of the pixel's surface are calculated based on the classical photometric stereoscopic reflection equation. Then, using the boundary line as the initial boundary for integration, a local two-dimensional path integral is performed on the surface gradient field, reconstructing the multispectral reflectivity gradient field into a physical height distribution matrix Z(x, y) reflecting the true shape. The partial derivatives of Z in the X and Y directions of the image coordinate system are calculated to construct a local tangent vector for cross product. The local normal vector of each pixel is obtained through vector cross product. Then, the least squares method is used to perform plane fitting on all spatial coordinate points within the local neighborhood window, thereby constructing the spatial tangent equation that accurately characterizes the local tilt of the solder surface. Subsequently, the system obtains the preset physical plane normal vector of the substrate, calculates the angle between the normal vector of the spatial tangent equation and the physical plane normal vector of the substrate, and obtains the dihedral angle value between the two planes through complementary angle conversion. This value is used as the physical edge wetting angle characterizing the degree of solder wetting of the pad. Specifically, the calculation of the height gradient value is based on the following premises: considering the specular reflection characteristics of the solder surface, when extracting the photoelectric response values ​​of channels with different spatial incident elevation angles, the original image is first separated by a multi-scale Retinex algorithm or guided filtering method, and the diffuse reflection component is extracted as an effective signal; then, combined with the known incident space vector of the light source in the underlying calibration parameters, the surface gradient is solved by a modified photometric stereoscopic reflection equation, wherein a specular reflection correction coefficient is introduced into the reflection equation, and this coefficient is pre-determined by a standard specular solder joint calibration component.

[0050] To calculate the three-dimensional envelope volume of the solder joint, the topological features of the solder climbing surface are used as a height field distribution map. The equivalent physical spatial dimensions of a single pixel in the underlying optical calibration parameters are then used. The physical height distribution matrix Z(x, y) reconstructed based on photometric stereo vision and gradient integral in the previous steps is extracted as the physical height value of the pixel set, and the physical area corresponding to the bottom area of ​​a single pixel is calculated. Subsequently, within the physical bounding box, discrete spatial integration is performed on all effective pixels located below the solder envelope surface. This involves multiplying the physical height of each pixel by its physical area. Specifically, the integration operation uses the physical plane of the substrate's upper surface defined in the component package coordinate map as the zero-height reference plane. The vertical difference between the physical height of each pixel and this reference plane is calculated, and this difference is used as the effective height of the microscopic three-dimensional cylinders for multiplication and summation. This eliminates the interference of the substrate's thickness on the solder joint volume calculation, obtaining the volume of a large number of microscopic three-dimensional cylinders. The volumes of all microscopic three-dimensional cylinders are then summed to calculate the three-dimensional envelope volume of the solder joint. For calculating the three-dimensional envelope volume of the solder joint, the upper surface of the PCB substrate defined in the component package coordinate map is used as the zero-height reference plane. The physical height distribution matrix Z(x, y) reconstructed based on photometric stereo vision and gradient integral in the previous steps is extracted, where Z(x, y) represents the vertical height value of the solder surface at pixel (x, y) relative to the reference plane. The equivalent physical space size of a single pixel in the underlying optical calibration parameters is called to calculate the physical area corresponding to the bottom area of ​​a single pixel. Then, within the physical bounding box, discrete volume integral operation is performed on all effective pixels, that is, the product of the effective height of each pixel and the physical area of ​​a single pixel is accumulated and summed.

[0051] To calculate the pin coplanarity deviation, the edge displacement vector field corresponding to each pin region of the component under test is extracted, and the feature component representing the vertical height offset is separated. The spatial coordinates of key feature points of all pins under the same component are summarized. Specifically, the key feature points are selected as the geometric center point of the contact area between the bottom of each pin and the pad, or the highest physical observation point of each pin in the vertical direction. By extracting the X, Y, and Z three-dimensional coordinates of these specific semantic positions to form a point set, it is ensured that the reference coplanar physical plane generated by least squares fitting can accurately represent the actual soldering horizontal plane of the component. The least squares method is used to perform plane fitting on these spatial coordinate points to construct a reference coplanar physical plane that can represent the overall soldering posture of the component. Subsequently, the orthogonal projection distance from the feature point of each pin to the reference coplanar physical plane is calculated one by one. By comparison, the maximum absolute value of the projection distance of each pin is obtained and used as the pin coplanarity deviation value representing the degree of tilting or horizontal deviation of each pin of the component.

[0052] Finally, the system summarizes the calculated physical edge wetting angle, the three-dimensional envelope volume of the solder joint, the pin coplanarity deviation value, and the local surface texture contrast data generated in the preceding steps into the feature processing module. The system employs differentiated mapping methods for dimensional normalization processing based on the engineering characteristics of different physical properties. The specific process is as follows: For the physical edge wetting angle, the optimal wetting angle range specified by industry standards (e.g., 15° to 45°) is used as the zero-offset benchmark. Nonlinear normalization is performed using a Gaussian membership function, smoothly mapping angles deviating from the optimal range to high-risk values. For the three-dimensional envelope volume of the solder joint, the ratio is calculated using the extracted theoretical solder paste deposition volume reference value as the denominator to obtain the relative deposition rate. For the pin coplanarity deviation value, linear mapping is performed using the maximum allowable physical tolerance in the physical geometric constraint parameters of the solder joint as the truncation threshold. Through the above differentiated mapping method, each physical attribute is transformed into a dimensionless feature space of [0, 1], ensuring that the contribution of each dimension after tensor splicing has physical consistency and interpretability, eliminating the influence of dimensional differences on subsequent spatial distance calculations. After normalization, the system performs tensor splicing of the above four feature values ​​in the feature space according to a preset dimensional order, constructing a one-dimensional feature sequence containing geometric morphology, spatial distribution, and surface quality features, which serves as the multi-dimensional feature vector.

[0053] By utilizing topological features and displacement vector fields to calculate the physical wetting angle, envelope volume, and coplanarity deviation, the abstract image spatial response is transformed into engineering physical indicators with clear dimensions. This achieves a logical mapping from "visual feature extraction" to "geometric spatial quantization," enabling the test results to directly correspond to the acceptance standards of the electronics manufacturing industry. It provides traceable and interpretable objective physical evidence for backend quality analysis, ensuring the production guidance value of automated test conclusions.

[0054] Furthermore, the process of outputting a quantitative assessment score for the physical health of a single solder joint includes: inputting the multidimensional feature vector into the state mapping model, wherein the state mapping model is a multidimensional physical tolerance envelope based on industrial acceptance standards; calculating the spatial deviation Euclidean distance of the multidimensional feature vector from the multidimensional physical tolerance envelope in the feature space; outputting a discrete level value representing the risk of mechanical fracture or cold solder joint at a single solder joint based on the preset danger step interval of the spatial deviation Euclidean distance, as the quantitative assessment score for the physical health of a single solder joint; and parsing the electronic design netlist file of the circuit board to be tested to extract each solder joint. The electrical series-parallel topology in the underlying circuit logic network is used for link retrieval. The quantitative evaluation scores of all solder joints on each electrical logic link are compared, and the maximum limit deviation value representing the highest open circuit risk on each link is extracted as the short-board evaluation extreme value that determines the overall physical conduction state of the link. The short-board evaluation extreme values ​​of all electrical logic links, the two-dimensional physical coordinates of the defective solder joints that generate the extreme values, and the failure feature classification codes are encapsulated in a data structure to generate an evaluation result feature vector. The evaluation result feature vector is then sent to the external monitoring terminal via the industrial fieldbus protocol of the edge computing node to execute corresponding actions.

[0055] First, the normalized multidimensional feature vector is loaded into the memory working area of ​​the edge computing node, and a pre-initialized state mapping model is retrieved. This model is represented in the underlying data structure as a set of multidimensional spatial boundary threshold matrices based on industrial acceptance standards, i.e., the multidimensional physical tolerance envelope. By traversing each dimension component of the multidimensional feature vector, the geometric deviation distance of the current input vector in the multidimensional feature space is calculated. Specifically, the system sequentially calculates the absolute difference between each dimension value of the input vector and each dimension value of the ideal zero deviation anchor point, divides the absolute difference by the safety tolerance width of the corresponding dimension for weighted normalization, then squares the normalized differences of each dimension and accumulates them, and finally performs a square root operation on the accumulated sum to obtain a scalar value based on the same dimension that represents the degree of spatial deviation, i.e., the spatial deviation Euclidean distance. Subsequently, the Euclidean distance is input into a preset step threshold comparator, and through an interval comparison and judgment operation, it is mapped to a specific preset danger step interval, thereby outputting an integer discrete level value (e.g., a danger rating of 0 to 5), which is used as the quantitative evaluation score characterizing the risk of mechanical fracture or poor soldering of the single solder joint.

[0056] Specifically, the stepped threshold comparator is represented in the system's underlying data structure as a one-dimensional static lookup table stored in the non-volatile memory of the edge computing node. The construction of the one-dimensional static lookup table is completed during the system's offline calibration phase. A standard reference circuit board that has passed manual inspection is selected, and the system collects and extracts the multi-dimensional feature vectors of all its solder joints. The average value of each dimension of the feature is calculated and used as the ideal zero deviation anchor point in the multi-dimensional feature space. The physical tolerance baselines specified in the industrial assembly acceptance standards (such as IPC-A-610) (e.g., maximum permissible deviation of coplanarity, lower limit of pin wetting angle limit) are extracted. These physical baselines are combined and substituted into the Euclidean distance calculation formula to deduce the limit Euclidean distance corresponding to the tolerance baseline in the multi-dimensional feature space. This limit is set as the trigger limit of the highest danger level (e.g., level 5). The numerical span from the zero deviation anchor point to the limit Euclidean distance is divided into multiple continuous discrete distance sub-intervals according to the non-linear segmentation strategy of equal interval segmentation or exponential increase. A mapping relationship is established between the upper and lower limit values ​​of each sub-interval and the low-risk danger ladder values ​​from 0 to 4. All values ​​greater than the limit Euclidean distance are mapped to level 5. The boundary values ​​of each distance sub-interval are used as addressing indexes, and the corresponding danger ladder values ​​are used as storage content. A key-value pair array is constructed in memory and solidified into the one-dimensional static lookup table. In the real-time detection mapping stage, after obtaining the spatial deviation Euclidean distance of the current solder joint, the value of the Euclidean distance (or its truncated and rounded value) is directly used as a memory addressing pointer to directly address and read the corresponding storage content in the one-dimensional static lookup table. This outputs a discretized level value characterizing the risk of mechanical fracture or cold solder joint of a single solder joint, which serves as the quantitative evaluation score for the physical health of a single solder joint.

[0057] In this embodiment, the safety tolerance limit Euclidean distance in the multidimensional feature space is pre-determined to be 10.0 (dimensionless unit after normalization). The one-dimensional static lookup table uses a non-linear incremental partitioning strategy to construct specific danger ladder intervals and storage mapping relationships as follows: Level 0 (Ideal State): Spatial deviation from Euclidean distance is in the range of [0, 1.5), indicating that the solder joint morphology is consistent with the standard reference height and the physical health is excellent. At this time, the lookup table returns a value of 0. Level 1 (Normal fluctuation): Spatial deviation from Euclidean distance in the range of [1.5, 3.5) indicates slight fluctuations in tin content or very small wetting angle, but is completely within the safety tolerance range of industrial acceptance standards. The lookup table returns 1. Level 2 (Warning Status): Spatial deviation from Euclidean distance in the range of [3.5, 6.0) indicates that the solder joint is in a sub-healthy state. Although it is currently conductive, there is a risk of fatigue cracking under long-term thermal shock. This triggers the production line warning record, and the lookup table returns a value of 2. Level 3 (Edge Defect): Spatial deviation from Euclidean distance in the range of [6.0, 7.5) indicates that the solder joint characteristics have approached the physical tolerance limit, with obvious insufficient solder or slight pin warping, and a high risk of occasional open circuit. The lookup table returns a value of 3. Level 4 (Fatal Flaw): Spatial deviation from Euclidean distance is in the range [7.5, 9.5). This indicates that the solder joint has substantially exceeded the safety limit, posing an extremely high risk of mechanical breakage or poor soldering. The lookup table returns a value of 4. Level 5 (Extreme Disconnection): Spatial deviation from Euclidean distance is in [9.5, 10], indicating a serious open circuit, short circuit or severely floating pin, which is directly determined as the absolute weak link that determines the conduction status of the electrical logic link, and the lookup table returns a value of 5.

[0058] After completing the single-point quantization evaluation, the system activates the electronic design netlist file (e.g., IPC-D-356 format) parsing engine to read the coordinates of each pin node and the network labels of their interconnections defined in the file. Based on these network connectivity attributes, the system constructs a graph data structure in memory with solder joints as nodes and electrical network connections as directed edges, accurately reconstructing the electrical series-parallel topology in the underlying circuit logic network. Next, using the power supply or signal start point in the graph data structure as the root node, the system performs a depth-first search (DFS) link retrieval, traversing each complete electrical logic link. Specifically, the DFS retrieval engine constraint for each complete electrical logic link is: using the signal output pin of an active component or the power supply output terminal of a power module as the starting root node, tracing along the directed edges of the electrical network until encountering the signal input pin, ground terminal, or independent test point of an active component as the retrieval termination node. This accurately decomposes the massive, fully connected global netlist into multiple point-to-point logic loops with independent electrical conduction significance. During the traversal of a single logical link, the system synchronously reads the quantitative evaluation scores of all solder joints along the link and calls the extreme value comparison operator to filter out the node with the largest evaluation score in the link. The system uses the largest evaluation score as the extreme value of the short board evaluation that determines the physical conduction status of the entire link and records it in the system log.

[0059] Finally, the system performs structured encapsulation of multi-source data. For each completed electrical logic link, the system extracts the short board evaluation extreme value generated in the previous steps and traces back to the defective solder joint corresponding to the extreme value. The system extracts the two-dimensional physical coordinates of the solder joint in the global coordinate system of the circuit board. At the same time, the system assigns a corresponding hexadecimal failure feature classification code based on the highest weight feature dimension (such as volume dimension or coplanarity dimension) that caused the abnormal evaluation score of the solder joint. Specifically, the extraction logic of the highest weight feature dimension is as follows: when the system calculates the spatial deviation Euclidean distance of the abnormal solder joint, it simultaneously caches the square difference values ​​of each feature dimension. By reverse comparison, the feature dimension that occupies the largest proportion of the total sum (i.e., the physical attribute that contributes the most to the spatial deviation) is extracted and locked as the main cause of failure. The failure feature classification code is generated based on the preset fault code dictionary (e.g., 0x01 represents too small volume, 0x02 represents excessive coplanarity). The system, following predetermined byte alignment and packet header / tail verification rules, combines and concatenates the short-board evaluation extreme value, two-dimensional physical coordinates, and failure characteristic classification code into a standard data frame format to generate an evaluation result feature vector. Subsequently, the edge computing node invokes the internally integrated industrial fieldbus protocol stack (such as EtherCAT or PROFINET protocol) to serialize the evaluation result feature vector into a low-level network message, which is then sent in real-time to the external monitoring terminal through the physical layer network interface, providing data instructions for subsequent production line operations.

[0060] By integrating multi-dimensional spatial feature lookup mapping with low-level electrical netlist retrieval, a leapfrog assessment from single-point physical morphology to global electrical reliability is achieved. Memory addressing is used to replace complex computing power, enabling defect risk classification at the edge. Simultaneously, graph search is used to optimize link bottlenecks, and the resulting standard industrial bus messages provide precise spatial coordinates and failure semantics for the detection results, offering highly real-time, traceable, and objective decision support for closed-loop quality interception on the production line.

[0061] By combining low-level optical calibration, physical prior slicing, and lightweight sparse quantization, the hardware contradiction between the limited computing power of edge computing nodes and the processing of massive multispectral pixels is effectively resolved. Nonlinear photoelectric signals are precisely reconstructed into physical measurement indicators (such as wetting angle and three-dimensional volume) characterizing the microstructure of solder joints. Furthermore, by deeply integrating static lookup table grading and netlist graph structure retrieval technologies, a leap from isolated single-point appearance evaluation to global electrical continuity risk assessment is achieved. Standard bus messages with clear physical dimensions and spatial failure semantics are output, thus providing an interpretable system-level solution for real-time closed-loop interception and quality traceability in electronic manufacturing production lines.

[0062] Example 2: Edge computing nodes control a multi-channel ring stroboscopic light source to perform time-series exposure on the pin array of SOP devices. The system extracts the lens distortion mapping matrix from the underlying optical calibration parameters and performs bilinear coordinate interpolation correction on the distorted pixels in the pin edge region. Subsequently, based on preset weight allocation coefficients matched with the sensor's spectral response characteristics, the system performs radiometric compensation and normalization on the corrected multi-band signals to offset optical interference caused by solder resist and flux residues on automotive-grade PCB boards, extracting pure monochromatic brightness components to generate spatial domain grayscale distribution data. Next, the system orthogonally stitches the SOP pin reflective signals acquired at different incident angles along the feature channel dimension to generate a multispectral brightness response map characterizing the gull-wing pin ramp gradient and metal reflectivity.

[0063] The system analyzes the EDA component package diagram of the ECU circuit board and extracts the center coordinates and aspect ratios of each array pad of the SOP device. Using these center coordinates as anchor points, the system reserves redundant pixels at the edges to cover the maximum solder spread tolerance, generating a rectangular physical bounding box covering each independent gull-wing pin, and simultaneously extracting local feature blocks in memory. Subsequently, the system performs edge-preserving smoothing filtering on the local multispectral feature blocks, filtering out high-frequency reflective noise caused by the micro-crystal roughness of the solder surface while retaining the step features of key physical boundaries, reconstructing a physical contour feature map that reflects the macro-curvature change from the pin root to the toe and a clear boundary contour; simultaneously, using the gradient differential calculation of local grayscale feature blocks, the system extracts local surface texture contrast data characterizing cold solder joints or surface pinhole defects.

[0064] The system searches for gradient abrupt change extreme points in the physical contour feature map, using these as the starting point of the physical interface between the pin metal and the solder wrapping layer. Following curvature continuity constraints, the system traces along orthogonal directions to generate closed pin solder creep boundary topology lines; simultaneously, it interpolates within the neighborhood to generate an edge displacement vector field recording microscopic deformations. To adapt to the low-power characteristics of edge computing nodes, the system retains only the effective non-zero nodes from the above features to construct a sparse feature matrix, and uses a static threshold truncation mechanism to compress and map it into a low-bit-width integer data stream for output, significantly reducing the memory overhead of pin array detection.

[0065] The system uses the physical boundary between the SOP pin toe and the pad as a reference, extracts the height gradient set in the local neighborhood, fits the local spatial sectional plane using the least squares method, and calculates the physical edge wetting angle, which characterizes the solder wetting and climbing capability. Simultaneously, using the PCB physical substrate surface as the zero-point reference, it performs discrete volume integration on the effective pixel height below the pin coverage area to obtain the three-dimensional envelope volume of the solder joint for a single pin. Furthermore, the system extracts the spatial coordinates of the top points of all pins on the same side of the SOP device, fits them to a reference coplanar physical plane, and calculates the maximum orthogonal distance of each pin from this plane, thus calculating the coplanarity deviation value, which characterizes the degree of pin warpage. Finally, the system performs tensor concatenation after interval normalization of the above physical quantities to construct a multi-dimensional feature vector comprehensively characterizing the health of a single pin.

[0066] During the offline phase, the system constructs a one-dimensional static lookup table based on the physical limits and tolerances of automotive electronics high reliability standards (such as IPC-A-610 Class 3 standard). During real-time monitoring, the system converts the multi-dimensional feature vector of the current pin into a spatial deviation Euclidean distance and directly uses this distance as a pointer to perform memory addressing and table lookup, outputting the discretized hazard level assessment score of the pin. Subsequently, the system reconstructs the electrical series-parallel topology (e.g., automotive CAN bus communication network) containing the SOP device based on the electronic netlist file, traverses the signal links using a depth-first graph search algorithm, and extracts the pin with the highest hazard assessment score on that link as the shortest board extreme value. Finally, the system encapsulates the shortest board extreme value, the pin's two-dimensional coordinates, and the failure characteristic code representing "pin warping" or "poor wetting" into a low-level industrial Ethernet message and sends it to the field master PLC or monitoring terminal, triggering rejection or rework actions.

[0067] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for evaluating the quality status of a circuit board based on edge computing, characterized in that, include: Obtain the component package coordinate map, solder joint physical geometric constraint parameters, and low-level optical calibration parameters of the smart sensor of the circuit board under test; The system uses a smart sensor to capture the original photoelectric conversion signal of the circuit board surface under a preset illumination sequence, and then uses the underlying optical calibration parameters to reconstruct the original photoelectric conversion signal into a multispectral brightness response map and spatial domain grayscale distribution data. The lightweight analysis model is invoked, and the region is extracted using the multispectral brightness response map. The topological features of the solder climbing surface at the connection between the component pin and the pad are identified. The local surface texture contrast data and the edge displacement vector field relative to the component package coordinate map are calculated based on the spatial domain grayscale distribution data. By utilizing the topological features of the solder climb surface, local surface texture contrast data, and edge displacement vector field, the physical edge wetting angle, the three-dimensional envelope volume of the solder joint, and the pin coplanarity deviation value are calculated, and a multi-dimensional feature vector is constructed. The multidimensional feature vector is input into the state mapping model, and the output is a quantitative evaluation score of the physical health of a single solder joint; the quantitative evaluation scores of all solder joints on the circuit board to be inspected are summarized and output to an external monitoring terminal.

2. The circuit board quality status assessment method based on edge computing according to claim 1, characterized in that, The process of acquiring various data of the circuit board under test includes: parsing the electronic design automation file of the circuit board under test, extracting the physical center coordinates, rotation angles, and matching two-dimensional contour boundaries of each component, and constructing the component package coordinate map; retrieving the preset industrial electronic assembly acceptance standard database, extracting the standard solder climb height ratio, theoretical solder paste deposition volume, and pin coplanarity physical tolerance corresponding to each component package type, as the physical geometric constraint parameters of the solder joint; and reading the lens distortion mapping matrix, single pixel physical space equivalent size, and white balance gain coefficient of the multispectral channel pre-stored in the non-volatile memory inside the smart sensor, as the underlying optical calibration parameters.

3. The circuit board quality status assessment method based on edge computing according to claim 1, characterized in that, The conversion process of the photoelectric conversion raw signal includes: using the clock interrupt signal of the edge computing node to synchronously trigger the multi-band array light source to alternately flash illumination according to the set spatial incident angle and wavelength timing; within each flash illumination cycle of the multi-band array light source, controlling the photoelectric coupling array inside the smart sensor to perform independent exposure, and collecting array level data including the high light reflection component and diffuse reflection component of the circuit board surface as the photoelectric conversion raw signal.

4. The circuit board quality status assessment method based on edge computing according to claim 1, characterized in that, The process of reconstructing the original photoelectric conversion signal into a multispectral brightness response map and spatial domain grayscale distribution data includes: using the lens distortion mapping matrix in the underlying optical calibration parameters to perform pixel-level spatial coordinate interpolation correction on the original photoelectric conversion signal; using the white balance gain coefficient in the underlying optical calibration parameters to perform radiance compensation and illuminance normalization processing on the corrected signal, and extracting the monochromatic brightness component to generate the spatial domain grayscale distribution data; and performing orthogonal splicing calculation on the feature channel dimension of multiple corrected signals obtained under different spatial incident angles and wavelength time sequences to generate the multispectral brightness response map characterizing the reflectivity gradient of the physical surface.

5. The circuit board quality status assessment method based on edge computing according to claim 1, characterized in that, The lightweight analysis model includes: a priori slicing layer: receiving the multispectral brightness response map and the spatial domain grayscale distribution data, generating physical bounding boxes corresponding to each pad using the component package coordinate map, and performing synchronous slicing extraction within the physical bounding boxes to construct local multispectral feature blocks and local grayscale feature blocks respectively; Decoupling mapping layer: The local multispectral feature blocks are separated into feature channels, and low-frequency signal channels that characterize the surface geometric undulations are extracted as physical contour feature maps; at the same time, the local grayscale feature blocks are used to perform pixel gradient statistics to generate the local surface texture contrast data. Contour Topology Tracking Layer: Obtain the physical contour feature map, perform geometric edge tracking with the pixel gradient extreme points in the region as the tracking starting point, generate closed topology line features representing the boundary of the solder climbing surface; and simultaneously use the local grayscale feature blocks to perform gradient interpolation calculation to generate the edge displacement vector field; Sparse quantization layer: Extract the closed topology features, local surface texture contrast data and non-zero effective nodes in the edge displacement vector field to construct a sparse feature matrix, and perform low bit precision compression mapping on the sparse feature matrix to reconstruct and output the solder climb surface topology features, local surface texture contrast data and edge displacement vector field in compressed data format.

6. The circuit board quality status assessment method based on edge computing according to claim 1, characterized in that, The process of calculating the physical edge wetting angle, the three-dimensional envelope volume of the solder joint, and the coplanarity deviation of the pins, and constructing a multi-dimensional feature vector, includes: using the curvature change gradient of the solder climb surface topology and the edge displacement vector field, calculating the spatial tangent equation at the interface between the solder and the pad, and solving for the dihedral angle between this spatial tangent and the physical plane of the substrate, which is taken as the physical edge wetting angle; constructing a microscopic three-dimensional envelope surface based on the solder climb surface topology, and combining the single-pixel physical spatial equivalent size in the underlying optical calibration parameters, calculating the physical edge wetting angle by performing spatial discrete integration on the effective pixel set under the microscopic three-dimensional envelope surface. The three-dimensional envelope volume of the solder joint is obtained; the vertical height offset component in the edge displacement vector field corresponding to each pin of the component to be tested is extracted, and the reference coplanar physical plane of the component is fitted using the least squares method. The maximum orthogonal distance of each pin from the reference coplanar physical plane is calculated as the pin coplanarity deviation value; the physical edge wetting angle, the three-dimensional envelope volume of the solder joint, the pin coplanarity deviation value, and the local surface texture contrast data characterizing cold solder defects are normalized in terms of dimensions, and tensor splicing is performed on the feature dimension to construct the multi-dimensional feature vector characterizing the comprehensive physical health of a single solder joint.

7. The circuit board quality status assessment method based on edge computing according to claim 1, characterized in that, The process of outputting a quantitative assessment score for the physical health of a single solder joint includes: inputting the multidimensional feature vector into the state mapping model, wherein the state mapping model is a multidimensional physical tolerance envelope based on industrial acceptance standards; calculating the spatial deviation Euclidean distance of the multidimensional feature vector from the multidimensional physical tolerance envelope in the feature space; and, based on the preset danger step interval where the spatial deviation Euclidean distance is located, outputting a discrete level value characterizing the risk of mechanical fracture or cold solder joint of a single solder joint, as the quantitative assessment score for the physical health of a single solder joint; and parsing the electronic design netlist file of the circuit board to be tested to extract the bottom... The electrical series-parallel topology in the layer circuit logic network is analyzed. Link retrieval is performed along the electrical series-parallel topology, comparing the quantitative evaluation scores of all solder joints on each electrical logic link. The maximum limit deviation value representing the highest open-circuit risk on each link is extracted as the short-board evaluation extreme value determining the overall physical conduction state of the link. The short-board evaluation extreme values ​​of all electrical logic links, the two-dimensional physical coordinates of the defective solder joints that generate the extreme values, and the failure feature classification codes are encapsulated in a data structure to generate an evaluation result feature vector. This evaluation result feature vector is then sent to the external monitoring terminal via the industrial fieldbus protocol of the edge computing node to execute corresponding actions.

8. A circuit board quality status assessment system based on edge computing, characterized in that, include: The data acquisition module acquires the component package coordinate map, solder joint physical geometric constraint parameters, and the underlying optical calibration parameters of the smart sensor of the circuit board under test. The system uses a smart sensor to capture the original photoelectric conversion signal of the circuit board surface under a preset illumination sequence, and then uses the underlying optical calibration parameters to reconstruct the original photoelectric conversion signal into a multispectral brightness response map and spatial domain grayscale distribution data. The edge computing module calls a lightweight analysis model, uses multispectral brightness response maps to extract regions, identifies the solder climbing surface topology features at the connection between component pins and pads, and calculates local surface texture contrast data and edge displacement vector field relative to the component package coordinate map based on spatial domain grayscale distribution data. The vector construction module utilizes the topological features of the solder climbing surface, local surface texture contrast data, and edge displacement vector field to calculate the physical edge wetting angle, the three-dimensional envelope volume of the solder joint, and the pin coplanarity deviation value, and constructs a multi-dimensional feature vector. The quantitative evaluation module inputs multi-dimensional feature vectors into the state mapping model and outputs a quantitative evaluation score for the physical health of a single solder joint; it also aggregates the quantitative evaluation scores of all solder joints on the circuit board to be inspected and outputs them to an external monitoring terminal.

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