Display device and detection method

Abstract

The application discloses a display device and a detection method, and relates to the display field.The display device comprises a timing controller, a level converter, an impedance detection circuit, a display panel and a circuit board.The impedance detection circuit comprises a to-be-detected impedance and a detection unit.The to-be-detected impedance is the equivalent impedance from the pressing position of the display panel and the chip on film (COF) to the pressing position of the COF and the circuit board.The first output end of the timing controller is connected with the input end of the level converter.The output end of the level converter is connected with the first end of the to-be-detected impedance.The second end of the to-be-detected impedance is connected with the first end of the detection unit.The second output end of the timing controller is connected with the opening control end of the detection unit.The level converter is used for outputting a preset detection voltage in the non-scanning period between frames.The timing controller is used for controlling the detection unit to be turned on in the non-scanning period between frames, and detecting the resistance value of the to-be-detected impedance through the detection unit.The application solves the technical problem of display abnormality.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to display devices and detection methods. Background Technology

[0002] As TFT-LCD (Thin Film Transistor Liquid Crystal Display) technology matures, the operating environment becomes increasingly complex. Ambient temperature has a particularly significant impact on TFT-LCD displays. Normal LCD (Liquid Crystal Display) products generally need to meet operating temperature requirements of -20 to 60°C to ensure normal operation under varying environmental temperatures.

[0003] As a key component of LCDs, the COF (Chip on Film) plays a crucial role in driving the TFT (Thin Film Transistor) display and transmitting GDL (Gate Driver Line) signals. During manufacturing, the COF is bonded to both ends of the XB (X Board) and the Cell (liquid crystal cell). However, in actual use, excessively cold or hot environments can cause changes in the bonding indentation. When the indentation becomes shallower, poor contact can occur, leading to signal loss or distortion and resulting in display abnormalities.

[0004] The above content is only used to help understand the technical solutions of the embodiments of this application, and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this application is to provide a display device and a detection method to solve the technical problem of display abnormalities.

[0006] To achieve the above objectives, this application provides a display device, which includes a timing controller, a level converter, an impedance detection circuit, a display panel, and a circuit board. The impedance detection circuit includes an impedance to be measured and a detection unit. The impedance to be measured is the equivalent impedance from the bonding point between the display panel and the flip-chip film to the bonding point between the flip-chip film and the circuit board. The first output terminal of the timing controller is connected to the input terminal of the level converter, the output terminal of the level converter is connected to the first terminal of the impedance to be measured, the second terminal of the impedance to be measured is connected to the first terminal of the detection unit, and the second output terminal of the timing controller is connected to the turn-on control terminal of the detection unit. The level converter is used to output a preset detection voltage during the non-scanning period between frames, and the preset detection voltage is less than the preset gate high level voltage. The timing controller is used to control the detection unit to be turned on during the non-scanning period between frames, and to detect the resistance value of the impedance to be measured through the detection unit.

[0007] In one embodiment, the detection unit includes a current detection resistor, a first resistor, a second resistor, a detection switch transistor, and an operational amplifier; The first end of the detection switch is used as the first end of the detection unit, and the second end of the detection switch is used as the turn-on control end of the detection unit. The first end of the detection switch is connected to the first end of the current detection resistor, and the second end of the current detection resistor is grounded. The first end of the current sensing resistor is also connected to the positive input terminal of the operational amplifier, the negative input terminal of the operational amplifier is connected to the first end of the first resistor, and the second end of the first resistor is grounded. The first end of the first resistor is also connected to the first end of the second resistor, the second end of the second resistor is also connected to the output end of the operational amplifier, and the output end of the operational amplifier is also connected to the detection input end of the timing controller.

[0008] In one embodiment, the display device further includes a gate drive strength adjustment circuit, which is disposed between the output terminal of the level converter and the impedance to be measured, and the control terminal of the gate drive strength adjustment circuit is connected to the second output terminal of the timing controller. The timing controller is used to control the gate drive strength adjustment circuit to adjust the drive strength of the gate drive signal output by the level converter during the non-scanning period between frames when the resistance value of the impedance to be measured is greater than a preset abnormal threshold.

[0009] In one embodiment, the gate drive strength adjustment circuit includes: a decoder, a preset number of adjustment capacitors, and a preset number of adjustment switching transistors, wherein the decoder includes multiple decoding output terminals; The input terminal of the decoder is used as the control terminal of the gate drive intensity adjustment circuit. For each adjustment switch, the first terminal of the adjustment switch is connected to the decoder output terminal, the second terminal of the adjustment switch is connected to the first terminal of the adjustment capacitor, and the third terminal of the adjustment switch is connected between the level converter and the impedance to be measured. The decoder output terminal and the adjustment capacitor connected to the adjustment switch are different for different adjustment switches. The second terminal of all the aforementioned adjustment capacitors is grounded.

[0010] In one embodiment, the display panel has an in-plane RC load, and the second end of the impedance to be measured is also connected to the in-plane RC load.

[0011] Furthermore, this application also provides a detection method, which is applied to the display device described above, the detection method comprising: During the non-scanning period between frames of the display device, a preset detection voltage is output to the impedance to be measured through the level converter of the display device, and the detection unit in the display device is turned on by the timing controller of the display device, wherein the preset detection voltage is less than the preset gate high level voltage; When the level converter outputs a preset detection voltage and the detection unit is turned on, the resistance value of the impedance to be measured is detected.

[0012] In one embodiment, the inter-frame non-scanning period is the time interval between the rising edge of the frame cutoff signal of the preceding frame and the rising edge of the frame start signal of the following frame; the method further includes: After a preset first redundancy duration following the rising edge of the frame cutoff signal, a preset detection voltage is output through the level converter, and the detection unit is turned on by the timing controller. Before the rising edge of the frame start signal, a preset second redundancy time is elapsed, and the control level converter stops outputting the preset detection voltage, and the timing controller controls the detection unit to turn off.

[0013] In one embodiment, the step of detecting the resistance value of the impedance to be measured includes: The output voltage of the operational amplifier in the detection unit is obtained when the voltage across the in-plane capacitor in the in-plane resistive-capacitive load of the display device is stable. The current flowing through the current detection resistor is calculated based on the output voltage, the first resistor, the second resistor, and the current detection resistor in the detection unit; The resistance value of the impedance to be measured is calculated based on the current, the current detection resistor, and the preset detection voltage.

[0014] In one embodiment, the detection method further includes: If the resistance value of the impedance to be measured is detected to be greater than a preset abnormal threshold, an impedance abnormality prompt is output, and the target capacitor corresponding to the resistance value of the impedance to be measured is obtained from the preset impedance-capacitance mapping relationship constructed by the preset impedance and the preset capacitor. Based on the target capacitance, the capacitor to be connected between the level converter and the impedance to be measured is determined in the gate drive strength adjustment circuit of the display device; The capacitor to be connected is connected between the level converter and the impedance to be measured to adjust the driving strength of the gate drive signal output by the level converter.

[0015] In one embodiment, the step of connecting the capacitor to be connected between the level converter and the impedance to be measured includes: The target adjustment switch connected to the capacitor to be connected is determined, and an adjustment control signal is generated based on the target decoding output terminal connected to the target adjustment switch. The adjustment control signal is input to the input terminal of the decoder in the gate drive strength adjustment circuit, so that the target decoder output terminal outputs a preset conduction level to conduct the target adjustment switch connected to the target decoder output terminal, so that the capacitor to be connected is connected between the level converter and the impedance to be measured.

[0016] Furthermore, to achieve the above objectives, this application also provides a display device, which includes: a memory, a processor, and a program for the detection method stored in the memory and executable on the processor. When the program for the detection method is executed by the processor, it can implement the steps of the detection method as described above.

[0017] In addition, to achieve the above objectives, embodiments of this application also provide a computer-readable storage medium storing a program for implementing the detection method, wherein the program for the detection method, when executed by a processor, implements the steps of the detection method as described above.

[0018] In addition, to achieve the above objectives, this application also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the detection method described above.

[0019] One or more technical solutions proposed in the embodiments of this application have at least the following technical effects: The display device of this application includes a timing controller, a level converter, an impedance detection circuit, a display panel and a circuit board. The impedance detection circuit includes the impedance to be measured and a detection unit. The impedance to be measured is the equivalent impedance from the bonding point between the display panel and the flip-chip film to the bonding point between the flip-chip film and the circuit board. The level converter can output a preset detection voltage during the non-scanning period between frames (without affecting the normal display of the display panel). The timing controller can control the detection unit to be turned on during the non-scanning period between frames, thereby enabling the detection unit to detect the resistance value of the impedance under test. This facilitates the early detection of issues such as shallowing of the flip-chip bonding indentation and poor contact through resistance detection, avoiding signal loss and distortion caused by poor contact, which could lead to display abnormalities. This eliminates the need to wait until display abnormalities occur before troubleshooting. Furthermore, by limiting the preset detection voltage to be lower than the preset gate high-level voltage, this application avoids interfering with the normal display of the display panel during the detection process during the non-scanning period between frames, ensuring that the detection process does not affect the normal display of the display panel. Therefore, this application can detect whether the flip-chip bonding indentation is shallowing in advance without affecting the normal display of the display panel, so as to deal with the shallowing of the indentation in advance and avoid display abnormalities. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with those of this application and, together with the specification, serve to explain the principles of the embodiments of this application.

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the crimping process; Figure 2 This is a schematic diagram of the indentation. Figure 3 This is a cross-sectional schematic diagram of the flip-chip film bonding area in the display device of this application embodiment; Figure 4 This is a waveform diagram of the GDL signal received in the display panel after the indentation becomes shallower. Figure 5 This is a schematic diagram of a module in one embodiment of the display device according to the present application; Figure 6 This is a schematic diagram of the module consisting of the impedance to be measured, the display panel, and the circuit board in the display device according to an embodiment of this application; Figure 7This is a schematic diagram of the driving timing of the GDL signal in the display device according to an embodiment of the present application when impedance detection is not performed on the impedance to be tested during the non-scanning period between frames. Figure 8 This is a schematic diagram of the driving timing of the GDL signal in the display device of this application when impedance detection is performed on the impedance to be tested during the non-scanning period between frames. Figure 9 This is a circuit diagram of the detection unit in the display device according to an embodiment of this application; Figure 10 This is a schematic diagram of the display device including a gate drive intensity adjustment circuit according to an embodiment of this application; Figure 11 This is a circuit diagram of the gate drive intensity adjustment circuit in the display device according to an embodiment of this application; Figure 12 This is a circuit diagram showing the display device including an in-plane resistive-capacitive load according to an embodiment of this application; Figure 13 This is a flowchart illustrating one embodiment of the detection method in this application. Figure 14 This is a schematic diagram of the GDL signal waveform when different adjustment capacitors are connected between the level converter and the impedance to be measured in the detection method of this application embodiment; Figure 15 This is a schematic diagram of the current and voltage waveforms of the GDL signal input to the display panel after the driving strength of the GDL signal is changed in the detection method of this application embodiment.

[0023] Explanation of icon numbers: 100, Timing Controller; 200, Level Shifter; 300, Impedance Detection Circuit; 310, Detection Unit; R0, Impedance to be Measured; COF, Chip-on-Foil Film; 400, Display Panel; 500, Circuit Board; 600, CB Board; Qj, Detection Switch; Ri, Current Detection Resistor; R1, First Resistor; R2, Second Resistor; OP1, Operational Amplifier; Vcc, Positive Voltage Connected to Operational Amplifier; Vss, Negative Voltage Connected to Operational Amplifier; V+, Positive Input Terminal of Operational Amplifier; V-, Negative Input Terminal of Operational Amplifier; Vout, Output Terminal of Operational Amplifier; 700, Gate Drive Strength Adjustment Circuit; 710, Decoder; Q1~Q8, Multiple Adjustment Switches; C1~C8, Multiple Adjustment Capacitors; Y01~Y08, Multiple Decoder Output Terminals; ABC, Multiple Sub-Input Terminals of Decoder; 800, In-plane RC Load; Rj1~Rjk, Multiple In-plane Resistors; Cj1~Cjk, Multiple In-plane Capacitors.

[0024] The objectives, features, and advantages of the embodiments described in this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0025] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of the embodiments of this application and are not intended to limit the embodiments of this application.

[0026] To better understand the technical solutions of the embodiments of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0027] As TFT-LCD display technology matures, the operating environment becomes increasingly complex. Among these factors, ambient temperature has a particularly significant impact on TFT-LCD displays. Normal LCD products generally need to meet the operating ambient temperature requirement of -20~60℃ to ensure that the display can operate normally under different ambient temperatures.

[0028] As a key component of LCD screens, the Co-fiber (COF) plays a crucial role in driving the TFT display and transmitting GDL signals. During manufacturing, the COF must be bonded to both the XB and Cell ends. However, in actual use, excessively cold or hot environments can cause changes in the bonding indentation. When the indentation becomes shallower, poor contact can occur, leading to signal loss or distortion within the plane and resulting in display abnormalities.

[0029] Currently, monitoring of indentation condition is primarily achieved through microscopic inspection during the manufacturing process. For example, one can refer to... Figure 1 , Figure 1 This diagram illustrates the bonding process. Figure 1 The demonstration specifically showcases the bonding process between the COF and the display panel, and the pressing process between the COF and the display panel, specifically the pressing of the COF onto the liquid crystal cells within the display panel. Figure 1 f1 is a side view of the press-fitting process. The TFT in f1 is a component within the display panel, and the CF (Color Filter) is mounted on the TFT. Figure 1 f2 in the diagram is the top view of the crimped joint. See also: Figure 2 , Figure 2 The images show two different states of indentation, obtained through microscopic observation. Figure 2 As can be seen, a has obvious indentation, which is a normal indentation, while the indentation on b has disappeared, and the surface is smooth.

[0030] Generally, the state of the indentation on a display device after it leaves the factory is unknown as it changes with the usage environment. When environmental factors cause the indentation to become shallower, the resulting display abnormalities are usually only discovered after the abnormality occurs. Therefore, real-time detection of the indentation state is currently not possible, which easily leads to display abnormalities.

[0031] Therefore, this embodiment provides a display device, which includes a timing controller, a level converter, an impedance detection circuit, a display panel, and a circuit board. The impedance detection circuit includes an impedance to be measured and a detection unit. The impedance to be measured is the equivalent impedance from the bonding point between the display panel and the flip-chip film to the bonding point between the flip-chip film and the circuit board. The level converter can output a preset detection voltage during the non-scanning period between frames (without affecting the normal display of the display panel). The timing controller can control the detection unit to be turned on during the non-scanning period between frames, so that the impedance to be tested can be detected by the detection unit. This facilitates the early detection of issues such as shallowing of the flip-chip bonding indentation and poor contact through resistance detection, avoiding signal loss and distortion caused by poor contact, which could lead to display abnormalities. This eliminates the need to wait until display abnormalities occur before troubleshooting. Furthermore, by limiting the preset detection voltage to be lower than the preset gate high-level voltage, this embodiment avoids interfering with the normal display of the display panel during the detection process during the non-scanning period between frames, ensuring that the detection process does not affect the normal display of the display panel. Therefore, this embodiment can detect whether the flip-chip bonding indentation is shallowing in advance without affecting the normal display of the display panel, so as to deal with the shallowing of the indentation in advance and avoid display abnormalities.

[0032] To better understand this embodiment, the reason for detecting the indentation state by detecting the resistance value of the impedance to be measured is explained below: (Refer to...) Figure 3 , Figure 3 The diagram shows a cross-sectional view of the flip-chip film, which can also be considered a cross-sectional view of the resistor under test at the point where the COF and Cell are bonded. Anisotropic Conductive Film (ACF) adhesive is used during bonding. ACF adhesive is characterized by a significant difference in resistance between the Z-axis electrical conduction direction and the XY insulating plane. When the difference between the Z-axis conduction resistance and the XY plane insulation resistance exceeds a certain ratio, it is considered to have good anisotropic conductivity. The conduction principle involves using conductive particles to connect the electrodes between the COF lead (the conductive wire of the flip-chip film) and the Cell lead (the conductive wire of the display panel), creating conductivity while preventing short circuits between adjacent electrodes, thus achieving conduction only in the Z-axis direction.

[0033] Thus, the impedance of the lead on the COF and the lead on the cell is determined by the number of conductive particles and the contact area between the conductive particles and the lead. The number of conductive particles is determined by the concentration of the ACF adhesive, while the contact area is determined by the temperature and pressure of the hot press head. For example... Figure 3 Force analysis of conductive particles reveals that they possess both resilience and adhesion forces. During LCD product operation, if high temperatures and large current impacts occur at the bonding area of ​​the flip-chip film, the adhesion force will be less than the resilience force. This causes the indentation to gradually become shallower, resulting in an indentation resembling... Figure 2 The shallowing of the indentation is a concern. Since contact resistance is inversely proportional to contact area, a shallower indentation leads to increased impedance. Therefore, detecting the impedance between the lead on the COF and the corresponding lead on the cell is crucial. Thus, this embodiment can detect the shallowing of the indentation in advance by detecting the resistance value of the impedance to be measured.

[0034] Additionally, you can refer to Figure 4 , Figure 4 The image shows the waveform of the GDL signal received in the display panel after the indentation becomes shallower. Figure 4 In this context, Vy represents the voltage waveform of the GDL signal, and Iy represents the current waveform of the GDL signal. Figure 4 As can be seen, the in-plane signal is lost or severely distorted when the indentation becomes shallower.

[0035] Based on this, embodiments of this application provide a display device, referring to... Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of the display device modules according to an embodiment of this application. Figure 6 This is a schematic diagram of the impedance to be measured, R0. The display device includes a timing controller 100, a level converter 200, an impedance detection circuit 300, a display panel 400, and a circuit board 500. The impedance detection circuit 300 includes the impedance to be measured, R0, and a detection unit 310. The impedance to be measured, R0, is the equivalent impedance from the point where the display panel 400 is pressed against the COF film to the point where the COF film is pressed against the circuit board 500. The first output terminal of the timing controller 100 is connected to the input terminal of the level converter 200, the output terminal of the level converter 200 is connected to the first terminal of the impedance to be measured R0, the second terminal of the impedance to be measured R0 is connected to the first terminal of the detection unit 310, and the second output terminal of the timing controller 100 is connected to the turn-on control terminal of the detection unit 310. Level converter 200 is used to output a preset detection voltage during non-scanning periods between frames, the preset detection voltage being less than a preset gate high-level voltage; The timing controller 100 is used to control the detection unit 310 to be turned on during the non-scanning period between frames, and to detect the resistance value of the impedance R0 to be measured through the detection unit 310.

[0036] It should be noted that the timing controller 100 can be a TCON, and the timing controller 100 can generate various timing control signals required for display driving. During impedance detection, the timing controller 100 is also responsible for outputting a detection on-state level to the detection unit 310 during the inter-frame non-scanning period, causing the detection unit 310 to conduct, thereby completing the resistance detection of the impedance R0 under test. The detection on-state level can be a high level or can be set based on actual conditions; this embodiment does not specifically limit this. The timing controller 100 can also provide a level control signal to the level converter 200 through its first output terminal. In response to the level control signal, the level converter 200 stops outputting the gate drive signal during the inter-frame non-scanning period and outputs a preset detection voltage to the impedance R0 under test; during the normal scanning period, the level converter 200 resumes outputting the normal gate drive signal.

[0037] The level converter 200 receives control commands from the timing controller 100 and performs voltage amplitude matching and signal conversion. The level converter 200 can output a gate drive signal that meets the image driving requirements during normal scanning, or it can output a preset detection voltage with an amplitude lower than the preset gate high-level voltage in the gate drive signal during non-scanning periods between frames. The gate drive signal includes a preset gate high-level voltage, which is used to drive the TFTs in the display panel 400 to conduct, thereby driving the display panel 400 to display normally.

[0038] The impedance detection circuit 300 is used to measure the equivalent impedance (i.e., the impedance to be measured, R0) of the path from the point where the display panel 400 is bonded to the chip-on-film (COF) to the point where the COF is bonded to the circuit board 500. The impedance detection circuit 300 includes the impedance to be measured, R0, and a detection unit 310. The circuit board 500 refers to a printed circuit board 500 or a flexible circuit board 500 bonded to the other end of the COF; in this embodiment, the circuit board 500 can be an XB. The XB can transmit drive signals to the display panel 400 through the COF.

[0039] The impedance to be measured, R0, refers to the equivalent resistance of the entire electrical path from the bonding point between the display panel 400 and the COF (cell bonding) to the bonding point between the COF and the circuit board 500 (XB bonding). Specifically, the bonding between the COF and the display panel can be the bonding between the COF and the cell liquid crystal cell within the display panel.

[0040] The impedance to be measured, R0, includes the resistance of the COF itself, the contact resistance between the COF lead and the Cell lead, and the contact resistance between the COF lead and the XB lead. For example, refer to... Figure 6 , Figure 6The diagram shows a display panel 400, a circuit board 500, a CB board 600 (control board), and a chip-on-film capacitor (COF). J1 refers to the bonding point between the COF and the display panel 400, and J2 refers to the bonding point between the COF and the XB board. The impedance to be measured, R0, is the impedance between J1 and J2, including J1 and J2. Circuit board 500 is the XB board, and the connection between the CB board 600 and the XB board is a wire. The timing controller 100 and the level converter 200 are both located on the CB board 600.

[0041] The inter-frame non-scanning period is the time between the rising edge of the frame cutoff signal of the previous frame and the rising edge of the frame start signal of the next frame in two adjacent frames; the inter-frame non-scanning period can correspond to V Blanking (vertical blanking period).

[0042] The preset gate high voltage refers to the high-level voltage (usually denoted as VGH, or Vgate High) output by the level converter 200 to the gate line in normal display mode, used to turn on the TFT. The preset detection voltage is the voltage output by the level converter 200 during the non-scanning period between frames, and the preset detection voltage is lower than VGH. The main purpose of keeping the preset detection voltage lower than the preset gate high voltage is to avoid interference with the display driver during the detection process. If the detection voltage is too high (close to or reaches VGH), the TFT on the gate line may be accidentally turned on during the non-scanning period between frames, resulting in abnormal pixel charging or display ghosting. Therefore, the preset detection voltage should be lower than the preset gate high voltage.

[0043] Because all gate lines are off during the non-scanning period between frames, the equivalent capacitance of the display panel 400 may be fully charged and no longer shunt current. Therefore, the current in the impedance detection circuit 300 is entirely determined by the impedance to be measured R0 and the components within the detection unit 310, resulting in the most accurate measurement. If the detection unit 310 is turned on during the normal scanning period, the charging and discharging current of the capacitors in the panel will be mixed into the detection circuit, causing measurement errors. Furthermore, performing detection during the non-scanning period between frames does not occupy display time, does not reduce the frame rate, or cause screen flicker.

[0044] For example, you can refer to Figure 7 and Figure 8 , Figure 7 A schematic diagram illustrating the driving timing of a typical GDL (Gate Driver Line) signal is shown. Figure 7This diagram illustrates the driving timing of the GDL signal when detecting the resistance value of the impedance R0 under test during the inter-frame non-scanning phase in this embodiment. The GDL signal includes the STV signal (frame start signal), CK1~CKn signals (clock signals), and the Terminate signal (frame cutoff signal). Line scan pulses are generated according to the timing sequence of CK1~CKn, sequentially turning on the TFTs of the first to nth rows of the display panel 400, thereby completing the line-by-line writing of one frame of image. When the level converter 200 receives the rising edge of the frame cutoff signal, the CK1~CKn signals stop outputting. Thus, the period from the rising edge of the frame cutoff signal of the previous frame to the rising edge of the STV signal of the next frame constitutes the inter-frame non-scanning period (V blanking, vertical blanking region).

[0045] Reference Figure 8 After entering the inter-frame non-scanning period, the timing controller 100 controls the level converter 200 to output a high level that is lower than the normal high level. That is, the level converter 200 outputs a preset detection voltage, which can be referenced. Figure 8 The high level during the D1 reference period. If the preset gate high level voltage is vgh0 during normal operation, then the preset detection voltage vgh1 during impedance detection should be less than vgh0 to avoid accidentally opening pixel rows in the V Blanking area. Figure 8 The Ctrl signal is an on / off control signal output by the timing controller 100. The on / off control signal includes a detection conduction level. In this embodiment, the detection conduction level is a high level, and the amplitude of the detection conduction level can be equal to the preset detection voltage. In this embodiment, in order to avoid affecting the normal display, the rising edge of the Ctrl signal needs to be a certain period of time after the rising edge of the Terminate signal, and the falling edge of the Ctrl signal needs to be a certain period of time before the rising edge of the next STV signal. The preset detection voltage output by the corresponding level converter 200 is also output a certain period of time after the rising edge of the Terminate signal and ends a certain period of time before the rising edge of the next STV signal.

[0046] In this embodiment, the resistance value of the impedance to be measured R0 can be detected during the inter-frame non-scanning period after each frame ends, or the resistance value of the impedance to be measured R0 can be detected periodically. This embodiment does not make specific limitations on this.

[0047] The display device in this embodiment includes a timing controller 100, a level converter 200, an impedance detection circuit 300, a display panel 400, and a circuit board 500. The impedance detection circuit 300 includes an impedance to be measured R0 and a detection unit 310. The impedance to be measured R0 is the equivalent impedance from the point where the display panel 400 is pressed against the COF film to the point where the COF film is pressed against the circuit board 500. The level converter 200 can output a preset detection voltage during the non-scanning period between frames (without affecting the normal display of the display panel 400). The timing controller 100 can control the detection unit 310 to be turned on during the non-scanning period between frames, so that the detection unit 310 can detect the resistance value of the impedance R0 under test. This facilitates the early detection of issues such as shallowing of the COF bonding indentation and poor contact through resistance detection, avoiding signal loss and distortion caused by poor contact, which could lead to display abnormalities. This eliminates the need to wait for display abnormalities to occur before troubleshooting. Furthermore, by limiting the preset detection voltage to be lower than the preset gate high-level voltage, this embodiment avoids interfering with the normal display of the display panel 400 during the detection process during the non-scanning period between frames, ensuring that the detection process does not affect the normal display of the display panel 400. Therefore, this embodiment can detect whether the COF bonding indentation of the flip-chip film has become shallow in advance without affecting the normal display of the display panel 400, so as to deal with the shallowing of the indentation in advance and avoid display abnormalities.

[0048] In one feasible embodiment, please refer to Figure 9 The detection unit 310 includes a current detection resistor Ri, a first resistor R1, a second resistor R2, a detection switch Qj, and an operational amplifier OP1; The first end of the detection switch transistor Qj is used as the first end of the detection unit 310, and the second end of the detection switch transistor Qj is used as the turn-on control end of the detection unit 310. The first end of the detection switch transistor Qj is connected to the first end of the current detection resistor Ri, and the second end of the current detection resistor Ri is grounded. The first end of the current sensing resistor Ri is also connected to the positive input terminal V+ of the operational amplifier, the negative input terminal V- of the operational amplifier is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is grounded. The first end of the first resistor R1 is also connected to the first end of the second resistor R2, the second end of the second resistor R2 is also connected to the output terminal Vout of the operational amplifier, and the output terminal of the operational amplifier OP1 is also connected to the detection input terminal of the timing controller 100.

[0049] It should be noted that the detection switch Qj can be an NMOS transistor, and the second terminal of the detection switch Qj can be the gate. When the gate of the detection switch Qj receives a high level, the detection switch Qj is turned on, and thus the detection unit 310 is turned on. In other embodiments, the detection switch Qj can also be a PMOS transistor. This embodiment does not specifically limit this, and the specific setting can be based on the actual situation. The first terminal of the detection switch Qj is connected to the second terminal of the impedance to be measured R0. The operational amplifier OP1 can be a negative feedback amplifier. During the non-scanning period between frames, when the capacitor in the in-plane RC load within the display panel 400 is fully charged, the current flowing through the current sensing resistor Ri and the current flowing through the impedance to be measured R0 are the same.

[0050] In this embodiment, the timing controller 100 can acquire the output voltage of the operational amplifier OP1 in the detection unit 310 when the voltage across the in-plane capacitor in the in-plane resistive-capacitive load of the display device is stable; based on the output voltage, the first resistor R1, the second resistor R2 in the detection unit 310, and the current detection resistor Ri, it calculates the current flowing through the current detection resistor Ri; based on the current, the current detection resistor Ri, and the preset detection voltage, it calculates the resistance value of the impedance to be measured R0. This allows for the detection of the resistance value of the impedance to be measured R0, thus facilitating the detection of the indentation state. (Refer to...) Figure 9 , Figure 9 In this context, Vcc is the positive voltage connected to the operational amplifier, and Vss is the negative voltage connected to the operational amplifier, used to power the operational amplifier.

[0051] In this embodiment, the detection switch Qj is turned on during the non-scanning period between frames, which ensures that the detection process does not affect the normal scanning of the display panel 400. Thus, real-time and accurate monitoring of the indentation of the COF film is achieved without interfering with the display. This effectively solves the problem of not being able to detect the shallowing of the indentation in real time, thereby improving the reliability and fault prediction capability of the display device.

[0052] In one feasible embodiment, please refer to Figure 10 The display device also includes a gate drive intensity adjustment circuit 700, which is disposed between the output terminal of the level converter 200 and the impedance to be measured R0. The control terminal of the gate drive intensity adjustment circuit 700 is connected to the second output terminal of the timing controller 100. The timing controller 100 is used to control the gate drive strength adjustment circuit 700 to adjust the drive strength of the gate drive signal output by the level converter 200 during the non-scanning period between frames when the resistance value of the impedance to be measured R0 is greater than the preset abnormal threshold.

[0053] It should be noted that the gate drive intensity adjustment circuit 700 can adjust the drive intensity of the gate drive signal. When the drive intensity of the gate drive signal is greater, the current surge received at the flip-chip COF bonding point will be greater. Excessive current surge will also cause the indentation to become shallower. Therefore, in this embodiment, the gate drive intensity adjustment circuit 700 can be used to adjust the drive intensity of the gate drive signal when needed. For example, when the resistance value of the impedance to be measured R0 is greater than the preset abnormal threshold, the timing controller 100 can control the gate drive intensity adjustment circuit 700 to adjust the drive intensity of the gate drive signal during the non-scanning period between frames, thereby reducing the current surge.

[0054] The preset anomaly threshold is a pre-set impedance critical value. This threshold can be set based on actual conditions, and this embodiment does not impose specific limitations. For example, the preset anomaly threshold could be an impedance value that has not yet caused display abnormalities, but where the indentation has become shallow enough to potentially lead to signal loss or distortion. In other words, when the resistance value of the impedance under test, R0, exceeds the preset anomaly threshold, although the current display may still appear normal, the risk of poor contact caused by the indentation of the COF (Chip-on-Foil) film is high. If not intervened in time (e.g., adjusting the drive strength), display abnormalities can easily occur under subsequent changes in ambient temperature or current surges. Therefore, the preset anomaly threshold can be an impedance value that has not yet caused display abnormalities, but where the indentation has become shallow enough to potentially lead to signal loss or distortion. This allows for proactive adjustment of the drive capability before display failure occurs, thereby preventing the actual occurrence of anomalies.

[0055] During the inter-frame non-scanning period, all gate lines are in the off state, and the level converter 200 stops outputting line scan pulses. Adjusting the drive strength during the inter-frame non-scanning period will not affect the progressive scan of the current frame, nor will it affect the progressive scan of the next frame, and will not cause screen flickering or tearing. Furthermore, in this embodiment, the drive strength can be adjusted when the resistance value of the impedance to be measured R0 is detected to be greater than the preset abnormal threshold during the current inter-frame non-scanning period, or the drive strength can be adjusted in the next inter-frame non-scanning period. Since the time between adjacent frames is short enough, the flip-chip COF bonding area will not deteriorate rapidly in such a short time. Therefore, even if the drive strength is adjusted in the next inter-frame non-scanning period, there will be no problem of untimely adjustment.

[0056] In one feasible embodiment, please refer to Figure 11 The gate drive strength adjustment circuit 700 includes: a decoder 710, a preset number of adjustment capacitors and a preset number of adjustment switching transistors. The decoder 710 includes multiple decoding output terminals. The input terminal of the decoder 710 is used as the control terminal of the gate drive strength adjustment circuit 700; For each adjusting switch, the first terminal of the adjusting switch is connected to the decoder output terminal, the second terminal of the adjusting switch is connected to the first terminal of the adjusting capacitor, and the third terminal of the adjusting switch is connected between the level converter 200 and the impedance to be measured R0. The connecting decoder output terminal is different for different adjusting switches, and the connecting adjusting capacitor is different for different adjusting switches. The second terminal of all regulating capacitors is grounded.

[0057] It should be noted that the preset quantity can be determined based on the actual situation. For example, the preset quantity can be 1 or an integer greater than or equal to 2. This embodiment does not make a specific limitation on this. The first terminal of the adjustment switch is the gate. When the decoder output terminal outputs a high level, the adjustment switch connected to the decoder output terminal is turned on. Then, the capacitor connected to the turned adjustment switch can be connected between the level converter 200 and the impedance to be measured R0. In this way, the driving strength of the gate drive signal output by the level converter 200 can be adjusted through the connected capacitor.

[0058] When the adjustment switch connected to the capacitor in the gate drive strength adjustment circuit 700 is turned off, the capacitor connected to the turned-off adjustment switch is not yet connected between the level converter 200 and the impedance to be measured R0. After the adjustment switch is turned on, the capacitor connected to the turned-on adjustment switch will be connected between the level converter 200 and the impedance to be measured R0. The size of the capacitor connected between the level converter 200 and the impedance to be measured R0 varies, and the corresponding drive strength adjustment also varies. The larger the capacitance value, the weaker the drive strength after the gate drive signal adjustment, and the less current surge is experienced at the flip-chip COF bonding point.

[0059] For example, refer to Figure 11 The decoder 710 may include multiple sub-inputs, for example, Figure 11 The diagram shows the three sub-input terminals of decoder 710. This embodiment uses a 3-to-8 decoder 710 as an example for illustration. In other embodiments, decoder 710 can also be of other specifications. This embodiment does not specifically limit this, for example, Figure 11 The decoder's input terminals are shown to include multiple sub-input terminals, designated A, B, and C. The second output terminal of the timing controller 100 may also include multiple sub-output terminals, each connected to a sub-input terminal. Different sub-output terminals in the timing controller 100 are connected to different sub-input terminals of the decoder 710. Figure 11 The diagram also shows multiple adjusting switches Q1~Q8 and multiple adjusting capacitors C1~C8; in other embodiments, the number of adjusting switches may be more than 8 or less than 8, and this embodiment does not specifically limit this.

[0060] In this embodiment, the adjustment switching transistors connected to different decoding output terminals are different, and the adjustment capacitors connected to different adjustment switching transistors are different. The capacitance values ​​of each adjustment capacitor in the gate drive strength adjustment circuit 700 can be different. For example, the capacitance values ​​of each adjustment capacitor can increase in multiples, such as the capacitance of the later capacitor being twice that of the earlier capacitor (i.e., set according to binary weights of 1, 2, 4, 8, etc.), thereby facilitating multi-level adjustment of the drive strength to adapt to different levels of impedance compensation requirements.

[0061] In one feasible embodiment, please refer to Figure 12 The display panel 400 has an in-plane RC load 800, and the second end of the impedance to be measured R0 is also connected to the in-plane RC load 800.

[0062] It should be noted that the in-plane RC load 800 is an RC load within the display panel 400. Within the display panel 400, the gate lines themselves have resistance, and parasitic capacitance is formed between the gate lines and the common electrode and pixel electrode. Data lines also have distributed resistance and capacitance to ground. Therefore, an in-plane RC load exists within the display panel 400. Specifically, the in-plane RC load includes multiple in-plane resistors Rj1~Rjk and multiple in-plane capacitors Cj1~Cjk, where k can be a positive integer greater than 1; this embodiment does not impose a specific limitation on this.

[0063] During the non-scanning period between frames, after the capacitor in the in-plane RC load is fully charged, the current flowing through the current detection resistor Ri is calculated, and then the resistance value of the impedance to be measured R0 is calculated based on the current, thereby ensuring the accuracy of the resistance value detection of the impedance to be measured R0, so as to improve the reliability of the display device.

[0064] Furthermore, based on the above embodiments of this application, in another embodiment of this application, the same or similar content as the above embodiments can be referred to the above description, and will not be repeated hereafter. On this basis, this embodiment also provides a detection method, which is applied to the above-mentioned display device, referring to... Figure 13 The detection method includes steps S10 to S20: Step S10: During the non-scanning period between frames of the display device, a preset detection voltage is output to the impedance to be measured through the level converter of the display device, and the detection unit in the display device is turned on through the timing controller of the display device. The preset detection voltage is less than the preset gate high level voltage. It should be noted that during the non-scanning period between frames, the timing controller can control the level converter to output a preset detection voltage, which facilitates the subsequent detection of the resistance value of the impedance under test. The timing controller also controls the detection unit to be turned on, so that the resistance value of the impedance under test can be detected subsequently through the detection unit.

[0065] For example, during each inter-frame non-scanning period, the timing controller of the display device can control the level converter to output a preset detection voltage, and the timing controller can also control the detection unit in the display device to turn on. In other embodiments, the timing controller of the display device can also control the level converter to output a preset detection voltage during the inter-frame non-scanning period according to a preset period, and the timing controller can also control the detection unit in the display device to turn on. The preset period can be every M frames, where M can be an integer greater than 2. This embodiment does not specifically limit this, and it can be set based on actual conditions.

[0066] In a feasible embodiment, the inter-frame non-scanning period is the time period between the rising edge of the frame cutoff signal of the previous frame and the rising edge of the frame start signal of the next frame in two adjacent frames; the detection method further includes steps S11 to S12: Step S11: After a preset first redundancy duration following the rising edge of the frame cutoff signal, a preset detection voltage is output through a level converter, and the detection unit is turned on through a timing controller. In step S12, before the rising edge of the frame start signal, a preset second redundancy time is set, the level converter is controlled to stop outputting the preset detection voltage, and the detection unit is controlled to turn off by the timing controller.

[0067] It should be noted that the preset first redundancy duration and the preset second redundancy duration can be set based on actual conditions. The preset first redundancy duration and the preset second redundancy duration can be the same or different. This embodiment does not impose specific limitations on this, and can determine them based on actual conditions. For example, the preset first redundancy duration can be 10% of the duration of the inter-frame non-scanning period, or it can be other percentages. This embodiment does not impose specific limitations on this, for example, it can also be 5%, or 15%, etc. The preset second redundancy duration can be equal to the preset first redundancy duration. The sum of the preset second redundancy duration and the preset first redundancy duration is less than the duration of the inter-frame non-scanning period.

[0068] For example, to avoid affecting the normal display of the display panel, in this embodiment, the level converter may not output a preset detection voltage and the detection unit may not be turned on throughout the entire non-scanning period between frames. Instead, the preset detection voltage is output by the level converter after a preset first redundancy period following the rising edge of the frame cutoff signal, and the detection unit is turned on by the timing controller. Before the rising edge of the frame start signal, a preset second redundancy period is reached, and the level converter stops outputting the preset detection voltage, while the detection unit is turned off by the timing controller. This facilitates the detection of the impedance to be measured without affecting the normal display of the display panel.

[0069] Step S20: When the level converter outputs a preset detection voltage and the detection unit is turned on, the resistance value of the impedance to be measured is detected.

[0070] It should be noted that during the non-scanning period between frames, there may be a situation where the level converter outputs a preset detection voltage and the detection unit is turned on. Detecting the resistance value of the impedance to be measured during the non-scanning period between frames can improve the accuracy of the detection and avoid affecting the normal display of the display panel. For example, in this embodiment, when the level converter outputs a preset detection voltage and the detection unit is turned on, the resistance value of the impedance to be measured can be detected. For example, the resistance value of the impedance to be measured can be calculated in the timing controller of the display device.

[0071] Because this embodiment can output a preset detection voltage during the non-scanning period between frames (without affecting the normal display of the display panel), it can control the detection unit to conduct during the non-scanning period between frames, thereby enabling the detection unit to detect the resistance value of the impedance under test. This facilitates the early detection of issues such as shallowing of the flip-chip bonding indentation and poor contact through resistance detection, avoiding signal loss and distortion caused by poor contact, which could lead to display abnormalities. This eliminates the need to wait until display abnormalities occur before troubleshooting. Furthermore, by limiting the preset detection voltage to be lower than the preset gate high-level voltage, this embodiment avoids interfering with the normal display of the display panel during the detection process during the non-scanning period between frames, ensuring that the detection process does not affect the normal display of the display panel. Therefore, this embodiment can detect whether the flip-chip bonding indentation is shallowing in advance without affecting the normal display of the display panel, so as to deal with the shallowing of the indentation in advance and avoid display abnormalities.

[0072] In a feasible embodiment, step S20 further includes steps S21 to S23: Step S21: Obtain the output voltage of the operational amplifier in the detection unit when the voltage across the in-plane capacitor in the in-plane resistive-capacitive load in the display device is stable. It should be noted that the output voltage refers to the voltage output by the operational amplifier when the voltage across the capacitor in the in-plane RC load is stable. The in-plane RC load includes a capacitor. After the preset detection voltage is output, the capacitor may undergo a brief charging or discharging process, and the voltage across the capacitor is in a dynamic fluctuation state. Therefore, in order to ensure the accuracy of the subsequent resistance value detection of the impedance to be measured, the voltage output by the operational amplifier should be obtained only when the voltage across the capacitor in the in-plane RC load is stable.

[0073] In an in-plane capacitive load, the voltage across the capacitor is stable when the capacitor has completed its charge-discharge balance and the voltage no longer changes. When the voltage across the capacitor is stable, no current flows into the in-plane capacitive load. Therefore, the current flowing through the current sensing resistor and the current flowing through the impedance to be measured will be equal, making it easier to detect the impedance to be measured.

[0074] For example, after a preset detection voltage is output, the voltage output by the operational amplifier can be continuously monitored by a timing controller during the inter-frame non-scanning period. The maximum voltage detected by the operational amplifier during the inter-frame non-scanning period can be used as the output voltage. In other embodiments, the output voltage of the operational amplifier can be obtained by the timing controller after a preset stabilization period following the start of the inter-frame non-scanning period. The preset stabilization period can be set based on actual conditions, and this embodiment does not impose a specific limitation on it. After the preset stabilization period, it indicates that the voltage across the capacitor in the in-plane resistive-capacitive load has stabilized. Therefore, the output voltage of the operational amplifier can also be obtained after the preset stabilization period.

[0075] Step S22: Calculate the current flowing through the current detection resistor based on the output voltage, the first resistor, the second resistor in the detection unit, and the current detection resistor; It should be noted that the following explanation of the process for calculating the current flowing through the current sensing resistor is based on the virtual short and virtual open characteristics of operational amplifiers. Therefore, according to the virtual short characteristic of operational amplifiers, Formula 1 exists: V+=V-(Formula 1) Where V+ is the voltage at the positive input terminal of the operational amplifier, and V- is the voltage at the negative input terminal of the operational amplifier.

[0076] Based on the virtual open characteristic of operational amplifiers, meaning no current flows through the input and output terminals, the current flowing through the first resistor and the second resistor is equal. Therefore, Formula 2 exists: (Vout-V-) / R2=V- / R1 (Formula 2); Where Vout is the output voltage, R1 is the first resistor, and R2 is the second resistor.

[0077] From formulas 1 and 2, we can obtain formula 3: Vout=V+*(R2+R1) / R1 (Formula 3); If the current flowing through the current sensing resistor is i1, then Equation 4 applies: V+=i1*Ri (Formula 4); Where Ri is the current sensing resistor. Formula 5 can be derived from Formulas 3 and 4: i1=V+ / Ri=Vout*R1 / ((R2+R1)*Ri) (Formula 5; In Equation 5, the timing controller can obtain Vout, and Ri, R1, and R2 are all known resistance values. Therefore, the timing controller can calculate the current i1 flowing through the current sensing resistor using Equation 5.

[0078] Step S23: Calculate the resistance value of the impedance to be measured based on the current, the current detection resistor, and the preset detection voltage.

[0079] It should be noted that since the capacitor within the in-plane resistive-capacitive load is already fully charged, no current will flow to the in-plane resistive-capacitive load. (Refer to...) Figure 12 The current flows through the impedance to be measured and then to the current sensing resistor. Therefore, the current flowing through the current sensing resistor is the same as the current flowing through the impedance to be measured, hence Formula 6 applies: i1=Vgh1 / (Ri+R0) (Formula 6); Where R0 is the impedance to be measured, and Vgh1 is the preset detection voltage. Formula 7 can be obtained from Formulas 6 and 5, and the timing controller can then calculate the resistance value of the impedance to be measured using Formula 7: R0=(R2+R1)*Ri*Vgh1 / (Vout*R1)-Ri (Formula 7); Where R0 is the impedance to be measured, and the resistance values ​​of the first resistor R1, the second resistor R2, the current sensing resistor Ri, the preset detection voltage Vgh1, and the output voltage Vout are all known, the impedance to be measured can be calculated using Formula 7, thereby enabling the detection of the impedance to be measured. For example, the resistance value of the impedance to be measured can be calculated by a timing controller based on the first resistor, the second resistor, the preset detection voltage, the current sensing resistor, and the output voltage.

[0080] This embodiment first obtains the operational amplifier output voltage when the voltage across the in-plane capacitor in the in-plane resistive-capacitive load is stable. Then, it uses the established relationship between this output voltage and the known first resistor, second resistor, and current detection resistor to calculate the current flowing through the current detection resistor. Finally, it combines this current, the current detection resistor, and the preset detection voltage to deduce the resistance value of the impedance to be measured. It utilizes the characteristic that the capacitor does not shunt current in steady state during the non-scanning period between frames and the virtual short and virtual open characteristics of the operational amplifier, so that the entire measurement process is not affected by the dynamic charging and discharging of the panel. The calculation is simple and highly accurate, so that the resistance value of the impedance to be measured can be accurately detected without affecting the normal display.

[0081] In a feasible embodiment, the detection method further includes steps A10 to A30: Step A10: If the resistance value of the impedance to be measured is detected to be greater than the preset abnormal threshold, an impedance abnormality prompt is output, and the target capacitor corresponding to the resistance value of the impedance to be measured is obtained from the preset impedance-capacitance mapping relationship constructed by the preset impedance and the preset capacitor. It should be noted that the impedance anomaly warning is an alert generated proactively by the display device when it detects that the resistance value of the measured impedance exceeds a preset anomaly threshold. The impedance anomaly warning can indicate that the contact performance at the flip-chip bonding interface has deteriorated, that poor contact may exist, or that poor contact is about to occur. The preset impedance-capacitance mapping relationship can be obtained in advance through experimentation. In this mapping relationship, the larger the preset impedance, the larger the corresponding preset capacitance value, and vice versa.

[0082] The target capacitor is a preset capacitor obtained from the preset impedance-capacitance mapping relationship that corresponds to the current resistance value of the impedance to be measured.

[0083] For example, if the resistance value of the impedance under test is detected to be greater than a preset abnormal threshold, an impedance abnormality warning can be output. Specifically, during the production process of the display device, the timing controller of the display device can monitor the resistance value of the impedance under test in real time. The timing controller can communicate with the host computer of the display device to transmit the detected resistance value of the impedance under test to the host computer. When the resistance value of the impedance under test is greater than the preset abnormal threshold, an alarm is issued to remind the production operators to handle it. After the display device leaves the factory, if the timing controller detects that the resistance value of the impedance under test is greater than the preset abnormal threshold during use, it can promptly respond through the SOC (System on Chip) in the display device, connect to the network, and respond through the manufacturer's after-sales service platform. It can also simultaneously adjust the drive strength of the GDL signal to reduce the current impact of the GDL signal on the flip-chip bonding point, thereby extending the product's service life.

[0084] Step A20: Based on the target capacitance, determine the capacitance to be connected between the level converter and the impedance to be measured in the gate drive strength adjustment circuit of the display device. It should be noted that the capacitor to be connected is the adjustment capacitor that needs to be turned on within the gate drive strength adjustment circuit. For example, a target adjustment capacitor with the same capacitance value as the target capacitor can be found among the adjustment capacitors included in the gate drive strength adjustment circuit as the capacitor to be connected; if there is no capacitor with the same capacitance value as the target capacitor among the adjustment capacitors, then the target adjustment capacitor with the smallest absolute value of the difference between its capacitance value and that of the target capacitor is found as the capacitor to be connected.

[0085] Step A30: Connect the capacitor to be connected between the level converter and the impedance to be measured to adjust the driving strength of the gate drive signal output by the level converter.

[0086] It should be noted that once the capacitor to be connected is determined, it can be connected between the level converter and the impedance to be measured. For example, the target adjustment switch connected to the capacitor can be turned on so that the capacitor is connected between the level converter and the impedance to be measured.

[0087] This embodiment outputs an impedance abnormality warning when an abnormality is detected in the measured impedance. This provides real-time alarms during production to remind operators to handle the issue promptly, or allows for proactive responses through a networked after-sales platform during user operation, thus effectively reducing display anomalies. Furthermore, the determination of the capacitor to be connected in this embodiment supports both accurate matching of the target capacitor and allows selection of the closest capacitance value when a perfect match is not possible, ensuring feasibility and effectiveness. By connecting the capacitor to the drive circuit through the corresponding adjustment switch, the driving capability of the gate drive signal can be adjusted, reducing the current surge at the flip-chip bonding point. This extends the product's lifespan while effectively preventing display anomalies caused by shallowing indentations, significantly improving the reliability of the display device.

[0088] In a feasible embodiment, step A30 further includes steps A31 to A32: Step A31: Determine the target adjustment switch connected to the capacitor to be connected, and generate an adjustment control signal based on the target decoding output terminal connected to the target adjustment switch. It should be noted that the target adjustment switch is the adjustment switch connected to the capacitor in the gate drive intensity adjustment circuit. The adjustment capacitor can be a single capacitor or multiple capacitors connected in parallel or series, etc. This embodiment does not make specific limitations on this.

[0089] The decoder has multiple independent decoding outputs, each connected to a corresponding adjustment switch. The target decoding output is directly connected to the target adjustment switch. The decoder can output a valid level at the target decoding output based on the input adjustment control signal, thereby controlling the target adjustment switch connected to the target decoding output to conduct, and thus connecting the target capacitor connected to the target adjustment switch between the level converter and the impedance to be measured.

[0090] The adjustment control signal is generated by the timing controller based on the target decoding output. The adjustment control signal is used to instruct the decoder to select the target decoding output, while other decoding outputs in the decoder are not selected.

[0091] Step A32: Input the adjustment control signal to the input terminal of the decoder in the gate drive strength adjustment circuit, so that the target decoder output terminal outputs a preset conduction level, thereby turning on the target adjustment switch connected to the target decoder output terminal, so that the capacitor to be connected is connected between the level converter and the impedance to be measured.

[0092] It should be noted that the decoder's input terminals include multiple sub-input terminals, and the adjustment control signal can be a string of binary codes. Different combinations of binary codes correspond to different decoding output terminals of the decoder.

[0093] For example, let's take a decoder with three sub-inputs (A, B, C) and eight outputs (Y01 to Y08), as shown in Table 1. Table 1:

[0094] As shown in Table 1, different adjustment control signals result in different target decoding output terminals being activated. The selected terminals in Table 1 refer to the target decoding output terminals. In this embodiment, a timing controller can generate a corresponding adjustment control signal based on the target decoding output terminal, and input the adjustment control signal to the input terminal of the decoder through the timing controller. This causes the decoder to activate the corresponding target decoding output terminal. When the target decoding output terminal is activated, it will output a preset activation level, which can be a high level. This activates the target adjustment switch connected to the target decoding output terminal, thereby connecting the target capacitor connected to the target adjustment switch between the level converter and the impedance to be measured.

[0095] In this embodiment, when the timing controller detects that the resistance value of the impedance to be measured is greater than a preset abnormal threshold, the timing controller determines the target adjustment capacitor and generates an adjustment control signal for turning on the target adjustment switch connected to the target adjustment capacitor. (Refer to...) Figure 14 , Figure 14 The diagram shows the waveform of the GDL signal when different adjustment capacitors are connected. The dashed line is the waveform output by the level converter, and the solid line is the waveform after connecting different adjustment capacitors. Since the adjustment capacitor is charged at the rising and falling edges of the GDL signal, the voltage at the rising and falling edges of the GDL signal will slow down after passing through the adjustment capacitor. At the same time, the peak value of the current of the GDL signal will also decrease, which can reduce the current impact at the flip-chip bonding point. Figure 15 The diagram shows the current and voltage waveforms of the GDL signal after changing the driving strength of the GDL signal. Figure 15 As can be seen from this, after reducing the driving intensity, compared to Figure 4 The absolute values ​​of the maximum and minimum GDL signal currents are small.

[0096] This embodiment utilizes a timing controller to generate a corresponding adjustment control signal (such as binary code) based on the target decoding output terminal, enabling the decoder to accurately select the target decoding output terminal and output a preset conduction level. This allows only the target adjustment switch connected to the capacitor to be connected to be turned on, achieving independent and conflict-free selection control of multiple adjustment capacitors. Furthermore, it can accurately adjust the driving strength of the gate drive signal, reducing the current surge received by the flip-chip film and thus facilitating the extension of the display device's lifespan.

[0097] The display device provided in this application, employing the detection method described in the above embodiments, can solve the technical problem of display abnormalities. Compared with the prior art, the beneficial effects of the display device provided in this application are the same as those of the detection method provided in the above embodiments, and other technical features of the display device are the same as those disclosed in the method of the previous embodiment, and will not be repeated here.

[0098] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0099] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0100] This embodiment provides a computer-readable storage medium having computer-readable program instructions stored thereon, which are used to execute the detection method in Embodiment 1 above.

[0101] The computer-readable storage medium provided in this application embodiment may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor devices, apparatuses, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable EPROM (Electrical Programmable Read Only Memory) or flash memory, optical fiber, portable compact disk CD-ROM (compact discread-only memory), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution device, apparatus, or apparatus. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0102] The aforementioned computer-readable storage medium may be included in the display device or may exist independently without being assembled into the display device.

[0103] The aforementioned computer-readable storage medium carries one or more programs that, when executed by a display device, cause the display device to: output a preset detection voltage to the impedance to be measured via a level converter of the display device during an inter-frame non-scanning period of the display device, and control the detection unit in the display device to be turned on via a timing controller of the display device, wherein the preset detection voltage is less than a preset gate high-level voltage; and detect the resistance value of the impedance to be measured when the level converter outputs the preset detection voltage and the detection unit is turned on.

[0104] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a LAN (local area network) or WAN (wide area network)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0105] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of devices, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based device that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0106] The modules described in the embodiments of this disclosure can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0107] The computer-readable storage medium provided in this application embodiment stores computer-readable program instructions for performing the above-described detection method, aiming to solve the technical problem of display anomalies. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application embodiment are the same as the beneficial effects of the detection method provided in the above embodiments, and will not be repeated here.

[0108] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the detection method described above.

[0109] The computer program product provided in this application aims to solve the technical problem of display anomalies. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the detection method provided in the above embodiments, and will not be repeated here.

[0110] The above are merely preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structural or procedural transformations made using the description and drawings of the present application, or direct or indirect applications in other related technical fields, are similarly included within the patent processing scope of the present application.

Claims

1. A display device, characterized in that, The display device includes a timing controller, a level converter, an impedance detection circuit, a display panel, and a circuit board. The impedance detection circuit includes an impedance to be measured and a detection unit. The impedance to be measured is the equivalent impedance from the bonding point between the display panel and the flip-chip film to the bonding point between the flip-chip film and the circuit board. The detection unit includes a current detection resistor, a first resistor, a second resistor, a detection switch transistor, and an operational amplifier. The first output terminal of the timing controller is connected to the input terminal of the level converter, the output terminal of the level converter is connected to the first terminal of the impedance to be measured, the second terminal of the impedance to be measured is connected to the first terminal of the detection unit, and the second output terminal of the timing controller is connected to the turn-on control terminal of the detection unit. The level converter is used to output a preset detection voltage during the non-scanning period between frames, and the preset detection voltage is less than the preset gate high level voltage. The timing controller is used to control the detection unit to be turned on during the non-scanning period between frames, and to detect the resistance value of the impedance to be measured through the detection unit; The first end of the detection switch is used as the first end of the detection unit, the second end of the detection switch is used as the turn-on control end of the detection unit, the third end of the detection switch is connected to the first end of the current detection resistor, and the second end of the current detection resistor is grounded. The first end of the current sensing resistor is also connected to the positive input terminal of the operational amplifier, the negative input terminal of the operational amplifier is connected to the first end of the first resistor, and the second end of the first resistor is grounded. The first end of the first resistor is also connected to the first end of the second resistor, the second end of the second resistor is connected to the output of the operational amplifier, and the output of the operational amplifier is also connected to the detection input of the timing controller.

2. The display device as claimed in claim 1, characterized in that, The display device further includes a gate drive strength adjustment circuit, which is disposed between the output terminal of the level converter and the impedance to be measured, and the control terminal of the gate drive strength adjustment circuit is connected to the third output terminal of the timing controller. The timing controller is used to control the gate drive strength adjustment circuit to adjust the drive strength of the gate drive signal output by the level converter during the non-scanning period between frames when the resistance value of the impedance to be measured is greater than a preset abnormal threshold.

3. The display device as claimed in claim 2, characterized in that, The gate drive strength adjustment circuit includes: a decoder, a preset number of adjustment capacitors, and a preset number of adjustment switching transistors. The decoder includes multiple decoding output terminals. The input terminal of the decoder is used as the control terminal of the gate drive intensity adjustment circuit. For each adjustment switch, the first terminal of the adjustment switch is connected to the decoder output terminal, the second terminal of the adjustment switch is connected to the first terminal of the adjustment capacitor, and the third terminal of the adjustment switch is connected between the level converter and the impedance to be measured. The decoder output terminal and the adjustment capacitor connected to different adjustment switches are different. The second terminal of all the aforementioned adjustment capacitors is grounded.

4. The display device as claimed in claim 1, characterized in that, The display panel has an in-plane RC load, and the second end of the impedance to be measured is also connected to the in-plane RC load.

5. A detection method, characterized in that, The detection method is applied to the display device as described in claim 3, and the detection method includes: During the non-scanning period between frames of the display device, a preset detection voltage is output to the impedance to be measured through the level converter of the display device, and the detection unit in the display device is turned on by the timing controller of the display device, wherein the preset detection voltage is less than the preset gate high level voltage; When the level converter outputs a preset detection voltage and the detection unit is turned on, the resistance value of the impedance to be measured is detected.

6. The detection method as described in claim 5, characterized in that, The inter-frame non-scanning period is the time interval between the rising edge of the frame cutoff signal of the preceding frame and the rising edge of the frame start signal of the following frame; the method further includes: After a preset first redundancy duration following the rising edge of the frame cutoff signal, a preset detection voltage is output through the level converter, and the detection unit is turned on by the timing controller. Before the rising edge of the frame start signal, a preset second redundancy time is elapsed, and the control level converter stops outputting the preset detection voltage, and the timing controller controls the detection unit to turn off.

7. The detection method as described in claim 5, characterized in that, The step of detecting the resistance value of the impedance to be measured includes: The output voltage of the operational amplifier in the detection unit is obtained when the voltage across the in-plane capacitor in the in-plane resistive-capacitive load of the display device is stable. The current flowing through the current detection resistor is calculated based on the output voltage, the first resistor, the second resistor, and the current detection resistor in the detection unit; The resistance value of the impedance to be measured is calculated based on the current, the current detection resistor, and the preset detection voltage.

8. The detection method as described in claim 5, characterized in that, The detection method further includes: If the resistance value of the impedance to be measured is detected to be greater than a preset abnormal threshold, an impedance abnormality prompt is output, and the target capacitor corresponding to the resistance value of the impedance to be measured is obtained from the preset impedance-capacitance mapping relationship constructed by the preset impedance and the preset capacitor. Based on the target capacitance, a capacitor to be connected between the level converter and the impedance to be measured is determined in the gate drive strength adjustment circuit of the display device. The capacitor to be connected is the adjustment capacitor that needs to be turned on in the gate drive strength adjustment circuit. The capacitor to be connected is connected between the level converter and the impedance to be measured to adjust the driving strength of the gate drive signal output by the level converter.

9. The detection method as described in claim 8, characterized in that, The step of connecting the capacitor to be connected between the level converter and the impedance to be measured includes: The target adjustment switch connected to the capacitor to be connected is determined, and an adjustment control signal is generated based on the target decoding output terminal connected to the target adjustment switch. The adjustment control signal is input to the input terminal of the decoder in the gate drive strength adjustment circuit, so that the target decoder output terminal outputs a preset conduction level to conduct the target adjustment switch connected to the target decoder output terminal, so that the capacitor to be connected is connected between the level converter and the impedance to be measured.

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