A display system, display module, memory and electronic device

Abstract

Embodiments of the present application relate to a display system, a display module, a memory and an electronic device, and relate to the technical field of display. The display system comprises a first display screen, a second display screen and a memory. The memory comprises a first end and a second end. The first display screen is coupled to the first end of the memory, and the second display screen is coupled to the second end of the memory. The color displayed by the first display screen is different from the color displayed by the second display screen. A first switch circuit is arranged on the transmission path between the first display screen and the memory, and a second switch circuit is arranged on the transmission path between the second display screen and the memory. In this way, the cost of the memory can be saved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display system, display module, memory, and electronic device. Background Technology

[0002] Electronic devices with display capabilities may include a display screen and memory, with the display screen coupled to the memory. During the screen startup process, the screen can read data from the memory, which may be the data required for the startup process. If an electronic device has multiple displays, multiple memories are required, resulting in higher costs. Summary of the Invention

[0003] This application provides a display system, display module, memory, and electronic device, which solves the problem of high cost of electronic devices in the prior art.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] In a first aspect, a display system is provided. The display system includes a first display screen, a second display screen, and a memory. The memory includes a first terminal and a second terminal. The first display screen is coupled to the first terminal of the memory, and the second display screen is coupled to the second terminal of the memory. The colors displayed by the first display screen and the second display screen are different. A first switching circuit is provided on the transmission path between the first display screen and the memory, and a second switching circuit is provided on the transmission path between the second display screen and the memory.

[0006] In the above technical solution, the first and second displays can be coupled to the same memory. When the first display writes data to the memory, the first switching circuit is turned on, and the second switching circuit is turned off. At any given time, only one display can operate on the data in the memory, thus avoiding multi-drive problems. Furthermore, the data from multiple displays can be stored in different locations within the same memory, requiring only one memory for all displays. This memory has high storage space utilization, reducing storage space waste. Additionally, the structures of the first and second switching circuits are relatively simple. The cost of setting up multiple switching circuits in a display system is lower than the cost of setting up multiple memories. Therefore, only one memory is needed to store the data from multiple displays, resulting in lower hardware costs and lower operating and standby power consumption. This reduces overall power consumption and improves overall system performance and standby battery life.

[0007] In one possible implementation of the first aspect, the first display screen includes a first functional circuit and a first switching circuit. The first functional circuit is coupled to a first terminal of the first switching circuit, and the second terminal of the first switching circuit is coupled to a first terminal of a memory. The second display screen includes a second functional circuit and a second switching circuit. The second functional circuit is coupled to a first terminal of the second switching circuit, and the second terminal of the second switching circuit is coupled to a second terminal of the memory. In the above possible implementations, the first switching circuit can be disposed in the first display screen, and the second switching circuit can be disposed in the second display screen. The cost of disposing of a single switching circuit within a display screen is relatively low. Furthermore, the switching circuit within the display screen can be controlled by the display screen's driver chip, and the control method and connection relationship of the switching circuit are relatively simple.

[0008] In one possible implementation of the first aspect, the first display screen further includes a first interface circuit. The first interface circuit includes a first terminal and a second terminal. A first functional circuit is coupled to the first terminal of the first interface circuit, the first terminal of the first interface circuit is coupled to the first terminal of a first switching circuit, the second terminal of the first switching circuit is coupled to the second terminal of the first interface circuit, and the second terminal of the first interface circuit is coupled to the first terminal of a memory. And / or, the second display screen further includes a second interface circuit. The second interface circuit includes a first terminal and a second terminal. A second functional circuit is coupled to the first terminal of the second interface circuit, the first terminal of the second interface circuit is coupled to the first terminal of the second switching circuit, the second terminal of the second switching circuit is coupled to the second terminal of the second interface circuit, and the second terminal of the second interface circuit is coupled to the second terminal of the memory. In the above possible implementations, the first switching circuit can specifically be disposed in the first interface circuit of the first display screen, and the second switching circuit can be disposed in the second interface circuit of the second display screen. Thus, the placement of the switching circuit will not affect the structure of other functional circuits of the display screen.

[0009] In one possible implementation of the first aspect, the first display screen further includes a first interface circuit. The first interface circuit includes a first terminal and a second terminal. A first functional circuit is coupled to the first terminal of the first interface circuit, the first terminal of the first interface circuit is coupled to the second terminal of the first interface circuit, the second terminal of the first interface circuit is coupled to the first terminal of a first switch circuit, and the second terminal of the first switch circuit is coupled to the first terminal of a memory. And / or, the second display screen further includes a second interface circuit. The second interface circuit includes a first terminal and a second terminal. A second functional circuit is coupled to the first terminal of the second interface circuit, the first terminal of the second interface circuit is coupled to the second terminal of the second interface circuit, the second terminal of the second interface circuit is coupled to the first terminal of a second switch circuit, and the second terminal of the second switch circuit is coupled to the second terminal of the memory. In the above possible implementations, the first switch circuit can specifically be located at the rear end of the first interface circuit of the first display screen, and the second switch circuit can be located at the rear end of the second interface circuit of the second display screen. Thus, the arrangement of the switch circuit will not affect the structure of the display screen's interface circuit and other functional circuits.

[0010] In one possible implementation of the first aspect, a first display screen is coupled to a first terminal of a first switching circuit, and a second terminal of the first switching circuit is coupled to a first terminal of a memory. And / or, a second display screen is coupled to a first terminal of a second switching circuit, and a second terminal of the second switching circuit is coupled to a second terminal of the memory. In the above possible implementations, the first switching circuit can be separately disposed from the first display screen and the second memory, and is disposed between the first display screen and the second memory. The second switching circuit can be separately disposed from the second display screen and the second memory, and is disposed between the second display screen and the second memory. Thus, the arrangement of the switching circuits does not affect the structure of the display screen.

[0011] In one possible implementation of the first aspect, the memory includes a storage circuit, a first switching circuit, and a second switching circuit. A first terminal of the memory is coupled to a first terminal of the first switching circuit. A second terminal of the first switching circuit is coupled to the storage circuit. A second terminal of the memory is coupled to a first terminal of the second switching circuit. A second terminal of the second switching circuit is coupled to the storage circuit. In the above possible embodiments, at least one of the first and second switching circuits can be disposed within the memory. Disposing of a switching circuit within the memory is less costly. Furthermore, the switching circuit within the memory can be controlled by a control circuit within the memory, and the control method and connection relationship of the switching circuit are relatively simple.

[0012] In one possible implementation of the first aspect, the memory further includes a third interface circuit. The third interface circuit includes a first terminal, a second terminal, and a third terminal. The first terminal of the memory is coupled to the first terminal of the third interface circuit, the first terminal of the third interface circuit is coupled to the first terminal of a first switching circuit, the second terminal of the first switching circuit is coupled to the third terminal of the third interface circuit, and the third terminal of the third interface circuit is coupled to the storage circuit. And / or, the second terminal of the memory is coupled to the second terminal of the third interface circuit, the second terminal of the third interface circuit is coupled to the first terminal of a second switching circuit, the second terminal of the second switching circuit is coupled to the third terminal of the third interface circuit, and the third terminal of the third interface circuit is coupled to the storage circuit. In the above possible implementations, at least one of the first and second switching circuits can be disposed in the third interface circuit of the memory. Thus, the placement of the switching circuit does not affect the structure of other circuits in the memory.

[0013] In one possible implementation of the first aspect, the memory further includes a third interface circuit. The third interface circuit includes a first terminal, a second terminal, and a third terminal. The first terminal of the memory is coupled to the first terminal of a first switching circuit, the second terminal of the first switching circuit is coupled to the first terminal of the third interface circuit, the first terminal of the third interface circuit is coupled to the third terminal of the third interface circuit, and the third terminal of the third interface circuit is coupled to the storage circuit. And / or, the second terminal of the memory is coupled to the first terminal of a second switching circuit, the second terminal of the second switching circuit is coupled to the second terminal of the third interface circuit, the second terminal of the third interface circuit is coupled to the third terminal of the third interface circuit, and the third terminal of the third interface circuit is coupled to the storage circuit. In the above possible implementations, at least one of the first and second switching circuits can be disposed at the rear end of the memory's third interface circuit. Thus, the placement of the switching circuit does not affect the structure of the memory's third interface circuit and other circuits.

[0014] In one possible implementation of the first aspect, the memory is configured to receive a read instruction via a target port. The read instruction is used to instruct the reading of data. The target port is either a first end or a second end of the memory. The memory is also configured to transmit data via the target port. In the above possible implementations, the memory determines the display screen for data transmission based on the port, ensuring correct data transmission.

[0015] In one possible implementation of the first aspect, the display system further includes a third display screen. The memory also includes a third terminal, to which the third display screen is coupled. The colors displayed by the third display screen, the first display screen, and the second display screen are all different. A third switching circuit is provided on the transmission path between the third display screen and the memory.

[0016] In the above possible implementations, the number of displays can be two, three, or even more. Therefore, it can be applied to a wide range of application scenarios.

[0017] In one possible implementation of the first aspect, the memory is a non-volatile memory. In the above possible implementations, the memory can stably store data from the display screen.

[0018] In one possible implementation of the first aspect, the first and second switching circuits are not simultaneously turned on. In the above possible implementations, at any given time, only one of the two switching circuits is on, while the other is off. That is, at any given time, only one display screen can transmit data to the memory, while the transmission path between the other display screen and the memory is disconnected, preventing data transmission. This avoids the multi-drive problem. Furthermore, hardware control via a simple switching circuit is simpler than software control.

[0019] Secondly, a display module is provided. The display module includes a first display screen and a second display screen. The colors displayed on the first display screen and the colors displayed on the second display screen are different. The first display screen includes a first functional circuit and a first switching circuit. The first functional circuit is coupled to a first terminal of the first switching circuit, and the second terminal of the first switching circuit is used to couple a memory. The second display screen includes a second functional circuit and a second switching circuit. The second functional circuit is coupled to a first terminal of the second switching circuit, and the second terminal of the second switching circuit is used to couple a memory.

[0020] In one possible implementation of the second aspect, the first display screen further includes a first interface circuit. The first interface circuit includes a first terminal and a second terminal. A first functional circuit couples to the first terminal of the first interface circuit, the first terminal of the first interface circuit couples to the first terminal of a first switching circuit, the second terminal of the first switching circuit couples to the second terminal of the first interface circuit, and the second terminal of the first interface circuit is used to couple a memory. And / or, the second display screen further includes a second interface circuit. The second interface circuit includes a first terminal and a second terminal. A second functional circuit couples to the first terminal of the second interface circuit, the first terminal of the second interface circuit couples to the first terminal of a second switching circuit, the second terminal of the second switching circuit couples to the second terminal of the second interface circuit, and the second terminal of the second interface circuit is used to couple a memory.

[0021] In one possible implementation of the second aspect, the first display screen further includes a first interface circuit. The first interface circuit includes a first terminal and a second terminal. A first functional circuit couples to the first terminal of the first interface circuit, the first terminal of the first interface circuit couples to the second terminal of the first interface circuit, and the second terminal of the first interface circuit couples to the first terminal of a first switching circuit. The second terminal of the first switching circuit is used to couple a memory. And / or, the second display screen further includes a second interface circuit. The second interface circuit includes a first terminal and a second terminal. A second functional circuit couples to the first terminal of the second interface circuit, the first terminal of the second interface circuit couples to the second terminal of the second interface circuit, and the second terminal of the second interface circuit couples to the first terminal of a second switching circuit. The second terminal of the second switching circuit is used to couple a memory.

[0022] In one possible implementation of the second aspect, the display system further includes a third display screen. The third display screen displays different colors from the first display screen and the second display screen. The third display screen includes a third functional circuit and a third switching circuit. The third functional circuit couples to a first terminal of the third switching circuit, and the second terminal of the third switching circuit couples to a memory.

[0023] In one possible implementation of the second aspect, the first switching circuit and the second switching circuit are not turned on simultaneously.

[0024] Thirdly, a memory is provided. The memory includes a first terminal, a second terminal, a storage circuit, a first switching circuit, and a second switching circuit. The first terminal of the memory is used to couple to a first display screen, and the second terminal of the memory is used to couple to a second display screen. The first terminal of the memory is coupled to the first terminal of the first switching circuit, and the second terminal of the memory is coupled to the first terminal of the second switching circuit. The second terminals of both the first and second switching circuits are coupled to the storage circuit.

[0025] In one possible implementation of the third aspect, the memory further includes a third interface circuit. The third interface circuit includes a first terminal, a second terminal, and a third terminal. The first terminal of the memory is coupled to the first terminal of the third interface circuit, the first terminal of the third interface circuit is coupled to the first terminal of a first switching circuit, the second terminal of the first switching circuit is coupled to the third terminal of the third interface circuit, and the third terminal of the third interface circuit is coupled to the storage circuit. And / or, the second terminal of the memory is coupled to the second terminal of the third interface circuit, the second terminal of the third interface circuit is coupled to the first terminal of a second switching circuit, the second terminal of the second switching circuit is coupled to the third terminal of the third interface circuit, and the third terminal of the third interface circuit is coupled to the storage circuit.

[0026] In one possible implementation of the third aspect, the memory further includes a third interface circuit. The third interface circuit includes a first terminal, a second terminal, and a third terminal. The first terminal of the memory is coupled to a first terminal of a first switching circuit, the second terminal of the first switching circuit is coupled to a first terminal of the third interface circuit, the first terminal of the third interface circuit is coupled to a third terminal of the third interface circuit, and the third terminal of the third interface circuit is coupled to the storage circuit. And / or, the second terminal of the memory is coupled to a first terminal of a second switching circuit, the second terminal of the second switching circuit is coupled to a second terminal of the third interface circuit, the second terminal of the third interface circuit is coupled to a third terminal of the third interface circuit, and the third terminal of the third interface circuit is coupled to the storage circuit.

[0027] In one possible implementation of the third aspect, the memory is used to receive read instructions via a target port. The read instructions instruct the reader to read data. The target port is either a first end or a second end of the memory. The memory is also used to transmit data via the target port.

[0028] In one possible implementation of the third aspect, the memory further includes a third terminal and a third switching circuit. The third terminal of the memory is used to couple to a third display screen. The third terminal of the memory is coupled to the first terminal of the third switching circuit, and the second terminal of the third switching circuit is coupled to the storage circuit. In one possible implementation of the third aspect, the memory is a non-volatile memory.

[0029] In one possible implementation of the third aspect, the first switching circuit and the second switching circuit are not turned on simultaneously.

[0030] Fourthly, an electronic device is provided. The electronic device includes a processor and a display system provided in the first aspect or any possible implementation thereof. The processor is used to control the display system to display colors.

[0031] It is understood that any of the display modules and memory provided above are applied to the display system described above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding display system described above, and will not be repeated here. Attached Figure Description

[0032] Figure 1 A schematic diagram of an electronic device provided in an embodiment of this application. Figure 1 ;

[0033] Figure 2 A schematic diagram of a display screen provided in an embodiment of this application. Figure 1 ;

[0034] Figure 3 A schematic diagram of a display screen provided in an embodiment of this application. Figure 2 ;

[0035] Figure 4 A schematic diagram of an electronic device provided in an embodiment of this application. Figure 2 ;

[0036] Figure 5 A schematic diagram of an electronic device provided in an embodiment of this application. Figure 3 ;

[0037] Figure 6 A schematic diagram of a display system provided in an embodiment of this application. Figure 1 ;

[0038] Figure 7 A schematic diagram of a display system provided in an embodiment of this application. Figure 2 ;

[0039] Figure 8 A schematic diagram of a display system provided in an embodiment of this application. Figure 3 ;

[0040] Figure 9 A schematic diagram of a display system provided in an embodiment of this application. Figure 4 ;

[0041] Figure 10 A schematic diagram of a display system provided in an embodiment of this application. Figure 5 ;

[0042] Figure 11 A schematic diagram of a display system provided in an embodiment of this application. Figure 6 ;

[0043] Figure 12 A schematic diagram of a display system provided in an embodiment of this application. Figure 7 ;

[0044] Figure 13 A schematic diagram of a display system provided in an embodiment of this application. Figure 8 ;

[0045] Figure 14 A schematic diagram of a display system provided in an embodiment of this application. Figure 9 ;

[0046] Figure 15 This is a schematic diagram of a display module provided in an embodiment of this application;

[0047] Figure 16 This is a schematic diagram of a memory provided in an embodiment of this application. Detailed Implementation

[0048] It should be noted that the terms "first" and "second" used in the embodiments of this application are only used to distinguish features of the same type and should not be construed as indicating relative importance, quantity, order, etc.

[0049] The terms "exemplary" or "for example" used in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0050] The terms "coupling" and "connection" used in the embodiments of this application should be interpreted broadly. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0051] First, the application scenarios of the embodiments of this application will be introduced.

[0052] The embodiments of this application can be applied to electronic devices with display functions. These electronic devices include, but are not limited to: mobile phones, tablets, computers, laptops, camcorders, cameras, wearable devices, in-vehicle devices, or terminal devices, etc.

[0053] In some possible implementations, such as Figure 1 As shown, the electronic device 1000 may include a processor 1100, a first memory 1200, and a display system 1300. The display system 1300 may include a display screen 1310 and a second memory 1320. The processor 1100, the first memory 1200, and the display system 1300 may be coupled via a bus. The display screen 1310 is coupled to the second memory 1320.

[0054] In some examples, processor 1100 can be used to control electronic device 1000. Processor 1100 can be a central processing unit (CPU), general-purpose processor, digital signal processor, neural network processor, graphics processing unit (GPU), image signal processor, microcontroller, or microprocessor, etc. The number of processors 1100 can be one or more. For example, when there are multiple processors 1100, the multiple processors 1100 can include CPUs and GPUs. Optionally, processor 1100 can also be referred to as control circuitry.

[0055] In some further examples, the first memory 1200 may be used to store control-type information of the processor 1100 and / or data-type information generated by the processor 1100. The first memory 1200 may be volatile memory or non-volatile memory. For example, volatile memory may be RAM, and non-volatile memory may be a hard disk. The number of first memories 1200 may be one or more. For example, when there are multiple first memories 1200, the multiple first memories 1200 may include RAM and hard disks.

[0056] In some other examples, display screen 1310 can be used to display colors, thereby forming an image. Second memory 1320 can be used to store data from display screen 1310. For example, second memory 1320 can be used to store control-type information of display screen 1310, such as data related to demura technology. Display screen 1310 can be used to read data from second memory 1320 under the control of processor 1100. This data may be data required during the startup process of display screen 1310. Processor 1100 can be used to control display system 1300 to display colors. Second memory 1320 can be non-volatile memory, such as flash memory.

[0057] For example, such as Figure 2 As shown, the display screen 1310 may include a pixel circuit 110 and a driver chip 120. The driver chip 120 may include an interface circuit ( Figure 2 (Not shown). The driver chip 120 can be coupled to the second memory 1320 through the interface circuit of the driver chip 120. For example, the interface circuit can be a serial peripheral interface (SPI), an inter-integrated circuit (I2C) interface, or other interfaces.

[0058] The driver chip 120 can be used to read data from the second memory 1320 through an interface circuit under the control of the processor 1100. The driver chip 120 can also decode and convert the data to adapt it to the display format of the display screen 1310. The driver chip 120 can forward the processed data to the pixel circuit 110. Optionally, the driver chip 120 can be separate from the pixel circuit 110. Alternatively, the driver chip 120 can be integrated with the pixel circuit 110 in the same circuit. This application embodiment does not impose any limitations on this.

[0059] In some possible implementations, the number of displays 1310 can be multiple. Take a micro light-emitting diode (Micro LED) display as an example. Single-chip full-color technology is not yet mature. Therefore, multiple displays 1310 can be used to combine colors using prisms to achieve a full-color image, where each display 1310 displays a different color.

[0060] like Figure 3 As shown in Figure (a), the plurality of displays 1310 may include a first display 1311, a second display 1312, and a third display 1313. The first display 1311, the second display 1312, and the third display 1313 may be arranged around the prism. Figure 3 As shown in Figure (b), the first display screen 1311 displays a first color, the second display screen 1312 displays a second color, and the third display screen 1313 displays a third color. Optionally, the first color can be red (R), and the first display screen 1311 can be a red display screen (R display). The second color can be green (G), and the second display screen 1312 can be a green display screen (G display). The third color can be blue (B), and the third display screen 1313 can be a blue display screen (B display). The first, second, and third colors can be combined using a prism to achieve a full-color image.

[0061] In some examples, each of the multiple displays 1310 is coupled to a second memory 1320; that is, the electronic device 1000 includes multiple second memories 1320. An example is given where all the multiple second memories 1320 are flash memory.

[0062] like Figure 4 As shown, multiple displays include a first display 1311, a second display 1312, and a third display 1313. Multiple second memories 1320 include a first flash memory 1321, a second flash memory 1322, and a third flash memory 1323. The first display 1311, second display 1312, and third display 1313 can all be coupled to the processor 1100 and the first memory 1200 via a bus. The first display 1311 is coupled to the first flash memory 1321. The second display 1312 is coupled to the second flash memory 1322. The third display 1313 is coupled to the third flash memory 1323. The first flash memory 1321 is used to store data for the first display 1311. The second flash memory 1322 is used to store data for the second display 1312. The third flash memory 1323 is used to store data for the third display 1313.

[0063] In this example, each display screen 1310 stores relatively little data in the second memory 1320, resulting in wasted storage space in each second memory 1320. Furthermore, multiple displays screens 1310 require multiple second memories 1320, which increases hardware costs and power consumption during operation and standby.

[0064] The storage capacity of a second memory 1320 is sufficient to store data from multiple displays 1310. However, storing data from multiple displays 1310 in the same second memory 1320 leads to a multi-drive problem. For example, the first display 1311, the second display 1312, and the third display 1313 are all coupled to the same second memory 1320. When the first display 1311 writes data to the second memory 1320, the second display 1312 needs to read the data from the second memory 1320, and the reading process of the second display 1312 will encounter problems. This is the multi-drive problem.

[0065] In other examples, multiple displays 1310 are coupled to the same second memory 1320, and a switching circuit is provided on the transmission path between each display 1310 and the second memory 1320.

[0066] like Figure 5 As shown, if there are two display screens 1310, the display system 1300 includes a first display screen 1311, a second display screen 1312, and a second memory 1320. The second memory 1320 includes a first terminal S1 and a second terminal S2. If there are three display screens 1310, the display system 1300 also includes a third display screen 1313, and the second memory 1320 also includes a third terminal S3. The number of display screens 1310 in this embodiment can be two, three, four, or more, and this embodiment does not limit this. This embodiment will now be described using multiple display screens 1310, including a first display screen 1311, a second display screen 1312, and a third display screen 1313, as an example.

[0067] The first display screen 1311, the second display screen 1312, and the third display screen 1313 can all be coupled to the processor 1100 and the first memory 1200 via a bus. The first display screen 1311 is coupled to the first terminal S1 of the second memory 1320. For example, the first display screen 1311 is coupled to the first terminal S1 of the second memory 1320 via a first transmission line. The second display screen 1312 is coupled to the second terminal S2 of the second memory 1320. For example, the second display screen 1312 is coupled to the second terminal S2 of the second memory 1320 via a second transmission line. The third display screen 1313 is coupled to the third terminal S3 of the second memory 1320. For example, the third display screen 1313 is coupled to the third terminal S3 of the second memory 1320 via a third transmission line. The colors displayed by the third display screen 1313, the first display screen 1311, and the second display screen 1312 are all different. A first switching circuit 211 is provided on the transmission path between the first display screen 1311 and the second memory 1320. A second switch circuit 212 is provided on the transmission path between the second display screen 1312 and the second memory 1320. A third switch circuit 213 is provided on the transmission path between the third display screen 1313 and the second memory 1320.

[0068] For example, the transmission path between the first display screen 1311 and the second memory 1320 can refer to the circuit through which the data passes during the data transmission process between the first display screen 1311 and the second memory 1320. The transmission path between the first display screen 1311 and the second memory 1320 can include: the circuit inside the first display screen 1311, the circuit inside the second memory 1320, and a first transmission line outside the first display screen 1311 and the second memory 1320.

[0069] The transmission path between the second display screen 1312 and the second memory 1320 can refer to the circuit through which the data passes during the data transmission process between the second display screen 1312 and the second memory 1320. The transmission path between the second display screen 1312 and the second memory 1320 can include: the circuitry inside the second display screen 1312, the circuitry inside the second memory 1320, and a second transmission line outside the second display screen 1312 and the second memory 1320.

[0070] The transmission path between the third display screen 1313 and the second memory 1320 can refer to the circuit through which the data passes during the data transmission process between the third display screen 1313 and the second memory 1320. The transmission path between the third display screen 1313 and the second memory 1320 can include the circuitry inside the third display screen 1313, the circuitry inside the second memory 1320, and a third transmission line outside the third display screen 1313 and the second memory 1320.

[0071] As an example, the first switching circuit 211, the second switching circuit 212, and the third switching circuit 213 can be circuits with switching functions. When the first switching circuit 211 is turned on, the first display screen 1311 can transmit data with the second memory 1320. When the first switching circuit 211 is turned off (e.g., set to high resistance), the first display screen 1311 cannot transmit data with the second memory 1320. When the second switching circuit 212 is turned on, the second display screen 1312 can transmit data with the second memory 1320. When the second switching circuit 212 is turned off (e.g., set to high resistance), the second display screen 1312 cannot transmit data with the second memory 1320. When the third switching circuit 213 is turned on, the third display screen 1313 can transmit data with the second memory 1320. When the third switching circuit 213 is turned off (e.g., set to high resistance), the third display screen 1313 cannot transmit data with the second memory 1320.

[0072] Optionally, the first switching circuit 211, the second switching circuit 212, or the third switching circuit 213 may be a single switching device, such as a transistor. Alternatively, the first switching circuit 211, the second switching circuit 212, or the third switching circuit 213 may be a circuit comprising multiple components, such as a circuit comprising resistors, capacitors, and transistors.

[0073] Optionally, the components and structures of the first switching circuit 211, the second switching circuit 212, and the third switching circuit 213 may be identical. Alternatively, at least two of the first switching circuit 211, the second switching circuit 212, and the third switching circuit 213 may have different components or structures.

[0074] As another example, the first switching circuit 211, the second switching circuit 212, and the third switching circuit 213 are not simultaneously turned on. At any given time, only one of these three switching circuits is on, while the other two are off. That is, at any given time, only one display screen can transmit data to the second memory 1320; the transmission paths between the other two display screens and the second memory 1320 are disconnected, and data transmission is impossible. This avoids the multi-drive problem. Furthermore, hardware control via simple switching circuits is simpler than software control.

[0075] As another example, the second memory 1320 can be a non-volatile memory. For example, the second memory 1320 can be flash memory. In this way, the second memory 1320 can stably store data for the display screen.

[0076] In this example, the first display screen 1311, the second display screen 1312, and the third display screen 1313 can be coupled to the same second memory 1320. When the first display screen 1311 writes data to the second memory 1320, the first switching circuit 211 is turned on, and the second switching circuit 212 and the third switching circuit 213 are turned off. At any given time, only one of the multiple display screens 1310 can operate on the data in the second memory 1320, thus avoiding multi-drive problems. Furthermore, the data of the multiple display screens 1310 can be stored in different locations within the same second memory 1320, requiring only one second memory 1320 to be configured for the multiple display screens 1310. The storage space utilization of the second memory 1320 is high, reducing storage space waste. Additionally, the structure of the first switching circuit 211, the second switching circuit 212, and the third switching circuit 213 is relatively simple. The cost of setting up multiple switching circuits in the display system 1300 is lower than the cost of setting up multiple second memories 1320. Therefore, only one secondary memory 1320 is needed to store data from multiple displays 1310, resulting in lower hardware costs and lower operating and standby power consumption. This reduces overall power consumption and improves overall performance and standby battery life.

[0077] In some possible implementations, Figure 5 In the display system 1300, the first switch circuit 211, the second switch circuit 212, and the third switch circuit 213 can be disposed in the corresponding display screens. Specifically, the first switch circuit 211 is disposed in the first display screen 1311, the second switch circuit 212 is disposed in the second display screen 1312, and the third switch circuit 213 is disposed in the third display screen 1313.

[0078] In some examples, such as Figure 6 As shown, the first display screen 1311 includes a first functional circuit 221 and a first switching circuit 211. The first functional circuit 221 is coupled to the first terminal K1 of the first switching circuit 211, and the second terminal K2 of the first switching circuit 211 is coupled to the first terminal S1 of the second memory 1320.

[0079] Optionally, the second display screen 1312 includes a second functional circuit 222 and a second switching circuit 212. The second functional circuit 222 is coupled to the first terminal K3 of the second switching circuit 212, and the second terminal K4 of the second switching circuit 212 is coupled to the second terminal S2 of the second memory 1320.

[0080] Optionally, the third display screen 1313 includes a third functional circuit 223 and a third switching circuit 213. The third functional circuit 223 is coupled to the first terminal K5 of the third switching circuit 213, and the second terminal K6 of the third switching circuit 213 is coupled to the third terminal S3 of the second memory 1320.

[0081] Optionally, the second memory 1320 may further include a storage circuit 230. The first terminal S1, the second terminal S2, and the third terminal S3 of the second memory 1320 are all coupled to the storage circuit 230.

[0082] For example, the first functional circuit 221, the second functional circuit 222, and the third functional circuit 223 can be circuits with preset functions. For instance, the first functional circuit 221, the second functional circuit 222, or the third functional circuit 223 can be a clock synchronization circuit used for clock synchronization. As another example, the first functional circuit 221, the second functional circuit 222, or the third functional circuit 223 can be a pixel circuit 110. At least two of the first functional circuits 221, the second functional circuit 222, and the third functional circuit 223 may have different functions. This application embodiment does not limit the functions of the first functional circuit 221, the second functional circuit 222, and the third functional circuit 223.

[0083] As another example, the storage circuit 230 can be used to store data. The storage circuit 230 may include circuitry such as a storage array.

[0084] As another example, the first switch circuit 211 can be disposed in the driver chip 120 of the first display screen 1311. The second switch circuit 212 can be disposed in the driver chip 120 of the second display screen 1312. The third switch circuit 213 can be disposed in the driver chip 120 of the third display screen 1313. The first switch circuit 211, the second switch circuit 212 and the third switch circuit 213 can all be turned on or off under the control of the driver chip 120.

[0085] In this example, the first switch circuit 211 can be located in the first display screen 1311, the second switch circuit 212 can be located in the second display screen 1312, and the third switch circuit 213 can be located in the third display screen 1313. Setting up one switch circuit in a display screen is relatively inexpensive. Furthermore, the switch circuits inside the display screen can be controlled by the display screen's driver chip 120, and the control method and connection relationship of the switch circuits are relatively simple.

[0086] In some other examples, such as Figure 7 As shown, in Figure 6Based on this, the first display screen 1311 also includes a first interface circuit 241. The first interface circuit 241 includes a first terminal A1, a second terminal A2, and a first switch circuit 211. A first functional circuit 221 is coupled to the first terminal A1 of the first interface circuit 241, the first terminal A1 of the first interface circuit 241 is coupled to the first terminal K1 of the first switch circuit 211, the second terminal K2 of the first switch circuit 211 is coupled to the second terminal A2 of the first interface circuit 241, and the second terminal A2 of the first interface circuit 241 is coupled to the first terminal S1 of the second memory 1320.

[0087] Optionally, in Figure 6 Based on this, the second display screen 1312 also includes a second interface circuit 242. The second interface circuit 242 includes a first terminal B1, a second terminal B2, and a second switch circuit 212. The second functional circuit 222 is coupled to the first terminal B1 of the second interface circuit 242, the first terminal B1 of the second interface circuit 242 is coupled to the first terminal K3 of the second switch circuit 212, the second terminal K4 of the second switch circuit 212 is coupled to the second terminal B2 of the second interface circuit 242, and the second terminal B2 of the second interface circuit 242 is coupled to the second terminal S2 of the second memory 1320.

[0088] Optionally, in Figure 6 Based on this, the third display screen 1313 also includes a third interface circuit 243. The third interface circuit 243 includes a first terminal C1, a second terminal C2, and a third switch circuit 213. The third functional circuit 223 couples to the first terminal C1 of the third interface circuit 243, the first terminal C1 of the third interface circuit 243 couples to the first terminal K5 of the third switch circuit 213, the second terminal K6 of the third switch circuit 213 couples to the second terminal C2 of the third interface circuit 243, and the second terminal C2 of the third interface circuit 243 couples to the third terminal S3 of the second memory 1320.

[0089] Optionally, in Figure 6 Based on this, the second memory 1320 may further include a fourth interface circuit 244. The fourth interface circuit 244 includes a first terminal S1, a second terminal D2, a third terminal D3, and a fourth terminal D4. The first terminal S1 of the second memory 1320 is coupled to the first terminal D1 of the fourth interface circuit 244; the second terminal S2 of the second memory 1320 is coupled to the second terminal D2 of the fourth interface circuit 244; and the third terminal S3 of the second memory 1320 is coupled to the third terminal D3 of the fourth interface circuit 244. The first terminal D1, the second terminal D2, and the third terminal D3 of the fourth interface circuit 244 are all coupled to the fourth terminal D4 of the fourth interface circuit 244. The fourth terminal D4 of the fourth interface circuit 244 is coupled to the storage circuit 230.

[0090] Exemplary, the first interface circuit 241, the second interface circuit 242, the third interface circuit 243, and the fourth interface circuit 244 can be used to transmit data according to a preset protocol. The first interface circuit 241 can be used to receive data and convert the data into a format that the first display screen 1311 can process according to the preset protocol. For example, the first interface circuit 241 can be a serial peripheral interface (SPI), and the first interface circuit 241 can be used to transmit data according to the SPI protocol. As another example, the first interface circuit 241 can be an inter-integrated circuit (I2C) interface, and the first interface circuit 241 can be used to transmit data according to the I2C protocol. The first interface circuit 241 can also be other interfaces. The functions and types of the second interface circuit 242, the third interface circuit 243, and the fourth interface circuit 244 can refer to the functions and types of the first interface circuit 241, and will not be repeated here in the embodiments of this application.

[0091] As another example, the first interface circuit 241 may be the interface circuit of the driver chip 120 of the first display screen 1311. The second interface circuit 242 may be the interface circuit of the driver chip 120 of the second display screen 1312. The third interface circuit 243 may be the interface circuit of the driver chip 120 of the third display screen 1313.

[0092] As another example, other circuits may exist between the first terminal K1 of the first switching circuit 211 and the first terminal A1 of the first interface circuit 241 (see reference). Figure 7 (The ellipsis in the text) For example, a cyclic redundancy check (CRC) circuit. That is, the first terminal K1 of the first switch circuit 211 and the first terminal A1 of the first interface circuit 241 are indirectly coupled through other circuits. Similarly, other circuits may exist between the second terminal K2 of the first switch circuit 211 and the second terminal A2 of the first interface circuit 241, between the first terminal K3 of the second switch circuit 212 and the first terminal B1 of the second interface circuit 242, between the second terminal K4 of the second switch circuit 212 and the second terminal B2 of the second interface circuit 242, between the first terminal K5 of the third switch circuit 213 and the first terminal C1 of the third interface circuit 243, between the second terminal K6 of the third switch circuit 213 and the second terminal C2 of the third interface circuit 243, between the first terminal D1 of the fourth interface circuit 244 and the fourth terminal D4 of the fourth interface circuit 244, between the second terminal D2 of the fourth interface circuit 244 and the fourth terminal D4 of the fourth interface circuit 244, and between the third terminal D3 of the fourth interface circuit 244 and the fourth terminal D4 of the fourth interface circuit 244.

[0093] In this example, the first switch circuit 211 can be specifically located in the first interface circuit 241 of the first display screen 1311, the second switch circuit 212 can be located in the second interface circuit 242 of the second display screen 1312, and the third switch circuit 213 can be located in the third interface circuit 243 of the third display screen 1313. Thus, the arrangement of the switch circuits will not affect the structure of other functional circuits of the display screen.

[0094] In some other examples, such as Figure 8 As shown, with Figure 7 Similarly, the first display screen 1311 also includes a first interface circuit 241, the second display screen 1312 also includes a second interface circuit 242, the third display screen 1313 also includes a third interface circuit 243, and the second memory 1320 also includes a fourth interface circuit 244. The connection relationships between the first interface circuit 241, the second interface circuit 242, the third interface circuit 243, and the fourth interface circuit 244 and other circuits can be found in [reference needed]. Figure 7 The connection relationships within are not elaborated further in this embodiment. Figure 7 The difference is that the first switch circuit 211 is located outside the first interface circuit 241, the second switch circuit 212 is located outside the second interface circuit 242, and the third switch circuit 213 is located outside the third interface circuit 243.

[0095] Optionally, the first functional circuit 221 is coupled to the first terminal A1 of the first interface circuit 241, the first terminal A1 of the first interface circuit 241 is coupled to the second terminal A2 of the first interface circuit 241, the second terminal A2 of the first interface circuit 241 is coupled to the first terminal K1 of the first switch circuit 211, and the second terminal K2 of the first switch circuit 211 is coupled to the first terminal S1 of the second memory 1320.

[0096] Optionally, the second functional circuit 222 is coupled to the first terminal B1 of the second interface circuit 242, the first terminal B1 of the second interface circuit 242 is coupled to the second terminal B2 of the second interface circuit 242, the second terminal B2 of the second interface circuit 242 is coupled to the first terminal K3 of the second switch circuit 212, and the second terminal K4 of the second switch circuit 212 is coupled to the second terminal S2 of the second memory 1320.

[0097] Optionally, the third functional circuit 223 is coupled to the first terminal C1 of the third interface circuit 243, the first terminal C1 of the third interface circuit 243 is coupled to the second terminal C2 of the third interface circuit 243, the second terminal C2 of the third interface circuit 243 is coupled to the first terminal K5 of the third switch circuit 213, and the second terminal K6 of the third switch circuit 213 is coupled to the third terminal S3 of the second memory 1320.

[0098] In this example, the first switch circuit 211 can be located at the rear end of the first interface circuit 241 of the first display screen 1311, the second switch circuit 212 can be located at the rear end of the second interface circuit 242 of the second display screen 1312, and the third switch circuit 213 can be located at the rear end of the third interface circuit 243 of the third display screen 1313. Thus, the arrangement of the switch circuits does not affect the structure of the display screen's interface circuits and other functional circuits.

[0099] In some other possible implementations Figure 5 In the display system 1300, the first switch circuit 211, the second switch circuit 212, and the third switch circuit 213 can be disposed on the corresponding transmission lines. Specifically, the first switch circuit 211 is disposed on the first transmission line, the second switch circuit 212 is disposed on the second transmission line, and the third switch circuit 213 is disposed on the third transmission line.

[0100] In some examples, such as Figure 9 As shown, the first display screen 1311 is coupled to the first terminal K1 of the first switching circuit 211, and the second terminal K2 of the first switching circuit 211 is coupled to the first terminal S1 of the second memory 1320. Optionally, the second display screen 1312 is coupled to the first terminal K3 of the second switching circuit 212, and the second terminal K4 of the second switching circuit 212 is coupled to the second terminal S2 of the second memory 1320. Optionally, the third display screen 1313 is coupled to the first terminal K5 of the third switching circuit 213, and the second terminal K6 of the third switching circuit 213 is coupled to the third terminal S3 of the second memory 1320. Optionally, the second memory 1320 may include a storage circuit 230, and the connection relationship between the storage circuit 230 and other circuits can be referred to the foregoing description, which will not be repeated here.

[0101] For example, the first switching circuit 211, the second switching circuit 212, or the third switching circuit 213 may be coupled to a switch control circuit. The switch control circuit is used to control the switching circuit to turn on or off. The switch control circuit may be a processor 1100, a driver chip 120, or other circuits with control functions; this application embodiment does not limit this.

[0102] In this example, the first switch circuit 211 can be separately configured from the first display screen 1311 and the second memory 1320, and is located between the first display screen 1311 and the second memory 1320. The second switch circuit 212 can be separately configured from the second display screen 1312 and the second memory 1320, and is located between the second display screen 1312 and the second memory 1320. The third switch circuit 213 can be separately configured from the third display screen 1313 and the second memory 1320, and is located between the third display screen 1313 and the second memory 1320. Thus, the configuration of the switch circuits does not affect the structure of the display screen.

[0103] In some other possible implementations Figure 5 In the display system 1300, the first switch circuit 211, the second switch circuit 212 and the third switch circuit 213 can be set in the second memory 1320.

[0104] In some examples, such as Figure 10 As shown, the second memory 1320 may include a storage circuit 230 and a first switching circuit 211. The first terminal S1 of the second memory 1320 is coupled to the first terminal K1 of the first switching circuit 211. The second terminal K2 of the first switching circuit 211 is coupled to the storage circuit 230.

[0105] Optionally, the second memory 1320 may include a second switching circuit 212. The second terminal S2 of the second memory 1320 is coupled to the first terminal K3 of the second switching circuit 212. The second terminal K4 of the second switching circuit 212 is coupled to the storage circuit 230.

[0106] Optionally, the second memory 1320 may include a second switching circuit 212 and a third switching circuit 213. The third terminal S3 of the second memory 1320 is coupled to the first terminal K5 of the third switching circuit 213. The second terminal K6 of the third switching circuit 213 is coupled to the storage circuit 230.

[0107] Optionally, the first display screen 1311 may include a first functional circuit 221, the second display screen 1312 may include a second functional circuit 222, and the third display screen 1313 may include a third functional circuit 223.

[0108] For example, the functions of the first functional circuit 221, the second functional circuit 222, the third functional circuit 223 and the storage circuit 230 can be referred to the above description, and will not be repeated here in the embodiments of this application.

[0109] In this example, at least one of the first switch circuit 211, the second switch circuit 212, and the third switch circuit 213 can be located in the second memory 1320. The cost of setting up switch circuits in the second memory 1320 is relatively low. Furthermore, the switch circuits inside the second memory 1320 can be controlled by circuits with control functions within the second memory 1320, and the control method and connection relationships of the switch circuits are relatively simple.

[0110] In some other examples, such as Figure 11 As shown, in Figure 10 Based on this, the second memory 1320 also includes a fourth interface circuit 244. The fourth interface circuit 244 includes a first terminal D1, a second terminal D2, a third terminal D3, and a fourth terminal D4.

[0111] Optionally, the first terminal S1 of the second memory 1320 is coupled to the first terminal D1 of the fourth interface circuit 244, the first terminal D1 of the fourth interface circuit 244 is coupled to the first terminal K1 of the first switch circuit 211, the second terminal K2 of the first switch circuit 211 is coupled to the fourth terminal D4 of the fourth interface circuit 244, and the fourth terminal D4 of the fourth interface circuit 244 is coupled to the storage circuit 230.

[0112] Optionally, the second terminal S2 of the second memory 1320 is coupled to the second terminal D2 of the fourth interface circuit 244, the second terminal D2 of the fourth interface circuit 244 is coupled to the first terminal K3 of the second switch circuit 212, the second terminal K4 of the second switch circuit 212 is coupled to the fourth terminal D4 of the fourth interface circuit 244, and the fourth terminal D4 of the fourth interface circuit 244 is coupled to the storage circuit 230.

[0113] Optionally, the third terminal S3 of the second memory 1320 is coupled to the third terminal D3 of the fourth interface circuit 244, the third terminal D3 of the fourth interface circuit 244 is coupled to the first terminal K5 of the third switch circuit 213, the second terminal K6 of the third switch circuit 213 is coupled to the fourth terminal D4 of the fourth interface circuit 244, and the fourth terminal D4 of the fourth interface circuit 244 is coupled to the storage circuit 230.

[0114] Optionally, the first display screen 1311 may further include a first interface circuit 241, the second display screen 1312 may further include a second interface circuit 242, and the third display screen 1313 may further include a third interface circuit 243.

[0115] For example, the functions and types of the first interface circuit 241, the second interface circuit 242, the third interface circuit 243 and the fourth interface circuit 244 can be referred to the above description, and will not be repeated here in the embodiments of this application.

[0116] As another example, other circuits may exist between the first terminal K1 of the first switching circuit 211 and the first terminal D1 of the fourth interface circuit 244 (see reference). Figure 11 (The ellipsis in the text) For example, a CRC circuit. That is, the first terminal K1 of the first switch circuit 211 and the first terminal D1 of the fourth interface circuit 244 are indirectly coupled through other circuits. Similarly, other circuits may exist between the second terminal K2 of the first switch circuit 211 and the fourth terminal D4 of the fourth interface circuit 244, between the first terminal K3 of the second switch circuit 212 and the second terminal D2 of the fourth interface circuit 244, between the second terminal K4 of the second switch circuit 212 and the fourth terminal D4 of the fourth interface circuit 244, between the first terminal K5 of the third switch circuit 213 and the third terminal D3 of the fourth interface circuit 244, between the second terminal K4 of the second switch circuit 212 and the fourth terminal D4 of the fourth interface circuit 244, between the first terminal A1 and the second terminal A2 of the first interface circuit 241, between the first terminal B1 and the second terminal B2 of the second interface circuit 242, and between the first terminal C1 and the second terminal C2 of the third interface circuit 243.

[0117] In this example, at least one of the first switch circuit 211, the second switch circuit 212, and the third switch circuit 213 can be located in the fourth interface circuit 244 of the second memory 1320. Thus, the location of the switch circuits does not affect the structure of other circuits in the second memory 1320.

[0118] In some other examples, such as Figure 12 As shown, with Figure 11 Similarly, the second memory 1320 also includes a fourth interface circuit 244. The first display screen 1311 may also include a first interface circuit 241, the second display screen 1312 may also include a second interface circuit 242, and the third display screen 1313 may also include a third interface circuit 243. The connection relationships between the first interface circuit 241, the second interface circuit 242, the third interface circuit 243, and the fourth interface circuit 244 and other circuits can be found in [reference needed]. Figure 11 The connection relationships within are not elaborated further in this embodiment. Figure 11 The difference is that at least one of the first switch circuit 211, the second switch circuit 212 and the third switch circuit 213 is located outside the fourth interface circuit 244.

[0119] Optionally, the first terminal S1 of the second memory 1320 is coupled to the first terminal K1 of the first switching circuit 211, the second terminal K2 of the first switching circuit 211 is coupled to the first terminal D1 of the fourth interface circuit 244, the first terminal D1 of the fourth interface circuit 244 is coupled to the fourth terminal D4 of the fourth interface circuit 244, and the fourth terminal D4 of the fourth interface circuit 244 is coupled to the storage circuit 230.

[0120] Optionally, the second terminal S2 of the second memory 1320 is coupled to the first terminal K3 of the second switching circuit 212, the second terminal K4 of the second switching circuit 212 is coupled to the second terminal D2 of the fourth interface circuit 244, the second terminal D2 of the fourth interface circuit 244 is coupled to the fourth terminal D4 of the fourth interface circuit 244, and the fourth terminal D4 of the fourth interface circuit 244 is coupled to the storage circuit 230.

[0121] Optionally, the third terminal S3 of the second memory 1320 is coupled to the first terminal K5 of the third switching circuit 213, the second terminal K6 of the third switching circuit 213 is coupled to the third terminal D3 of the fourth interface circuit 244, the third terminal D3 of the fourth interface circuit 244 is coupled to the fourth terminal D4 of the fourth interface circuit 244, and the fourth terminal D4 of the fourth interface circuit 244 is coupled to the storage circuit 230.

[0122] In this example, at least one of the first switch circuit 211, the second switch circuit 212, and the third switch circuit 213 can be located at the rear end of the fourth interface circuit 244 of the second memory 1320. Thus, the arrangement of the switch circuits does not affect the structure of the fourth interface circuit 244 and other circuits of the second memory 1320.

[0123] In some other possible implementations Figure 5 The first switch circuit 211, the second switch circuit 212, and the third switch circuit 213 can be set in different positions.

[0124] In some examples, such as Figure 13 As shown, the first switch circuit 211 and the second switch circuit 212 are disposed in the second memory 1320, and the positions of the first switch circuit 211 and the second switch circuit 212 are as follows: Figure 12 The positions of the first switch circuit 211 and the second switch circuit 212 are specified. The third switch circuit 213 is disposed in the third display screen 1313, and the position of the third switch circuit 213 is specified. Figure 7 The position of the third switch circuit 213 in the circuit.

[0125] In this embodiment of the application, the location of the first switch circuit 211 can be... Figures 6-12 The first switching circuit 211 can be positioned in any of the following configurations. The second switching circuit 212 can be positioned in any of the following configurations. Figures 6-12The second switch circuit 212 can be positioned in any of the following configurations. The third switch circuit 213 can be positioned in any of the following configurations. Figures 6-12 The third switch circuit 213 can be positioned in any of the following configurations. The positions of the first switch circuit 211, the second switch circuit 212, and the third switch circuit 213 can be the same or different.

[0126] In some possible implementations, when the second memory 1320 receives a read instruction from one of the multiple displays, it determines which display to send the read data to based on the port from which the read instruction was received. The read instruction is used to indicate the reading of data.

[0127] In some examples, the second memory 1320 is used to receive read commands through a target port. The target port is a first terminal S1, a second terminal S2, or a third terminal S3 of the second memory 1320. The second memory 1320 is also used to send data through the target port.

[0128] For example, such as Figure 14 As shown, the second memory 1320 may include a first storage space, a second storage space, and a third storage space. The first storage space is used to store data of the first display screen 1311. The second storage space is used to store data of the second display screen 1312. The third storage space is used to store data of the third display screen 1313. Optionally, the first storage space, the second storage space, and the third storage space may be located in the aforementioned storage circuit 230.

[0129] For example, the target port can be a port coupled to the display screen currently communicating with the second memory 1320. The second memory 1320 receives a read command through the target port and outputs the read command to the port of the fourth interface circuit 244 coupled to the target port. The fourth interface circuit 244 outputs the read command to the storage circuit 230 through its fourth terminal D4. The storage circuit 230 reads the data of the corresponding storage space according to the address in the read command. The storage circuit 230 outputs the data to the fourth interface circuit 244 through its fourth terminal D4. The fourth interface circuit 244 outputs the data to the target port through the port coupled to the target port. Thus, the data is transmitted to the display screen coupled to the target port through the target port. Therefore, the second memory 1320 can determine which display screen to send the read data to based on the port from which the read command is received.

[0130] As another example, the first terminal S1 of the second memory 1320 and the first terminal D1 of the fourth interface circuit 244 can be the same port, the second terminal S2 of the second memory 1320 and the second terminal D2 of the fourth interface circuit 244 can be the same port, and the third terminal S3 of the second memory 1320 and the third terminal D3 of the fourth interface circuit 244 can be the same port.

[0131] In this example, the memory determines the display screen for data transmission based on the port, ensuring that data transmission is performed correctly.

[0132] This application also provides a display module 300. For example... Figure 15 As shown, the display module 300 includes a first display screen 1311 and a second display screen 1312. The colors displayed on the first display screen 1311 and the second display screen 1312 are different. The first display screen 1311 includes a first functional circuit 221 and a first switching circuit 211. The first functional circuit 221 is coupled to a first terminal K1 of the first switching circuit 211, and the second terminal K2 of the first switching circuit 211 is used to couple to a first terminal S1 of the second memory 1320. The second display screen 1312 includes a second functional circuit 222 and a second switching circuit 212. The second functional circuit 222 is coupled to a first terminal K3 of the second switching circuit 212, and the second terminal K4 of the second switching circuit 212 is used to couple to a second terminal S2 of the second memory 1320.

[0133] In some possible implementations, the display module 300 further includes a third display screen 1313. The colors displayed by the third display screen 1313, the first display screen 1311, and the second display screen 1312 are all different. The third display screen 1313 includes a third functional circuit 223 and a third switching circuit 213. The third functional circuit 223 is coupled to a first terminal K5 of the third switching circuit 213, and the second terminal K6 of the third switching circuit 213 is used to couple to a third terminal S3 of the second memory 1320.

[0134] In some examples, the second memory 1320 includes a first terminal S1, a second terminal S2, a third terminal S3, and a storage circuit 230. The second terminal K2 of the first switching circuit 211 is used to couple the first terminal S1 of the second memory 1320. The second terminal K4 of the second switching circuit 212 is used to couple the second terminal S2 of the second memory 1320. The second terminal K6 of the third switching circuit 213 is used to couple the third terminal S3 of the second memory 1320. The first terminal S1, the second terminal S2, and the third terminal S3 of the second memory 1320 are all coupled to the storage circuit 230.

[0135] In some possible implementations, the first display screen 1311 further includes a first interface circuit 241. The first interface circuit 241 includes a first terminal A1, a second terminal A2, and a first switch circuit 211. A first functional circuit 221 couples to the first terminal A1 of the first interface circuit 241, the first terminal A1 of the first interface circuit 241 couples to the first terminal K1 of the first switch circuit 211, the second terminal K2 of the first switch circuit 211 couples to the second terminal A2 of the first interface circuit 241, and the second terminal A2 of the first interface circuit 241 is used to couple to the first terminal S1 of the second memory 1320.

[0136] Optionally, the second display screen 1312 further includes a second interface circuit 242. The second interface circuit 242 includes a first terminal B1, a second terminal B2, and a second switch circuit 212. The second functional circuit 222 couples to the first terminal B1 of the second interface circuit 242, the first terminal B1 of the second interface circuit 242 couples to the first terminal K3 of the second switch circuit 212, the second terminal K4 of the second switch circuit 212 couples to the second terminal B2 of the second interface circuit 242, and the second terminal B2 of the second interface circuit 242 is used to couple to the second terminal S2 of the second memory 1320.

[0137] Optionally, the third display screen 1313 further includes a third interface circuit 243. The third interface circuit 243 includes a first terminal C1, a second terminal C2, and a third switch circuit 213. The third functional circuit 223 couples to the first terminal C1 of the third interface circuit 243, the first terminal C1 of the third interface circuit 243 couples to the first terminal K5 of the third switch circuit 213, the second terminal K6 of the third switch circuit 213 couples to the second terminal C2 of the third interface circuit 243, and the second terminal C2 of the third interface circuit 243 is used to couple to the third terminal S3 of the second memory 1320.

[0138] In some other possible implementations, the first display screen 1311 further includes a first interface circuit 241. The first interface circuit 241 includes a first terminal A1 and a second terminal A2.

[0139] The first functional circuit 221 couples to the first terminal A1 of the first interface circuit 241, the first terminal A1 of the first interface circuit 241 couples to the second terminal A2 of the first interface circuit 241, the second terminal A2 of the first interface circuit 241 couples to the first terminal K1 of the first switch circuit 211, and the second terminal K2 of the first switch circuit 211 is used to couple to the first terminal S1 of the second memory 1320.

[0140] Optionally, the second display screen 1312 further includes a second interface circuit 242. The second interface circuit 242 includes a first terminal B1 and a second terminal B2. The second functional circuit 222 couples to the first terminal B1 of the second interface circuit 242, the first terminal B1 of the second interface circuit 242 couples to the second terminal B2 of the second interface circuit 242, the second terminal B2 of the second interface circuit 242 couples to the first terminal K3 of the second switch circuit 212, and the second terminal K4 of the second switch circuit 212 is used to couple to the second terminal S2 of the second memory 1320.

[0141] Optionally, the third display screen 1313 further includes a third interface circuit 243. The third interface circuit 243 includes a first terminal C1 and a second terminal C2. The third functional circuit 223 couples the first terminal C1 of the third interface circuit 243, the first terminal C1 of the third interface circuit 243 couples the second terminal C2 of the third interface circuit 243, the second terminal C2 of the third interface circuit 243 couples the first terminal K5 of the third switch circuit 213, and the second terminal K6 of the third switch circuit 213 is used to couple the third terminal S3 of the second memory 1320.

[0142] In some possible implementations, the first switching circuit 211, the second switching circuit 212, and the third switching circuit 213 are not turned on simultaneously.

[0143] It is understood that the first display screen 1311, the second display screen 1312, and the third display screen 1313 in the aforementioned display module 300, and their possible internal structures, can be referenced to the first display screen 1311, the second display screen 1312, and the third display screen 1313, and their possible internal structures, in the aforementioned embodiment of the display system 1300. Each component of the display module 300 is used to implement the functions and effects of the aforementioned embodiment of the display system 1300. Since the components have been described in detail in the aforementioned embodiment of the display system 1300, they will not be repeated here.

[0144] This application embodiment also provides a memory, the structure of which can refer to the structure of the aforementioned second memory 1320. For example... Figure 16 As shown, the second memory 1320 includes a first terminal S1, a second terminal S2, a storage circuit 230, a first switching circuit 211, and a second switching circuit 212. The first terminal S1 of the second memory 1320 is used to couple to the first display screen 1311, and the second terminal S2 of the second memory 1320 is used to couple to the second display screen 1312. The first terminal S1 of the second memory 1320 is coupled to the first terminal K1 of the first switching circuit 211, and the second terminal S2 of the second memory 1320 is coupled to the first terminal K3 of the second switching circuit 212. The second terminals K2 of the first switching circuit 211 and K4 of the second switching circuit 212 are both coupled to the storage circuit 230.

[0145] In some possible implementations, the second memory 1320 further includes a third terminal S3 and a third switching circuit 213. The third terminal S3 of the second memory 1320 is used to couple the third display screen 1313. The third terminal S3 of the second memory 1320 is coupled to the first terminal K5 of the third switching circuit 213, and the second terminal K6 of the third switching circuit 213 is coupled to the storage circuit 230.

[0146] In some possible implementations, the second memory 1320 further includes a fourth interface circuit 244. The fourth interface circuit 244 includes a first terminal D1, a second terminal D2, and a fourth terminal D4.

[0147] Optionally, the first terminal S1 of the second memory 1320 is coupled to the first terminal D1 of the fourth interface circuit 244, the first terminal D1 of the fourth interface circuit 244 is coupled to the first terminal K1 of the first switch circuit 211, the second terminal K2 of the first switch circuit 211 is coupled to the fourth terminal D4 of the fourth interface circuit 244, and the fourth terminal D4 of the fourth interface circuit 244 is coupled to the storage circuit 230.

[0148] Optionally, the second terminal S2 of the second memory 1320 is coupled to the second terminal D2 of the fourth interface circuit 244, the second terminal D2 of the fourth interface circuit 244 is coupled to the first terminal K3 of the second switch circuit 212, the second terminal K4 of the second switch circuit 212 is coupled to the fourth terminal D4 of the fourth interface circuit 244, and the fourth terminal D4 of the fourth interface circuit 244 is coupled to the storage circuit 230.

[0149] Optionally, the fourth interface circuit 244 further includes a third terminal D3. The third terminal S3 of the second memory 1320 is coupled to the third terminal D3 of the fourth interface circuit 244, the third terminal D3 of the fourth interface circuit 244 is coupled to the first terminal K5 of the third switch circuit 213, the second terminal K6 of the third switch circuit 213 is coupled to the fourth terminal D4 of the fourth interface circuit 244, and the fourth terminal D4 of the fourth interface circuit 244 is coupled to the storage circuit 230.

[0150] In some other possible implementations, the second memory 1320 further includes a fourth interface circuit 244. The fourth interface circuit 244 includes a first terminal D1, a second terminal D2, and a fourth terminal D4.

[0151] Optionally, the first terminal S1 of the second memory 1320 is coupled to the first terminal K1 of the first switching circuit 211, the second terminal K2 of the first switching circuit 211 is coupled to the first terminal D1 of the fourth interface circuit 244, the first terminal D1 of the fourth interface circuit 244 is coupled to the fourth terminal D4 of the fourth interface circuit 244, and the fourth terminal D4 of the fourth interface circuit 244 is coupled to the storage circuit 230.

[0152] Optionally, the second terminal S2 of the second memory 1320 is coupled to the first terminal K3 of the second switching circuit 212, the second terminal K4 of the second switching circuit 212 is coupled to the second terminal D2 of the fourth interface circuit 244, the second terminal D2 of the fourth interface circuit 244 is coupled to the fourth terminal D4 of the fourth interface circuit 244, and the fourth terminal D4 of the fourth interface circuit 244 is coupled to the storage circuit 230.

[0153] Optionally, the fourth interface circuit 244 also includes a third terminal. The third terminal S3 of the second memory 1320 is coupled to the first terminal K5 of the third switching circuit 213, the second terminal K6 of the third switching circuit 213 is coupled to the third terminal D3 of the fourth interface circuit 244, the third terminal D3 of the fourth interface circuit 244 is coupled to the fourth terminal D4 of the fourth interface circuit 244, and the fourth terminal D4 of the fourth interface circuit 244 is coupled to the storage circuit 230.

[0154] In some possible implementations, the second memory 1320 is used to receive read instructions via a target port. The read instructions are used to instruct the reading of data. The target port is either a first terminal S1 or a second terminal S2 of the second memory 1320. The second memory 1320 is also used to transmit data via the target port.

[0155] In some possible implementations, the second memory 1320 is a non-volatile second memory 1320.

[0156] In some possible implementations, the first switching circuit 211 and the second switching circuit 212 are not turned on at the same time.

[0157] It is understood that the second memory 1320 and its possible internal structure described above can be referred to in the aforementioned embodiment of the display system 1300. Each component of the second memory 1320 is used to implement the functions and effects of the aforementioned embodiment of the display system 1300. Since the components have been described in detail in the aforementioned embodiment of the display system 1300, they will not be repeated here.

[0158] The processor involved in the embodiments of this application can be a chip. For example, it can be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0159] The memory involved in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the systems and memories described herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0160] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display system, characterized in that, The display system includes a first display screen, a second display screen, and a memory; the memory includes a first terminal and a second terminal. The first display screen is coupled to a first end of the memory, and the second display screen is coupled to a second end of the memory; the colors displayed on the first display screen and the colors displayed on the second display screen are different; A first switching circuit is provided on the transmission path between the first display screen and the memory, and a second switching circuit is provided on the transmission path between the second display screen and the memory.

2. The display system according to claim 1, characterized in that, The first display screen includes a first functional circuit and a first switching circuit; the first functional circuit is coupled to a first terminal of the first switching circuit, and the second terminal of the first switching circuit is coupled to a first terminal of the memory. The second display screen includes a second functional circuit and a second switching circuit; The second functional circuit is coupled to the first terminal of the second switching circuit, and the second terminal of the second switching circuit is coupled to the second terminal of the memory.

3. The display system according to claim 2, characterized in that, The first display screen further includes a first interface circuit; the first interface circuit includes a first terminal and a second terminal; The first functional circuit is coupled to a first terminal of the first interface circuit, the first terminal of the first interface circuit is coupled to a first terminal of the first switching circuit, the second terminal of the first switching circuit is coupled to a second terminal of the first interface circuit, and the second terminal of the first interface circuit is coupled to a first terminal of the memory; and / or, The second display screen further includes a second interface circuit; the second interface circuit includes a first terminal and a second terminal; The second functional circuit is coupled to the first end of the second interface circuit, the first end of the second interface circuit is coupled to the first end of the second switch circuit, the second end of the second switch circuit is coupled to the second end of the second interface circuit, and the second end of the second interface circuit is coupled to the second end of the memory.

4. The display system according to claim 2, characterized in that, The first display screen further includes a first interface circuit; the first interface circuit includes a first terminal and a second terminal; The first functional circuit is coupled to a first terminal of the first interface circuit, the first terminal of the first interface circuit is coupled to a second terminal of the first interface circuit, the second terminal of the first interface circuit is coupled to a first terminal of the first switching circuit, and the second terminal of the first switching circuit is coupled to a first terminal of the memory; and / or, The second display screen further includes a second interface circuit; the second interface circuit includes a first terminal and a second terminal; The second functional circuit is coupled to the first end of the second interface circuit, the first end of the second interface circuit is coupled to the second end of the second interface circuit, the second end of the second interface circuit is coupled to the first end of the second switch circuit, and the second end of the second switch circuit is coupled to the second end of the memory.

5. The display system according to claim 1, characterized in that, The first display screen is coupled to a first terminal of the first switching circuit, and the second terminal of the first switching circuit is coupled to a first terminal of the memory; and / or, The second display screen is coupled to the first terminal of the second switching circuit, and the second terminal of the second switching circuit is coupled to the second terminal of the memory.

6. The display system according to claim 1, characterized in that, The memory includes a storage circuit, a first switching circuit, and a second switching circuit; The first terminal of the memory is coupled to the first terminal of the first switching circuit; the second terminal of the first switching circuit is coupled to the memory circuit. The second terminal of the memory is coupled to the first terminal of the second switching circuit; the second terminal of the second switching circuit is coupled to the memory circuit.

7. The display system according to claim 6, characterized in that, The memory further includes a third interface circuit; the third interface circuit includes a first terminal, a second terminal, and a third terminal; The first terminal of the memory is coupled to the first terminal of the third interface circuit, the first terminal of the third interface circuit is coupled to the first terminal of the first switching circuit, the second terminal of the first switching circuit is coupled to the third terminal of the third interface circuit, and the third terminal of the third interface circuit is coupled to the memory circuit; and / or, The second terminal of the memory is coupled to the second terminal of the third interface circuit, the second terminal of the third interface circuit is coupled to the first terminal of the second switch circuit, the second terminal of the second switch circuit is coupled to the third terminal of the third interface circuit, and the third terminal of the third interface circuit is coupled to the memory circuit.

8. The display system according to claim 6, characterized in that, The memory further includes a third interface circuit; the third interface circuit includes a first terminal, a second terminal, and a third terminal; The first terminal of the memory is coupled to the first terminal of the first switching circuit, the second terminal of the first switching circuit is coupled to the first terminal of the third interface circuit, the first terminal of the third interface circuit is coupled to the third terminal of the third interface circuit, and the third terminal of the third interface circuit is coupled to the memory circuit; and / or, The second terminal of the memory is coupled to the first terminal of the second switching circuit, the second terminal of the second switching circuit is coupled to the second terminal of the third interface circuit, the second terminal of the third interface circuit is coupled to the third terminal of the third interface circuit, and the third terminal of the third interface circuit is coupled to the memory circuit.

9. The display system according to any one of claims 1-8, characterized in that, The memory is used to receive a read instruction through a target port; the read instruction is used to instruct the reading of data; the target port is either a first terminal or a second terminal of the memory. The memory is also used to send the data through the target port.

10. The display system according to any one of claims 1-9, characterized in that, The display system further includes a third display screen; the memory further includes a third terminal, and the third display screen is coupled to the third terminal of the memory; the colors displayed by the third display screen, the colors displayed by the first display screen, and the colors displayed by the second display screen are all different; A third switching circuit is provided on the transmission path between the third display screen and the memory.

11. The display system according to any one of claims 1-10, characterized in that, The memory is a non-volatile memory.

12. The display system according to any one of claims 1-11, characterized in that, The first switching circuit and the second switching circuit are not turned on at the same time.

13. A display module, characterized in that, The display module includes a first display screen and a second display screen; the colors displayed on the first display screen and the colors displayed on the second display screen are different. The first display screen includes a first functional circuit and a first switching circuit; the first functional circuit is coupled to a first terminal of the first switching circuit, and the second terminal of the first switching circuit is used to couple to a memory. The second display screen includes a second functional circuit and a second switching circuit; the second functional circuit is coupled to a first terminal of the second switching circuit, and the second terminal of the second switching circuit is used to couple the memory.

14. The display module according to claim 13, characterized in that, The first display screen further includes a first interface circuit; the first interface circuit includes a first terminal and a second terminal; The first functional circuit is coupled to a first terminal of the first interface circuit, the first terminal of the first interface circuit is coupled to a first terminal of the first switching circuit, the second terminal of the first switching circuit is coupled to a second terminal of the first interface circuit, and the second terminal of the first interface circuit is used to couple the memory; and / or The second display screen further includes a second interface circuit; the second interface circuit includes a first terminal and a second terminal; The second functional circuit is coupled to the first end of the second interface circuit, the first end of the second interface circuit is coupled to the first end of the second switch circuit, the second end of the second switch circuit is coupled to the second end of the second interface circuit, and the second end of the second interface circuit is used to couple the memory.

15. The display module according to claim 13, characterized in that, The first display screen further includes a first interface circuit; the first interface circuit includes a first terminal and a second terminal; The first functional circuit is coupled to a first terminal of the first interface circuit, the first terminal of the first interface circuit is coupled to a second terminal of the first interface circuit, the second terminal of the first interface circuit is coupled to a first terminal of the first switching circuit, and the second terminal of the first switching circuit is used to couple the memory; and / or The second display screen further includes a second interface circuit; the second interface circuit includes a first terminal and a second terminal; The second functional circuit is coupled to the first end of the second interface circuit, the first end of the second interface circuit is coupled to the second end of the second interface circuit, the second end of the second interface circuit is coupled to the first end of the second switch circuit, and the second end of the second switch circuit is used to couple the memory.

16. The display module according to any one of claims 13-15, characterized in that, The display module also includes a third display screen; the colors displayed on the third display screen, the colors displayed on the first display screen, and the colors displayed on the second display screen are all different; The third display screen includes a third functional circuit and a third switching circuit; the third functional circuit is coupled to a first terminal of the third switching circuit, and the second terminal of the third switching circuit is used to couple the memory.

17. The display module according to any one of claims 13-16, characterized in that, The first switching circuit and the second switching circuit are not turned on at the same time.

18. A memory, characterized in that, The memory includes a first terminal, a second terminal, a storage circuit, a first switching circuit, and a second switching circuit; The first end of the memory is used to couple the first display screen, and the second end of the memory is used to couple the second display screen; The first terminal of the memory is coupled to the first terminal of the first switching circuit, and the second terminal of the memory is coupled to the first terminal of the second switching circuit. The second terminal of the first switching circuit and the second terminal of the second switching circuit are both coupled to the storage circuit.

19. The memory according to claim 18, characterized in that, The memory further includes a third interface circuit; the third interface circuit includes a first terminal, a second terminal, and a third terminal; The first terminal of the memory is coupled to the first terminal of the third interface circuit, the first terminal of the third interface circuit is coupled to the first terminal of the first switching circuit, the second terminal of the first switching circuit is coupled to the third terminal of the third interface circuit, and the third terminal of the third interface circuit is coupled to the memory circuit; and / or, The second terminal of the memory is coupled to the second terminal of the third interface circuit, the second terminal of the third interface circuit is coupled to the first terminal of the second switch circuit, the second terminal of the second switch circuit is coupled to the third terminal of the third interface circuit, and the third terminal of the third interface circuit is coupled to the memory circuit.

20. The memory according to claim 18, characterized in that, The memory further includes a third interface circuit; the third interface circuit includes a first terminal, a second terminal, and a third terminal; The first terminal of the memory is coupled to the first terminal of the first switching circuit, the second terminal of the first switching circuit is coupled to the first terminal of the third interface circuit, the first terminal of the third interface circuit is coupled to the third terminal of the third interface circuit, and the third terminal of the third interface circuit is coupled to the memory circuit; and / or, The second terminal of the memory is coupled to the first terminal of the second switching circuit, the second terminal of the second switching circuit is coupled to the second terminal of the third interface circuit, the second terminal of the third interface circuit is coupled to the third terminal of the third interface circuit, and the third terminal of the third interface circuit is coupled to the memory circuit.

21. The memory according to any one of claims 18-20, characterized in that, The memory is used to receive a read instruction through a target port; the read instruction is used to instruct the reading of data; the target port is either a first terminal or a second terminal of the memory. The memory is also used to send the data through the target port.

22. The memory according to any one of claims 18-21, characterized in that, The memory also includes a third terminal and a third switching circuit; The third terminal of the memory is used to couple to the third display screen; the third terminal of the memory is coupled to the first terminal of the third switching circuit, and the second terminal of the third switching circuit is coupled to the storage circuit.

23. The memory according to any one of claims 18-22, characterized in that, The memory is a non-volatile memory.

24. The memory according to any one of claims 18-23, characterized in that, The first switching circuit and the second switching circuit are not turned on at the same time.

25. An electronic device, characterized in that, The electronic device includes a processor and a display system as described in any one of claims 1-12; The processor is used to control the display system to display colors.

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