A shift register unit, display device and driving method

Abstract

The present disclosure relates to the technical field of display, and discloses a shift register unit, a display device and a driving method. The shift register unit comprises a shift register and a node compensation circuit, the node compensation circuit is coupled with a first pull-up node of the shift register. In the implementation process, the node compensation circuit can stabilize the level of the first pull-up node according to the signal of the clock signal end, that is, by compensating the level drop at the first pull-up node and pre-boosting the level at the first pull-up node multiple times, the influence of the level drop of the first pull-up node on the scan signal output by the driving output end of the shift register is reduced, that is, the falling time of the scan signal output by the driving output end of the shift register is reduced, the power consumption of the scan signal is reduced, and the display effect is improved.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and provides a shift register unit, a display device, and a driving method. Background Technology

[0002] In related technologies, a common approach to reduce the power consumption of display panels is to reduce the driving voltage of the display panels. The driving voltages used in display panels mainly include data voltage and scanning voltage.

[0003] During the display process, the magnitude of the data voltage is related to the transmittance of the display panel. Furthermore, the magnitude of the data voltage is closely related to the material and type of the display panel. The influence of these factors will limit the variable range of the data voltage.

[0004] The scan voltage is related to the scan drive of the display panel and the loading of the data voltage on the display panel. To reduce the power consumption of the scan voltage, related technologies typically use the method of increasing the size of the transistor used to drive the output of the shift register to pull down the scan voltage with the clock signal. However, while increasing the size of the transistor driving the output, the capacitor connected to the clock signal also increases simultaneously, causing the decrease in the scan voltage's fall time to gradually decrease and tend to saturate. In other words, the reduction in fall time using the above method is limited. Summary of the Invention

[0005] This disclosure provides a shift register unit, a display device, and a driving method to reduce the fall time of the scan signal output from the drive output terminal of the shift register, thereby reducing the power consumption of the scan signal and improving the display effect.

[0006] The specific technical solution provided in this disclosure is as follows: In a first aspect, embodiments of this disclosure provide a shift register unit, including: Shift register; The node compensation circuit is coupled to the first pull-up node of the shift register. The node compensation circuit is configured to stabilize the level of the first pull-up node according to the signal at the clock signal terminal, thereby reducing the fall time of the scan signal output from the drive output terminal of the shift register.

[0007] In some possible implementations, the node compensation circuit includes a first node compensation sub-circuit and / or a second node compensation sub-circuit. The first node compensation sub-circuit is coupled to the first pull-up node and is configured to provide the signal from the setting port of the n+f level shift register unit or the clock signal input of the g+y level shift register unit to the first pull-up node, where n, f, g and y are all positive integers. The second node compensation sub-circuit is configured to provide the setting port signal of the nh-th stage shift register unit to the first pull-up node in response to the setting port signal of the nh-th stage shift register unit; to perform a stage-specific reset on the first pull-up node in response to the setting port signal of the nk-th stage shift register unit; and to perform a frame-specific reset on the first pull-up node in response to the frame reset signal, wherein h and k are both positive integers.

[0008] In some possible implementations, the first node compensation sub-circuit includes: a first capacitor; The first terminal of the first capacitor is coupled to the setting port of the (n+f)th stage shift register unit or the clock signal input of the (g+y)th stage shift register unit, and the second terminal of the first capacitor is coupled to the first pull-up node, where m is a positive integer.

[0009] In some possible implementations, the second node compensation sub-circuit includes: a first transistor, a second capacitor, a second transistor, a third transistor, and a fourth transistor; The control terminal of the first transistor is coupled to the setting port of the nh-th stage shift register unit, the first terminal of the first transistor is coupled to the setting port of the nh-th stage shift register unit, and the second terminal of the first transistor is coupled to the second pull-up node. The first terminal of the second capacitor is coupled to the second pull-up node, and the second terminal of the second capacitor is coupled to the first pull-up node. The control terminal of the second transistor is coupled to the setting port of the nk-th stage shift register unit, the first terminal of the second transistor is coupled to the second pull-up node, and the second terminal of the second transistor is coupled to the first reference signal terminal. The control terminal of the third transistor is coupled to the setting port of the (n+t)th stage shift register unit, the first terminal of the third transistor is coupled to the second pull-up node, and the second terminal of the third transistor is coupled to the first reference signal terminal, wherein t is a positive integer; The control terminal of the fourth transistor is coupled to the frame reset signal terminal, the first terminal of the fourth transistor is coupled to the second pull-up node, and the second terminal of the fourth transistor is coupled to the first reference signal terminal.

[0010] In some possible implementations, the shift register includes: The input circuit is configured to provide the signal of the setting port of the nk-th stage shift register unit to the first pull-up node in response to the signal of the setting port of the nk-th stage shift register unit. The reset circuit at this stage is configured to provide the signal at the first reference signal terminal to the first pull-up node in response to the signal at the setting port of the (n+t)th stage shift register unit. The frame reset circuit is configured to provide the signal of the first reference signal terminal to the first pull-up node in response to the signal of the frame reset signal terminal. The node control circuit is configured to control the signals of the first pull-up node, the first pull-down node, and the second pull-down node; The output circuit is configured to provide the clock signal terminal to the drive output terminal in response to the signal of the first pull-up node; and to provide the second reference signal terminal to the drive output terminal in response to the signal of the drive output terminal of the (n+b)th stage shift register unit, where b is a positive integer; The third capacitor, coupled between the first pull-up node and the drive output, is configured to stabilize the level of the first pull-up node.

[0011] In some possible implementations, the capacitance of the third capacitor is smaller than that of the first capacitor; The capacitance of the second capacitor is less than or equal to the capacitance of the first capacitor.

[0012] In some possible implementations, the absolute value of the signal at the second reference signal terminal is greater than the absolute value of the signal at the first reference signal terminal.

[0013] In some possible implementations, the input circuit includes: a fifth transistor; The control terminal of the fifth transistor is coupled to the setting port of the nk-th stage shift register unit, the first terminal of the fifth transistor is coupled to the setting port of the nk-th stage shift register unit, and the second terminal of the fifth transistor is coupled to the first pull-up node.

[0014] In some possible implementations, the reset circuit at this stage includes: a sixth transistor; The control terminal of the sixth transistor is coupled to the setting port of the (n+t)th stage shift register unit, the first terminal of the sixth transistor is coupled to the first pull-up node, and the second terminal of the sixth transistor is coupled to the first reference signal terminal.

[0015] In some possible implementations, the frame reset circuit includes: a seventh transistor; The control terminal of the seventh transistor is coupled to the frame reset signal terminal, the first terminal of the seventh transistor is coupled to the first pull-up node, and the second terminal of the seventh transistor is coupled to the first reference signal terminal.

[0016] In some possible implementations, the node control circuit includes: The first node control sub-circuit is configured to respond to the signal of the first pull-up node by providing the clock signal to the setting port of the shift register unit at this stage. The second node control sub-circuit is configured to control the signal of the first pull-down node in response to the signal of the setting port of the first power supply terminal and the nk-th stage shift register unit. The third node control sub-circuit is configured to control the signal of the second pull-down node in response to the signals of the second power supply terminal and the setting port of the nk-th stage shift register unit.

[0017] In some possible implementations, the first node control sub-circuit includes: an eighth transistor; The control terminal of the eighth transistor is coupled to the first pull-up node, the first terminal of the eighth transistor is coupled to the clock signal terminal, and the second terminal of the eighth transistor is coupled to the setting port of the shift register unit of this stage.

[0018] In some possible implementations, the second node control sub-circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; The control terminal of the ninth transistor is coupled to the first power supply terminal, the first terminal of the ninth transistor is coupled to the first power supply terminal, and the second terminal of the ninth transistor is coupled to the first pull-down node. The control terminal of the tenth transistor is coupled to the setting port of the nk-th stage shift register unit, the first terminal of the tenth transistor is coupled to the first pull-down node, and the second terminal of the tenth transistor is coupled to the first reference signal terminal. The control terminal of the eleventh transistor is coupled to the first pull-up node, the first terminal of the eleventh transistor is coupled to the first pull-down node, and the second terminal of the eleventh transistor is coupled to the first reference signal terminal. The control terminal of the twelfth transistor is coupled to the first pull-down node, the first terminal of the twelfth transistor is coupled to the first pull-up node, and the second terminal of the twelfth transistor is coupled to the first reference signal terminal. The control terminal of the thirteenth transistor is coupled to the first pull-down node, the first terminal of the thirteenth transistor is coupled to the setting port of the shift register unit of this stage, and the second terminal of the thirteenth transistor is coupled to the first reference signal terminal. The control terminal of the fourteenth transistor is coupled to the first pull-down node, the first terminal of the fourteenth transistor is coupled to the drive output terminal, and the second terminal of the fourteenth transistor is coupled to the second reference signal terminal.

[0019] In some possible implementations, the third node control sub-circuit includes: the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, and the twentieth transistor; The control terminal of the fifteenth transistor is coupled to the second power supply terminal, the first terminal of the fifteenth transistor is coupled to the second power supply terminal, and the second terminal of the fifteenth transistor is coupled to the second pull-down node. The control terminal of the sixteenth transistor is coupled to the setting port of the nk-th stage shift register unit, the first terminal of the sixteenth transistor is coupled to the second pull-down node, and the second terminal of the sixteenth transistor is coupled to the first reference signal terminal. The control terminal of the seventeenth transistor is coupled to the first pull-up node, the first terminal of the seventeenth transistor is coupled to the second pull-down node, and the second terminal of the seventeenth transistor is coupled to the first reference signal terminal. The control terminal of the eighteenth transistor is coupled to the second pull-down node, the first terminal of the eighteenth transistor is coupled to the first pull-up node, and the second terminal of the eighteenth transistor is coupled to the first reference signal terminal. The control terminal of the nineteenth transistor is coupled to the second pull-down node, the first terminal of the nineteenth transistor is coupled to the setting port of the shift register unit of this stage, and the second terminal of the nineteenth transistor is coupled to the first reference signal terminal. The control terminal of the twentieth transistor is coupled to the second pull-down node, the first terminal of the twentieth transistor is coupled to the drive output terminal, and the second terminal of the twentieth transistor is coupled to the second reference signal terminal.

[0020] In some possible implementations, the output circuit includes: a twenty-first transistor and a twenty-second transistor; The control terminal of the 21st transistor is coupled to the first pull-up node, the first terminal of the 21st transistor is coupled to the clock signal terminal, and the second terminal of the 21st transistor is coupled to the drive output terminal. The control terminal of the 22nd transistor is coupled to the drive output terminal of the (n+b)th stage shift register unit, the first terminal of the 22nd transistor is coupled to the drive output terminal, and the second terminal of the 22nd transistor is coupled to the second reference signal terminal.

[0021] Secondly, embodiments of this disclosure also provide a gate driving circuit, including: a plurality of cascaded shift register units as described in any of the above; The input signal terminal of the first-stage shift register unit is configured to be coupled to the frame start signal terminal; In each pair of adjacent shift register units, the input signal terminal of the nth-level shift register unit is configured to be coupled to the set port of the nk-level shift register unit; In each pair of adjacent shift register units, the setting port of the (n+t)th stage shift register unit is configured to be coupled to the reset port of the nth stage shift register unit.

[0022] Thirdly, embodiments of this disclosure also provide a display device including the gate driving circuit described above.

[0023] Fourthly, embodiments of this disclosure also provide a method for driving the shift register unit of any of the above claims, comprising: The shift register outputs a scan signal through its drive output terminal; The node compensation circuit stabilizes the level of the first pull-up node based on the clock signal, thereby reducing the fall time of the scan signal output from the drive output of the shift register.

[0024] The beneficial effects of this disclosure are as follows: In summary, this disclosure provides a shift register unit, a display device, and a driving method. The shift register unit includes a shift register and a node compensation circuit. The node compensation circuit is coupled to a first pull-up node of the shift register. During implementation, the node compensation circuit can stabilize the level of the first pull-up node according to the clock signal. That is, by compensating for the level drop at the first pull-up node and increasing the level at the first pull-up node in advance through multiple boosts, the impact of the level drop at the first pull-up node on the scan signal output from the drive output terminal of the shift register is reduced. This reduces the drop duration of the scan signal output from the drive output terminal of the shift register, thereby reducing the power consumption of the scan signal and improving the display effect.

[0025] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings: Figure 1 This is a circuit connection diagram of a shift register unit in related technologies; Figure 2 This is a schematic diagram of the scan voltage and PU point waveforms in a shift register unit in a related technology. Figure 3 This is a connection diagram of the first type of shift register unit in the embodiments of this disclosure; Figure 4 This is a connection diagram of the second type of shift register unit in the embodiments of this disclosure; Figure 5 This is a circuit connection diagram of the first type of shift register unit in the embodiments of this disclosure; Figure 6 This is a schematic diagram of the scan signal and the waveform of point PU1 in the first type of shift register unit in this embodiment of the present disclosure; Figure 7 This is a connection diagram of the third type of shift register unit in the embodiments of this disclosure; Figure 8 This is a circuit connection diagram of the second type of shift register unit in the embodiments of this disclosure; Figure 9This is a waveform diagram of point PU1 in the second type of shift register unit in this embodiment of the present disclosure; Figure 10 This is a connection diagram of the fourth type of shift register unit in the embodiments of this disclosure; Figure 11 This is a circuit connection diagram of the third type of shift register unit in the embodiments of this disclosure; Figure 12 This is a schematic diagram of the scan signal and the waveform of point PU1 in the third type of shift register unit in this embodiment of the present disclosure; Figure 13 This is a connection diagram of the fifth type of shift register unit in the embodiments of this disclosure; Figure 14 This is a circuit connection diagram of the fourth type of shift register unit in the embodiments of this disclosure; Figure 15 This is a circuit connection diagram of the fifth type of shift register unit in the embodiments of this disclosure; Figure 16 This is a timing diagram of a shift register unit in an embodiment of this disclosure; Figure 17 This is a schematic diagram of a cascaded gate drive circuit according to an embodiment of the present disclosure; Figure 18 This is a flowchart of a driving method applied to a shift register unit according to an embodiment of the present disclosure. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the technical solutions of this disclosure, and not all embodiments. Based on the embodiments recorded in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the technical solutions of this disclosure.

[0028] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.

[0029] In related technologies, a common approach to reduce the power consumption of display panels is to reduce the driving voltage of the display panels. The driving voltages used in display panels mainly include data voltage and scanning voltage.

[0030] During the display process, the magnitude of the data voltage is related to the transmittance of the display panel. Furthermore, the magnitude of the data voltage is closely related to the material and type of the display panel. The influence of these factors will limit the variable range of the data voltage.

[0031] The scan voltage is related to the scan drive of the display panel and the loading of the data voltage on the display panel. To reduce the power consumption of the scan voltage, related technologies typically use the method of increasing the size of the transistor used to drive the output of the shift register to pull down the scan voltage with the clock signal. However, while increasing the size of the transistor driving the output, the capacitor connected to the clock signal also increases simultaneously, causing the decrease in the scan voltage's fall time to gradually decrease and tend to saturate. In other words, the reduction in fall time using the above method is limited.

[0032] See Figure 1 As shown, in the related technology, the transistor used to drive the output in the shift register unit is transistor M3. When the size of transistor M3 is increased, the capacitance of capacitor C1 connected to the clock signal terminal CKm will also increase synchronously. However, simply increasing the size of transistor M3 can only reduce the scanning voltage drop time by a very limited margin.

[0033] See Figure 2 As shown, during the operation of the shift register unit, the voltage level of the pull-up node PU will first rise from the initial voltage to voltage v1, and then rise from voltage v1 to voltage v2. When the voltage of the clock signal terminal CKm drops, the voltage level of the pull-up node PU will drop from voltage v2 to voltage v3. Figure 2 It can be seen that the voltage level at the PU point drops slowly from voltage v2 to voltage v3, and voltage v3 appears after the high level of the scan voltage. Therefore, the scan voltage is affected by this slow drop from voltage v2 to voltage v3, resulting in a longer scan voltage drop time, i.e., a smoother falling edge. In this case, to ensure normal drive of the scan voltage, more power is required to increase the driving capability of the scan voltage.

[0034] The preferred embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0035] See Figure 3 As shown in the embodiment of this application, a shift register unit includes a shift register 10 and a node compensation circuit 20.

[0036] The node compensation circuit 20 is coupled to the first pull-up node PU1 of the shift register 10. The node compensation circuit 20 is configured to stabilize the level of the first pull-up node PU1 according to the signal of the clock signal terminal CKm, thereby reducing the fall time of the scan signal output by the drive output terminal G(n) of the shift register 10.

[0037] Considering that during the output of the scan signal at the drive output terminal G(n) of shift register 10, the level of the first pull-up node PU1 is closely related to the effective level of the scan signal. That is, only when the level of the first pull-up node PU1 can fully turn on the drive output transistor can the effective level of the clock signal terminal CKm be provided to the drive output terminal G(n) through the fully turned-on transistor. When the signal of the clock signal terminal CKm changes from an effective level to an ineffective level, the level of the first pull-up node PU1 will also be affected, resulting in a longer fall time of the scan signal output at the drive output terminal G(n), that is, a slower fall edge of the scan signal. In order to ensure normal display, the corresponding drive power consumption will increase.

[0038] In this embodiment of the application, in order to reduce the falling time of the scan signal output by the drive output terminal G(n) of the shift register 10, even if the falling edge of the scan signal is steeper, a node compensation circuit 20 is coupled at the first pull-up node PU1.

[0039] During implementation, when the clock signal terminal CKm changes from an active level to an inactive level, the node compensation circuit 20 can stabilize the level of the first pull-up node PU1. In this way, the drive output transistor can remain fully open, so that the transition of the clock signal terminal CKm from an active level to an inactive level can be quickly output through the drive output transistor. That is, the falling time of the scan signal output by the control drive output terminal G(n) is shortened, and the falling edge of the corresponding scan signal is steeper, which helps to reduce power consumption.

[0040] In this embodiment of the application, the node compensation circuit 20 includes a first node compensation sub-circuit 201 and / or a second node compensation sub-circuit 202.

[0041] It should be noted that, in order to shorten the fall time of the scan signal output by the drive output terminal G(n), the embodiments of this application specifically provide a first node compensation sub-circuit 201 and a second node compensation sub-circuit 202, and achieve the purpose of shortening the fall time of the scan signal by combining the first node compensation sub-circuit 201 and the second node compensation sub-circuit 202 to form three schemes.

[0042] The three schemes mentioned above are as follows: Scheme 1: Using the first node compensation sub-circuit 201 as the node compensation circuit 20; Scheme 2: Using the second node compensation sub-circuit 202 as the node compensation circuit 20; Scheme 3: Using the first node compensation sub-circuit 201 and the second node compensation sub-circuit 202 as the node compensation circuit 20. These will be described in detail below.

[0043] For the specific implementation plan of Option 1 above, please refer to Figure 4and Figure 5 As shown, the first node compensation sub-circuit 201 is coupled to the first pull-up node PU1. The first node compensation sub-circuit 201 is configured to provide the signal of the setting port Out_C(n+f) of the n+f-th stage shift register unit or the clock signal terminal CKg+y of the g+y-th stage shift register unit to the first pull-up node PU1, wherein n, f, g and y are all positive integers.

[0044] When the clock signal CKm transitions from an active level to an inactive level, the level of the first pull-up node PU1 will also be pulled low by the transition, thereby driving the output transistor (for example, Figure 5 The 21st transistor (T21) in the clock signal is not fully turned on, and the signal transition at the aforementioned clock signal terminal CKm cannot cause the scanning signal to quickly produce a falling edge.

[0045] Based on this, during implementation, the first node compensation sub-circuit 201 can provide the signal of the setting port Out_C(n+f) of the n+f-th stage shift register unit or the clock signal input CKg+y of the g+y-th stage shift register unit to the first pull-up node PU1 after the signal transition of the clock signal terminal CKm. The signal of the setting port Out_C(n+f) of the n+f-th stage shift register unit or the clock signal input CKg+y of the g+y-th stage shift register unit is at an effective level, thereby compensating for the signal transition of the clock signal terminal CKm. That is, the level of the first pull-up node PU1 is stabilized at a level range that can keep the drive output transistor fully turned on. After the drive output transistor is fully turned on, the signal transition of the clock signal terminal CKm can make the scan signal quickly appear a falling edge, thereby effectively reducing the drive power consumption.

[0046] For example, if the value of f is 4, the signal of the setting port Out_C(n+4) of the (n+4)th stage shift register unit is provided to the first pull-up node PU1 via the first node compensation sub-circuit 201, and the signal of the setting port Out_C(n+4) is at an active level. If the value of y is also 4, the clock signal CKm (i.e., CKm+4) input to the (m+4)th stage shift register unit is provided to the first pull-up node PU1, and the clock signal CKm (i.e., CKm+4) is at an active level.

[0047] See Figure 5 As shown, the first node compensation sub-circuit 201 includes: a first capacitor C1.

[0048] The first terminal of the first capacitor C1 is coupled to the setting port Out_C(n+f) of the n+f-th stage shift register unit or the clock signal terminal CKg+y input of the g+y-th stage shift register unit, and the second terminal of the first capacitor C1 is coupled to the first pull-up node PU1, wherein m is a positive integer.

[0049] See Figure 6 As shown, after the level of the first pull-up node PU1 of the shift register unit is raised from level u1 to level u2, due to the addition of the first node compensation sub-circuit 201 in the shift register unit, that is, after the level of the first pull-up node PU1 is compensated by the first node compensation sub-circuit 201, compared with the related technology... Figure 2 As shown, the aforementioned level u2 reaches level u3 in a relatively short time, and level u3 is relatively... Figure 2 The value of level v3 is higher, so that the tube driving the output can be fully turned on under the action of level u3. The signal transition of the clock signal terminal CKm can make the scanning signal fall edge quickly, the falling time of the scanning signal is shorter, and the falling edge of the scanning signal is steeper, which helps to reduce the driving power consumption.

[0050] For the specific implementation plan of Option 2 above, please refer to [link / reference]. Figure 7 and Figure 8 As shown, the second node compensation sub-circuit 202 is configured to provide the setting port Out_C(nh) of the nh-th stage shift register unit to the first pull-up node PU1 in response to the signal of the setting port Out_C(nh) of the nh-th stage shift register unit; and to perform a stage-specific reset on the first pull-up node PU1 in response to the signal of the setting port Out_C(nk) of the nk-th stage shift register unit. Furthermore, it performs a frame-specific reset on the first pull-up node PU1 in response to the frame reset signal TRST, where h and k are both positive integers.

[0051] The above-mentioned scheme two is essentially a newly added coupling pull-up module. This coupling pull-up module can act on the first pull-up node PU1, that is, scheme two compensates for and raises the level of the first pull-up node PU1, thereby raising the level of the first pull-up node PU1 higher. Thus, when the clock signal CKm transitions from an active level to an inactive level, the impact on the level of the first pull-up node PU1 will be relatively reduced, thereby enabling the drive output transistor (exemplary, ...) to... Figure 8 The 21st transistor (T21) is kept fully turned on, and the signal transition of the clock signal terminal CKm causes the scan signal to quickly produce a falling edge, thereby reducing the drive power consumption.

[0052] Based on this, during implementation, the second node compensation sub-circuit 202 can provide the setting port Out_C(nh) of the nh-th stage shift register unit to the first pull-up node PU1 after the signal transition at the clock signal terminal CKm. This allows the first pull-up node PU1 to experience another level rise under the influence of the setting port signal, thus raising the level of the first pull-up node PU1 to a higher value. In this way, when the clock signal terminal CKm transitions from an active level to an inactive level (i.e., the level of the first pull-up node PU1 drops from a higher level), it can still remain stable within the range that keeps the drive output transistor fully on. With the drive output transistor fully on, the signal transition at the clock signal terminal CKm enables the scan signal to quickly produce a falling edge, thereby effectively reducing drive power consumption.

[0053] For example, the value of h is 2, that is, the signal of the setting port Out_C(n-2) of the (n-2)th stage shift register unit is provided to the first pull-up node PU1 through the second node compensation sub-circuit 202, and the signal of the setting port Out_C(n-2) is at an active level.

[0054] Meanwhile, to ensure the normal operation of the coupling pull-up module in the shift register unit, the aforementioned second node compensation sub-circuit 202 can also perform a level-specific reset of the first pull-up node PU1 under the action of the setting port Out_C(nk) signal of the nk-th level shift register unit. That is, when the setting port Out_C(nk) signal of the nk-th level shift register unit is active, the active level is used to perform a level-specific reset of the first pull-up node PU1 of the current level shift register unit, thereby reducing the impact on the scanning signal of the next level shift register unit. Furthermore, the aforementioned second node compensation sub-circuit 202 can also perform a frame-specific reset of the first pull-up node PU1 using the frame reset signal TRST. That is, after a frame of image display is completed, the entire display image is reset using the frame reset signal TRST.

[0055] See Figure 8 As shown, the second node compensation sub-circuit 202 includes: a first transistor T1, a second capacitor C2, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0056] The control terminal of the first transistor T1 is coupled to the setting port Out_C(nh) of the nh-th stage shift register unit, the first terminal of the first transistor T1 is coupled to the setting port Out_C(nh) of the nh-th stage shift register unit, and the second terminal of the first transistor T1 is coupled to the second pull-up node PU2.

[0057] For example, the first transistor T1 can be turned on under the control of the effective level of the setting port Out_C(nh) of the nh-th shift register unit, and can be turned off under the control of the ineffective level of the setting port Out_C(nh) of the nh-th shift register unit. For example, if the first transistor T1 is set as an N-type transistor, then the effective level of the signal at the setting port Out_C(nh) of the nh-th shift register unit is a high level, and the ineffective level of the signal at the setting port Out_C(nh) of the nh-th shift register unit is a low level. Alternatively, if the first transistor T1 is set as a P-type transistor, then the effective level of the signal at the setting port Out_C(nh) of the nh-th shift register unit is a low level, and the ineffective level of the signal at the setting port Out_C(nh) of the nh-th shift register unit is a high level.

[0058] See Figure 8 As shown, the first transistor T1 is an N-type transistor. When the signal of the setting port Out_C(nh) of the nh-th stage shift register unit is high, the first transistor T1 is turned on, and the signal of the setting port Out_C(nh) of the nh-th stage shift register unit is provided as an input signal to the second pull-up node PU2 via the first transistor T1.

[0059] Furthermore, the first terminal of the second capacitor C2 is coupled to the second pull-up node PU2, and the second terminal of the second capacitor C2 is coupled to the first pull-up node PU1. Thus, the signal provided to the second pull-up node PU2 can be further coupled to the first pull-up node PU1 via the second capacitor C2. Compared to Figure 2 The waveform of the first pull-up node PU1 corresponding to the second node compensation sub-circuit 202 is as follows: Figure 9 As shown, under the action of the first transistor T1 and the second capacitor C2, the voltage level of the first pull-up node PU1 experienced three rises: first, the voltage level of the first pull-up node PU1 rose to voltage V1, then from voltage V1 to voltage V2, and then from voltage V2 to voltage V3. When the clock signal terminal CKm switched from an active level to an inactive level, the voltage level of the first pull-up node PU1 switched from voltage V3 to voltage V4. Compared to Figure 2 The value of voltage V3 is higher than the value of level v2. Thus, even if voltage V3 jumps to voltage V4, the value of voltage V4 will still be higher than the value of level v3. The first pull-up node PU1 can maintain a higher level, thereby keeping the drive output transistor fully turned on. When the drive output transistor is fully turned on, the signal transition of the clock signal terminal CKm can make the scan signal quickly appear a falling edge, thereby effectively reducing drive power consumption.

[0060] See Figure 8 As shown, the control terminal of the second transistor T2 is coupled to the setting port Out_C(nk) of the nk-th stage shift register unit, the first terminal of the second transistor T2 is coupled to the second pull-up node PU2, and the second terminal of the second transistor T2 is coupled to the first reference signal terminal VGL1.

[0061] For example, the second transistor T2 can be turned on under the control of the effective level of the setting port Out_C(nk) of the nk-th shift register unit, and can be turned off under the control of the ineffective level of the setting port Out_C(nk) of the nk-th shift register unit. For example, if the second transistor T2 is configured as an N-type transistor, then the effective level of the signal at the setting port Out_C(nk) of the nk-th shift register unit is high, and the ineffective level of the signal at the setting port Out_C(nk) of the nk-th shift register unit is low. Alternatively, if the second transistor T2 is configured as a P-type transistor, then the effective level of the signal at the setting port Out_C(nk) of the nk-th shift register unit is low, and the ineffective level of the signal at the setting port Out_C(nk) of the nk-th shift register unit is high.

[0062] See Figure 8 As shown, the second transistor T2 is an N-type transistor. When the signal of the setting port Out_C(nk) of the nk-th stage shift register unit is high, the second transistor T2 is turned on, and the signal of the first reference signal terminal VGL1 is provided to the second pull-up node PU2 through the second transistor T2, thereby realizing the reset of the second pull-up node PU2.

[0063] See Figure 8 As shown, the control terminal of the third transistor T3 is coupled to the setting port Out_C(n+t) of the n+t stage shift register unit, the first terminal of the third transistor T3 is coupled to the second pull-up node PU2, and the second terminal of the third transistor T3 is coupled to the first reference signal terminal VGL1.

[0064] For example, the third transistor T3 can be turned on under the control of the valid level of the setting port Out_C(n+t) of the (n+t)-th stage shift register unit, and can be turned off under the control of the invalid level of the setting port Out_C(n+t) of the (n+t)-th stage shift register unit. For example, if the third transistor T3 is set as an N-type transistor, then the valid level of the signal at the setting port Out_C(n+t) of the (n+t)-th stage shift register unit is a high level, and the invalid level of the signal at the setting port Out_C(n+t) of the (n+t)-th stage shift register unit is a low level. Alternatively, if the third transistor T3 is set as a P-type transistor, then the valid level of the signal at the setting port Out_C(n+t) of the (n+t)-th stage shift register unit is a low level, and the invalid level of the signal at the setting port Out_C(n+t) of the (n+t)-th stage shift register unit is a high level.

[0065] See Figure 8 As shown, the third transistor T3 is an N-type transistor. When the signal of the setting port Out_C(n+t) of the n+t stage shift register unit is high, the third transistor T3 is turned on. The signal of the first reference signal terminal VGL1 is provided to the second pull-up node PU2 through the third transistor T3, thereby realizing the reset of the second pull-up node PU2 at this stage.

[0066] See Figure 8 As shown, the control terminal of the fourth transistor T4 is coupled to the frame reset signal terminal TRST, the first terminal of the fourth transistor T4 is coupled to the second pull-up node PU2, and the second terminal of the fourth transistor T4 is coupled to the first reference signal terminal VGL1.

[0067] For example, the fourth transistor T4 can be turned on under the control of the active level of the frame reset signal terminal TRST, and can be turned off under the control of the inactive level of the frame reset signal terminal TRST. For example, if the fourth transistor T4 is set as an N-type transistor, then the active level of the frame reset signal terminal TRST is a high level, and the inactive level of the frame reset signal terminal TRST is a low level. Alternatively, if the fourth transistor T4 is set as a P-type transistor, then the active level of the frame reset signal terminal TRST is a low level, and the inactive level of the frame reset signal terminal TRST is a high level.

[0068] See Figure 8 As shown, the fourth transistor T4 is an N-type transistor. When the frame reset signal terminal TRST is high, the fourth transistor T4 is turned on, and the signal of the first reference signal terminal VGL1 is provided to the second pull-up node PU2 through the fourth transistor T4, thereby realizing the frame reset of the second pull-up node PU2.

[0069] The configuration of the second transistor T2, the third transistor T3, and the fourth transistor T4 enables the second pull-up node PU2 to maintain a stable invalid level, thereby effectively avoiding the fluctuations caused by noise, interference, etc. to the second pull-up node PU2.

[0070] For the detailed implementation plan of Option 3 above, please refer to [link / reference]. Figure 10 and Figure 11 As shown, the first node compensation sub-circuit 201 and the second node compensation sub-circuit 202 are simultaneously set in the shift register unit. The first node compensation sub-circuit 201 and the second node compensation sub-circuit 202 work together to maintain the first pull-up node PU1 at a stable level, thus keeping the drive output transistor fully turned on. The signal transition at the clock signal terminal CKm enables the scan signal to quickly produce a falling edge, i.e., the falling edge of the scan signal is steeper, thereby effectively reducing drive power consumption. The specific working process of the first node compensation sub-circuit 201 and the second node compensation sub-circuit 202 is the same as described above.

[0071] See Figure 12 As shown, when the first node compensation sub-circuit 201 and the second node compensation sub-circuit 202 are simultaneously set in the shift register unit, the level of the first pull-up node PU1 can not only be raised three times under the action of the second node compensation sub-circuit 202, that is, the level of the first pull-up node PU1 is raised from 0 to level U1, then from level U1 to level U2, and then from level U2 to level U3, but the level of the first pull-up node PU1 can also be quickly lowered to level U4 under the action of the first node compensation sub-circuit 201. Because the aforementioned level U3 will be higher than... Figure 2 The voltage value of level v2 in the middle is higher, and at the same time, the time taken for the level of the first pull-up node PU1 to drop from the highest level U3 to level U4 is longer than that of the second pull-up node PU1. Figure 2 The time it takes for the voltage level v2 to drop to level v3 is shorter. Therefore, when the clock signal CKm transitions from an active to an inactive level, the voltage level of the first pull-up node PU1 can remain at a relatively stable high level, thus ensuring... Figure 11 When the 21st transistor T21, which drives the output, is fully turned on, the signal transition at the clock signal terminal CKm can cause the scanning signal to fall rapidly, making the falling edge of the scanning signal steeper, thereby effectively reducing drive power consumption.

[0072] After introducing the first node compensation sub-circuit 201 and the second node compensation sub-circuit 202, the structure of the shift register 10 will be described in detail below.

[0073] See Figure 13As shown, the shift register 10 includes: an input circuit 101, a local reset circuit 102, a local frame reset circuit 103, a node control circuit 104, and an output circuit 105. The following describes the process in conjunction with... Figure 14 The composition of each of the above circuit parts will be described in detail.

[0074] Input circuit 101 is configured to provide the signal of the setting port Out_C(nk) of the nk-th stage shift register unit to the first pull-up node PU1 in response to the signal of the setting port Out_C(nk) of the nk-th stage shift register unit.

[0075] During implementation, when the signal of the setting port Out_C(nk) of the nk-th stage shift register unit is at an active level, the input circuit 101 is turned on, and the signal of the setting port Out_C(nk) of the nk-th stage shift register unit is provided to the first pull-up node PU1 through the input circuit 101.

[0076] For example, the value of k is 4, that is, when the signal of the setting port of the (n-4)th level shift register unit is at an effective level, the effective level is provided as an input signal to the input circuit 101, the input circuit 101 is turned on, and the signal of the setting port of the (n-4)th level shift register unit is provided to the first pull-up node PU1 through the input circuit 101.

[0077] See Figure 14 As shown, the input circuit 101 includes: a fifth transistor T5.

[0078] The control terminal of the fifth transistor T5 is coupled to the setting port Out_C(nk) of the nk-th stage shift register unit, the first terminal of the fifth transistor T5 is coupled to the setting port Out_C(nk) of the nk-th stage shift register unit, and the second terminal of the fifth transistor T5 is coupled to the first pull-up node PU1.

[0079] For example, the fifth transistor T5 can be turned on under the control of the effective level of the setting port Out_C(nk) of the nk-th shift register unit, and can be turned off under the control of the ineffective level of the setting port Out_C(nk) of the nk-th shift register unit. For example, if the fifth transistor T5 is set as an N-type transistor, then the effective level of the signal at the setting port Out_C(nk) of the nk-th shift register unit is high, and the ineffective level of the signal at the setting port Out_C(nk) of the nk-th shift register unit is low. Alternatively, if the fifth transistor T5 is set as a P-type transistor, then the effective level of the signal at the setting port Out_C(nk) of the nk-th shift register unit is low, and the ineffective level of the signal at the setting port Out_C(nk) of the nk-th shift register unit is high.

[0080] See Figure 14 As shown, the fifth transistor T5 is an N-type transistor. When the signal of the setting port Out_C(nk) of the nk-th stage shift register unit is high, the fifth transistor T5 is turned on, and the signal of the setting port Out_C(nk) of the nk-th stage shift register unit is provided to the first pull-up node PU1 through the fifth transistor T5, thereby making the level of the first pull-up node PU1 high.

[0081] See Figure 13 As shown, the shift register 10 also includes a local reset circuit 102, which is configured to provide the signal of the first reference signal terminal VGL1 to the first pull-up node PU1 in response to the signal of the setting port Out_C(n+t) of the n+t-th stage shift register unit.

[0082] During implementation, when the signal of the setting port Out_C(n+t) of the (n+t)th stage shift register unit is at an active level, the reset circuit 102 of this stage is turned on, and the signal of the first reference signal terminal VGL1 is provided to the first pull-up node PU1 through the turned-on reset circuit 102, thereby realizing the reset of the first pull-up node PU1 of the shift register unit of this stage.

[0083] For example, the value of m is 3, that is, when the signal of the setting port of the (n+3)th level shift register unit is at an effective level, the reset circuit 102 of this level is turned on, and the signal of the first reference signal terminal VGL1 is provided to the first pull-up node PU1 through the turned-on reset circuit 102 of this level.

[0084] See Figure 14 As shown, the reset circuit 102 of this stage includes: the sixth transistor T6.

[0085] The control terminal of the sixth transistor T6 is coupled to the setting port Out_C(n+t) of the n+t stage shift register unit, the first terminal of the sixth transistor T6 is coupled to the first pull-up node PU1, and the second terminal of the sixth transistor T6 is coupled to the first reference signal terminal VGL1.

[0086] For example, the sixth transistor T6 can be turned on under the control of the valid level of the setting port Out_C(n+t) of the (n+t)-th stage shift register unit, and can be turned off under the control of the invalid level of the setting port Out_C(n+t) of the (n+t)-th stage shift register unit. For example, if the sixth transistor T6 is configured as an N-type transistor, then the valid level of the signal at the setting port Out_C(n+t) of the (n+t)-th stage shift register unit is high, and the invalid level of the signal at the setting port Out_C(n+t) of the (n+t)-th stage shift register unit is low. Alternatively, if the sixth transistor T6 is configured as a P-type transistor, then the valid level of the signal at the setting port Out_C(n+t) of the (n+t)-th stage shift register unit is low, and the invalid level of the signal at the setting port Out_C(n+t) of the (n+t)-th stage shift register unit is high.

[0087] See Figure 14 As shown, the sixth transistor T6 is an N-type transistor. When the signal of the setting port Out_C(n+t) of the (n+t)th stage shift register unit is high, the sixth transistor T6 is turned on. The signal of the first reference signal terminal VGL1 is provided to the first pull-up node PU1 through the sixth transistor T6, thereby realizing the reset of the first pull-up node PU1 of this stage shift register unit.

[0088] See Figure 13 As shown, the shift register 10 also includes a frame reset circuit 103, which is configured to provide the signal of the first reference signal terminal VGL1 to the first pull-up node PU1 in response to the signal of the frame reset signal terminal TRST.

[0089] During implementation, when the TRST signal at the frame reset signal terminal is at an effective level, the frame reset circuit 103 is turned on, and the signal at the first reference signal terminal VGL1 is provided to the first pull-up node PU1 through the turned-on frame reset circuit 103, thereby realizing the frame reset of the first pull-up node PU1 after the current frame display screen is finished.

[0090] See Figure 14 As shown, the current frame reset circuit 103 includes: a seventh transistor T7.

[0091] The control terminal of the seventh transistor T7 is coupled to the frame reset signal terminal TRST, the first terminal of the seventh transistor T7 is coupled to the first pull-up node PU1, and the second terminal of the seventh transistor T7 is coupled to the first reference signal terminal VGL1.

[0092] For example, the seventh transistor T7 can be turned on under the control of the active level of the frame reset signal terminal TRST, and can be turned off under the control of the inactive level of the frame reset signal terminal TRST. For example, if the seventh transistor T7 is set as an N-type transistor, then the active level of the frame reset signal terminal TRST is a high level, and the inactive level of the frame reset signal terminal TRST is a low level. Alternatively, if the seventh transistor T7 is set as a P-type transistor, then the active level of the frame reset signal terminal TRST is a low level, and the inactive level of the frame reset signal terminal TRST is a high level.

[0093] See Figure 14 As shown, the seventh transistor T7 is an N-type transistor. When the frame reset signal terminal TRST is high, the seventh transistor T7 is turned on, and the signal of the first reference signal terminal VGL1 is provided to the first pull-up node PU1 through the seventh transistor T7, thereby realizing the frame reset of the first pull-up node PU1 after the current frame display is completed.

[0094] See Figure 13 As shown, the shift register 10 also includes a node control circuit 104, which is configured to control the signals of the first pull-up node PU1, the first pull-down node PD1, and the second pull-down node PD2.

[0095] During implementation, the main function of the node control circuit 104 is to control whether the signal levels of the first pull-up node PU1, the first pull-down node PD1, and the second pull-down node PD2 are valid or invalid.

[0096] See Figure 13 and Figure 14 As shown, the node control circuit 104 in this embodiment includes: a first node control sub-circuit 1041, a second node control sub-circuit 1042, and a third node control sub-circuit 1043.

[0097] The first node control sub-circuit 1041 is configured to provide the clock signal terminal CKm to the setting port Out_C(n) of the shift register unit in response to the signal of the first pull-up node PU1.

[0098] During implementation, when the signal of the first pull-up node PU1 is at an effective level, the first node control sub-circuit 1041 is turned on. The signal of the clock signal terminal CKm is provided to the setting port Out_C(n) of the shift register unit at this level through the turned-on first node control sub-circuit 1041. That is, the signal level of the setting port Out_C(n) of the shift register unit at this level is controlled by the signal of the clock signal terminal CKm.

[0099] See Figure 14 As shown, the first node control sub-circuit 1041 includes: the eighth transistor T8.

[0100] The control terminal of the eighth transistor T8 is coupled to the first pull-up node PU1, the first terminal of the eighth transistor T8 is coupled to the clock signal terminal CKm, and the second terminal of the eighth transistor T8 is coupled to the setting port Out_C(n) of the shift register unit of this stage.

[0101] For example, the eighth transistor T8 can be turned on under the control of the effective level of the first pull-up node PU1, and can be turned off under the control of the ineffective level of the first pull-up node PU1. For example, if the eighth transistor T8 is set as an N-type transistor, then the effective level of the signal of the first pull-up node PU1 is a high level, and the ineffective level of the signal of the first pull-up node PU1 is a low level. Alternatively, if the eighth transistor T8 is set as a P-type transistor, then the effective level of the signal of the first pull-up node PU1 is a low level, and the ineffective level of the signal of the first pull-up node PU1 is a high level.

[0102] See Figure 14 As shown, the eighth transistor T8 is an N-type transistor. When the signal of the first pull-up node PU1 is high, the eighth transistor T8 is turned on, and the clock signal terminal CKm is provided to the setting port Out_C(n) of the shift register unit of this stage through the eighth transistor T8.

[0103] The aforementioned second node control sub-circuit 1042 is configured to control the signal of the first pull-down node PD1 in response to the signals of the first power supply terminal VDDO and the setting port Out_C(nk) of the nk-th stage shift register unit.

[0104] During implementation, the second node control sub-circuit 1042 can control the signal of the first pull-down node PD1 to be either valid or invalid after receiving the signals from the first power supply terminal VDDO and the setting port Out_C(nk) of the nk-th stage shift register unit.

[0105] See Figure 14 As shown, the second node control sub-circuit 1042 includes: a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14.

[0106] See Figure 14 As shown, the control terminal of the ninth transistor T9 is coupled to the first power supply terminal VDDO, the first terminal of the ninth transistor T9 is coupled to the first power supply terminal VDDO, and the second terminal of the ninth transistor T9 is coupled to the first pull-down node PD1.

[0107] For example, the ninth transistor T9 can be turned on under the control of the active level of the first power supply terminal VDDO, and can be turned off under the control of the inactive level of the first power supply terminal VDDO. For example, if the ninth transistor T9 is configured as an N-type transistor, then the active level of the signal at the first power supply terminal VDDO is a high level, and the inactive level of the signal at the first power supply terminal VDDO is a low level. Alternatively, if the ninth transistor T9 is configured as a P-type transistor, then the active level of the signal at the first power supply terminal VDDO is a low level, and the inactive level of the signal at the first power supply terminal VDDO is a high level.

[0108] See Figure 14 As shown, the ninth transistor T9 is an N-type transistor. When the signal at the first power supply terminal VDDO is high, the ninth transistor T9 is turned on, and the signal at the first power supply terminal VDDO is provided to the first pull-down node PD1 through the ninth transistor T9, thereby setting the first pull-down node PD1 to a high-level state.

[0109] See Figure 14 As shown, the control terminal of the tenth transistor T10 is coupled to the setting port Out_C(nk) of the nk-th stage shift register unit, the first terminal of the tenth transistor T10 is coupled to the first pull-down node PD1, and the second terminal of the tenth transistor T10 is coupled to the first reference signal terminal VGL1.

[0110] For example, the tenth transistor T10 can be turned on under the control of the effective level of the setting port Out_C(nk) of the nk-th shift register unit, and can be turned off under the control of the ineffective level of the setting port Out_C(nk) of the nk-th shift register unit. For example, if the tenth transistor T10 is set as an N-type transistor, then the effective level of the signal at the setting port Out_C(nk) of the nk-th shift register unit is high, and the ineffective level of the signal at the setting port Out_C(nk) of the nk-th shift register unit is low. Alternatively, if the tenth transistor T10 is set as a P-type transistor, then the effective level of the signal at the setting port Out_C(nk) of the nk-th shift register unit is low, and the ineffective level of the signal at the setting port Out_C(nk) of the nk-th shift register unit is high.

[0111] See Figure 14 As shown, the tenth transistor T10 is an N-type transistor. When the signal of the setting port Out_C(nk) of the nk-th stage shift register unit is high, for example, the value of k is 4, that is, when the signal of the setting port of the (n-4)-th stage shift register unit is high, the tenth transistor T10 is turned on, and the signal of the first reference signal terminal VGL1 is provided to the first pull-down node PD1 through the tenth transistor T10.

[0112] See Figure 14 As shown, the control terminal of the eleventh transistor T11 is coupled to the first pull-up node PU1, the first terminal of the eleventh transistor T11 is coupled to the first pull-down node PD1, and the second terminal of the eleventh transistor T11 is coupled to the first reference signal terminal VGL1.

[0113] For example, the eleventh transistor T11 can be turned on under the control of the effective level of the first pull-up node PU1, and can be turned off under the control of the ineffective level of the first pull-up node PU1. For example, if the eleventh transistor T11 is set as an N-type transistor, then the effective level of the signal of the first pull-up node PU1 is a high level, and the ineffective level of the signal of the first pull-up node PU1 is a low level. Alternatively, if the eleventh transistor T11 is set as a P-type transistor, then the effective level of the signal of the first pull-up node PU1 is a low level, and the ineffective level of the signal of the first pull-up node PU1 is a high level.

[0114] See Figure 14 As shown, the eleventh transistor T11 is an N-type transistor. When the signal of the first pull-up node PU1 is high, the eleventh transistor T11 is turned on, and the signal of the first reference signal terminal VGL1 is provided to the first pull-down node PD1 through the eleventh transistor T11.

[0115] See Figure 14 As shown, the control terminal of the twelfth transistor T12 is coupled to the first pull-down node PD1, the first terminal of the twelfth transistor T12 is coupled to the first pull-up node PU1, and the second terminal of the twelfth transistor T12 is coupled to the first reference signal terminal VGL1.

[0116] For example, the twelfth transistor T12 can be turned on under the control of the active level of the first pull-down node PD1, and can be turned off under the control of the inactive level of the first pull-down node PD1. For example, if the twelfth transistor T12 is set as an N-type transistor, then the active level of the signal of the first pull-down node PD1 is a high level, and the inactive level of the signal of the first pull-down node PD1 is a low level. Alternatively, if the twelfth transistor T12 is set as a P-type transistor, then the active level of the signal of the first pull-down node PD1 is a low level, and the inactive level of the signal of the first pull-down node PD1 is a high level.

[0117] See Figure 14 As shown, the twelfth transistor T12 is an N-type transistor. When the signal of the first pull-down node PD1 is high, the twelfth transistor T12 is turned on, and the signal of the first reference signal terminal VGL1 is provided to the first pull-up node PU1 through the twelfth transistor T12.

[0118] See Figure 14As shown, the control terminal of the thirteenth transistor T13 is coupled to the first pull-down node PD1, the first terminal of the thirteenth transistor T13 is coupled to the setting port Out_C(n) of the shift register unit of this stage, and the second terminal of the thirteenth transistor T13 is coupled to the first reference signal terminal VGL1.

[0119] For example, the thirteenth transistor T13 can be turned on under the control of the active level of the first pull-down node PD1, and can be turned off under the control of the inactive level of the first pull-down node PD1. For example, if the thirteenth transistor T13 is set as an N-type transistor, then the active level of the signal of the first pull-down node PD1 is a high level, and the inactive level of the signal of the first pull-down node PD1 is a low level. Alternatively, if the thirteenth transistor T13 is set as a P-type transistor, then the active level of the signal of the first pull-down node PD1 is a low level, and the inactive level of the signal of the first pull-down node PD1 is a high level.

[0120] See Figure 14 As shown, the thirteenth transistor T13 is an N-type transistor. When the signal of the first pull-down node PD1 is high, the thirteenth transistor T13 is turned on, and the signal of the first reference signal terminal VGL1 is provided to the setting port Out_C(n) of the shift register unit of this stage through the thirteenth transistor T13.

[0121] See Figure 14 As shown, the control terminal of the fourteenth transistor T14 is coupled to the first pull-down node PD1, the first terminal of the fourteenth transistor T14 is coupled to the drive output terminal G(n), and the second terminal of the fourteenth transistor T14 is coupled to the second reference signal terminal VGL2.

[0122] First, it should be noted that the absolute value of the signal at the second reference signal terminal VGL2 is greater than the absolute value of the signal at the first reference signal terminal VGL1. Typically, both the signals at the first reference signal terminal VGL1 and the second reference signal terminal VGL2 are negative potentials. The level of the signal at the second reference signal terminal VGL2 is more negative than that at the first reference signal terminal VGL1. Therefore, when the signal at the second reference signal terminal VGL2 is provided to the drive output terminal G(n), the invalid level of the scan signal can be maintained at a low level, thereby effectively suppressing the influence of noise, interference, and other factors on the scan signal.

[0123] For example, the fourteenth transistor T14 can be turned on under the control of the active level of the first pull-down node PD1, and can be turned off under the control of the inactive level of the first pull-down node PD1. For example, if the fourteenth transistor T14 is set as an N-type transistor, then the active level of the signal of the first pull-down node PD1 is a high level, and the inactive level of the signal of the first pull-down node PD1 is a low level. Alternatively, if the fourteenth transistor T14 is set as a P-type transistor, then the active level of the signal of the first pull-down node PD1 is a low level, and the inactive level of the signal of the first pull-down node PD1 is a high level.

[0124] See Figure 14 As shown, the fourteenth transistor T14 is an N-type transistor. When the signal of the first pull-down node PD1 is high, the fourteenth transistor T14 is turned on, and the signal of the second reference signal terminal VGL2 is provided to the drive output terminal G(n) through the fourteenth transistor T14.

[0125] In this embodiment of the present disclosure, in order to effectively control the potential of the pull-down node, two pull-down nodes are provided in each stage of the shift register unit, namely the first pull-down node PD1 and the second pull-down node PD2.

[0126] The aforementioned second node control sub-circuit 1042 is primarily used to control the potential of the first pull-down node PD1. (See also...) Figure 14 As shown, the ninth transistor T9 can set the first pull-down node PD1 under the action of the first power supply terminal VDDO; the tenth transistor T10 can reset the first pull-down node PD1 under the action of the setting port Out_C(nk) of the nth stage shift register unit; the eleventh transistor T11 can reset the first pull-down node PD1 using the first reference signal terminal VGL1 under the action of the first pull-up node PU1; the twelfth transistor T12 can reset the first pull-up node PU1 using the first reference signal terminal VGL1 under the action of the first pull-down node PD1; the thirteenth transistor T13 can provide the signal of the first reference signal terminal VGL1 to the setting port Out_C(n) of the nth stage shift register unit under the action of the first pull-down node PD1; and the fourteenth transistor T14 can provide the signal of the second reference signal terminal VGL2 to the drive output terminal G(n) of the nth stage shift register unit under the action of the first pull-down node PD1.

[0127] The aforementioned third node control sub-circuit 1043 is configured to control the signal of the second pull-down node PD2 in response to the signals of the second power supply terminal VDDE and the setting port Out_C(nk) of the nk-th stage shift register unit.

[0128] During implementation, the third node control sub-circuit 1043 can control the signal of the second pull-down node PD2 to be either valid or invalid after receiving the signals from the second power supply terminal VDDE and the setting port Out_C(nk) of the nk-th stage shift register unit.

[0129] See Figure 14 As shown, the third node control sub-circuit 1043 includes: the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, and the twentieth transistor T20.

[0130] The aforementioned third node control sub-circuit 1043 is primarily used to control the potential of the second pull-down node PD2. (See also...) Figure 14 As shown, the fifteenth transistor T15 can set the second pull-down node PD2 under the action of the second power supply terminal VDDE. The sixteenth transistor T16 can reset the second pull-down node PD2 using the first reference signal terminal VGL1 under the action of the setting port Out_C(nk) of the nth stage shift register unit. The seventeenth transistor T17 can reset the second pull-down node PD2 using the first reference signal terminal VGL1 under the action of the first pull-up node PU1. The eighteenth transistor T18 can reset the first pull-up node PU1 using the first reference signal terminal VGL1 under the action of the second pull-down node PD2. The nineteenth transistor T19 can provide the signal of the first reference signal terminal VGL1 to the setting port Out_C(n) of the nth stage shift register unit under the action of the second pull-down node PD2. The twentieth transistor T20 can provide the signal of the second reference signal terminal VGL2 to the drive output terminal G(n) of the nth stage shift register unit under the action of the second pull-down node PD2.

[0131] The above-mentioned second node control sub-circuit 1042 and third node control sub-circuit 1043 enable effective control of the first pull-down node PD1 and the second pull-down node PD2, effectively avoiding the influence of noise interference on the potential of the first pull-down node PD1 and the second pull-down node PD2, thereby making the signal output by the drive output terminal G(n) of the nth stage shift register unit more stable.

[0132] The control terminal of the fifteenth transistor T15 is coupled to the second power supply terminal VDDE, the first terminal of the fifteenth transistor T15 is coupled to the second power supply terminal VDDE, and the second terminal of the fifteenth transistor T15 is coupled to the second pull-down node PD2.

[0133] For example, the fifteenth transistor T15 can be turned on under the control of the active level of the second power supply terminal VDDE, and can be turned off under the control of the inactive level of the second power supply terminal VDDE. For example, if the fifteenth transistor T15 is set as an N-type transistor, then the active level of the signal at the second power supply terminal VDDE is a high level, and the inactive level of the signal at the second power supply terminal VDDE is a low level. Alternatively, if the fifteenth transistor T15 is set as a P-type transistor, then the active level of the signal at the second power supply terminal VDDE is a low level, and the inactive level of the signal at the second power supply terminal VDDE is a high level.

[0134] See Figure 14 As shown, the fifteenth transistor T15 is an N-type transistor. When the signal at the second power supply terminal VDDE is high, the fifteenth transistor T15 is turned on, and the signal at the second power supply terminal VDDE is provided to the second pull-down node PD2 through the fifteenth transistor T15.

[0135] It should be added that, in the embodiments of this application, the signal of the second power supply terminal VDDE and the signal of the first power supply terminal VDDO are generally equal in magnitude and have the same phase. For ease of layout and routing, shift register units of different levels are typically arranged in odd-numbered rows and even-numbered rows. For example, the signal of the second power supply terminal VDDE can be used to provide voltage to the shift register units of each level in the odd-numbered rows, and the signal of the first power supply terminal VDDO can be used to provide voltage to the shift register units of each level in the even-numbered rows. Alternatively, the signal of the second power supply terminal VDDE can be used to provide voltage to the shift register units of each level in the even-numbered rows, and the signal of the first power supply terminal VDDO can be used to provide voltage to the shift register units of each level in the odd-numbered rows.

[0136] See Figure 14 As shown, the control terminal of the sixteenth transistor T16 is coupled to the setting port Out_C(nk) of the nk-th stage shift register unit, the first terminal of the sixteenth transistor T16 is coupled to the second pull-down node PD2, and the second terminal of the sixteenth transistor T16 is coupled to the first reference signal terminal VGL1.

[0137] For example, the sixteenth transistor T16 can be turned on under the control of the active level of the setting port Out_C(nk) of the nk-th shift register unit, and can be turned off under the control of the inactive level of the setting port Out_C(nk) of the nk-th shift register unit. For example, if the sixteenth transistor T16 is configured as an N-type transistor, then the active level of the signal at the setting port Out_C(nk) of the nk-th shift register unit is high, and the inactive level of the signal at the setting port Out_C(nk) of the nk-th shift register unit is low. Alternatively, if the sixteenth transistor T16 is configured as a P-type transistor, then the active level of the signal at the setting port Out_C(nk) of the nk-th shift register unit is low, and the inactive level of the signal at the setting port Out_C(nk) of the nk-th shift register unit is high.

[0138] See Figure 14 As shown, the sixteenth transistor T16 is an N-type transistor. When the signal of the setting port Out_C(nk) of the nk-th stage shift register unit is high, the sixteenth transistor T16 is turned on, and the signal of the first reference signal terminal VGL1 is provided to the second pull-down node PD2 through the sixteenth transistor T16.

[0139] See Figure 14 As shown, the control terminal of the seventeenth transistor T17 is coupled to the first pull-up node PU1, the first terminal of the seventeenth transistor T17 is coupled to the second pull-down node PD2, and the second terminal of the seventeenth transistor T17 is coupled to the first reference signal terminal VGL1.

[0140] For example, the seventeenth transistor T17 can be turned on under the control of the effective level of the first pull-up node PU1, and can be turned off under the control of the ineffective level of the first pull-up node PU1. For example, if the seventeenth transistor T17 is set as an N-type transistor, then the effective level of the signal of the first pull-up node PU1 is a high level, and the ineffective level of the signal of the first pull-up node PU1 is a low level. Alternatively, if the seventeenth transistor T17 is set as a P-type transistor, then the effective level of the signal of the first pull-up node PU1 is a low level, and the ineffective level of the signal of the first pull-up node PU1 is a high level.

[0141] See Figure 14 As shown, the seventeenth transistor T17 is an N-type transistor. When the signal of the first pull-up node PU1 is high, the seventeenth transistor T17 is turned on, and the signal of the first reference signal terminal VGL1 is provided to the second pull-down node PD2 through the seventeenth transistor T17.

[0142] See Figure 14As shown, the control terminal of the eighteenth transistor T18 is coupled to the second pull-down node PD2, the first terminal of the eighteenth transistor T18 is coupled to the first pull-up node PU1, and the second terminal of the eighteenth transistor T18 is coupled to the first reference signal terminal VGL1.

[0143] For example, the eighteenth transistor T18 can be turned on under the control of the active level of the second pull-down node PD2, and can be turned off under the control of the inactive level of the second pull-down node PD2. For example, if the eighteenth transistor T18 is set as an N-type transistor, then the active level of the signal of the second pull-down node PD2 is a high level, and the inactive level of the signal of the second pull-down node PD2 is a low level. Alternatively, if the eighteenth transistor T18 is set as a P-type transistor, then the active level of the signal of the second pull-down node PD2 is a low level, and the inactive level of the signal of the second pull-down node PD2 is a high level.

[0144] See Figure 14 As shown, the eighteenth transistor T18 is an N-type transistor. When the signal of the second pull-down node PD2 is high, the eighteenth transistor T18 is turned on, and the signal of the first reference signal terminal VGL1 is provided to the first pull-up node PU1 through the eighteenth transistor T18.

[0145] See Figure 14 As shown, the control terminal of the nineteenth transistor T19 is coupled to the second pull-down node PD2, the first terminal of the nineteenth transistor T19 is coupled to the setting port Out_C(n) of the shift register unit of this stage, and the second terminal of the nineteenth transistor T19 is coupled to the first reference signal terminal VGL1.

[0146] For example, the nineteenth transistor T19 can be turned on under the control of the active level of the second pull-down node PD2, and can be turned off under the control of the inactive level of the second pull-down node PD2. For example, if the nineteenth transistor T19 is set as an N-type transistor, then the active level of the signal of the second pull-down node PD2 is a high level, and the inactive level of the signal of the second pull-down node PD2 is a low level. Alternatively, if the nineteenth transistor T19 is set as a P-type transistor, then the active level of the signal of the second pull-down node PD2 is a low level, and the inactive level of the signal of the second pull-down node PD2 is a high level.

[0147] See Figure 14 As shown, the nineteenth transistor T19 is an N-type transistor. When the signal of the second pull-down node PD2 is high, the nineteenth transistor T19 is turned on, and the signal of the first reference signal terminal VGL1 is provided to the setting port Out_C(n) of the shift register unit of this stage through the nineteenth transistor T19.

[0148] See Figure 14As shown, the control terminal of the twentieth transistor T20 is coupled to the second pull-down node PD2, the first terminal of the twentieth transistor T20 is coupled to the drive output terminal G(n), and the second terminal of the twentieth transistor T20 is coupled to the second reference signal terminal VGL2.

[0149] For example, the twentieth transistor T20 can be turned on under the control of the active level of the second pull-down node PD2, and can be turned off under the control of the inactive level of the second pull-down node PD2. For example, if the twentieth transistor T20 is set to an N-type transistor, then the active level of the signal of the second pull-down node PD2 is a high level, and the inactive level of the signal of the second pull-down node PD2 is a low level. Alternatively, if the twentieth transistor T20 is set to a P-type transistor, then the active level of the signal of the second pull-down node PD2 is a low level, and the inactive level of the signal of the second pull-down node PD2 is a high level.

[0150] See Figure 14 As shown, the twentieth transistor T20 is an N-type transistor. When the signal of the second pull-down node PD2 is high, the twentieth transistor T20 is turned on, and the signal of the second reference signal terminal VGL2 is provided to the drive output terminal G(n) through the twentieth transistor T20.

[0151] See Figure 13 and Figure 14 As shown, the output circuit 105 is configured to provide the clock signal terminal CKm to the drive output terminal G(n) in response to the signal of the first pull-up node PU1; and to provide the signal of the second reference signal terminal VGL2 to the drive output terminal G(n) in response to the signal of the drive output terminal G(n+b) of the (n+b)th stage shift register unit.

[0152] During implementation, when the signal of the first pull-up node PU1 is at an active level, the output circuit is turned on, and the clock signal terminal CKm is provided to the drive output terminal G(n) through the turned-on output circuit. Also, when the signal of the drive output terminal G(n+b) of the (n+b)th stage shift register unit is at an active level, the output circuit is turned on, and the signal of the second reference signal terminal VGL2 is provided to the drive output terminal G(n) through the turned-on output circuit.

[0153] See Figure 14 As shown, the output circuit includes: the twenty-first transistor T21 and the twenty-second transistor T22.

[0154] The control terminal of the twenty-first transistor T21 is coupled to the first pull-up node PU1, the first terminal of the twenty-first transistor T21 is coupled to the clock signal terminal CKm, and the second terminal of the twenty-first transistor T21 is coupled to the drive output terminal G(n).

[0155] For example, the twenty-first transistor T21 can be turned on under the control of the effective level of the first pull-up node PU1, and can be turned off under the control of the ineffective level of the first pull-up node PU1. For example, if the twenty-first transistor T21 is set as an N-type transistor, then the effective level of the signal of the first pull-up node PU1 is a high level, and the ineffective level of the signal of the first pull-up node PU1 is a low level. Alternatively, if the twenty-first transistor T21 is set as a P-type transistor, then the effective level of the signal of the first pull-up node PU1 is a low level, and the ineffective level of the signal of the first pull-up node PU1 is a high level.

[0156] See Figure 14 As shown, the twenty-first transistor T21 is an N-type transistor. When the signal of the first pull-up node PU1 is high, the twenty-first transistor T21 is turned on, and the signal of the clock signal terminal CKm is provided to the drive output terminal G(n) through the twenty-first transistor T21.

[0157] See Figure 14 As shown, the control terminal of the twenty-second transistor T22 is coupled to the drive output terminal G(n+b) of the n+b-th stage shift register unit, the first terminal of the twenty-second transistor T22 is coupled to the drive output terminal G(n), and the second terminal of the twenty-second transistor T22 is coupled to the second reference signal terminal VGL2.

[0158] For example, the twenty-second transistor T22 can be turned on under the control of the effective level of the drive output terminal G(n+b) of the (n+b)-th stage shift register unit, and can be turned off under the control of the ineffective level of the drive output terminal G(n+b) of the (n+b)-th stage shift register unit. For example, if the twenty-second transistor T22 is configured as an N-type transistor, then the effective level of the signal at the drive output terminal G(n+b) of the (n+b)-th stage shift register unit is a high level, and the ineffective level of the signal at the drive output terminal G(n+b) of the (n+b)-th stage shift register unit is a low level. Alternatively, if the twenty-second transistor T22 is configured as a P-type transistor, then the effective level of the signal at the drive output terminal G(n+b) of the (n+b)-th stage shift register unit is a low level, and the ineffective level of the signal at the drive output terminal G(n+b) of the (n+b)-th stage shift register unit is a high level.

[0159] See Figure 14 As shown, the twenty-second transistor T22 is an N-type transistor. When the signal at the drive output terminal G(n+b) of the n+b-th stage shift register unit is high, the twenty-second transistor T22 is turned on, and the signal at the second reference signal terminal VGL2 is provided to the drive output terminal G(n) through the twenty-second transistor T22.

[0160] See Figure 14As shown, the shift register 10 also includes a third capacitor C3, which is coupled between the first pull-up node PU1 and the drive output terminal G(n) and is configured to stabilize the level of the first pull-up node PU1.

[0161] It should be noted that the capacitance of the third capacitor C3 is less than that of the first capacitor C1.

[0162] In this embodiment, to effectively compensate for the level of the first pull-up node PU1, the capacitance of the third capacitor C3 is smaller than that of the first capacitor C1. That is, a larger first capacitor C1 is used as the first node compensation sub-circuit 201. In this way, when the clock signal terminal CKm changes from an effective level to an ineffective level, the setting port Out_C(n+f) of the n+f-th stage shift register unit or the clock signal terminal CKg+y input of the g+y-th stage shift register unit can be coupled to the first pull-up node PU1 through the first capacitor C1. Thus, even if the potential of the first pull-up node PU1 drops under the action of the third capacitor C3, the compensation effect of the larger first capacitor C1 can keep the first pull-up node PU1 in a stable high-level state, thereby enabling the twenty-first transistor T21 to be fully turned on. The signal change of the clock signal terminal CKm can make the scanning signal quickly appear a falling edge, that is, the falling edge of the scanning signal is steeper, thereby effectively reducing the driving power consumption.

[0163] The capacitance of the second capacitor C2 is less than or equal to the capacitance of the first capacitor C1.

[0164] Furthermore, in this embodiment, the function of the second capacitor C2 is similar to that of the third capacitor C3. That is, the second capacitor C2 is coupled to the second pull-up node PU2, and the level of the second pull-up node PU2 will be raised under the action of the second capacitor C2. The third capacitor C3 is coupled to the first pull-up node PU1, and the level of the first pull-up node PU1 will be raised under the action of the third capacitor C3. Based on this, the capacitance value of the second capacitor C2 is less than or equal to the capacitance value of the first capacitor C1.

[0165] The following section describes the circuit connection. Figure 15 Timing diagram Figure 16 The working process of the shift register unit in the embodiments of this application is described in detail.

[0166] In this context, 0 represents a low signal level, and 1 represents a high signal level.

[0167] Timing T1 stage: Clock signal CKm=1, setting port Out_C(n-4) of the (n-4)th stage shift register unit=1, setting port Out_C(n-2) of the (n-2)th stage shift register unit=0, setting port Out_C(n) of the nth stage shift register unit=0, setting port Out_C(n) of the (n+2)th stage shift register unit=0, setting port Out_C(n+3) of the (n+3)th stage shift register unit=0, drive output G(n) of the nth stage shift register unit=0, first pull-up node PU1=first level.

[0168] When the signal at the setting port of the (n-4)th stage shift register unit is high, the fifth transistor T5 is turned on. The signal at the setting port of the (n-4)th stage shift register unit is provided to the first pull-up node PU1 through the turned-on fifth transistor T5, that is, the first pull-up node PU1 is raised from the initial level (assuming it is 0V) to the first level.

[0169] Timing T2 stage: Clock signal CKm=0, setting port Out_C(n-4) of the (n-4)th stage shift register unit=0, setting port Out_C(n-2) of the (n-2)th stage shift register unit=1, setting port Out_C(n) of the nth stage shift register unit=0, setting port Out_C(n+2) of the (n+2)th stage shift register unit=0, setting port Out_C(n+3) of the (n+3)th stage shift register unit=0, drive output G(n) of the nth stage shift register unit=0, first pull-up node PU1=second level.

[0170] When the signal at the setting port of the (n-2)th stage shift register unit is high, the first transistor T1 is turned on. The high-level signal at the setting port of the (n-2)th stage shift register unit is provided to the second pull-up node PU2 through the turned-on first transistor T1. The high-level signal is coupled to the first pull-up node PU1 through the second capacitor C2, and the level of the first pull-up node PU1 is raised from the first level to the second level.

[0171] Timing T3 stage: Clock signal CKm=1, setting port Out_C(n-4) of the (n-4)th stage shift register unit=0, setting port Out_C(n-2) of the (n-2)th stage shift register unit=0, setting port Out_C(n) of the nth stage shift register unit=1, setting port Out_C(n+2) of the (n+2)th stage shift register unit=0, setting port Out_C(n+3) of the (n+3)th stage shift register unit=0, drive output G(n) of the nth stage shift register unit=1, first pull-up node PU1=third level.

[0172] After the level of the first pull-up node PU1 is raised to the second level, the twenty-first transistor T21 is fully turned on. The high level of the clock signal terminal CKm is provided to the drive output terminal G(n) through the turned-on twenty-first transistor T21, which is the effective level of the output scan signal. At the same time, due to the coupling effect of the third capacitor C3, the level of the first pull-up node PU1 continues to be raised from the second level to the third level.

[0173] Timing T4 stage: Clock signal CKm=0, setting port Out_C(n-4) of the (n-4)th stage shift register unit=0, setting port Out_C(n-2) of the (n-2)th stage shift register unit=0, setting port Out_C(n) of the nth stage shift register unit=0, setting port Out_C(n) of the (n+2)th stage shift register unit=1, setting port Out_C(n+3) of the (n+3)th stage shift register unit changes from 0 to 1, drive output G(n) of the nth stage shift register unit=0, first pull-up node PU1= jumps from the third level to the fourth level, and then jumps from the fourth level back to zero.

[0174] When the clock signal CKm transitions from high to low, the level of the first pull-up node PU1 decreases from the third level to the fourth level under the coupling effect of the third capacitor C3. However, in this embodiment, due to the setting of the first capacitor C1, the high-level signal of the setting port of the (n+2)th stage shift register unit can be provided to the first pull-up node PU1 through the coupling effect of the first capacitor C1, thereby effectively reducing the time for the first pull-up node PU1 to transition from the third level to the fourth level. Furthermore, the voltage value of the fourth level is relatively high in this case, and the twenty-first transistor T21 can remain on under the action of the fourth level, causing the scan signal to quickly produce a relatively steep falling edge, thereby effectively reducing the driving power consumption.

[0175] Based on the same inventive concept, this disclosure provides a gate driving circuit, see reference. Figure 17 As shown, it includes: multiple cascaded shift register units as described above.

[0176] The input signal terminal of the first-stage shift register unit SR(1) is configured to be coupled to the frame start signal terminal STV0.

[0177] During implementation, the frame start signal terminal STV0 inputs a signal to the input signal terminal Out_C(1) of the first-stage shift register unit SR(1), and the entire gate drive circuit starts working. In this embodiment, the drive output terminal G(n) of each stage shift register unit outputs a scan signal to the gate line.

[0178] For example, see Figure 17As shown, the frame start signal terminal STV0 inputs a signal to the input signal terminal Out_C(1) of the first-stage shift register unit SR(1), thereby enabling the entire gate drive circuit to start working.

[0179] In each pair of adjacent shift register units, the input signal terminal of the nth-stage shift register unit is configured to be coupled to the setting port Out_C(nk) of the nk-stage shift register unit.

[0180] During implementation, when the setting port Out_C(nk) of the nk-th stage shift register unit SR(nk) outputs a signal, the signal output by the setting port is provided to the input signal terminal of the n-th stage shift register unit SR(n), that is, the signal output by the setting port is used as the input signal of the n-th stage shift register unit SR(n).

[0181] For example, see Figure 17 As shown, in order to realize the cascading relationship between shift register units at each level, the signal output from the setting port Out_C(n-4-k) of the (n-4-k)th shift register unit SR(n-4) is used as the input signal of the (n-4)th shift register unit SR(n-4).

[0182] For example, see Figure 17 As shown, the signal output from the setting port Out_C(n-2-k) of the (n-2-k)th stage shift register unit SR(n-2) is used as the input signal of the (n-2)th stage shift register unit SR(n-2).

[0183] For example, see Figure 17 As shown, the signal output from the setting port Out_C(n+2-k) of the (n+2-k)th stage shift register unit SR(n+2) is used as the input signal of the (n+2)th stage shift register unit SR(n+2).

[0184] For example, see Figure 17 As shown, the signal output from the setting port Out_C(n+3-k) of the (n+3-k)th stage shift register unit SR(n+3) is used as the input signal of the (n+3)th stage shift register unit SR(n+3).

[0185] For example, see Figure 17 As shown, the signal output from the setting port Out_C(n+4-k) of the (n+4-k)th stage shift register unit SR(n+4) is used as the input signal of the (n+4)th stage shift register unit SR(n+4).

[0186] In each pair of adjacent shift register units, the setting port Out_C(n+t) of the (n+t)th shift register unit is configured to be coupled to the reset terminal of the nth shift register unit, where t is a positive integer.

[0187] During implementation, when the setting port Out_C(n+t) of the (n+t)th stage shift register unit outputs a signal, the signal output by the setting port is provided to the reset terminal of the nth stage shift register unit, that is, the signal output by the setting port serves as the reset signal of the nth stage shift register unit.

[0188] In this embodiment of the disclosure, it is assumed that the value of t is 3.

[0189] For example, see Figure 17 As shown, the setting port Out_C(4) of the fourth-level shift register unit SR(4) is configured to be coupled to the local reset terminal of the first-level shift register unit SR(1), that is, the setting port Out_C(4) of the fourth-level shift register unit SR(4) provides a reset signal to the local reset terminal Rst(1) of the first-level shift register unit SR(1).

[0190] For example, see Figure 17 As shown, the setting port Out_C(n-1) of the (n-1)th stage shift register unit SR(n-1) is configured to be coupled to the reset terminal of the (n-4)th stage shift register unit SR(n-4), that is, the setting port Out_C(n-1) of the (n-1)th stage shift register unit SR(n-1) provides a reset signal to the reset terminal Rst(n-4) of the (n-4)th stage shift register unit SR(n-4).

[0191] For example, see Figure 17 As shown, the setting port Out_C(n+1) of the (n+1)th stage shift register unit SR(n+1) is configured to be coupled to the reset terminal of the (n-2)th stage shift register unit SR(n-2), that is, the setting port Out_C(n+1) of the (n+1)th stage shift register unit SR(n+1) provides a reset signal to the reset terminal Rst(n-2) of the (n-2)th stage shift register unit SR(n-2).

[0192] For example, see Figure 17 As shown, the setting port Out_C(n+5) of the (n+5)th stage shift register unit SR(n+5) is configured to be coupled to the reset terminal of the (n+2)th stage shift register unit SR(n+2), that is, the setting port Out_C(n+5) of the (n+5)th stage shift register unit SR(n+5) provides a reset signal to the reset terminal Rst(n+2) of the (n+2)th stage shift register unit SR(n+2).

[0193] For example, see Figure 17 As shown, the setting port Out_C(n+6) of the (n+6)th shift register unit SR(n+6) is configured to be coupled to the reset terminal of the (n+3)th shift register unit SR(n+3), that is, the setting port Out_C(n+6) of the (n+6)th shift register unit SR(n+6) provides a reset signal to the reset terminal Rst(n+3) of the (n+3)th shift register unit SR(n+3).

[0194] For example, see Figure 17 As shown, the setting port Out_C(n+7) of the (n+7)th shift register unit SR(n+7) is configured to be coupled to the reset terminal of the (n+4)th shift register unit SR(n+4), that is, the setting port Out_C(n+7) of the (n+7)th shift register unit SR(n+7) provides a reset signal to the reset terminal Rst(n+4) of the (n+4)th shift register unit SR(n+4).

[0195] It should also be noted that, in this embodiment of the disclosure, a first power supply terminal VDDO and a second power supply terminal VDDE are provided to facilitate the separate control of the first pull-down node PD1 and the second pull-down node PD2. Each shift register unit is electrically connected to the aforementioned first power supply terminal VDDO and second power supply terminal VDDE.

[0196] Combination Figure 15 It can be seen that in each shift register unit, the first power supply terminal VDDO, in conjunction with the ninth transistor T9, sets the first pull-down node PD1. The second power supply terminal VDDE, in conjunction with the fifteenth transistor T15, sets the second pull-down node PD2.

[0197] Furthermore, in the cascading relationship of the shift register units at each level in the embodiments of this disclosure, the control terminal of the twenty-second transistor T22 of the nth-level shift register unit SR(n) is electrically connected to the drive output terminal G(n+b) of the (n+b)th-level shift register unit SR(n+b), combined with Figure 15 As can be seen, for example, the value of b above is 2, that is, the turn-on and turn-off of the twenty-second transistor T22 is controlled by the drive output terminal G(n+2) of the (n+2)th stage shift register unit SR(n+2), i.e., see [reference]. Figure 15 As shown, when the signal at the drive output terminal G(n+2) is high, the 22nd transistor T22 is turned on, and the signal at the second reference signal terminal VGL2 is provided to the drive output terminal G(n) through the turned-on 22nd transistor T22. That is, the low level of the second reference signal terminal VGL2 makes the drive output terminal G(n) output a constant low level signal.

[0198] In addition, combined Figure 15 As can be seen, in the cascade relationship of the shift register units at each level in the embodiments of this disclosure, the control terminals of the tenth transistor T10 and the sixteenth transistor T16 of the nth shift register unit SR(n) are electrically connected to the setting port Out_C(n-4) of the (n-4)th shift register unit SR(n-4). That is, the signal of the setting port Out_C(n-4) controls whether the tenth transistor T10 and the sixteenth transistor T16 are turned on or off. Of course, in other embodiments, the control terminals of the tenth transistor T10 and the sixteenth transistor T16 can also be connected to other signal ports, which will not be described in detail here.

[0199] Based on the same inventive concept, this disclosure provides a display device including the gate driving circuit of any of the above.

[0200] In this embodiment of the invention, the display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention.

[0201] Based on the same inventive concept, this disclosure provides a driving method for a shift register unit, see below. Figure 18 As shown, it includes: Step 201: Shift register 10 outputs a scan signal through the drive output terminal G(n).

[0202] During implementation, when the level of the first pull-up node PU1 in the shift register 10 is active, the transistor used to drive the output, namely the twenty-first transistor T21, is turned on. The clock signal terminal CKm is provided to the drive output terminal G(n) through the turned-on twenty-first transistor T21, and the drive output terminal G(n) outputs a scan signal.

[0203] Step 202: The node compensation circuit 20 stabilizes the level of the first pull-up node PU1 according to the clock signal terminal CKm, and reduces the fall time of the scan signal output by the drive output terminal G(n) of the shift register 10.

[0204] During implementation, when the clock signal terminal CKm transitions from an active level to an inactive level, the node compensation circuit 20 can stabilize the level of the first pull-up node PU1 at a higher value. In this way, the transistor used to drive the output, namely the twenty-first transistor T21, can remain fully turned on, so that the transition of the clock signal terminal CKm from an active level to an inactive level can be quickly output through the transistor driving the output. That is, the falling time of the scan signal output by the control drive output terminal G(n) is shortened, and the falling edge of the scan signal is steeper, which helps to reduce power consumption.

[0205] In summary, the present disclosure provides a shift register unit, a display device, and a driving method. The shift register unit includes a shift register and a node compensation circuit. The node compensation circuit is coupled to a first pull-up node of the shift register. During implementation, the node compensation circuit can stabilize the level of the first pull-up node according to the clock signal. That is, by compensating for the level drop at the first pull-up node and increasing the level at the first pull-up node in advance through multiple boosts, the impact of the level drop at the first pull-up node on the scan signal output from the drive output terminal of the shift register is reduced. This reduces the drop duration of the scan signal output from the drive output terminal of the shift register, thereby reducing the power consumption of the scan signal and improving the display effect.

[0206] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program product systems. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product system implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0207] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program product systems according to this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0208] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0209] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0210] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A shift register unit, characterized in that, include: Shift register; A node compensation circuit is coupled to the first pull-up node of the shift register. The node compensation circuit is configured to stabilize the level of the first pull-up node according to the signal at the clock signal terminal, thereby reducing the fall time of the scan signal output from the drive output terminal of the shift register.

2. The shift register unit as described in claim 1, characterized in that, The node compensation circuit includes a first node compensation sub-circuit and / or a second node compensation circuit; The first node compensation sub-circuit is coupled to the first pull-up node and is configured to provide the signal of the setting port of the n+f-th stage shift register unit or the clock signal input of the g+y-th stage shift register unit to the first pull-up node, wherein n, f, g and y are all positive integers; The second node compensation sub-circuit is configured to provide the signal of the setting port of the nh-th stage shift register unit to the first pull-up node in response to the signal of the setting port of the nh-th stage shift register unit; to perform a stage-specific reset on the first pull-up node in response to the signal of the setting port of the nk-th stage shift register unit; and to perform a frame-specific reset on the first pull-up node in response to the signal of the frame reset signal terminal, wherein h and k are both positive integers.

3. The shift register unit as described in claim 2, characterized in that, The first node compensation sub-circuit includes: a first capacitor; The first terminal of the first capacitor is coupled to the setting port of the (n+f)th stage shift register unit or the clock signal input of the (g+y)th stage shift register unit, and the second terminal of the first capacitor is coupled to the first pull-up node, wherein m is a positive integer.

4. The shift register unit as described in claim 2, characterized in that, The second node compensation sub-circuit includes: a first transistor, a second capacitor, a second transistor, a third transistor, and a fourth transistor; The control terminal of the first transistor is coupled to the setting port of the nh-th level shift register unit, the first terminal of the first transistor is coupled to the setting port of the nh-th level shift register unit, and the second terminal of the first transistor is coupled to the second pull-up node. The first end of the second capacitor is coupled to the second pull-up node, and the second end of the second capacitor is coupled to the first pull-up node; The control terminal of the second transistor is coupled to the setting port of the nk-th stage shift register unit, the first terminal of the second transistor is coupled to the second pull-up node, and the second terminal of the second transistor is coupled to the first reference signal terminal. The control terminal of the third transistor is coupled to the setting port of the (n+t)th stage shift register unit, the first terminal of the third transistor is coupled to the second pull-up node, and the second terminal of the third transistor is coupled to the first reference signal terminal, wherein t is a positive integer; The control terminal of the fourth transistor is coupled to the frame reset signal terminal, the first terminal of the fourth transistor is coupled to the second pull-up node, and the second terminal of the fourth transistor is coupled to the first reference signal terminal.

5. The shift register unit as described in any one of claims 1-4, characterized in that, The shift register includes: The input circuit is configured to provide the signal of the setting port of the nk-th stage shift register unit to the first pull-up node in response to the signal of the setting port of the nk-th stage shift register unit. The reset circuit at this stage is configured to provide the signal at the first reference signal terminal to the first pull-up node in response to the signal at the setting port of the (n+t)th stage shift register unit. The frame reset circuit is configured to provide the signal of the first reference signal terminal to the first pull-up node in response to the signal of the frame reset signal terminal. The node control circuit is configured to control the signals of the first pull-up node, the first pull-down node, and the second pull-down node; The output circuit is configured to provide a clock signal to the drive output terminal in response to a signal from the first pull-up node; and to provide a second reference signal to the drive output terminal in response to a signal from the drive output terminal of the (n+b)th stage shift register unit, wherein b is a positive integer. The third capacitor, coupled between the first pull-up node and the drive output terminal, is configured to stabilize the level of the first pull-up node.

6. The shift register unit as described in claim 5, characterized in that, The capacitance of the third capacitor is less than that of the first capacitor; The capacitance of the second capacitor is less than or equal to the capacitance of the first capacitor.

7. The shift register unit as described in claim 5, characterized in that, The absolute value of the signal at the second reference signal terminal is greater than the absolute value of the signal at the first reference signal terminal.

8. The shift register unit as described in claim 6, characterized in that, The input circuit includes: a fifth transistor; The control terminal of the fifth transistor is coupled to the setting port of the nth stage shift register unit, the first terminal of the fifth transistor is coupled to the setting port of the nth stage shift register unit, and the second terminal of the fifth transistor is coupled to the first pull-up node.

9. The shift register unit as described in claim 6, characterized in that, The reset circuit at this level includes: a sixth transistor; The control terminal of the sixth transistor is coupled to the setting port of the (n+t)th stage shift register unit, the first terminal of the sixth transistor is coupled to the first pull-up node, and the second terminal of the sixth transistor is coupled to the first reference signal terminal.

10. The shift register unit as described in claim 6, characterized in that, The current frame reset circuit includes: a seventh transistor; The control terminal of the seventh transistor is coupled to the frame reset signal terminal, the first terminal of the seventh transistor is coupled to the first pull-up node, and the second terminal of the seventh transistor is coupled to the first reference signal terminal.

11. The shift register unit as described in claim 6, characterized in that, The node control circuit includes: The first node control sub-circuit is configured to respond to the signal of the first pull-up node by providing the signal of the clock signal terminal to the setting port of the shift register unit at this stage. The second node control sub-circuit is configured to control the signal of the first pull-down node in response to the signal of the first power supply terminal and the setting port of the nk-th stage shift register unit. The third node control sub-circuit is configured to control the signal of the second pull-down node in response to signals from the second power supply terminal and the setting port of the nk-th stage shift register unit.

12. The shift register unit as described in claim 11, characterized in that, The first node control sub-circuit includes: an eighth transistor; The control terminal of the eighth transistor is coupled to the first pull-up node, the first terminal of the eighth transistor is coupled to the clock signal terminal, and the second terminal of the eighth transistor is coupled to the setting port of the shift register unit of this stage.

13. The shift register unit as described in claim 11, characterized in that, The second node control sub-circuit includes: the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the fourteenth transistor; The control terminal of the ninth transistor is coupled to the first power supply terminal, the first terminal of the ninth transistor is coupled to the first power supply terminal, and the second terminal of the ninth transistor is coupled to the first pull-down node. The control terminal of the tenth transistor is coupled to the setting port of the nk-th stage shift register unit, the first terminal of the tenth transistor is coupled to the first pull-down node, and the second terminal of the tenth transistor is coupled to the first reference signal terminal. The control terminal of the eleventh transistor is coupled to the first pull-up node, the first terminal of the eleventh transistor is coupled to the first pull-down node, and the second terminal of the eleventh transistor is coupled to the first reference signal terminal. The control terminal of the twelfth transistor is coupled to the first pull-down node, the first terminal of the twelfth transistor is coupled to the first pull-up node, and the second terminal of the twelfth transistor is coupled to the first reference signal terminal. The control terminal of the thirteenth transistor is coupled to the first pull-down node, the first terminal of the thirteenth transistor is coupled to the setting port of the shift register unit of this stage, and the second terminal of the thirteenth transistor is coupled to the first reference signal terminal. The control terminal of the fourteenth transistor is coupled to the first pull-down node, the first terminal of the fourteenth transistor is coupled to the drive output terminal, and the second terminal of the fourteenth transistor is coupled to the second reference signal terminal.

14. The shift register unit as described in claim 11, characterized in that, The third node control sub-circuit includes: the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, and the twentieth transistor; The control terminal of the fifteenth transistor is coupled to the second power supply terminal, the first terminal of the fifteenth transistor is coupled to the second power supply terminal, and the second terminal of the fifteenth transistor is coupled to the second pull-down node. The control terminal of the sixteenth transistor is coupled to the setting port of the nk-th stage shift register unit, the first terminal of the sixteenth transistor is coupled to the second pull-down node, and the second terminal of the sixteenth transistor is coupled to the first reference signal terminal. The control terminal of the seventeenth transistor is coupled to the first pull-up node, the first terminal of the seventeenth transistor is coupled to the second pull-down node, and the second terminal of the seventeenth transistor is coupled to the first reference signal terminal. The control terminal of the eighteenth transistor is coupled to the second pull-down node, the first terminal of the eighteenth transistor is coupled to the first pull-up node, and the second terminal of the eighteenth transistor is coupled to the first reference signal terminal. The control terminal of the nineteenth transistor is coupled to the second pull-down node, the first terminal of the nineteenth transistor is coupled to the setting port of the shift register unit of this stage, and the second terminal of the nineteenth transistor is coupled to the first reference signal terminal. The control terminal of the twentieth transistor is coupled to the second pull-down node, the first terminal of the twentieth transistor is coupled to the drive output terminal, and the second terminal of the twentieth transistor is coupled to the second reference signal terminal.

15. The shift register unit as described in claim 6, characterized in that, The output circuit includes: a twenty-first transistor and a twenty-second transistor; The control terminal of the 21st transistor is coupled to the first pull-up node, the first terminal of the 21st transistor is coupled to the clock signal terminal, and the second terminal of the 21st transistor is coupled to the drive output terminal. The control terminal of the twelfth transistor is coupled to the drive output terminal of the (n+b)th stage shift register unit, the first terminal of the twelfth transistor is coupled to the drive output terminal, and the second terminal of the twelfth transistor is coupled to the second reference signal terminal.

16. A gate driving circuit, characterized in that, include: Multiple cascaded shift register units as described in any one of claims 1-15; The input signal terminal of the first-stage shift register unit is configured to be coupled to the frame start signal terminal; In each pair of adjacent shift register units, the input signal terminal of the nth-level shift register unit is configured to be coupled to the set port of the nk-level shift register unit; In each pair of adjacent shift register units, the setting port of the shift register unit at stage n+t is configured to be coupled to the reset port of the current stage of the shift register unit n.

17. A display device, characterized in that, Includes the gate drive circuit as described in claim 16.

18. A driving method for a shift register unit as described in any one of claims 1-15, characterized in that, include: The shift register outputs a scan signal through its drive output terminal; The node compensation circuit stabilizes the level of the first pull-up node based on the clock signal, thereby reducing the fall time of the scan signal output from the drive output terminal of the shift register.

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