A gate driving circuit, a gate driving method and a display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit, a gate driving method and a display panel. The gate driving circuit comprises N cascaded gate driving units, and the nth gate driving unit comprises: a pull-up module connected with a driving control node and configured to charge the driving control node in response to an output signal of the nth-i gate driving unit; an output module connected with the driving control node and a clock signal line of a current stage and configured to output a stage transmission signal and a gate driving signal under the action of a driving voltage on the driving control node and the current stage clock signal; and a first local refresh control module connected with a driving output end of the output module and a scan line and configured to, in a local refresh mode, control the driving output end to be electrically connected with the scan line if the current stage is a refresh row, and control the driving output end to be disconnected from the scan line if the current stage is a non-refresh row. The application can reduce the aging speed of the display panel.

Description

Technical Field

[0001] This application belongs to the field of display driving technology, specifically relating to a gate driving circuit, a gate driving method, and a display panel. Background Technology

[0002] Among related technologies, Gate Driver Less (GDL) is a technical solution based on amorphous silicon (a-SiTFT) fabrication that directly integrates the shift register circuit of an external gate driver integrated circuit onto the display panel array substrate. This solution can completely replace a separate gate driver IC, simplifying the display driver architecture through process integration, thereby significantly reducing device procurement and module assembly costs. However, the frequent pixel refresh control by the gate driver IC will accelerate the aging of the display panel and reduce its lifespan.

[0003] Therefore, how to reduce the aging rate of display panels is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit, a gate driver, and a display panel, which solves the problem that frequent pixel refresh control by the gate driver IC will accelerate the aging of the display panel.

[0005] In a first aspect, this application provides a gate driving circuit, the gate driving circuit comprising N cascaded gate driving units, wherein the nth gate driving unit comprises: a pull-up module connected to a drive control node and configured to: charge the drive control node in response to the output signal of the nth gate driving unit; an output module connected to the drive control node and the clock signal line of the current stage and configured to: output a stage transmission signal and a gate driving signal under the action of the drive voltage on the drive control node and the clock signal of the current stage; and a first local refresh control module connected to the drive output terminal of the output module and a scan line and configured to: in local refresh mode, if the current stage is a refresh line, control the drive output terminal to be electrically connected to the scan line; if the current stage is a non-refresh line, control the drive output terminal to be disconnected from the scan line.

[0006] Optionally, the first local scan control module includes: a first transistor; the control terminal of the first transistor is connected to the first local scan control terminal, the first terminal of the first transistor is connected to the drive output terminal of the output module, and the second terminal of the first transistor is connected to the scan line.

[0007] Optionally, the nth-stage gate drive unit further includes a discharge module connected to the first local refresh control module, configured to pull down the output of the first local refresh control module to a low potential if the current stage is a non-refresh row in the local refresh mode.

[0008] Optionally, the discharge module includes: a second transistor; the control terminal of the second transistor is connected to the control terminal of the second brush, the first terminal of the second transistor is connected to the output terminal of the first brush control module, and the second terminal of the second transistor is connected to a low-level terminal.

[0009] Optionally, the first local brush control module includes: at least two second transistors connected in series; the control terminal of each second transistor is connected to the second local brush control terminal, the first terminal of the first second transistor in the at least two series-connected second transistors is connected to the output terminal of the first local brush control module, and the second terminal of the last second transistor in the at least two series-connected second transistors is connected to a low-level terminal.

[0010] Optionally, the first local scan control module comprises a first transistor, a second transistor, a third transistor, and a fourth transistor; the control terminal of the first transistor is connected to the first local scan control terminal, the first terminal of the first transistor is connected to the drive output terminal of the output module and the first terminal of the second transistor, and the second terminal of the first transistor is connected to the scan line, the first terminal of the third transistor, and the control terminal of the fourth transistor, respectively; the control terminal of the second transistor is connected to the second local scan control terminal, and the second terminal of the second transistor is connected to the control terminal of the third transistor and the first terminal of the fourth transistor, respectively; the second terminals of the third transistor and the second terminals of the fourth transistor are connected to a low-level terminal.

[0011] Optionally, the nth-stage gate driving unit further includes: a second local refresh control module, connected to the pull-up module, configured to: in local refresh mode, if the current stage is a refresh row, control the pull-up module to charge the drive control node; if the current stage is a non-refresh row, control the pull-up module to stop charging the drive control node.

[0012] Secondly, this application provides a gate driving method applied to the gate driving circuit described in any one of the first aspects. The method includes: a pull-up module charging a drive control node in response to the output signal of the ni-th stage gate driving unit; an output module outputting a stage transmission signal and a gate driving signal under the action of the drive voltage on the drive control node and the current stage clock signal; in a local refresh mode, if the current stage is a refresh line, a first local refresh control module controls the drive output terminal to be electrically connected to the scan line; if the current stage is a non-refresh line, the first local refresh control module controls the drive output terminal of the output module to be disconnected from the scan line.

[0013] Optionally, when the first local refresh control module includes a first transistor, a second transistor, a third transistor, and a fourth transistor, in local refresh mode, if the current level is a refresh line, the first local refresh control module controls the drive output terminal to be electrically connected to the scan line, including: controlling the first transistor and the fourth transistor to be turned on and the second transistor and the third transistor to be turned off through the first local refresh control terminal and the second local refresh control terminal, so that the drive output terminal is electrically connected to the scan line; if the current level is a non-refresh line, the first local refresh control module controls the drive output terminal of the output module to be disconnected from the scan line, including: controlling the first transistor and the fourth transistor to be turned off and the second transistor and the third transistor to be turned on through the first local refresh control terminal and the second local refresh control terminal, so that the drive output terminal is electrically connected to the scan line.

[0014] Thirdly, this application provides a display panel including a display area and a non-display area, the display area including a plurality of scan lines, the non-display area including a gate driving circuit as described in any one of the first aspects, and the output module of the gate driving circuit being connected to the at least one of the scan lines.

[0015] The technical solution provided in this application has at least the following beneficial effects:

[0016] In this application, the first refresh control module is connected to the drive output terminal of the output module and the scan line. In partial refresh mode, if the current level is a refresh line, the drive output terminal of the control output module is electrically connected to the scan line, and the output module will output a gate drive signal to the scan line to drive the pixel for partial refresh. If the current level is a non-refresh line, the drive output terminal of the control output module is disconnected from the scan line, and the gate drive signal of the output module will not be output to the scan line. The pixel will maintain its original state and will not be refreshed, thereby reducing the number of pixel refreshes and improving the service life of the display panel. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 A schematic diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0019] Figure 2 A circuit diagram of a first type of gate driving unit provided in an embodiment of this application is shown.

[0020] Figure 3 The diagram shows the operating timing of a gate drive circuit according to an embodiment of this application.

[0021] Figure 4 A circuit diagram of a second gate driving unit provided in an embodiment of this application is shown.

[0022] Figure 5 A circuit diagram of a third gate driving unit provided in an embodiment of this application is shown.

[0023] Figure 6 A circuit diagram of a fourth gate driving unit provided in an embodiment of this application is shown.

[0024] Figure 7 A circuit diagram of a fifth gate driving unit provided in an embodiment of this application is shown.

[0025] Figure 8 A schematic flowchart of a gate driving method provided in an embodiment of this application is shown.

[0026] Explanation of reference numerals in the attached figures: 100 Gate driving unit; 110 Pull-up module; 120 Output module; 130 First brush control module; 140 Pull-down module; 150 Noise reduction module; 160 Discharge module; 170 Second brush control module; 171 First control submodule; 172 Second control submodule.

[0027] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; T13, thirteenth transistor; T14, fourteenth transistor; T15, fifteenth transistor; T16, sixteenth transistor; CC, bootstrap capacitor; VGH, high-level terminal; VSS, low-level terminal; SW1, first brush control terminal; SW2, second brush control terminal; SW3, third brush control terminal; SW4, fourth brush control terminal; LC, noise reduction signal output terminal. Detailed Implementation

[0028] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0029] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0030] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0031] Figure 1 A schematic diagram of a gate driving circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 1 As shown, the gate driving circuit includes N cascaded gate driving units 100. The nth gate driving unit 100 includes: a pull-up module 110, an output module 120, and a first-stage brush control module 130. The pull-up module 110 is connected to the drive control node Qn. The pull-up module 110 and the output module 120 are connected to the drive control node Qn. The output module 120 is connected to the drive control node Qn and the clock signal line CKm of the current stage. The first-stage brush control module 130 is connected to the drive output terminal of the output module 120 and the scan line.

[0032] It should be noted that in the figure, CKm-1, CKm, and CKm+1 represent clock signal lines; Gn represents the drive output terminal of the current stage output module 120; Gout_n represents the output terminal of the first brush control module 130, i.e., the connection terminal with the scan line; Fn represents the stage transmission output terminal of the current stage output module 120; Fn-i represents the stage transmission output terminal of the ni-th stage output module 120; and Gn-i represents the drive output terminal of the ni-th stage output module 120, where i can be 1.

[0033] In some embodiments, the pull-up module 110 is configured to charge the drive control node Qn in response to the output signal of the nth gate drive unit 100.

[0034] For example, the drive control node Qn is precharged in response to the output signal of the gate drive unit 100 of the preceding stage.

[0035] In some embodiments, the output module 120 is configured to output a stage transmission signal and a gate drive signal under the action of the drive voltage on the drive control node Qn and the current stage clock signal.

[0036] For example, when the output module 120 receives the driving voltage on the driving control node Qn and the current stage clock signal, the output module 120 will be turned on, thereby outputting the current stage transmission signal for transmission and outputting the gate driving signal to drive the pixel.

[0037] In some embodiments, the first refresh control module 130 is configured to: in partial refresh mode, if the current level is a refresh line, control the drive output terminal to be electrically connected to the scan line; if the current level is a non-refresh line, control the drive output terminal to be disconnected from the scan line.

[0038] For example, in partial refresh mode, if the current level is a refresh row, it means that the pixels of the current level need to be refreshed. The drive output terminal of the control output module 120 is electrically connected to the scan line, and the output module 120 will output a gate drive signal to the scan line to drive the pixel for partial refresh. If the current level is a non-refresh row, it means that the pixels of the current level do not need to be refreshed. The drive output terminal of the control output module 120 is disconnected from the scan line, and the gate drive signal of the output module 120 will not be output to the scan line. The pixel will maintain its original state and will not be refreshed, thereby reducing the number of pixel refreshes and improving the service life of the display panel.

[0039] Figure 2 A circuit diagram of a first type of gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 As shown, the first scan control module 130 includes: a first transistor T1; the control terminal of the first transistor T1 is connected to the first scan control terminal SW1, the first terminal of the first transistor T1 is connected to the drive output terminal of the output module 120, and the second terminal of the first transistor T1 is connected to the scan line.

[0040] Figure 3 A timing diagram of a gate drive circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 3As shown in the figure, the waveforms of the Nth frame signal, the N+1th frame signal, and the N+2th frame signal are displayed. The Nth frame signal and the N+2th frame signal are the waveforms of each signal during the normal refresh process. In the N+1th frame signal, it indicates that levels 1 to n will be refreshed, levels n+1 to n+100 will not be refreshed, and levels n+101 to n+200 will be refreshed, which are the waveforms of each signal in the partial refresh mode. CKm represents the clock signal line of the current stage, Fn-1 represents the output terminal of the (n-1)th stage transmission signal, Qn represents the drive control node Qn of the nth stage, Gn represents the drive output terminal of the nth stage output module 120, Gout_n represents the output terminal of the first brush control module 130 of the nth stage, Fn represents the stage transmission output terminal of the nth stage output module 120, Qn+1 represents the drive control node Qn of the (n+1)th stage, CKm+1 represents the clock signal line of the (m+1)th stage, Gn+1 represents the drive output terminal of the (n+1)th stage output module 120, Gout_n+1 represents the output terminal of the first brush control module 130 of the (n+1)th stage, and Gn+100 represents the (n+1)th stage transmission signal line. The output terminals of the 00th level output module 120 are: Gout_n+100, Gn+101, Gout_n+101, Gout_n+200, Gout_n+200, SW1, SW2, VGH, and VGL. SW1 represents the first brush control terminal, SW2 represents the second brush control terminal, VGH represents a high-level signal, and VGL represents a low-level signal.

[0041] For example, please refer to Figure 2 and Figure 3 As shown, the first refresh control terminal SW1 can be the control terminal of the controller, which can specifically be a timing controller. When the controller determines that the pixel of the current level is different from the pixel of the previous frame signal, it determines that the current level is a refresh line and needs to output a gate drive signal to update the pixel. The controller sends a first refresh control signal to the control terminal of the first transistor T1 through the first refresh control terminal SW1. The first transistor T1 is turned on, thereby controlling the drive output terminal of the output module 120 to connect with the scan line. When the controller determines that the pixel of the current level is the same as the pixel of the previous frame signal, it determines that the current level is a non-refresh line. The current level can maintain the pixel of the previous frame signal, and there is no need to output a gate drive signal to update the pixel. The controller sends a maintenance control signal to the control terminal of the first transistor T1 through the first refresh control terminal SW1. The first transistor T1 is turned off, thereby controlling the drive output terminal of the output module 120 to disconnect from the scan line.

[0042] It should be noted that when the first transistor T1 is N-type, the first refresh control signal can be a high-level signal and the sustain control signal can be a low-level signal; when the first transistor T1 is P-type, the refresh control signal can be a low-level signal and the sustain signal can be a high-level signal. The control principle for subsequent transistor types is similar and will not be elaborated further.

[0043] In some embodiments, the pull-up module 110 includes: a fifth transistor T5, the control terminal of the fifth transistor T5 being connected to the stage transmission output terminal or drive output terminal of the ni-th stage output module 120, the first terminal of the fifth transistor T5 being connected to the stage transmission output terminal or drive output terminal of the ni-th stage output module 120, and the second terminal of the fifth transistor T5 being connected to the drive control node Qn.

[0044] For example, Figure 1 In this example, the control terminal of the fifth transistor T5 is connected to the stage transmission output terminal of the ni-th stage output module 120, and the first terminal of the fifth transistor T5 is connected to the drive output terminal of the ni-th stage output module 120 (taking i = 1 as an example). When the control terminal of the fifth transistor T5 receives the stage transmission signal from the ni-th stage output module 120, and the first terminal of the fifth transistor T5 receives the gate drive signal from the ni-th stage output module 120, it is turned on to precharge the drive control node Qn.

[0045] In some embodiments, the output module 120 includes: a sixth transistor T6, a seventh transistor T7, and a bootstrap capacitor CC; the control terminal of the sixth transistor T6 is connected to the drive control node Qn, the control terminal of the seventh transistor T7, and the first terminal of the bootstrap capacitor CC, respectively; the first terminal of the sixth transistor T6 is connected to the clock signal line of the current stage and the first terminal of the seventh transistor T7, respectively; the second terminal of the sixth transistor T6 is the stage transmission output terminal; the second terminal of the seventh transistor T7 and the second terminal of the bootstrap capacitor CC are the drive output terminal and are connected to the first brush control module 130.

[0046] For example, when the ni-th stage output module 120 outputs the stage transmission signal and the gate drive signal, the bootstrap capacitor CC is charged. Under the action of the current stage clock signal and the drive voltage on the drive control node Qn, the control terminals of the sixth transistor T6 and the seventh transistor T7 are bootstrapped by the voltage on the bootstrap capacitor CC. The sixth transistor T6 and the seventh transistor T7 will be turned on. The second terminal of the sixth transistor T6 outputs the stage transmission signal, and the second terminal of the seventh transistor T7 outputs the gate drive signal.

[0047] In some embodiments, the nth-stage gate driving unit 100 further includes a pull-down module 140, which is connected to the drive control node Qn, the output terminal of the first local brush control module 130, and the stage transmission output terminal of the (n+i)th-stage output module 120, and is configured to pull down the drive control node Qn and the drive output terminal of the first local brush control module 130 to a low potential under the action of the stage transmission signal of the (n+i)th-stage output module 120.

[0048] In some embodiments, the pull-down module 140 includes an eighth transistor T8 and a ninth transistor T9. The control terminal of the eighth transistor T8 is connected to the stage transmission output terminal of the (n+i)th stage output module 120 and the control terminal of the ninth transistor T9, respectively. The first terminal of the eighth transistor T8 is connected to the drive control node Qn. The second terminal of the eighth transistor T8 and the second terminal of the ninth transistor T9 are connected to the low-level terminal VSS. The first terminal of the ninth transistor T9 is connected to the output terminal of the first brush control module 130.

[0049] For example, when the control terminals of the eighth transistor T8 and the ninth transistor T9 receive the stage transmission signal output by the (n+i)th stage output module 120, the eighth transistor T8 and the ninth transistor T9 are turned on, pulling down the output terminals of the drive control node Qn and the first brush control module 130 to a low potential, controlling the first brush control module to no longer output the gate drive signal, and when the next frame signal arrives, the pull-up module 110 can charge the drive control node Qn again.

[0050] In some embodiments, the nth gate driving unit 100 further includes a noise reduction module 150, which includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14. The control terminal of the tenth transistor T10 is connected to the output terminal LC of the noise reduction signal and the first terminal of the tenth transistor T10, respectively. The second terminal of the tenth transistor T10 is connected to the first terminal of the eleventh transistor T11, the control terminal of the twelfth transistor T12, the control terminal of the thirteenth transistor T13, and the fourteenth transistor T14, respectively. The control terminal of transistor T14 is connected; the control terminal of the eleventh transistor T11 is connected to the drive control node Qn; the second terminals of the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are connected to the low-level terminal VSS; the first terminal of the twelfth transistor T12 is connected to the drive control node Qn; the first terminal of the thirteenth transistor T13 is connected to the drive signal output terminal of the output module 120; and the second terminal of the fourteenth transistor T14 is connected to the cascade signal output terminal of the output module 120.

[0051] For example, the output terminal LC of the noise reduction signal is continuously in a high-level state. When the driving voltage of the eleventh transistor T11 is low, the twelfth transistor T12, the thirteenth transistor T13 and the fifth transistor T5 will receive the high-level signal and be turned on. The twelfth transistor T12 pulls down the driving control node Qn to a low level, the thirteenth transistor T13 pulls down the driving output terminal of the output module 120 to a low level, and the fourteenth transistor T14 pulls down the stage transmission output terminal of the output module 120 to a low level, thereby realizing noise reduction of the driving control node Qn, the driving output terminal of the output module 120 and the stage transmission output terminal.

[0052] Figure 4 A circuit diagram of a second type of gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 and Figure 4 As shown, the nth gate drive unit 100 further includes a discharge module 160, which is connected to the first local refresh control module 130 and is configured to pull down the output terminal of the first local refresh control module 130 to a low potential if the current level is a non-refresh row in local refresh mode.

[0053] For example, by setting the discharge module 160, in the partial refresh mode, if the current level is a non-refresh line, the output terminal of the first refresh control module 130 is pulled down to a low potential. The output terminal of the first refresh control module 130 is also connected to the scan line of the current level, and the scan line of the current level will also maintain a low potential, so that no gate drive signal is output. This can further ensure that the scan line does not input a gate drive signal, so that the pixel maintains the state of the previous frame and does not refresh.

[0054] Please see Figure 3 and Figure 4 As shown, in some embodiments, the discharge module 160 includes: a second transistor T2; the control terminal of the second transistor T2 is connected to the second brush control terminal SW2, the first terminal of the second transistor T2 is connected to the output terminal of the first brush control module 130, and the second terminal of the second transistor T2 is connected to the low-level terminal VSS.

[0055] For example, the second refresh control terminal SW2 can be a controller terminal. If the controller determines that the current level is a non-refresh line, it outputs a discharge signal to turn on the second transistor T2. The output terminal of the first refresh module will be connected to the low-level terminal VSS through the second transistor T2, thereby maintaining the scan line of the current level at a low potential. If the controller determines that the current level is a refresh line, it outputs a second refresh control signal to turn off the second transistor T2. The output terminal of the first refresh control module 130 will remain disconnected from the low-level terminal VSS.

[0056] Figure 5A circuit diagram of a third type of gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 and Figure 5 As shown, the first brush control module 130 includes: at least two second transistors T2 connected in series; the control terminal of each second transistor T2 is connected to the second brush control terminal SW2, the first terminal of the first second transistor T2 in the at least two series-connected second transistors T2 is connected to the output terminal of the first brush control module 130, and the second terminal of the last second transistor T2 in the at least two series-connected second transistors T2 is connected to the low-level terminal VSS.

[0057] For example, each second transistor T2 can receive a discharge signal from the controller, causing at least two second transistors T2 to conduct simultaneously. When the current stage is a non-refresh row, the output of the first refresh control module 130 is pulled down to the low level VSS. By setting multiple second transistors T2, the leakage path can be increased, thereby reducing the risk of leakage. Figure 4 Taking the setting of two second transistors T2 as an example.

[0058] Figure 6 A circuit diagram of a fourth gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 and Figure 6 As shown, the first brush control module 130 consists of a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The control terminal of the first transistor T1 is connected to the first brush control terminal SW1. The first terminal of the first transistor T1 is connected to the drive output terminal of the output module 120 and the first terminal of the second transistor T2. The second terminal of the first transistor T1 is connected to the scan line, the first terminal of the third transistor T3, and the control terminal of the fourth transistor T4, respectively. The control terminal of the second transistor T2 is connected to the second brush control terminal SW2. The second terminal of the second transistor T2 is connected to the control terminal of the third transistor T3 and the first terminal of the fourth transistor T4, respectively. The second terminals of the third transistor T3 and the fourth transistor T4 are connected to the low-level terminal VSS.

[0059] For example, if the controller determines that the current level is a refresh row, it sends a first refresh control signal to the control terminal of the first transistor T1 and a second refresh control signal to the control terminal of the second transistor T2. The first transistor T1 will be turned on, the second transistor T2 will be turned off, and thus the fourth transistor T4 will be turned on, the third transistor T3 will be turned off, and the gate drive signal will be output to the scan line through the second terminal of the first transistor T1. If the controller determines that the current level is a non-refresh row, it sends a sustain control signal to the control terminal of the first transistor T1 and a discharge signal to the control terminal of the second transistor T2. The first transistor T1 will be turned off, the second transistor T2 will be turned on, the fourth transistor T4 will be turned off, and the third transistor T3 will be turned on, and thus the drive output terminal of the output module 120 will not output the gate drive signal to the scan line. It should be noted that when the control terminal of the first transistor T1 is a high-level signal, the control terminal of the second transistor T2 is a low-level signal, and when the control terminal of the first transistor T1 is a low-level signal, the control terminal of the second transistor T2 is a high-level signal. This enables interlocking between refreshing and not refreshing, thereby improving the reliability of the first refresh control module 130.

[0060] Figure 7 A circuit diagram of the sixth gate drive circuit provided in this application embodiment is shown. Please refer to [link / reference]. Figure 7 As shown, the nth gate drive unit 100 further includes a second local refresh control module 170, which is connected to the pull-up module 110 and is configured to: in local refresh mode, if the current level is a refresh row, control the pull-up module 110 to charge the drive control node Qn; if the current level is a non-refresh row, control the pull-up module 110 to stop charging the drive control node Qn.

[0061] For example, in partial refresh mode, only pixels in some rows or regions are refreshed. If the current level is a refreshed row, the pull-up module 110 is controlled to charge the drive control node Qn, and the output module 120 will output the gate drive signal of the current level under the action of the drive voltage on the drive control node Qn and the clock signal of the current level; if the current level is a non-refreshed row, the pull-up module 110 is controlled to stop charging the drive control node Qn, no drive voltage will be generated on the drive control node Qn, and the output module 120 will not output the gate drive signal.

[0062] In some embodiments, the second local brush control module 170 includes: a first control submodule 171 and a second control submodule 172. The first control submodule 171 is connected to the first signal input terminal A and / or the second signal input terminal B of the pull-up module 110, and the second control submodule 172 is connected to the first signal input terminal A and the second signal input terminal B of the pull-up module 110.

[0063] In some embodiments, the first control submodule 171 is configured to: in partial refresh mode, if the current level is a non-refresh row, control the pull-up module 110 to stop charging the drive control node Qn; if the current level is a refresh row, control the pull-up module 110 to charge the drive control node Qn.

[0064] For example, by setting the first control submodule 171, in the partial refresh mode, if the current level is a refresh row, the control pull-up module 110 charges the drive control node Qn, and a drive voltage will be generated on the drive control node Qn. The output module 120 outputs the gate drive signal under the action of the drive voltage and the current level clock signal. If the current level is a non-refresh row, the control pull-up module 110 stops charging the drive control node Qn, and no drive voltage will be generated on the drive control node Qn. The output module 120 will not output the gate drive signal.

[0065] In some embodiments, the second control submodule 172 is configured to: in partial refresh mode, if the nith level is a non-refresh line and the current level is a refresh line, control the pull-up module 110 to charge the drive control node Qn.

[0066] For example, if the ni-th level is a non-refresh line, the pull-up module 110 of the ni-th level will not charge the drive control node Qn, so the ni-th level will not output the stage pass signal and the gate drive signal. When the current level is a refresh line, the pull-up module 110 will not receive the stage pass signal and / or the gate drive signal to charge the drive control node Qn. By setting the second control submodule 172 to control the pull-up module 110 to charge the drive control node Qn, the output module 120 of the current level outputs the gate drive signal to drive the pixel, thereby realizing that only a local area of ​​the display panel is refreshed, while other areas can still display the pixels of the previous frame.

[0067] In some embodiments, the first control submodule 171 includes: a fifteenth transistor T15; the control terminal of the fifteenth transistor T15 is connected to the third brush control terminal SW3, the first terminal of the fifteenth transistor T15 is connected to the first signal input terminal A and / or the second signal input terminal B of the pull-up module 110, and the second terminal of the fifteenth transistor T15 is connected to the low-level terminal VSS.

[0068] For example, the third refresh control terminal SW3 can be a controller terminal, specifically a timing controller. When the controller determines that the pixel of the current stage is different from the pixel of the previous frame signal, it determines that the current stage is a refresh row and needs to output a gate drive signal to update the pixel. The controller sends a third refresh control signal to the control terminal of the fifteenth transistor T15 through the third refresh control terminal SW3. The fifteenth transistor T15 is turned off, and the pull-up module 110 will normally charge the drive control node Qn; when the controller determines that the pixel of the current stage is the same as the pixel of the previous frame signal, then... If the current level is determined to be a non-refreshing row, then the current level can maintain the pixels of the previous frame signal. Therefore, there is no need to output a gate drive signal to update the pixels. The controller sends a maintenance control signal to the control terminal of the fifteenth transistor T15 through the third refresh control terminal SW3. The fifteenth transistor T15 is turned on, and the fifteenth transistor T15 pulls down the first signal input terminal A and / or the second signal input terminal B of the pull-up module 110 to a low potential. The pull-up module 110 will not charge the drive control node Qn, and the output module 120 will not output a gate drive signal to refresh the pixels.

[0069] In some embodiments, the second control submodule 172 includes: a sixteenth transistor T16; the control terminal of the sixteenth transistor T16 is connected to the fourth brush control terminal SW4, the first terminal of the sixteenth transistor T16 is connected to the high-level terminal VGH, and the second terminal of the sixteenth transistor T16 is connected to the first signal input terminal A and the second signal input terminal B of the pull-up module 110.

[0070] For example, if the ni-th level is a non-refreshing row and the current level is a refreshing row, the ni-th level will not output the stage pass signal and the gate drive signal. The pull-up module 110 of the current level will not charge the drive control node Qn, and the output module 120 will not be able to output the gate drive signal to refresh the pixel. When the controller determines that the ni-th level is a non-refreshing row and the current level is a refreshing row, it sends the fourth refresh control signal to the control terminal of the sixteenth transistor T16 through the fourth refresh control terminal SW4. The sixteenth transistor T16 will be turned on, and the first signal input terminal and the second signal input terminal of the pull-up module 110 will both be connected to the high-level terminal VGH. The pull-up module 110 will charge the drive control node Qn, and the output module 120 will output the gate drive signal to refresh the pixel.

[0071] By setting the second refresh control module 170 to control the pull-up module 110 and working together with the first refresh control module 130, it can be further ensured that when the current level is a refresh row, the gate drive signal is output to refresh the pixel; when the current level is a non-refresh row, the gate drive signal is not output to refresh the pixel, thereby further improving the reliability of the gate drive circuit.

[0072] Figure 8 This document shows a schematic flowchart of a gate driving method provided in an embodiment of this application. Please refer to [link / reference]. Figure 8 As shown, the gate driving method provided in this application is applied to the gate driving circuit described above, and the method includes the following steps S110 to S130.

[0073] S110, the pull-up module responds to the output signal of the ni-th gate drive unit and charges the drive control node.

[0074] S120, under the action of the drive voltage and the current stage clock signal on the drive control node, the output module outputs the signal and the gate drive signal.

[0075] S130. In partial refresh mode, if the current level is a refresh line, the first refresh control module controls the drive output terminal to be electrically connected to the scan line; if the current level is a non-refresh line, the first refresh control module controls the drive output terminal of the output module to be disconnected from the scan line.

[0076] In some embodiments, when the first local refresh control module includes a first transistor, a second transistor, a third transistor, and a fourth transistor, in local refresh mode, if the current level is a refresh line, the first local refresh control module controls the drive output terminal to be electrically connected to the scan line, including: controlling the first transistor and the fourth transistor to be turned on and the second transistor and the third transistor to be turned off through the first local refresh control terminal and the second local refresh control terminal, so that the drive output terminal is electrically connected to the scan line; if the current level is a non-refresh line, the first local refresh control module controls the drive output terminal of the output module to be disconnected from the scan line, including: controlling the first transistor and the fourth transistor to be turned off and the second transistor and the third transistor to be turned on through the first local refresh control terminal and the second local refresh control terminal, so that the drive output terminal is electrically connected to the scan line.

[0077] It should be noted that the gate driving method and the gate driving circuit work in the same way, and will not be described again here.

[0078] In some embodiments, this application also provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the aforementioned gate driving circuit. The output module of the gate driving circuit is connected to at least one scan line.

[0079] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0080] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0081] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes N cascaded gate driving units, and the nth gate driving unit includes: The pull-up module, connected to the drive control node, is configured to charge the drive control node in response to the output signal of the nith gate drive unit. The output module, connected to the drive control node and the clock signal line of the current stage, is configured to output the stage transmission signal and the gate drive signal under the action of the drive voltage on the drive control node and the clock signal of the current stage. The first refresh control module, connected to the drive output terminal and scan line of the output module, is configured to: in partial refresh mode, if the current level is a refresh line, control the drive output terminal to be electrically connected to the scan line; if the current level is a non-refresh line, control the drive output terminal to be disconnected from the scan line. The second round of brush control module includes: first control submodule and second control submodule; The first control submodule, connected to the low-level terminal and the third refresh control terminal, and also connected to the first signal input terminal and / or the second signal input terminal of the pull-up module, is configured to: in partial refresh mode, if the current level is a non-refresh line, pull down the first signal input terminal and / or the second signal input terminal of the pull-up module to a low potential according to the third refresh control signal, so as to control the pull-up module to stop charging the drive control node; if the current level is a refresh line, stop pulling down the first signal input terminal and / or the second signal input terminal of the pull-up module to a low potential according to the sustain control signal, so as to control the pull-up module to charge the drive control node; The second control submodule, connected to the high-level terminal, the fourth local refresh control terminal, the first signal input terminal of the pull-up module, and the second signal input terminal of the pull-up module, is configured to: in local refresh mode, if the ni-th level is a non-refresh line and the current level is a refresh line, pull up the first signal input terminal of the pull-up module and the second output terminal of the pull-up module to a high potential according to the fourth refresh control signal, so as to control the pull-up module to charge the drive control node.

2. The gate driving circuit according to claim 1, characterized in that, The first refresh control module includes: a first transistor; The control terminal of the first transistor is connected to the first brush control terminal, the first terminal of the first transistor is connected to the drive output terminal of the output module, and the second terminal of the first transistor is connected to the scan line.

3. The gate driving circuit according to claim 1, characterized in that, The nth-stage gate drive unit also includes: The discharge module, connected to the first local refresh control module, is configured to: in the local refresh mode, if the current level is a non-refresh line, pull down the output terminal of the first local refresh control module to a low potential.

4. The gate driving circuit according to claim 3, characterized in that, The discharge module includes: a second transistor; The control terminal of the second transistor is connected to the control terminal of the second brush, the first terminal of the second transistor is connected to the output terminal of the first brush control module, and the second terminal of the second transistor is connected to the low-level terminal.

5. The gate driving circuit according to claim 3, characterized in that, The first brush control module includes: at least two second transistors connected in series; The control terminal of each second transistor is connected to the second brush control terminal. The first terminal of the first second transistor in the at least two series-connected second transistors is connected to the output terminal of the first brush control module. The second terminal of the last second transistor in the at least two series-connected second transistors is connected to the low-level terminal.

6. The gate driving circuit according to claim 1, characterized in that, The first local refresh control module comprises a first transistor, a second transistor, a third transistor, and a fourth transistor; The control terminal of the first transistor is connected to the control terminal of the first brush, the first terminal of the first transistor is connected to the drive output terminal of the output module and the first terminal of the second transistor, and the second terminal of the first transistor is connected to the scan line, the first terminal of the third transistor and the control terminal of the fourth transistor respectively. The control terminal of the second transistor is connected to the control terminal of the second brush, and the second terminal of the second transistor is connected to the control terminal of the third transistor and the first terminal of the fourth transistor, respectively. The second terminal of the third transistor and the second terminal of the fourth transistor are connected to the low-level terminal.

7. A gate driving method, characterized in that, Applied to the gate drive circuit according to any one of claims 1-6, the method comprises: The pull-up module responds to the output signal of the nith gate drive unit and charges the drive control node. Under the influence of the drive voltage and the current stage clock signal at the drive control node, the output module outputs the stage transmission signal and the gate drive signal. In partial refresh mode, if the current level is a refresh line, the first refresh control module controls the drive output terminal to be electrically connected to the scan line; if the current level is a non-refresh line, the first refresh control module controls the drive output terminal of the output module to be disconnected from the scan line. In partial refresh mode, if the current level is a non-refresh row, the first control submodule pulls down the first signal input terminal and / or the second signal input terminal of the pull-up module to a low potential according to the third refresh control signal, so as to control the pull-up module to stop charging the drive control node; if the current level is a refresh row, the first control submodule stops pulling down the first signal input terminal and / or the second signal input terminal of the pull-up module to a low potential according to the maintenance control signal, so as to control the pull-up module to charge the drive control node. If the nith level is a non-refresh line and the current level is a refresh line, the second control submodule pulls the first signal input terminal and the second output terminal of the pull-up module to a high potential according to the fourth refresh control signal, so as to control the pull-up module to charge the drive control node.

8. The gate driving method according to claim 7, characterized in that, When the first local refresh control module includes: a first transistor, a second transistor, a third transistor, and a fourth transistor, in local refresh mode, If the current level is a refresh line, the first refresh control module controls the drive output terminal to be electrically connected to the scan line, including: The first and fourth transistors are turned on and the second and third transistors are turned off by controlling the first and second brush control terminals, so that the drive output terminal is electrically connected to the scan line. If the current level is a non-refresh line, the first refresh control module controls the output module's drive output terminal to disconnect from the scan line, including: The first and fourth transistors are turned off and the second and third transistors are turned on by controlling the first and second brush control terminals, so that the drive output terminal is electrically connected to the scan line.

9. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-6, wherein the output module of the gate driving circuit is connected to at least one of the scan lines.

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