A gate driving circuit, a gate driving method and a display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit, a gate driving method and a display panel. The circuit comprises N cascaded gate driving units, and the nth gate driving unit comprises: a pull-up module connected with a driving control node and configured to charge the driving control node in response to an output signal of the nth-i gate driving unit in a global refresh mode; an output module connected with the driving control node and a current stage clock signal line respectively and configured to output a stage transmission signal and a gate driving signal of the current stage under the action of a driving voltage on the driving control node and the current stage clock signal; and a first local refresh control module connected with the pull-up module and configured to control the pull-up module to charge the driving control node if the current stage is a refresh row in a local refresh mode, and control the pull-up module to stop charging the driving control node if the current stage is a non-refresh row. The application can reduce the aging speed of the display panel.

Description

Technical Field

[0001] This application belongs to the field of display driving technology, specifically relating to a gate driving circuit, a gate driving method, and a display panel. Background Technology

[0002] Among related technologies, Gate Driver Less (GDL) is a technical solution based on amorphous silicon (a-SiTFT) fabrication that directly integrates the shift register circuit of an external gate driver integrated circuit onto the display panel array substrate. This solution can completely replace a separate gate driver IC, simplifying the display driver architecture through process integration, thereby significantly reducing device procurement and module assembly costs. However, the frequent pixel refresh control by the gate driver IC will accelerate the aging of the display panel and reduce its lifespan.

[0003] Therefore, how to reduce the aging rate of display panels is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit, a gate driving method, and a display panel, which solves the problem that frequent pixel refresh controlled by the gate driving IC will accelerate the aging of the display panel.

[0005] In a first aspect, this application provides a gate driving circuit, the gate driving circuit including N cascaded gate driving units, the nth gate driving unit including: a pull-up module connected to a driving control node, configured to: in global refresh mode, charge the driving control node in response to the output signal of the nth gate driving unit; an output module connected to the driving control node and the clock signal line of the current stage respectively, configured to: output the cascade signal and gate driving signal of the current stage under the action of the driving voltage on the driving control node and the clock signal of the current stage; a first local refresh control module connected to the pull-up module, configured to: in local refresh mode, if the current stage is a refresh row, control the pull-up module to charge the driving control node; if the current stage is a non-refresh row, control the pull-up module to stop charging the driving control node.

[0006] Optionally, the first local refresh control module includes: a first control submodule, connected to the first signal input terminal and / or the second signal input terminal of the pull-up module, configured to: in the local refresh mode, if the current level is a non-refresh line, control the pull-up module to stop charging the drive control node; if the current level is a refresh line, control the pull-up module to charge the drive control node; and a second control submodule, connected to the first signal input terminal and the second signal input terminal of the pull-up module, configured to: in the local refresh mode, if the ni-th level is a non-refresh line and the current level is a refresh line, control the pull-up module to charge the drive control node.

[0007] Optionally, the nth gate driving unit further includes a second local refresh control module, which is connected to the drive output terminal and the scan line of the output module, and is configured to: in local refresh mode, if the current level is a refresh line, control the drive output terminal to be electrically connected to the scan line; if the current level is a non-refresh line, control the drive output terminal to be disconnected from the scan line.

[0008] Optionally, the first control submodule includes: a first transistor; the control terminal of the first transistor is connected to the first brush control terminal, the first terminal of the first transistor is connected to the first signal input terminal of the pull-up module and / or the second signal input terminal of the pull-up module, and the second terminal of the first transistor is connected to a low-level terminal.

[0009] Optionally, the first control submodule includes: at least two first transistors connected in series; the control terminal of each first transistor is connected to a first brush control terminal, the first terminal of the first first transistor of the at least two first transistors is connected to the first signal input terminal and / or the second signal input terminal of the pull-up module, and the second terminal of the last first transistor of the at least two first transistors is connected to a low-level terminal.

[0010] Optionally, the second control submodule includes: a second transistor; the control terminal of the second transistor is connected to the control terminal of the second brush, the first terminal of the second transistor is connected to the high-level terminal, and the second terminal of the second transistor is connected to the first signal input terminal and the second signal input terminal of the pull-up module.

[0011] Optionally, the second control submodule includes: at least two second transistors connected in series; the control terminal of each second transistor is connected to the control terminal of the second circuit breaker, the first terminal of the first second transistor of the at least two second transistors is connected to the high-level terminal, and the second terminal of the last second transistor of the at least two second transistors is connected to the first signal input terminal and the second signal input terminal of the pull-up module.

[0012] Optionally, the first local refresh control module includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; the control terminal of the first transistor is connected to the first local refresh control terminal, the first terminal of the first transistor is connected to the first signal input terminal of the pull-up module, the second signal input terminal of the pull-up module, and the first terminal of the second transistor, and the second terminal of the first transistor is connected to the high-level terminal, the first terminal of the third transistor, and the control terminal of the fourth transistor, respectively; the control terminal of the second transistor is connected to the second local refresh control terminal, and the second terminal of the second transistor is connected to the control terminal of the third transistor and the first terminal of the fourth transistor, respectively; the second terminals of the third transistor and the second terminals of the fourth transistor are connected to the low-level terminal.

[0013] Secondly, this application provides a gate driving method applied to the gate driving circuit described in any one of the first aspects. The method includes: in global refresh mode, a pull-up module responds to the output signal of the ni-th level gate driving unit to charge the driving control node; an output module outputs the current level's transmission signal and gate driving signal under the action of the driving voltage on the driving control node and the current level's clock signal; in local refresh mode, if the current level is a refresh row, a first local refresh control module controls the pull-up module to charge the driving control node; if the current level is a non-refresh row, the first local refresh control module controls the pull-up module to stop charging the driving control node.

[0014] Thirdly, this application provides a display panel including a display area and a non-display area, wherein the display area includes a plurality of scan lines, and the non-display area includes a gate driving circuit as described in any one of the first aspects, and the output module of the gate driving circuit is connected to at least one of the scan lines.

[0015] The technical solution provided in this application has at least the following beneficial effects:

[0016] In this application, by setting a first control submodule, in partial refresh mode, if the current level is a refresh row, the control pull-up module charges the drive control node, and a drive voltage is generated on the drive control node. The output module outputs a gate drive signal under the action of the drive voltage and the current level clock signal to drive the pixel of the current level. If the current level is a non-refresh row, the control pull-up module stops charging the drive control node, and no drive voltage is generated on the drive control node. The output module will not output a gate drive signal, so the pixel will not be refreshed, which can reduce the number of pixel refreshes and improve the service life of the display panel. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 A schematic diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0019] Figure 2 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown.

[0020] Figure 3 The diagram shows the operating timing of a gate drive circuit according to an embodiment of this application.

[0021] Figure 4 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown.

[0022] Figure 5 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown.

[0023] Figure 6 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown.

[0024] Figure 7 A schematic flowchart of a gate driving method provided in an embodiment of this application is shown.

[0025] Explanation of reference numerals in the attached figures: 100 Gate driving unit; 110 Pull-up module; 120 Output module; 130 First brush control module; 131 First control submodule; 132 Second control submodule; 140 Pull-down module; 150 Noise reduction module; 160 Second brush control module.

[0026] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; T13, thirteenth transistor; T14, fourteenth transistor; T15, fifteenth transistor; CC, bootstrap capacitor; VGH, high-level terminal; VSS, low-level terminal; SW1, first brush control terminal; SW2, second brush control terminal; SW3, third brush control terminal; LC, noise reduction signal output terminal. Detailed Implementation

[0027] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0028] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0029] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0030] Figure 1 A schematic diagram of a gate driving circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 1 As shown, the gate driving circuit includes N cascaded gate driving units 100. The nth stage gate driving circuit includes a pull-up module 110, an output module 120, and a first brush control module 130. The pull-up module 110 is connected to the drive control node Qn. The output module 120 is connected to the drive control node Qn and the clock signal line CKm of the current stage, respectively. The first brush control module 130 is connected to the pull-up module 110.

[0031] In some embodiments, the pull-up module 110 is configured to charge the drive control node Qn in response to the output signal of the ni-th gate drive unit 100 in global refresh mode.

[0032] For example, the global refresh mode is the normal refresh mode, which refreshes each row of pixels. i can be 1, and the drive control node Qn is pre-charged in response to the output signal of the gate drive unit 100 in the preceding stage.

[0033] In some embodiments, the output module 120 is configured to output the current stage transmission signal and the gate drive signal under the action of the drive voltage on the drive control node Qn and the current stage clock signal.

[0034] For example, when the output module 120 receives the driving voltage on the driving control node Qn and the current stage clock signal, the output module 120 will be turned on, thereby outputting the current stage transmission signal for transmission and outputting the gate driving signal to drive the pixel.

[0035] In some embodiments, the first refresh control module 130 is configured to: in partial refresh mode, if the current level is a refresh row, control the pull-up module 110 to charge the drive control node Qn; if the current level is a non-refresh row, control the pull-up module 110 to stop charging the drive control node Qn.

[0036] For example, in partial refresh mode, only pixels in certain rows or areas are refreshed. If the current level is a refreshed row, the pull-up module 110 charges the drive control node Qn, and the output module 120 outputs the gate drive signal of the current level under the action of the drive voltage on the drive control node Qn and the clock signal of the current level to drive the pixels. If the current level is a non-refreshed row, the pull-up module 110 stops charging the drive control node Qn, no drive voltage is generated on the drive control node Qn, and the output module 120 will not output the gate drive signal, thus not refreshing the pixels, reducing the number of pixel refreshes and improving the lifespan of the display panel.

[0037] Figure 2 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 As shown, the first control module 130 includes: a first control submodule 131 and a second control submodule 132. The first control submodule 131 is connected to the first signal input terminal A and / or the second signal input terminal B of the pull-up module 110. The second control submodule 132 is connected to the first signal input terminal A and the second signal input terminal B of the pull-up module 110.

[0038] In some embodiments, the first control submodule 131 is configured to: in partial refresh mode, if the current level is a non-refresh row, control the pull-up module 110 to stop charging the drive control node Qn; if the current level is a refresh row, control the pull-up module 110 to charge the drive control node Qn.

[0039] For example, by setting the first control submodule 131, in partial refresh mode, if the current level is a refresh row, the control pull-up module 110 charges the drive control node Qn, and a drive voltage will be generated on the drive control node Qn. The output module 120 outputs a gate drive signal under the action of the drive voltage and the current level clock signal to drive the pixel of the current level; if the current level is a non-refresh row, the control pull-up module 110 stops charging the drive control node Qn, and no drive voltage will be generated on the drive control node Qn. The output module 120 will not output a gate drive signal, so the pixel will not be refreshed, which can reduce the number of pixel refreshes and improve the service life of the display panel.

[0040] In some embodiments, the second control submodule 132 is configured to: in partial refresh mode, if the nith level is a non-refresh line and the current level is a refresh line, control the pull-up module 110 to charge the drive control node Qn.

[0041] For example, if the ni-th level is a non-refresh line, the pull-up module 110 of the ni-th level will not charge the drive control node Qn, so the ni-th level will not output the stage pass signal and the gate drive signal. When the current level is a refresh line, the pull-up module 110 will not receive the stage pass signal and / or the gate drive signal to charge the drive control node Qn. By setting the second control submodule 132 to control the pull-up module 110 to charge the drive control node Qn, the output module 120 of the current level outputs the gate drive signal to drive the pixel, thereby realizing that only a local area of ​​the display panel is refreshed, while other areas can still display the pixels of the previous frame.

[0042] Figure 3 The following is a timing diagram illustrating the operation of a gate driving unit according to an embodiment of this application. Please refer to [link / reference]. Figure 3As shown in the figure, the waveforms of the Nth frame signal, the N+1th frame signal, and the N+2th frame signal are displayed. The Nth frame signal and the N+2th frame signal are the waveforms of each signal during the normal refresh process. In the N+1th frame signal, it indicates that the 1st to the nth level will be refreshed, the n+1st to the n+100th level will be refreshed, the n+101st to the n+200th level will not be refreshed, the n+201st level will not be refreshed, and the n+202nd level will be refreshed. CKm represents the clock signal line of the current stage, Fn-1 represents the output terminal of the (n-1)th stage transmission signal, Qn represents the drive control node Qn of the nth stage, Gn represents the drive output terminal of the output module 120 of the nth stage, Fn represents the stage transmission output terminal of the output module 120 of the nth stage, Qn+1 represents the drive control node Qn of the (n+1)th stage, Gn+1 represents the drive output terminal of the output module 120 of the (n+1)th stage, Gn+100 represents the drive output terminal of the output module 120 of the (n+100)th stage, and Fn+100 represents the stage transmission output terminal of the (n+10)th stage. The level 0 output module 120 has the following output terminals: Gn+101 represents the drive output terminal of the (n+101)th output module 120; Fn+101 represents the level transmission output terminal of the (n+101)th output module 120; Gn+201 represents the drive output terminal of the (n+201)th output module 120; Gn+202 represents the drive output terminal of the (n+202)th output module 120; SW1 represents the first brush control terminal; SW2 represents the second brush control terminal; VGH represents a high-level signal; and VGL represents a low-level signal.

[0043] Please see Figure 2 and Figure 3 As shown, the first control submodule 131 includes: a first transistor T1; the control terminal of the first transistor T1 is connected to the first local brush control terminal SW1, the first terminal of the first transistor T1 is connected to the first signal input terminal A and / or the second signal input terminal B of the pull-up module 110, and the second terminal of the first transistor T1 is connected to the low-level terminal VSS.

[0044] For example, the first refresh control terminal SW1 can be the control terminal of the controller, which can specifically be a timing controller. When the controller determines that the pixel of the current level is different from the pixel of the previous frame signal, it determines that the current level is a refresh row and needs to output a gate drive signal to update the pixel. The controller sends a first refresh control signal to the control terminal of the first transistor T1 through the first refresh control terminal SW1. The first transistor T1 is turned off, and the pull-up module 110 will charge the drive control node Qn normally. When the controller determines that the pixel of the current level is the same as the pixel of the previous frame signal, it determines that the current level is a non-refresh row. The current level can maintain the pixel of the previous frame signal and does not need to output a gate drive signal to update the pixel. The controller sends a maintenance control signal to the control terminal of the first transistor T1 through the first refresh control terminal SW1. The first transistor T1 is turned on, and the first transistor T1 pulls down the first signal input terminal A and / or the second signal input terminal B of the pull-up module 110 to a low potential. The pull-up module 110 will not charge the drive control node Qn, and the output module 120 will not output a gate drive signal to refresh the pixel.

[0045] It should be noted that when the first transistor T1 is N-type, the first refresh control signal can be a high-level signal and the sustain control signal can be a low-level signal; when the first transistor T1 is P-type, the refresh control signal can be a low-level signal and the sustain signal can be a high-level signal. The control principle for subsequent transistor types is similar and will not be elaborated further.

[0046] In some embodiments, the pull-up module 110 includes: a fifth transistor T5, the control terminal of the fifth transistor T5 being connected to the stage transmission output terminal or drive output terminal of the ni-th stage output module 120, the first terminal of the fifth transistor T5 being connected to the stage transmission output terminal or drive output terminal of the ni-th stage output module 120, and the second terminal of the fifth transistor T5 being connected to the drive control node Qn.

[0047] For example, Figure 1 In this example, the control terminal of the fifth transistor T5 is connected to the stage transmission output terminal of the ni-th stage output module 120, and the first terminal of the fifth transistor T5 is connected to the drive output terminal of the ni-th stage output module 120 (taking i = 1 as an example). When the control terminal of the fifth transistor T5 receives the stage transmission signal from the ni-th stage output module 120, and the first terminal of the fifth transistor T5 receives the gate drive signal from the ni-th stage output module 120, it is turned on to precharge the drive control node Qn.

[0048] For example, if the current level is a non-refresh row, when the control terminal of the first transistor T1 receives a sustain signal, the first transistor T1 will be turned on, thereby pulling down the control terminal of the fifth transistor T5 and / or the first terminal of the fifth transistor T5 to a low potential, and the fifth transistor T5 will be turned off, so as not to charge the drive control node Qn.

[0049] For example, if the ni-th level is a non-refresh line and the current level is a refresh line, during the working period of the ni-th level, when the control terminal of the second transistor T2 receives the first refresh control signal, the second transistor T2 is turned on, the control terminal of the second transistor T2 and the first terminal of the second transistor T2 are pulled up to a high potential, and the fifth transistor T5 is turned on, thereby charging the drive control node Qn so that the output module 120 outputs the gate drive signal to drive the pixel.

[0050] In some embodiments, the output module 120 includes: a sixth transistor T6, a seventh transistor T7, and a bootstrap capacitor CC; the control terminal of the sixth transistor T6 is connected to the drive control node Qn, the control terminal of the seventh transistor T7, and the first terminal of the bootstrap capacitor CC, respectively; the first terminal of the sixth transistor T6 is connected to the clock signal line of the current stage and the first terminal of the seventh transistor T7, respectively; the second terminal of the sixth transistor T6 is the stage transmission output terminal; the second terminal of the seventh transistor T7 and the second terminal of the bootstrap capacitor CC are the drive output terminal and are connected to the first brush control module 130.

[0051] For example, when the ni-th stage output module 120 outputs the stage transmission signal and the gate drive signal, the bootstrap capacitor CC is charged. Under the action of the current stage clock signal and the drive voltage on the drive control node Qn, the control terminals of the sixth transistor T6 and the seventh transistor T7 are bootstrapped by the voltage on the bootstrap capacitor CC. The sixth transistor T6 and the seventh transistor T7 will be turned on. The second terminal of the sixth transistor T6 outputs the stage transmission signal, and the second terminal of the seventh transistor T7 outputs the gate drive signal.

[0052] In some embodiments, the nth-stage gate driving unit 100 further includes a pull-down module 140, which is connected to the drive control node Qn, the output terminal of the first local brush control module 130, and the stage transmission output terminal of the (n+i)th-stage output module 120, and is configured to pull down the drive control node Qn and the drive output terminal of the first local brush control module 130 to a low potential under the action of the stage transmission signal of the (n+i)th-stage output module 120.

[0053] In some embodiments, the pull-down module 140 includes an eighth transistor T8 and a ninth transistor T9. The control terminal of the eighth transistor T8 is connected to the stage output terminal of the (n+i)th stage output module 120 and the control terminal of the ninth transistor T9, respectively. The first terminal of the eighth transistor T8 is connected to the drive control node Qn. The second terminal of the eighth transistor T8 and the second terminal of the ninth transistor T9 are connected to the low-level terminal VSS. The first terminal of the ninth transistor T9 is connected to the output terminal of the first brush control module 130.

[0054] For example, when the control terminals of the eighth transistor T8 and the ninth transistor T9 receive the stage transmission signal output by the (n+i)th stage output module 120, the eighth transistor T8 and the ninth transistor T9 are turned on, pulling down the output terminals of the drive control node Qn and the first brush control module 130 to a low potential, controlling the first brush control module to no longer output the gate drive signal, and when the next frame signal arrives, the pull-up module 110 can charge the drive control node Qn again.

[0055] In some embodiments, the nth gate driving unit 100 further includes a noise reduction module 150, which includes: a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14. The control terminal of the tenth transistor T10 is connected to the output terminal LC of the noise reduction signal and the first terminal of the tenth transistor T10, respectively. The second terminal of the tenth transistor T10 is connected to the first terminal of the eleventh transistor T11, the control terminal of the twelfth transistor T12, the control terminal of the thirteenth transistor T13, and the fourteenth transistor T14, respectively. The control terminal of transistor T14 is connected; the control terminal of transistor T11 is connected to drive control node Qn; the second terminal of transistor T11, the second terminal of transistor T12, the second terminal of transistor T13, and the second terminal of transistor T14 are connected to the low-level terminal VSS; the first terminal of transistor T12 is connected to drive control node Qn; the first terminal of transistor T13 is connected to drive output terminal of output module 120; and the second terminal of transistor T14 is connected to stage transmission output terminal of output module 120.

[0056] For example, the output terminal LC of the noise reduction signal is continuously in a high-level state. When the driving voltage received by the control terminal of the eleventh transistor T11 is low, the twelfth transistor T12, the thirteenth transistor T13 and the fifth transistor T5 will receive a high-level signal and be turned on. The twelfth transistor T12 pulls down the driving control node Qn to a low level, the thirteenth transistor T13 pulls down the driving output terminal of the output module 120 to a low level, and the fourteenth transistor T14 pulls down the stage transmission output terminal of the output module 120 to a low level, thereby realizing noise reduction of the driving control node Qn, the driving output terminal and the stage transmission output terminal of the output module 120.

[0057] Figure 4 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 4 As shown, the first control submodule 131 includes: at least two first transistors T1 connected in series; the control terminal of each first transistor T1 is connected to the first brush control terminal SW1, the first terminal of the first first transistor T1 among the at least two first transistors T1 is connected to the first signal input terminal A of the pull-up module 110 and / or the second signal input terminal B of the pull-up module, and the second terminal of the last first transistor T1 among the at least two first transistors T1 is connected to the low-level terminal VSS.

[0058] For example, if the current level is a refresh row, each first transistor T1 can receive the first refresh signal from the first refresh control terminal SW1 and be turned off, and the pull-up module 110 will normally charge the drive control node Qn; if the current level is a non-refresh row, each first transistor T1 can receive the sustain signal from the first refresh control terminal SW1 and be turned on, pulling down the first signal input terminal A and / or the second signal input terminal B of the pull-up module 110 to a low potential, the pull-up module 110 will stop charging the drive control node Qn, and the output module 120 will not output the gate drive signal to refresh the pixel. By setting at least two first transistors T1 connected in series, the leakage path can be increased, thereby reducing the risk of leakage. Figure 4 Taking the setting of two first transistors T1 as an example.

[0059] Please see Figure 2 and Figure 4 As shown, the second control submodule 132 includes: a second transistor T2; the control terminal of the second transistor T2 is connected to the second brush control terminal SW2, the first terminal of the second transistor T2 is connected to the high-level terminal VGH, and the second terminal of the second transistor T2 is connected to the first signal input terminal A and the second signal input terminal B of the pull-up module 110.

[0060] For example, if the ni-th level is a non-refreshing row and the current level is a refreshing row, the ni-th level will not output the stage pass signal and the gate drive signal. The pull-up module 110 of the current level will not charge the drive control node Qn, and the output module 120 will not be able to output the gate drive signal to refresh the pixel. When the controller determines that the ni-th level is a non-refreshing row and the current level is a refreshing row, it sends the second refresh control signal to the control terminal of the second transistor T2 through the second refresh control terminal SW2. The second transistor T2 will be turned on, and the first signal input terminal A and the second signal input terminal B of the pull-up module 110 will be connected to the high-level terminal VGH. The pull-up module 110 will charge the drive control node Qn, and the output module 120 will output the gate drive signal to refresh the pixel.

[0061] Please see Figure 3 and Figure 4 As shown, the second control submodule 132 includes: at least two second transistors T2 connected in series; the control terminal of each second transistor T2 is connected to the second brush control terminal SW2, the first terminal of the first second transistor T2 among the at least two second transistors T2 is connected to the high-level terminal VGH, and the second terminal of the last second transistor T2 among the at least two second transistors T2 is connected to the first signal input terminal and the second signal input terminal of the pull-up module 110.

[0062] For example, in the ni-th stage, which is a non-refreshing row and the current stage is a refreshing row, the control terminal of each second transistor T2 can receive the second refresh control signal from the second refresh terminal and be turned on. During the working period of the ni-th stage, the first signal input terminal A and the second signal input terminal B of the pull-up module 110 are both connected to the high-level terminal VGH. The pull-up module 110 will charge the drive control node Qn, and the output module 120 will output the gate drive signal to refresh the pixel. By setting at least two second transistors T2 connected in series, the leakage path can be increased, thereby reducing the risk of leakage. Figure 5 Taking the setting of two second transistors T2 as an example.

[0063] Figure 5 This paper shows a circuit diagram of another gate driving unit provided in an embodiment of the present application. Figure 3 Please see Figure 5 As shown, the first brush control module 130 includes: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4; the control terminal of the first transistor T1 is connected to the first brush control terminal SW1, the first terminal of the first transistor T1 is connected to the first signal input terminal of the pull-up module 110, the second signal input terminal of the pull-up module 110, and the first terminal of the second transistor T2, and the second terminal of the first transistor T1 is connected to the high-level terminal VGH, the first terminal of the third transistor T3, and the control terminal of the fourth transistor T4, respectively; the control terminal of the second transistor T2 is connected to the second brush control terminal SW2, and the second terminal of the second transistor T2 is connected to the control terminal of the third transistor T3 and the first terminal of the fourth transistor T4, respectively; the second terminals of the third transistor T3 and the second terminals of the fourth transistor T4 are connected to the low-level terminal VSS.

[0064] For example, if the controller determines that the current level is a refresh row, it sends a first refresh control signal to the control terminal of the first transistor T1 and a second refresh control signal to the control terminal of the second transistor T2. The first transistor T1 is turned on, the second transistor T2 will be turned off, and thus the fourth transistor T4 will be turned on and the third transistor T3 will be turned off. The second terminal of the first transistor T1 is connected to the high-level terminal VGH. Even when the pull-up module 110 does not receive the signal output by the gate drive unit 100 of the ni level, it can still receive the signal input from the high-level terminal VGH through the second terminal of the first transistor T1 during the working period of the ni level to charge the drive control node Qn and refresh the pixels of the current level. If the current row is not refreshed, a sustain control signal is sent to the control terminal of the first transistor T1, and a discharge control signal is sent to the control terminal of the second transistor T2. The first transistor T1 will be turned off, the second transistor T2 will be turned on, the fourth transistor T4 will be turned off, and the third transistor T3 will be turned on. This pulls the first and second signal input terminals of the pull-up module 110 down to the low level VSS. The pull-up module 110 will not charge the drive control node Qn, thus preventing pixel refresh. It should be noted that when the control terminal of the first transistor T1 is high, the control terminal of the second transistor T2 is low, and vice versa. This interlocking of refresh and non-refresh functions improves the reliability of the first refresh control module 130.

[0065] Figure 6 This paper shows a circuit diagram of another gate driving unit provided in an embodiment of this application. Please refer to [the diagram]. Figure 6 As shown, the nth-stage gate drive unit 100 further includes a second local refresh control module 160, which is connected to the drive output terminal and the scan line of the output module 120, and is configured to: in local refresh mode, if the current stage is a refresh line, control the drive output terminal to be electrically connected to the scan line; if the current stage is a non-refresh line, control the drive output terminal to be disconnected from the scan line.

[0066] For example, in partial refresh mode, if the current level is a refresh line, the drive output terminal of the control output module 120 is electrically connected to the scan line, and the output module 120 will output a gate drive signal to the scan line to drive the pixel for partial refresh. If the current level is a non-refresh line, the drive output terminal of the control output module 120 is disconnected from the scan line, and the gate drive signal of the output module 120 will not be output to the scan line. The pixel will maintain its original state and will not be refreshed, thereby reducing the number of pixel refreshes and improving the lifespan of the display panel.

[0067] The second-pass control module 160 includes: a fifteenth transistor T15; the control terminal of the fifteenth transistor T15 is connected to the third-pass control terminal SW3, the first terminal of the fifteenth transistor T15 is connected to the drive output terminal of the output module 120, and the second terminal of the fifteenth transistor T15 is connected to the scan line.

[0068] The third refresh control terminal SW3 can be the control terminal of the controller, specifically a timing controller. When the controller determines that the pixel of the current level is different from the pixel of the previous frame signal, it determines that the current level is a refresh line and needs to output a gate drive signal to update the pixel. The controller sends a third refresh control signal to the control terminal of the fifteenth transistor T15 through the second refresh control module 160. The fifteenth transistor T15 is turned on, thereby controlling the drive output terminal of the output module 120 to connect with the scan line. When the controller determines that the pixel of the current level is the same as the pixel of the previous frame signal, it determines that the current level is a non-refresh line. The current level can maintain the pixel of the previous frame signal, and there is no need to output a gate drive signal to update the pixel. The controller sends a maintenance control signal to the control terminal of the fifteenth transistor T15 through the second refresh control module 160. The fifteenth transistor T15 is turned off, thereby controlling the drive output terminal of the output module 120 to disconnect from the scan line.

[0069] By simultaneously setting the second refresh control module 160 to control the output module 120, working together with the first refresh control module 130, it can be further ensured that when the current level is a refresh row, the gate drive signal is output to refresh the pixel; when the current level is a non-refresh row, the gate drive signal is not output to refresh the pixel, thereby further improving the reliability of the gate drive circuit.

[0070] Figure 7 This document shows a schematic flowchart of a gate driving method provided in an embodiment of this application. Please refer to it. Figure 7 As shown, this method is applied to a gate drive circuit and includes the following steps S110 to S130.

[0071] S110. In global refresh mode, the pull-up module responds to the output signal of the ni-th gate drive unit and charges the drive control node.

[0072] S120, under the action of the drive voltage on the drive control node and the current stage clock signal, the output module outputs the current stage transmission signal and the gate drive signal.

[0073] S130. In partial refresh mode, if the current level is a refresh row, the first refresh control module controls the pull-up module to charge the drive control node; if the current level is a non-refresh row, the first refresh control module controls the pull-up module to stop charging the drive control node.

[0074] In some embodiments, this application also provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the aforementioned gate driving circuit. The output module of the gate driving circuit is connected to at least one scan line.

[0075] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0076] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0077] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes N cascaded gate driving units, and the nth gate driving unit includes: The pull-up module, connected to the drive control node, is configured to charge the drive control node in response to the output signal of the nith gate drive unit in global refresh mode. The output module, which is connected to the drive control node and the clock signal line of the current stage respectively, is configured to output the stage transmission signal and the gate drive signal of the current stage under the action of the drive voltage on the drive control node and the clock signal of the current stage. The first round of brushing control module includes: first control submodule and second control submodule; The first control submodule, connected to the low-level terminal and the first local refresh control terminal, and connected to the first signal input terminal and / or the second signal input terminal of the pull-up module, is configured to: in partial refresh mode, if the current level is a non-refresh line, pull down the first signal input terminal and / or the second signal input terminal of the pull-up module to a low potential according to the first local refresh control signal, so as to control the pull-up module to stop charging the drive control node; if the current level is a refresh line, stop pulling down the first signal input terminal and / or the second signal input terminal of the pull-up module to a low potential according to the sustain control signal, so as to control the pull-up module to charge the drive control node; The second control submodule, connected to the high-level terminal, the second local refresh control terminal, the first signal input terminal of the pull-up module, and the second signal input terminal of the pull-up module, is configured to: in local refresh mode, if the ni-th level is a non-refresh line and the current level is a refresh line, pull the first signal input terminal and the second signal input terminal of the pull-up module to a high potential according to the second local refresh control signal, so as to control the pull-up module to charge the drive control node.

2. The gate driving circuit according to claim 1, characterized in that, The nth-stage gate driving unit further includes: The second refresh control module, connected to the drive output terminal and scan line of the output module, is configured to: in partial refresh mode, if the current level is a refresh line, control the drive output terminal to be electrically connected to the scan line; if the current level is a non-refresh line, control the drive output terminal to be disconnected from the scan line.

3. The gate driving circuit according to claim 1, characterized in that, The first control submodule includes: a first transistor; The control terminal of the first transistor is connected to the control terminal of the first brush, the first terminal of the first transistor is connected to the first signal input terminal of the pull-up module and / or the second signal input terminal of the pull-up module, and the second terminal of the first transistor is connected to the low-level terminal.

4. The gate driving circuit according to claim 1, characterized in that, The first control submodule includes: at least two first transistors connected in series; The control terminal of each of the first transistors is connected to the first brush control terminal, the first terminal of the first of at least two first transistors is connected to the first signal input terminal and / or the second signal input terminal of the pull-up module, and the second terminal of the last of at least two first transistors is connected to the low-level terminal.

5. The gate driving circuit according to claim 1, characterized in that, The second control submodule includes: a second transistor; The control terminal of the second transistor is connected to the control terminal of the second brush, the first terminal of the second transistor is connected to the high-level terminal, and the second terminal of the second transistor is connected to the first signal input terminal and the second signal input terminal of the pull-up module.

6. The gate driving circuit according to claim 1, characterized in that, The second control submodule includes: at least two second transistors connected in series; The control terminal of each second transistor is connected to the control terminal of the second brush, the first terminal of the first second transistor of at least two second transistors is connected to the high-level terminal, and the second terminal of the last second transistor of at least two second transistors is connected to the first signal input terminal and the second signal input terminal of the pull-up module.

7. The gate driving circuit according to claim 1, characterized in that, The first local refresh control module includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; The control terminal of the first transistor is connected to the control terminal of the first brush. The first terminal of the first transistor is connected to the first signal input terminal of the pull-up module, the second signal input terminal of the pull-up module, and the first terminal of the second transistor. The second terminal of the first transistor is connected to the high-level terminal, the first terminal of the third transistor, and the control terminal of the fourth transistor, respectively. The control terminal of the second transistor is connected to the control terminal of the second brush, and the second terminal of the second transistor is connected to the control terminal of the third transistor and the first terminal of the fourth transistor, respectively. The second terminal of the third transistor and the second terminal of the fourth transistor are connected to the low-level terminal.

8. A gate driving method, characterized in that, Applied to the gate drive circuit according to any one of claims 1-7, the method comprises: In global refresh mode, the pull-up module responds to the output signal of the ni-th gate drive unit and charges the drive control node; Under the influence of the drive voltage and the current stage clock signal at the drive control node, the output module outputs the current stage transmission signal and the gate drive signal. In partial refresh mode, if the current level is a refresh row, the first refresh control module controls the pull-up module to charge the drive control node; if the current level is a non-refresh row, the first refresh control module controls the pull-up module to stop charging the drive control node.

9. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-7, wherein the output module of the gate driving circuit is connected to at least one of the scan lines.

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