Display control method and circuit, chip, and display device

Abstract

The application discloses a display control method and circuit, a chip and a display device. The display device comprises a plurality of display modules and corresponding control cards in cascade. The display control method comprises the following steps: acquiring the number of each control card; acquiring the unit delay of each control card; determining the display delay of each control card according to the corresponding number and unit delay; and delaying the frame synchronization signal according to the display delay by each control card, and driving the display module according to the delayed frame synchronization signal. Timing compensation is performed through the display delay, so that the display actions of the control cards at all levels are synchronously triggered at the same time, the picture tearing caused by the multi-level cascade of the control cards is eliminated, and the display quality is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display control method, circuit, chip, and display device. Background Technology

[0002] With the widespread adoption of small-pitch LED screens, the requirements for LED control systems are becoming increasingly stringent. However, the LED pixel area that a single control card can support is limited. When the required pixel area exceeds the maximum capacity of a single control card, multiple control cards need to be cascaded, with each card driving a portion of the LED screen.

[0003] However, during the display process, the display data needs to be transmitted step by step through the cascaded control cards. Each level of control card needs to complete decoding and encoding operations, which introduces a non-negligible transmission delay. When the number of cascaded cards increases, the cumulative delay between the first and last control cards increases significantly, causing the display time of different areas of the screen to be misaligned, resulting in visual abnormalities such as screen tearing and ghosting. Summary of the Invention

[0004] In view of the above problems, the purpose of this application is to provide a display control method, circuit, chip, and display device to eliminate the display asynchrony caused by the delay introduced by the cascading of control cards.

[0005] According to one aspect of this application, a display control method for a display device is provided, the display device including a plurality of cascaded display modules and corresponding control cards, wherein the display control method includes: obtaining a number of each control card; obtaining a unit delay of each control card; determining a display delay of each control card according to the corresponding number and the unit delay; and each control card delaying a frame synchronization signal according to the display delay, and driving the display modules according to the delayed frame synchronization signal.

[0006] Optionally, obtaining the number of each control card includes: sending a data packet to the control card; each level of the control card decoding the received data packet to obtain its own level number and decoded data; obtaining the number and data of the subsequent level control card based on the own level number and the decoded data; encoding the number and data of the subsequent level control card, and providing the encoded new data packet to the subsequent level control card.

[0007] Optionally, each control card drives the display module according to the delayed frame synchronization signal based on the display delay, including: extracting local data from the decoded data; obtaining display data of the corresponding display module and the frame synchronization signal based on the local data; timing based on the frame synchronization signal, and driving the display module according to the display data when the timing duration is equal to the value of the display delay.

[0008] Optionally, the step of obtaining the number and data of the downstream control card based on the local level number and the decoded data includes: adding 1 to the local level number to obtain the number of the downstream control card.

[0009] Optionally, the control cards are numbered sequentially as 1, 2, 3...N, with the control card numbered 1 being the first to receive the data packet. The display delay for each control card is T×(N−i), where i is the control card number, T is the unit delay, N is the total number of control card levels, and i and N are both positive integers, 1≤i≤N.

[0010] Optionally, the step of obtaining the unit delay includes: obtaining the decoding time required for the local control card to decode the received data packets; obtaining the encoding time required for the local control card to encode new data packets; obtaining the buffering time required for the local control card to buffer the decoded data; and obtaining the unit delay based on the decoding time, the encoding time, and the buffering time.

[0011] Optionally, the step of obtaining the unit delay includes: starting timing when the local control card receives a data packet; and ending timing when the local control card sends a data packet, and the obtained timing result is the unit delay of the local control card.

[0012] According to another aspect of this application, a display control circuit for a display device is provided, wherein the display device includes a plurality of cascaded display modules, and the display control circuit includes a control card corresponding to each of the display modules. Each control card includes: a communication unit for acquiring the number of the control card at this level; a timing unit for acquiring the unit delay of the control card at this level; a calculation unit for determining the display delay of the control card at this level based on the corresponding number and the unit delay; and a driving unit for delaying a frame synchronization signal according to the display delay and driving the display module according to the delayed frame synchronization signal.

[0013] Optionally, the communication unit includes: a first interface module for receiving data packets and decoding the received data packets to obtain a local level number and decoded data; a data processing module for caching the decoded data and the local level number; and a second interface module for obtaining the number and data of the downstream control card based on the local level number and the decoded data, encoding the number and data of the downstream control card, and providing the encoded new data packet to the downstream control card. The data processing module is also used to extract local level data from the decoded data. The driving unit obtains corresponding display data and the frame synchronization signal based on the local level data, performs timing based on the frame synchronization signal, and drives the corresponding display module based on the display data when the timing duration is equal to the display delay value.

[0014] Optionally, the second interface module increments the current level number by 1 to obtain the number of the subsequent control card. The control cards are numbered sequentially as 1, 2, 3...N. The control card numbered 1 is the control card that receives the data packet first. The display delay of each control card is T×(N−i), where i is the control card number, T is the unit delay, N is the total number of control card levels, and i and N are both positive integers, 1≤i≤N.

[0015] Optionally, the first interface module is further configured to provide a timing start signal when receiving a data packet, and the second interface module is further configured to provide a timing end signal when sending a data packet, wherein the timing unit performs timing based on the timing start signal and the timing end signal to obtain the unit delay.

[0016] According to another aspect of this application, a chip is provided, wherein the display control circuit of any of the above is included.

[0017] According to another aspect of this application, a display device is provided, comprising: a plurality of cascaded display modules; and a display control circuit of any of the above.

[0018] According to the display control method, circuit, chip, and display device provided in this application, each level of control card calculates the display delay based on its number and unit delay, and performs timing compensation through the display delay, so that each level of control card triggers the display action synchronously at the same time, eliminating screen tearing caused by multi-level cascading of control cards, thereby improving display quality. Attached Figure Description

[0019] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0020] Figure 1 This application shows a schematic diagram of the structure of the display device and display control circuit according to an embodiment of the present application;

[0021] Figure 2 Show Figure 1 The diagram shows the structure of the control card.

[0022] Figure 3 A schematic flowchart illustrating the control method shown in an embodiment of this application is provided.

[0023] Figure 4 The diagram shows the working waveform of the display control method according to an embodiment of this application. Detailed Implementation

[0024] Various embodiments of the present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0025] Furthermore, certain terms are used in this specification and claims to refer to specific components. Those skilled in the art will understand that manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0026] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0027] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0028] It should also be noted that in the various methods and processes of this application, the order of the steps does not imply the order of execution, nor does it constitute any limitation on the implementation process of the embodiments of this application.

[0029] Figure 1 This diagram illustrates the structure of a display device and a display control circuit according to an embodiment of this application. In the following embodiments, an LED display device is used as an example for explanation.

[0030] refer to Figure 1The display device includes multiple cascaded display modules and a display control circuit. The display control circuit includes multiple control cards 1 to N, where N is a positive integer, corresponding to each display module. Each control card drives its corresponding display module. Figure 1 The example shows display modules 1-N and control cards 1-N.

[0031] To more clearly illustrate the display control circuit of the embodiments of this application, Figure 2 It shows Figure 1 The diagram shows the structure of control card i. Control card i can be any one of control cards 1 to N, where 1 ≤ i ≤ N.

[0032] In this embodiment, after connecting the display modules and control cards at each level, the number of each control card is obtained through data packet transmission. The control card number indicates the cascading order of the control cards, that is, the order in which data packets are received. For example, control card number 1 is the first control card to receive data packets, and control card number N is the last control card to receive data packets.

[0033] In some embodiments, the data packet may be numbered once during each data packet transmission. In still other embodiments, the data packet may be numbered once during the first data packet transmission and the number is stored in each control card for subsequent use.

[0034] Combination Figure 1 and Figure 2 During the display process, the host computer 10 sends a data packet to the control card 1. The data packet contains a number, display data for the current frame, and timing control data. It should be understood that the timing control data is the timing information used by the control card to drive the display module based on the display data, including, for example, frame synchronization signals, line synchronization signals, and data enable signals. Specifically, the frame synchronization signal marks the refresh of a frame; the line synchronization signal marks the refresh of a line of pixels; and the data enable signal marks valid display data.

[0035] The i-th level control card includes: a communication unit 110, a timing unit 120, a calculation unit 130, and a drive unit 140.

[0036] The communication unit 110 is used to obtain the local control card number (local number) and local data from the data packets received from the local control card. It also obtains new data packets based on the local number and local data to provide to the downstream control card.

[0037] Specifically, refer to Figure 2 The communication unit 110 includes a first interface module 111, a data processing module 112, and a second interface module 113.

[0038] The first interface module 111 is used to receive the data packet Data_in and decode the data packet Data_in to obtain the current level number i and the decoded data Data'.

[0039] The data processing module 112 is used to cache the decoded data Data' and the current level number i, and send the current level data Data_p extracted from the decoded data Data' to the driver unit 140.

[0040] The second interface module 113 is used to obtain the number and data of the downstream control card based on the current level number i and the decoded data Data'. The second interface module 113 is also used to encode the number and data of the downstream control card and provide the newly encoded data packet Data_out to the downstream control card.

[0041] In some embodiments, the second interface module 113 obtains a new number based on the current level number i by adding 1 to the current level number i. This new number is also the number of the subsequent control card. In this way, each control card can automatically update its number when forwarding data packets.

[0042] In some embodiments, the initial number in the data packet is 1. That is, the control card that receives the data packet first is numbered 1. Subsequently, each level of control card is numbered 2, 3, ... N in sequence during the forwarding of data packets.

[0043] It should be understood that in some embodiments, the second interface module 113 increments the current level number i by 1 to obtain a new number using binary operations. However, this application is not limited to this.

[0044] In some embodiments, the second interface module 113 obtaining new data from the decoded data Data' specifically means treating all of the decoded data Data' as new data. In still other embodiments, the second interface module 113 obtaining new data from the decoded data Data' specifically means treating the remaining data in the decoded data Data', excluding the data at the current level, as new data. In yet other embodiments, the second interface module 113 obtaining new data from the decoded data Data' specifically means processing the decoded data Data' or the remaining data in the decoded data Data' to obtain new data. These processes may include format conversion, compression, or encryption, etc. That is to say, the second interface module 113 can obtain new data according to any relevant technology, and this application does not impose too many restrictions.

[0045] The timing unit 120 is used to acquire the unit delay Td of the control card at this level. This unit delay Td represents the transmission delay introduced during the forwarding of data packets by the communication unit 110. That is, the delay between the time the control card sends data packets and the time it receives data packets.

[0046] In some embodiments, when the first interface module 111 receives a data packet, it provides a timing start signal to trigger the timing unit 120 to start timing; when the second interface module 113 forwards a data packet, it provides a timing end signal to trigger the timing unit 120 to stop timing, thereby obtaining the unit delay Td of the data transmission at this level.

[0047] It should be understood that the timing start signal should be provided earlier than the time when the first interface module 111 performs data packet decoding. For example, the timing start signal can be provided when the first interface module 111 starts receiving data packets. Similarly, the timing end signal should be provided later than the time when the second interface module 113 completes data packet encoding. For example, the timing end signal can be provided when the second interface module 113 completes data packet transmission. In this way, the Td measured by the timing unit 120 can accurately cover the full-link delay of the communication unit 110.

[0048] In some other embodiments, the timing unit 120 may also time the decoding process of the first interface module 111 to obtain the decoding duration, time the data caching process of the data processing module 112 to obtain the caching duration, and time the encoding process of the second interface module 113 to obtain the encoding duration, and add the three together to obtain the unit delay Td.

[0049] The calculation unit 130 is used to determine the display delay Tp of the control card at this level based on the unit delay Td and the level number i.

[0050] In some embodiments, the calculation unit 130 may, for example, perform a multiplication operation, multiplying the unit delay Td measured by the timing unit 120 by the delay level (Ni) that the current control card needs to compensate for, to obtain the display delay Tp of the current control card.

[0051] That is, TP = (Ni) × Td.

[0052] Where i is the number of the control card at this level, N is the total number of control card levels, Td is the unit delay, and Tp is the display delay.

[0053] In some embodiments, the total number of levels N of the control cards is also sent to each control card along with the data packet. The data processing module 112 provides the total number of levels N to the computing unit based on the cached decoded data. In addition, each control card can obtain the total number of levels N according to any relevant technology.

[0054] The driving unit 140 drives the display module according to the display delay frame synchronization signal and the delayed frame synchronization signal.

[0055] In some embodiments, the driving unit 140 may obtain display data and timing control data based on the local data Data_p. The driving unit 140 performs timing based on the frame synchronization signal in the timing control data, and drives the display screen to refresh according to the display data when the timing duration is equal to the display delay Tp.

[0056] In some embodiments, the driving unit 140 may use a countdown or a forward countdown to time the display delay Tp, and this application does not impose any restrictions.

[0057] According to the display control circuit and display device provided in this application, each level of control card calculates the display delay based on its number and unit delay, and performs timing compensation through the display delay, so that each level of control card triggers the display action synchronously at the same time, eliminating screen tearing caused by multi-level cascading of control cards, thereby improving display quality.

[0058] Figure 3 This diagram illustrates a schematic flowchart of a display control method according to an embodiment of this application. This display control method can, for example, be used to achieve synchronous display of different display modules in an LED display device. In some embodiments, this display control method can be implemented via any of the display control circuits described above.

[0059] refer to Figure 3 The display control method includes steps S11 to S14.

[0060] Step S11: Obtain the number of each control card.

[0061] In this embodiment, after connecting the display modules and control cards at each level, the number of each control card is obtained through data packet transmission. The control card number indicates the cascading order of the control cards, that is, the order in which data packets are received. For example, control card number 1 is the first control card to receive data packets, and control card number N is the last control card to receive data packets.

[0062] In some embodiments, the data packet may be numbered once during each data packet transmission. In still other embodiments, the data packet may be numbered once during the first data packet transmission and the number is stored in each control card for subsequent use.

[0063] Specifically, the above numbering process may include the following steps S111 to S114.

[0064] Step S111: Send a data packet to the control card. The data packet contains the number, image data of the image displayed in the current frame, and timing control data.

[0065] In step S112, each level control card decodes the data packets it receives to obtain its level number and decoded data.

[0066] Step S113: Obtain the number and data of the subsequent control card based on the current level number and the decoded data.

[0067] Step S114: Encode the number and data of the downstream control card, and provide the newly encoded data packet to the downstream control card.

[0068] The decoding in step S112 and the encoding in step S114 can be implemented with reference to any relevant technology, and this application does not impose too many restrictions.

[0069] In some embodiments, obtaining a new number based on the current level number in step S113 specifically means adding 1 to the current level number to obtain a new number. This new number is also the number of the subsequent control card. In this way, each control card can automatically update its number when forwarding data packets.

[0070] In some embodiments, the initial number in the data packet is 1. That is, the control card that receives the data packet first is numbered 1. Subsequently, each level of control card is numbered 2, 3, ... N in sequence during the forwarding of data packets.

[0071] It should be understood that in some embodiments, step S113, which adds 1 to the current level number to obtain a new number, is a binary operation. However, this application is not limited to this.

[0072] In some embodiments, obtaining new data from the decoded data in step S113 specifically means treating all the decoded data as new data. In still other embodiments, obtaining new data from the decoded data in step S113 specifically means treating the remaining data in the decoded data, excluding the data at the current level, as new data. In yet another embodiment, obtaining new data from the decoded data in step S113 specifically means processing the decoded data or the remaining data in the decoded data to obtain new data. These processes may include format conversion, compression, or encryption. That is to say, new data can be obtained in step S113 using any relevant technology, and this application does not impose excessive limitations.

[0073] Step S12: Obtain the unit delay of the control card. This unit delay represents the transmission delay introduced during the forwarding of data packets through the local control card. In other words, it is the delay between the time the data packet is sent and the time it is received by the local control card.

[0074] In some embodiments, a timing start signal may be provided when the local control card receives a data packet to start timing; and a timing end signal may be provided when the local control card sends a data packet to stop timing, thereby obtaining the unit delay of local data transmission.

[0075] It should be understood that the start time of the timing should be earlier than the time when the control card at this level begins decoding the data packets. For example, the start signal can be provided when the control card at this level begins receiving data packets. Similarly, the stop time of the timing should be later than the time when the control card at this level completes encoding the data packets. For example, the end signal can be provided when the control card at this level completes transmitting the data packets. This helps to improve the accuracy of unit delay.

[0076] In some other embodiments, the decoding time required for the local control card to decode the received data packets, the encoding time required for the local control card to encode new data packets, and the buffering time required for the local control card to buffer the decoded data can be obtained separately, and the sum of the three can be used as the unit delay.

[0077] Step S13: Determine the display delay of each control card according to the corresponding number and unit delay.

[0078] In some embodiments, the display delay of the control card can be obtained by multiplying the unit delay by the number of delay levels that the control card needs to compensate.

[0079] That is, TP = (Ni) × Td.

[0080] Where i is the number of the control card at this level, N is the total number of control card levels, Td is the unit delay, and Tp is the display delay.

[0081] In some embodiments, the total number of levels N of the control cards is also sent to each control card along with the data packet. Furthermore, each control card can obtain the total number of levels N according to any relevant technology.

[0082] In step S14, each control card drives the display module according to the display delay frame synchronization signal and the delayed frame synchronization signal.

[0083] In some embodiments, step S14 may include:

[0084] In step S141, the data of this level is extracted from the decoded data;

[0085] In step S142, display data and timing control data of the corresponding display module are obtained based on the data at this level. This timing control data includes, for example, a frame synchronization signal; and

[0086] In step S143, timing is performed based on the frame synchronization signal, and when the timing duration equals the display delay value, the display module is driven according to the display data. The method for timing the display delay can be either a countdown or a forward countdown; this application does not impose any restrictions.

[0087] Figure 4The diagram shows the working waveform of the display control method according to an embodiment of this application. The times t1, t2, ..., tn-1 and tn are the times when control card 1, control card 2, ..., control card n-1 and control card n receive the frame synchronization signal, respectively.

[0088] Ideally, each control card should receive the frame synchronization signal synchronously, i.e., t1=t2=…=tn.

[0089] However, in actual transmission, the signal propagates step by step in the cascaded link, which inevitably introduces an inherent transmission delay, resulting in t1 < t2 < ... < tn.

[0090] exist Figure 4 In this example, the inherent delay (i.e., unit delay) introduced by each level of control card is the same, Td. Therefore, t2 = t1 + Td, t3 = t2 + Td = t1 + 2Td, ..., tn = t1 + (n−1)Td.

[0091] When displaying according to the display control method provided in this application, each level of control card starts timing after the frame synchronization signal is triggered, based on the display delay Tp calculated by itself, and drives the display module to display when the timing duration is equal to the value of the display delay Tp.

[0092] For control card 1, Tp = (N-1) × Td, so its display time is t1 + Tp = t1 + (N-1) Td = tn; for control card 2, Tp = (N-2) × Td, so its display time is t2 + Tp = t2 + (N-2) Td = t1 + Td + (N-2) Td = tn; and so on. The display time of each level of control card is precisely calibrated to tn, thereby achieving strict synchronization of the entire link display and eliminating visual misalignment caused by cascade transmission delay.

[0093] This application also provides a chip that may include the display control circuit of any of the above embodiments, and thus may also achieve any of the above-described beneficial effects.

[0094] The embodiments described above, as per the examples of this application, do not exhaustively describe all details, nor do they limit this application to the specific embodiments described above. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. The scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A display control method for a display device, the display device comprising multiple cascaded display modules and corresponding control cards, in, The display control method includes: Obtain the number of each control card; Obtain the unit delay for each control card; The display delay of each control card is determined according to the corresponding number and the unit delay; and Each control card drives the display module according to the display delay frame synchronization signal and the delayed frame synchronization signal.

2. The display control method according to claim 1, wherein, The process of obtaining the number of each control card includes: Send data packets to the control card; Each level of the control card decodes the data packets it receives to obtain the level number and the decoded data; The number and data of the subsequent control card are obtained based on the current level number and the decoded data; The number and data of the downstream control card are encoded, and the new data packet obtained by encoding is provided to the downstream control card.

3. The display control method according to claim 2, wherein, Each control card drives the display module according to the display delay frame synchronization signal and the delayed frame synchronization signal, including: Extract the data at this level from the decoded data; Based on the data at this level, the display data of the corresponding display module and the frame synchronization signal are obtained; Timing is performed based on the frame synchronization signal, and when the timing duration is equal to the display delay value, the display module is driven according to the display data.

4. The display control method according to claim 2, wherein, The steps for obtaining the number and data of the subsequent control card based on the current level number and the decoded data include: Add 1 to the current level number to obtain the number of the subsequent level control card.

5. The display control method according to claim 4, wherein, The control cards are numbered sequentially as 1, 2, 3...N, with the control card numbered 1 being the first to receive the data packet. The display delay for each control card is T×(N−i), where i is the control card number, T is the unit delay, N is the total number of control card levels, and i and N are both positive integers, 1≤i≤N.

6. The display control method according to claim 2, wherein, The steps for obtaining the unit delay include: Obtain the decoding time required for the control card at this level to decode the received data packets; The encoding time required when obtaining new data packets from the current level control card; Obtain the buffer duration required for the decoded data to be cached by the control card at this level; and The unit delay is obtained based on the decoding duration, the encoding duration, and the buffer duration.

7. The display control method according to claim 1, wherein, The steps for obtaining the unit delay include: The timer starts when the control card at this level receives a data packet; and The timing ends when the control card at this level sends a data packet, and the obtained timing result is the unit delay of the control card at this level.

8. A display control circuit for a display device, wherein, The display device includes multiple cascaded display modules, and the display control circuit includes control cards corresponding to each display module. Each of the control cards includes: The communication unit is used to obtain the number of the control card at this level; The timing unit is used to obtain the unit delay of the control card at this level; A calculation unit is configured to determine the display delay of the control card at this level based on the corresponding number and the unit delay; and A driving unit is configured to drive the display module according to the display delay frame synchronization signal and the delayed frame synchronization signal.

9. The display control circuit according to claim 8, wherein, The communication unit includes: The first interface module is used to receive data packets and decode the received data packets to obtain the current level number and decoded data; The data processing module caches the decoded data and the local number; and The second interface module obtains the number and data of the downstream control card based on the current level number and the decoded data, encodes the number and data of the downstream control card, and provides the encoded new data packet to the downstream control card. The data processing module is also used to extract local data from the decoded data. The driving unit obtains the corresponding display data and the frame synchronization signal based on the local data, and performs timing based on the frame synchronization signal. When the timing duration is equal to the value of the display delay, the driving unit drives the corresponding display module based on the display data.

10. The display control circuit according to claim 9, wherein, The second interface module increments the current level number by 1 to obtain the number of the subsequent control card. The control cards are numbered sequentially as 1, 2, 3...N, with the control card numbered 1 being the first to receive the data packet. in, The display delay for each control card is T×(N−i), where i is the control card number, T is the unit delay, N is the total number of control card levels, and i and N are both positive integers, 1≤i≤N.

11. The display control circuit according to claim 9, wherein, The first interface module is also used to provide a timing start signal when receiving data packets. The second interface module is also used to provide a timing end signal when sending data packets. The timing unit performs timing based on the timing start signal and the timing end signal to obtain the unit delay.

12. A chip, wherein, Includes the display control circuit as described in any one of claims 8-11.

13. A display device, wherein, include: Multiple cascaded display modules; as well as The display control circuit as described in any one of claims 8-11.

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