Gate driving circuit, driving method thereof and display panel

Abstract

Embodiments of the present application disclose a gate driving circuit, a driving method thereof and a display panel. The gate driving circuit comprises a plurality of cascaded shift registers, each of which comprises a control module, a stage transmission output module and a gate output module; the control module is connected with the stage transmission output module and the gate output module; the gate output module is connected with a pulse mode control signal; the control module is configured to control an output end of the stage transmission output module to output a stage transmission signal according to at least an input signal and at least one clock signal; and the plurality of shift registers are configured to control output ends of the gate output modules of the plurality of shift registers to output a first pulse simultaneously in a first output mode and to output a second pulse in turn in a second output mode according to the pulse mode control signal. The embodiments of the present application can improve the reliability of the output signal of the gate driving circuit and / or improve the display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a gate driving circuit and its driving method, and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display panels needs improvement. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above technical background, this application provides a gate driving circuit and driving method thereof, and a display panel, which aims to improve the performance of the display panel.

[0005] This application provides a gate driving circuit, characterized in that it includes: multiple cascaded shift registers.

[0006] The shift register includes: a control module, a stage output module, and a gate output module; The control module is connected to the stage output module and the gate output module. The gate output module receives the pulse mode control signal. The control module is used to transmit signals from the output terminal of the control stage module based on at least the input signal and at least one clock signal. Multiple shift registers are used to control the output terminals of the gate output modules of the multiple shift registers to simultaneously output a first pulse according to the pulse mode control signal. In the first output mode, the output terminals of the gate output modules of the multiple shift registers output a second pulse sequentially.

[0007] This application also provides a display panel, including at least one gate driving circuit provided in any embodiment of this application.

[0008] This application embodiment also provides a driving method, applied to the gate driving circuit provided in this application embodiment, the driving method including: In the first output mode, the gate output modules of multiple shift registers are controlled to simultaneously output the first pulse; In the second output mode, the gate output modules of multiple shift registers output the second pulse sequentially.

[0009] In this embodiment, the control module is connected to the stage output module and the gate output module, and the gate output module receives a pulse mode control signal. The control module is used to control the output terminal of the stage output module to output a stage transmission signal based on at least the input signal and at least one clock signal. Multiple shift registers are used to control the output terminals of the gate output modules of the multiple shift registers to simultaneously output a first pulse (e.g., a simultaneous pulse) in a first output mode, and in a second output mode, the output terminals of the gate output modules of the multiple shift registers to sequentially output a second pulse (e.g., a progressive scan pulse), thereby separating the stage transmission signal and the gate drive signal. The stage transmission signal and the gate drive signal are output through different modules, which improves the reliability of the gate drive circuit signal output, ensures stable cascading of shift registers, and allows the same gate drive circuit to output simultaneous pulses and progressive scan pulses. This enables higher pixel resolution (PPI), improves display effect, facilitates narrow bezels, and increases screen-to-body ratio. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of this application.

[0012] Figure 2 This is a timing waveform diagram of a gate driving circuit provided in an embodiment of this application.

[0013] Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of this application.

[0014] Figure 4 The timing waveform diagram is provided for another gate drive circuit according to an embodiment of this application.

[0015] Figure 5 This is a schematic diagram of the structure of a shift register provided in an embodiment of this application.

[0016] Figure 6 The timing waveform diagram of a shift register provided in an embodiment of this application is shown.

[0017] Figure 7 The timing waveform diagram of another shift register provided in the embodiments of this application.

[0018] Figure 8 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0019] Figure 9 The timing waveform diagram of another shift register provided in the embodiments of this application.

[0020] Figure 10 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0021] Figure 11 This is a schematic diagram of another gate drive circuit provided in an embodiment of this application.

[0022] Figure 12 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0023] Figure 13 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0024] Figure 14 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0025] Figure 15 The timing waveform diagram is provided for another gate drive circuit according to an embodiment of this application.

[0026] Figure 16 The timing waveform diagram is provided for another gate drive circuit according to an embodiment of this application.

[0027] Figure 17 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0028] Figure 18 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0029] Figure 19 This is a timing waveform diagram of a first type of display frame provided in an embodiment of this application.

[0030] Figure 20 This is a timing waveform diagram of a second type of display frame provided in an embodiment of this application.

[0031] Figure 21 This is a schematic diagram of another display panel structure provided in an embodiment of this application.

[0032] Figure 22 This is a flowchart illustrating a driving method provided in an embodiment of this application.

[0033] Figure 23 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0035] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0036] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0037] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0038] For certain elements, terms such as "above" or "over" are sometimes used when describing the position of an element located in the Z direction, and "below" or "under" are used when describing the position of an element located in the opposite direction. Furthermore, when using terms such as "above," "over," "below," "under," and "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly connected, but also the state where the two elements are separated by a gap or other elements. Additionally, the terms "first," "second," and "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance or order. At least one may include one or more. At least one may include one or more. At least part may include part or all. The first direction and the second direction intersect, for example, they may be perpendicular. At least one may include one or more. The connection may include a direct connection or an indirect connection. The connection may be an electrical connection. Equal or identical means equal or identical within a reasonable range of errors such as manufacturing errors, process errors, and measurement errors. The transistor may be a P-type transistor or an N-type transistor. A P-type transistor is turned on when its gate is connected to a low level and turned off when its gate is connected to a high level. An N-type transistor conducts when its gate is connected to a high level and turns off when its gate is connected to a low level. One of the first and second terminals of the same transistor can be the source, and the other can be the drain. P-type transistors can include polysilicon transistors. N-type transistors can include metal-oxide transistors, such as IGZO (indium gallium zinc oxide) transistors. For example, all transistors in a pixel circuit have the same channel type, and the active layer material of each transistor (or all transistors) in the pixel circuit is the same, thus simplifying the manufacturing process.

[0039] This application provides a gate driving circuit. Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of this application. Figure 2 A timing waveform diagram of a gate drive circuit provided in an embodiment of this application. See also... Figure 1 and Figure 2 The gate drive circuit 400 includes a plurality of cascaded shift registers 401.

[0040] The shift register 401 includes: a control module 10, a stage output module 20, and a gate output module 30.

[0041] The control module 10 is connected to the stage output module 20 and the gate output module 30. The gate output module 30 is connected to the pulse mode control signal RST.

[0042] The control module 10 is used to transmit the Carry output stage signal P3 to the output terminal of the control module 20 based on at least the input signal SIN and at least one clock signal (e.g., the first clock signal SCK1).

[0043] Multiple shift registers 401 are used to control the output terminals Sout of the gate output modules 30 of the multiple shift registers 401 to simultaneously output the first pulse P1 (i.e., simultaneous pulse) according to the pulse mode control signal RST in the first output mode Z1. In the second output mode Z2, the output terminals Sout of the gate output modules 30 of the multiple shift registers 401 sequentially output the second pulse P2.

[0044] For example, Figure 1 and Figure 2 An example is drawn of the first to fourth stage shift registers 401. By controlling the level of the pulse mode control signal RST, the output terminals Sout_1 to Sout_4 of the gate output module 30 of the first to fourth stage shift registers 401 simultaneously output the first pulses P11 to P14 in the first output mode Z1, and the output terminals Sout_1 to Sout_4 of the gate output module 30 of the first to fourth stage shift registers 401 sequentially output the second pulses P21 to P24 in the second output mode Z2.

[0045] Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. For example, combined with... Figures 1 to 3 As shown, in the first output mode (i.e., the simultaneous mode), the output terminals Sout of the gate output modules 30 of multiple shift registers 401 simultaneously output the first pulse P1 to the switching transistor M2 of the multi-row (e.g., all rows, including the first and last rows) pixel circuit 200, so that the switching transistor M2 of the multi-row pixel circuit 200 is turned on simultaneously. The switching transistor M2 of the multi-row pixel circuit 200 can transmit the initialization voltage Vini to the gate of the driving transistor M1 to initialize the gate of the driving transistor M1, that is, the gate of the driving transistor M1 of the multi-row (e.g., all rows, including the first and last rows) pixel circuit 200 is initialized simultaneously.

[0046] For example, in the second output mode (i.e., line-by-line scanning mode), the output terminals Sout of the gate output modules 30 of the multiple shift registers 401 sequentially output the second pulse P2 to the switching transistor M2 of the multi-line pixel circuit 200, so that the switching transistor M2 of the multi-line pixel circuit 200 is turned on line by line. The switching transistor M2 of the multi-line pixel circuit 200 can transmit the data voltage Vdata to the gate of the driving transistor M1 to realize the writing of data line by line to the multi-line (e.g., all lines, including the first and last lines) pixel circuit 200.

[0047] For example, in simultaneous light emission mode, the gates of the light emission control transistors M3 of the multi-row pixel circuit 200 are simultaneously turned on, causing the light emission elements 100 connected to the multi-row (e.g., all rows) pixel circuits 200 to emit light simultaneously. Simultaneous light emission mode may include a first output mode. In simultaneous light emission mode or the first output mode, the voltage of the input signal SIN at the input terminal of the first-stage shift register 401 remains unchanged, i.e., constant, or DC potential. No pulse signal is input to the input terminal of the first-stage shift register 401, so the input signal SIN will not affect the output of the gate output module 30. In simultaneous light emission mode or the first output mode, the gate output module 30 of the shift register 401 outputs the pulse mode control signal RST as a gate drive signal to the output terminal Sout of the gate output module 30. Multiple shift registers 401 can be connected to the same pulse mode control signal RST. Therefore, by controlling the high and low levels of the mode control signal RST, the output terminal Sout of the gate output module 30 of multiple shift registers 401 can be controlled to be high or low at the same time, thereby enabling the light-emitting elements connected to multiple rows of pixel circuits to emit light or not emit light at the same time.

[0048] For example, in the progressive emission mode, the gate of the light-emitting control transistor M3 of the multi-row pixel circuit 200 receives a conduction level row by row, so that the light-emitting elements 100 connected to the multi-row pixel circuit 200 emit light row by row. The progressive emission mode may include a second output mode Z2. In the progressive emission mode or the second output mode, the voltage of the pulse mode control signal RST remains unchanged, that is, a DC potential, which can be a disabled level, so that the output modes and output waveforms of the gate output module 30 and the stage transmission output module 20 in the same shift register 401 are the same. In the progressive emission mode or the second output mode, the input signal SIN at the input terminal of the first stage shift register 401 includes the pulse signal P4, so the input signal SIN will affect the output of the stage transmission output module 20 and the gate output module 30, so that the output terminals Carry of the stage transmission output modules 20 of the multiple shift registers 401 output the stage transmission signal stage by stage, and the output terminals Sout of the gate output modules 30 of the multiple shift registers 401 output the second pulse P2 stage by stage, thereby realizing that the light-emitting elements connected to the multi-row pixel circuit emit light row by row. The pulse signal P4 (e.g., a low-level pulse) may overlap with the effective level pulse (e.g., a low-level pulse) of the second clock signal SCK2. The pulse width of the pulse signal P4 may be W3.

[0049] In the second output mode, shift register 401 is used to shift the pulse signal P4 of the input signal SIN at the input terminal to obtain the stage transmission signal P3, which is output to the output terminal Carry of the stage transmission output module 20, and to obtain the second pulse P2, which is output to the output terminal Sout of the gate output module 30.

[0050] In related technologies, the gate output module 30 is not provided. Instead, the stage output module 20 is connected to the pulse mode control signal RST, controlling the stage output module 20 of multiple shift registers 401 to output two types of pulses: simultaneous pulses and stage-by-stage output pulses to the pixel circuit. Furthermore, the stage output module 20 outputs stage-transfer pulse signals to the input of the control module of the next-stage shift register. This means the stage-transfer signal and the gate drive signal are not separated. Consequently, if the gate drive signal output by the current stage shift register becomes abnormal due to disturbance, all stage shift registers will fail because they cannot be cascaded. Additionally, because the lower branch of the stage output module 20 has clock signal coupling fluctuations, there will be losses when the output waveform of the stage output module 20 is the same as that corresponding to RST; that is, the waveform fluctuates with the clock signal, resulting in unstable output. This means the stage output module 20 has a large load and is prone to output abnormalities.

[0051] This embodiment of the application sets up a stage transmission output module 20 and a gate output module 30. The gate output module 30 is connected to a pulse mode control signal RST. The stage transmission output module 20 outputs a stage transmission signal, and the gate output module 30 outputs gate drive signals corresponding to two output modes. According to the pulse mode control signal RST, multiple shift registers 401 control the output terminals Sout of the gate output modules 30 of the multiple shift registers 401 to simultaneously output the first pulse P1 in the first output mode Z1. In the second output mode Z2, the output terminals Sout of the gate output modules 30 of the multiple shift registers 401 sequentially output the second pulse P2. That is, the stage transmission signal and the gate drive signal are separated. The stage transmission signal and the gate drive signal are output through different modules, which can improve the reliability of signal output, improve the display effect, and achieve the effects of compressing the bezel, enhancing the output driving force, and improving the output stability in a high pixel resolution PPI display panel.

[0052] In this embodiment, the control module 10 is connected to the stage output module 20 and the gate output module 30, which is connected to the pulse mode control signal RST. The control module 10 is used to control the output terminal Carry of the stage output module 20 to output the stage transmission signal P3 based on at least the input signal SIN and at least one clock signal. Multiple shift registers 401 are used to control the output terminals Sout of the gate output modules 30 of the multiple shift registers 401 to simultaneously output the first pulse P1 (i.e., simultaneous pulse) under the first output mode Z1, and under the second output mode Z2, the output terminals Sout of the gate output modules 30 of the multiple shift registers 401 sequentially output the second pulse P2, thereby separating the stage transmission signal and the gate drive signal. The stage transmission signal and the gate drive signal are output through different modules, which can improve the reliability of the gate drive circuit signal output, ensure the stable cascading of shift registers, and allow the same gate drive circuit to output simultaneous pulses and progressive scan pulses, achieving higher pixel resolution (PPI), which is beneficial for narrow bezels and increasing screen ratio.

[0053] For example, see Figure 2 In the first output mode Z1, the start time (e.g., time t11) and end time (e.g., time t12) of the first pulse P1 output by the output terminals Sout of the gate output modules 30 of the multiple shift registers 401 are the same. That is, in the first output mode Z1, the width of the first pulse P1 output by the output terminals Sout of the multiple shift registers 401 is the same, for example, W1. The width of the first pulse P1 can be arbitrarily set as needed.

[0054] For example, see Figure 2 In the second output mode Z2, the second pulse P2 output by the gate output module 30 of the (i+1)th stage shift register 401 lags behind the second pulse P2 output by the gate output module 30 of the i-th stage shift register 401 lags behind the second pulse P2 output by the gate output module 30 of the i-th stage shift register 401 lags behind the second pulse P21 output by the gate output module 30 of the first ...

[0055] For example, see Figure 2 In the second output mode Z2, the second pulse P2 output by the gate output module 30 of the (i+1)th stage shift register 401 does not overlap with the second pulse P2 output by the gate output module 30 of the i-th stage shift register 401.

[0056] In some embodiments, in the second output mode Z2, the second pulse P2 output by the output terminal Sout of the gate output module 30 of the (i+1)th stage shift register 401 overlaps with the second pulse P2 output by the output terminal Sout of the gate output module 30 of the i-th stage shift register 401.

[0057] For example, see Figure 2 The effective level (e.g., low level) of the first pulse P1 is the same as the effective level (e.g., low level) of the second pulse P2.

[0058] For example, the effective level of the first pulse P1 and the effective level of the second pulse P2 are both low, or the effective level of the first pulse P1 and the effective level of the second pulse P2 are both high.

[0059] Figure 4 A timing waveform diagram of another gate drive circuit provided in an embodiment of this application. For example, in the same display frame, the pulse mode control signal RST includes a transition edge (see [reference]). Figure 2 ) or at least two transition edges (see Figure 4 ).

[0060] For example, the transition edge can be a rising edge or a falling edge. A rising edge occurs when the signal transitions from a low level to a high level. A falling edge occurs when the signal transitions from a high level to a low level. The number of transition edges of the pulse mode control signal RST within a single display frame can be set as needed to achieve various functions.

[0061] For example, in at least a portion of the time period of the first output mode Z1, the voltage of the pulse mode control signal RST is a first level V1, and in the second output mode Z2, the voltage of the pulse mode control signal RST is a second level V2, where one of the first level V1 and the second level V2 is low and the other is high.

[0062] For example, see Figure 2 Within the same display frame, the voltage of the pulse mode control signal RST initially reaches a first level V1, then transitions to a second level V2. Alternatively, see, for example, [link to relevant documentation]. Figure 4 In the same display frame, the voltage of the pulse mode control signal RST starts at the second level V2, then jumps to the first level V1, and then jumps back to the second level V2.

[0063] For example, see Figure 2 or Figure 4 In the first output mode Z1, the voltage of the pulse mode control signal RST is a DC voltage or a variable voltage.

[0064] For example, the width of the first pulse P1 (which can be W1) is greater than the width of the second pulse P2 (which can be W2). That is, W1 is greater than W2. For example, W3 is greater than or equal to W2.

[0065] For example, see Figure 2 or Figure 4 In the first output mode Z1, the voltage output by the gate output module 30 of the multiple shift registers 401 simultaneously changes from high level to low level, and / or simultaneously changes from low level to high level.

[0066] For example, see Figure 2 or Figure 4 In the second output mode Z2, the width of the second pulse P2 output by the output terminal Sout of the gate output module 30 of the multiple shift registers 401 is the same, for example, both are W2.

[0067] For example, the effective level of the first pulse P1 and the effective level of the second pulse P2 are the first level V1, such as a low level.

[0068] In some embodiments, the effective level of the first pulse P1 and the effective level of the second pulse P2 are the first level V1, such as a high level.

[0069] Figure 5 This is a schematic diagram of a shift register provided in an embodiment of this application. For example, see... Figure 5 The gate output module 30 includes a first output unit 31 and a second output unit 32.

[0070] The first terminal of the first output unit 31 is connected to the pulse mode control signal RST. The second terminal of the first output unit 31 and the second terminal of the second output unit 32 are connected to the output terminal Sout of the gate output module 30. The first terminal of the second output unit 32 is connected to the first clock signal SCK1 or the power supply signal or the DC potential.

[0071] The control terminal of the first output unit 31 is connected to the first output terminal out1 of the control module 10, for example, to the third node N3. The control terminal of the second output unit 32 is connected to the second output terminal out2 of the control module 10.

[0072] The first output unit 31 is used to turn on the first output mode Z1 and output the pulse mode control signal RST to the output terminal Sout of the gate output module 30. With this configuration, the output terminals Sout of the gate output modules 30 of multiple shift registers 401 can simultaneously output the first pulse P1 (i.e., simultaneous pulse).

[0073] The second output unit 32 is used to turn off in the first output mode Z1.

[0074] The second output units 32 of multiple shift registers 401 are sequentially turned on in the second output mode Z2, so that the output terminals Sout of the gate output modules 30 of the multiple shift registers 401 sequentially output the second pulse P2. For example, the second output unit 32 of the first-stage shift register 401 is turned on first, then the second output unit 32 of the second-stage shift register 401 is turned on, then the second output unit 32 of the third-stage shift register 401 is turned on, and then the second output unit 32 of the fourth-stage shift register 401 is turned on. For example, when the second output unit 32 is turned on, the first clock signal SCK1, power supply signal, or DC potential connected to the first terminal of the second output unit 32 can be output to obtain the second pulse P2.

[0075] For example, see Figure 5 The first output unit 31 includes a first transistor T9, the first electrode of the first transistor T9 is the first terminal of the first output unit 31, the second electrode of the first transistor T9 is the second terminal of the first output unit 31, and the gate of the first transistor T9 is the control terminal of the first output unit 31.

[0076] For example, the first transistor T9 can be a P-type transistor (see [reference]). Figure 5 ) or N-type transistor.

[0077] For example, see Figure 5 The second output unit 32 includes a second transistor T10, the first electrode of the second transistor T10 is the first terminal of the second output unit 32, the second electrode of the second transistor T10 is the second terminal of the second output unit 32, and the gate of the second transistor T10 is the control terminal of the second output unit 32.

[0078] For example, the second transistor T10 can be a P-type transistor (see [reference]). Figure 5 ) or N-type transistor.

[0079] For example, see Figure 5 The shift register 401 also includes a first coupling module 33. The first coupling module 33 is connected between the first terminal of the first output unit 31 and the control terminal of the first output unit 31.

[0080] For example, when the pulse mode control signal RST transitions from the second level V2 to the first level V1 (e.g., when the pulse mode control signal RST transitions from a high level to a low level), the voltage at the control terminal of the first output unit 31 can be reduced through the coupling effect of the first coupling module 33. This allows the first output unit 31 to conduct more fully, enabling the pulse mode control signal RST to be output losslessly to the second terminal of the first output unit 31 or the output terminal Sout of the gate output module 30, ensuring the quality of waveform reproduction. For example, the control terminal of the first output unit 31 can be connected to the fourth node N4.

[0081] For example, see Figure 5 The first coupling module 33 includes a first capacitor C2, which is connected between the first terminal of the first output unit 31 and the control terminal of the first output unit 31.

[0082] For example, see Figure 5 The shift register 401 also includes a first protection module 34. The first output terminal out1 of the control module 10 is connected to the control terminal of the first output unit 31 via the first protection module 34. The control terminal of the first protection module 34 is connected to a conduction level, a DC potential, or a second potential signal VGL.

[0083] For example, the first output terminal out1 of the control module 10 can be connected to the third node N3. The first protection module 34 can isolate the first output terminal out1 of the control module 10 from the control terminal of the first output unit 31. That is, the first protection module 34 can isolate the third node N3 and the fourth node N4, avoiding or improving the phenomenon that the voltage of the fourth node N4 is too low when the pulse mode control signal RST jumps from the second level V2 to the first level V1, causing the transistor connected to the third node N3 in the control module 10 to be damaged. The first protection module 34 is equivalent to being normally open.

[0084] For example, see Figure 5 The first protection module 34 includes a third transistor T11. The first output terminal of the control module 10 is connected to the control terminal of the first output unit 31 via the third transistor T11. The gate of the third transistor T11 is connected to an on-level, a DC potential, or a second potential signal VGL.

[0085] For example, the third transistor T11 can be a P-type transistor (see [reference]). Figure 5 ) or N-type transistor.

[0086] For example, see Figure 2 During at least a portion of the first output mode Z1, the gate output module 30 and the stage output module 20 in the same shift register 401 output different values. For example, see... Figure 2During at least a portion of the first output mode Z1, one of the gate output module 30 and the stage output module 20 in the same shift register 401 outputs a high level, while the other outputs a low level. For example, during at least a portion of the first output mode Z1, in the same shift register 401, the output terminal Sout of the gate output module 30 outputs a first level V1, such as a low level, and the output terminal Carry of the stage output module 20 outputs a second level V2, such as a low level.

[0087] For example, see Figure 2 In the second output mode Z2, while the gate output module 30 in the same shift register 401 simultaneously outputs the second pulse P2, the output terminal Carry of the stage transmission module 20 outputs the stage transmission signal P3. The pulse widths of the second pulse P2 and the stage transmission signal are the same, for example, both are W2. See also Figure 2 In the second output mode Z2, the output terminals Carry_1 to Carry_4 of the first to fourth stage shift registers 401 of the stage transmission output module 20 sequentially output the stage transmission signals P31 to P34.

[0088] For example, see Figure 1 The output terminal Carry of the stage output module 20 of the i-th stage shift register 401 is connected to the input terminal (which can be connected to the input signal SIN) of the control module 10 of the (i+1)-th stage shift register 401.

[0089] For example, see Figure 1 The stage transfer signal P3 output by the stage transfer output module 20 of the i-th stage shift register 401 is used as the input signal SIN of the control module 10 of the (i+1)-th stage shift register 401. Here, i is an integer greater than or equal to 1.

[0090] For example, the input signal SIN_1 of the control module 10 of the first-stage shift register 401 is provided by the start signal line or the driver chip, and the input terminal of the control module 10 of the first-stage shift register 401 (which can be connected to the input signal SIN_1) is connected to the start signal line or the driver chip.

[0091] For example, see Figure 5 The level output module 20 includes a third output unit 21 and a fourth output unit 22.

[0092] The first terminal of the third output unit 21 is connected to the first potential signal VGH, the second terminal of the third output unit 21 and the second terminal of the fourth output unit 22 are connected to the output terminal Carry of the stage transmission output module 20, and the first terminal of the fourth output unit 22 is connected to the first clock signal SCK1.

[0093] The control terminal of the third output unit 21 is connected to the first output terminal out1 of the control module 10. The control terminal of the fourth output unit 22 is connected to the second output terminal out2 of the control module 10.

[0094] For example, when the third output unit 21 is turned on, the first potential signal VGH connected to the first terminal of the third output unit 21 can be transmitted to the output terminal Carry of the stage transmission module 20. For example, when the fourth output unit 22 is turned on, the first clock signal SCK1 connected to the first terminal of the fourth output unit 22 can be transmitted to the output terminal Carry of the stage transmission module 20, so that the output terminal Carry of the transmission module 20 outputs the stage transmission signal P3.

[0095] For example, the fourth output unit 22 is used to turn off in the first output mode Z1.

[0096] For example, the fourth output unit 22 of multiple shift registers 401 is sequentially turned on in the second output mode Z2, so that the output terminal Carry of the stage transmission output module 20 of multiple shift registers 401 sequentially outputs the stage transmission signal P3. For example, the fourth output unit 22 of the first stage shift register 401 is turned on first, then the fourth output unit 22 of the second stage shift register 401 is turned on, then the fourth output unit 22 of the third stage shift register 401 is turned on, and then the fourth output unit 22 of the fourth stage shift register 401 is turned on.

[0097] For example, in the second output mode Z2, the stage transfer signal P3 output by the stage transfer output module 20 of the (i+1)th stage shift register 401 lags behind the stage transfer signal P3 output by the stage transfer output module 20 of the i-th stage shift register 401 lags behind the stage transfer signal P3 output by the stage transfer output module 20 of the i-th stage shift register 401 lags behind the stage transfer signal P31 output by the stage transfer output module 20 of the first stage shift register 401 lags behind the stage transfer signal P31 output by the stage transfer output module 20 of the first stage shift register 401 lags behind the stage transfer signal P31 output by the stage transfer output module 20 of the first stage shift register 401 lags behind the stage transfer signal P32 ...2 output by the stage transfer output module 20 of the first stage shift register 401 lags behind the stage transfer signal P32 output by the stage transfer output module 20 of the first stage shift register 401 lags behind the stage transfer signal P32 output by the stage transfer output module 20 of the first stage shift register 401 lag

[0098] For example, see Figure 2 In the second output mode Z2, the stage transmission signal P3 output by the stage transmission output module 20 of the (i+1)th stage shift register 401 does not overlap with the stage transmission signal P3 output by the stage transmission output module 20 of the i-th stage shift register 401.

[0099] In some embodiments, in the second output mode Z2, the stage transmission signal P3 output by the output terminal Carry of the stage transmission output module 20 of the (i+1)th stage shift register 401 overlaps with the stage transmission signal P3 output by the output terminal Carry of the stage transmission output module 20 of the i-th stage shift register 401.

[0100] For example, the stage transmission signal P3 can be a pulse signal.

[0101] For example, the first end of the second output unit 32 and the first end of the fourth output unit 22 are connected to the same signal, and / or the first end of the second output unit 32 and the first end of the fourth output unit 22 are connected.

[0102] For example, in the same shift register 401, the first output unit 31 and the third output unit 21 have the same switching state, for example, they are both on and both off at the same time.

[0103] For example, in the same shift register 401, the control terminal of the first output unit 31 and the control terminal of the third output unit 21 are connected.

[0104] For example, in the same shift register 401, the second output unit 32 and the fourth output unit 22 have the same switching state, for example, they are both on and both off at the same time.

[0105] For example, in the same shift register 401, the control terminal of the second output unit 32 is connected to the control terminal of the fourth output unit 22.

[0106] For example, the control terminal of the second output unit 32 is connected to the second node N2.

[0107] For example, the second output terminal out2 of the control module 10 is connected to the first node N1.

[0108] For example, see Figure 5 The third output unit 21 includes a fourth transistor T7. The first electrode of the fourth transistor T7 is the first terminal of the third output unit 21, the second electrode of the fourth transistor T7 is the second terminal of the third output unit 21, and the gate of the fourth transistor T7 is the control terminal of the third output unit 21.

[0109] For example, the fourth transistor T7 can be a P-type transistor (see [reference]). Figure 5 ) or N-type transistor.

[0110] For example, see Figure 5 The fourth output unit 22 includes a fifth transistor T6. The first electrode of the fifth transistor T6 is the first terminal of the fourth output unit 22, the second electrode of the fifth transistor T6 is the second terminal of the fourth output unit 22, and the gate of the fifth transistor T6 is the control terminal of the fourth output unit 22.

[0111] For example, the fifth transistor T6 can be a P-type transistor (see [reference]). Figure 5 ) or N-type transistor.

[0112] For example, see Figure 5The shift register 401 also includes a third coupling module 23, which is connected between the first end of the third output unit 21 and the control end of the third output unit 21.

[0113] For example, see Figure 5 The shift register 401 also includes a second coupling module 24, which is connected between the second end of the fourth output unit 22 and the control end of the fourth output unit 22.

[0114] For example, see Figure 5 The third coupling module 23 includes a third capacitor C1, which is connected between the first terminal of the third output unit 21 and the control terminal of the third output unit 21.

[0115] For example, see Figure 5 The second coupling module 24 includes a second capacitor C3, which is connected between the second terminal of the fourth output unit 22 and the control terminal of the fourth output unit 22.

[0116] For example, see Figure 5 The control module 10 includes an input unit 11, a first control unit 12, and a second control unit 13.

[0117] Input unit 11 is used to control the second control signal output by the second output terminal out2 of control module 10 according to the input signal SIN and the second clock signal SCK2. For example, input unit 11 is connected to the second output terminal of control module 10. For example, input unit 11 is connected to the input terminal of control module 10 (where the input signal SIN can be input).

[0118] The first control unit 12 is used to control the first control signal output by the first output terminal out1 of the control module 10 according to the second clock signal SCK2 and the second control signal. For example, the first control unit 12 is connected to the first output terminal out1 of the control module 10.

[0119] The second control unit 13 is used to control the second control signal output by the second output terminal out2 of the control module 10 according to the first clock signal SCK1 and the first control signal. For example, the second control unit 13 is connected to the first output terminal out1 of the control module 10. For example, the second control unit 13 is connected to the second output terminal out2 of the control module 10.

[0120] For example, the first clock signal SCK1 and the second clock signal SCK2 have the same frequency but different phases, such as opposite phases.

[0121] For example, see Figure 5The input unit 11 includes a sixth transistor T1. The first terminal of the sixth transistor T1 is connected to the input signal SIN, and the second terminal of the sixth transistor T1 is connected to the second output terminal out2 of the control module 10. The gate of the sixth transistor T1 is connected to the second clock signal SCK2.

[0122] For example, the sixth transistor T1 can be a P-type transistor (see [reference]). Figure 5 ) or N-type transistor.

[0123] For example, see Figure 5 The first control unit 12 includes a seventh transistor T4 and an eighth transistor T5. The first terminal of the seventh transistor T4 is connected to the second clock signal SCK2, the second terminal of the seventh transistor T4 is connected to the first output terminal out1 of the control module 10, and the gate of the seventh transistor T4 is connected to the second output terminal out2 of the control module 10. The first terminal of the eighth transistor T5 is connected to the second potential signal VGL, the second terminal of the eighth transistor T5 is connected to the first output terminal out1 of the control module 10, and the gate of the eighth transistor T5 is connected to the second clock signal SCK2.

[0124] For example, the seventh transistor T4 can be a P-type transistor (see [reference]). Figure 5 ) or N-type transistor.

[0125] For example, the eighth transistor T5 can be a P-type transistor (see [reference]). Figure 5 ) or N-type transistor.

[0126] For example, see Figure 5 The second control unit 13 includes a ninth transistor T2 and a tenth transistor T3. The second terminals of the ninth transistor T2 and the tenth transistor T3 are connected. One of the first terminals of the ninth transistor T2 and the tenth transistor T3 is connected to the second output terminal out2 of the control module 10, and the other is connected to the first potential signal VGH. One of the gates of the ninth transistor T2 and the tenth transistor T3 is connected to the first output terminal out1 of the control module 10, and the other is connected to the first clock signal SCK1.

[0127] For example, the first terminal of the ninth transistor T2 is connected to the first potential signal VGH, and the first terminal of the tenth transistor T3 is connected to the second output terminal out2 of the control module 10. Alternatively, the first terminal of the ninth transistor T2 is connected to the second output terminal out2 of the control module 10, and the first terminal of the tenth transistor T3 is connected to the first potential signal VGH.

[0128] For example, the gate of the ninth transistor T2 is connected to the first clock signal SCK1, and the gate of the tenth transistor T3 is connected to the first output terminal out1 of the control module 10. Alternatively, the gate of the ninth transistor T2 is connected to the first output terminal out1 of the control module 10, and the gate of the tenth transistor T3 is connected to the first clock signal SCK1.

[0129] For example, one of the first potential signal VGH and the second potential signal VGL is at a high level, and the other is at a low level.

[0130] For example, the first potential signal VGH is high and the second potential signal VGL is low. Or, for example, the first potential signal VGH is low and the second potential signal VGL is high.

[0131] For example, the ninth transistor T2 can be a P-type transistor (see [reference]). Figure 5 ) or N-type transistor.

[0132] For example, the tenth transistor T3 can be a P-type transistor (see [reference]). Figure 5 ) or N-type transistor.

[0133] For example, see Figure 5 The shift register 401 also includes a second protection module 25. The second output terminal out2 of the control module 10 is connected to the control terminal of the second output unit 32 via the second protection module 25. The control terminal of the second protection module 25 is connected to a conduction level, a DC potential, or a second potential signal VGL. For example, the second output terminal out2 of the control module 10 is connected to the control terminal of the fourth output unit 22 via the second protection module 25.

[0134] For example, see Figure 5 The second protection module 25 includes an eleventh transistor T8. The second output terminal out2 of the control module 10 is connected to the control terminal of the second output unit 32 via the eleventh transistor T8. The gate of the eleventh transistor T8 is connected to an on-level, a DC potential, or a second potential signal VGL.

[0135] For example, the eleventh transistor T8 can be a P-type transistor (see [reference]). Figure 5 ) or N-type transistor.

[0136] For example, the control terminal of the first output unit 31 is connected to the control terminal of the third output unit 21 via the first protection module 34.

[0137] For example, the control terminal of the second output unit 32 is connected to the control terminal of the fourth output unit 22 via the second protection module 25. Figure 5 An example is drawn showing the case where all transistors in the shift register are P-type transistors.

[0138] Figure 6The timing waveform diagram of a shift register provided in an embodiment of this application is shown. Figure 6 Applicable to Figure 5 The shift register. See also Figure 5 and Figure 6 The operation of shift registers is described, for example, the operation of the first-stage shift register, as the operating principles of each stage are similar. The display frame may include a first stage, a second stage t2, a third stage t3, and a fourth stage t4. The first stage may include a first sub-stage t0 and a second sub-stage t1. For example, in the first sub-stage t0 and the second sub-stage t1, the gate drive circuit 400 may operate in the first output mode Z1. In the third stage t3, the gate drive circuit 400 may operate in the second output mode Z2. In the second stage t2, the gate drive circuit 400 can also be considered to be operating in the first output mode Z1.

[0139] In the first sub-stage t0, the input signal SIN (e.g., SIN_1) is at the second level, for example, a high level; the pulse mode control signal RST is at the second level V2, for example, a high level; the first node N1 and the second node N2 are at the second level, for example, a high level; the third node N3 and the fourth node N4 are at the first level, for example, a low level; the fourth output unit 22 (which can be the fifth transistor T6) and the second output unit 32 (which can be the second transistor T10) are turned off; the third output unit 21 (which can be the fourth transistor T7) and the first output unit 31 (which can be the first transistor T9) are turned on; the voltage of the third node N3 and the fourth node N4 can be VGL-Vth, where Vth can be the threshold voltage of the eighth transistor T5; the output terminal Carry of the stage output module 20 outputs the first potential signal VGH transmitted through the turned-on third output unit 21 (which can be the fourth transistor T7), for example, a high level; the output terminal Sout of the gate output module 30 outputs the pulse mode control signal RST transmitted through the turned-on first output unit 31 (which can be the first transistor T9), for example, a high level.

[0140] In the second sub-stage t1, the input signal SIN remains unchanged at the second level, for example, a high level. The pulse mode control signal RST is at the first level V1, for example, transitioning from a high level to a low level. The first node N1 and the second node N2 are at the second level, for example, a high level. The third node N3 and the fourth node N4 are at the first level, for example, a low level. The fourth output unit 22 (which can be the fifth transistor T6) and the second output unit 32 (which can be the second transistor T10) are turned off. The third output unit 21 (which can be the fourth transistor T7) and the first output unit 31 (which can be the first transistor T9) are turned on. The voltage of the third node N3 can be VGL-Vth. Vth can be the threshold voltage of the eighth transistor T5. The output terminal Carry of the stage transmission module 20 outputs the first potential signal VGH transmitted through the turned-on third output unit 21 (which can be the fourth transistor T7), for example, a high level. The voltage of the fourth node N4 jumps due to the pulse mode control signal RST, and is coupled through the first coupling module 33 (which can be the first capacitor C2) to generate bootstrapping. The fourth node N4 is at a very low level. The output terminal Sout of the gate output module 30 outputs the pulse mode control signal RST transmitted through the turned-on first output unit 31 (which can be the first transistor T9) without loss, for example, a low level, ensuring the quality of waveform reproduction. By setting the first coupling module 33 (which can be the first capacitor C2) and the pulse mode control signal RST, the fourth node N4 is bootstrapping to an extremely low level, and the first protection module 34 (which can be the third transistor T11) is set to isolate the extremely low level. This allows for the normal output of low-level pulses that simultaneously reset all rows, while preventing the transistors related to node N1 from being damaged by large voltage stress. The third transistor T11 is used to isolate the third node N3 and the fourth node N4, preventing the fourth transistor T7, the tenth transistor T3, and the seventh transistor T4 from breaking down.

[0141] In the second stage t2, the input signal SIN remains unchanged and is at the second level, for example, a high level. The pulse mode control signal RST is at the second level, for example, it jumps from a low level to a high level. The fourth node N4 jumps from an extremely low level back to the original VGL-Vth. The output terminal Sout of the gate output module 30 outputs the pulse mode control signal RST transmitted through the first output unit 31 (which can be the first transistor T9), for example, at a high level. The output terminal Carry of the stage output module 20 still maintains the first potential signal VGH, for example, at a high level. Thus, the output terminal Sout of the gate output module 30 can completely replicate the waveform of the pulse mode control signal RST. The pulse mode control signal RST can be adjusted arbitrarily in time, and the output terminal Sout of the gate output module 30 can replicate it.

[0142] In the third stage t3, the pulse mode control signal RST is at the second level, for example, a high level, and the input signal SIN is at the first level, for example, transitioning from a high level to a low level. When the second clock signal SCK2 is low, the first node N1 and the second node N2 are fed a low level VGL-Vth and maintain this level. When the second clock signal SCK2 transitions to a high level, due to the inverter-off function of the seventh transistor T4, the seventh transistor T4 is turned on, feeding a high level to the control terminal of the third output unit 21 (which can be the gate of the fourth transistor T7) and the control terminal of the first output unit 31 (which can be the gate of the first transistor T9). The third node N3 and the fourth node N4 become high, and the third output unit 21... When the first output unit 31 (which can be the fourth transistor T7) and the first output unit 31 (which can be the first transistor T9) are turned off, the fourth output unit 22 (which can be the fifth transistor T6) and the second output unit 32 (which can be the second transistor T10) are connected to the first clock signal SCK1. They are bootstrapped through the second coupling module 24 (which can be the second capacitor C3). The second node N2 is at an extremely low level, and the fourth output unit 22 (which can be the fifth transistor T6) and the second output unit 32 (which can be the second transistor T10) are more fully turned on. Thus, the first clock signal SCK1 of the lower branch is output. That is, the output terminal Carry of the stage output module 20 and the output terminal Sout of the gate output module 30 output the waveform of the first clock signal SCK1.

[0143] In the fourth stage t4, the pulse mode control signal RST is at the second level, for example, a high level, and the input signal SIN becomes high. When the second clock signal SCK2 jumps to low level for the next time, the high level of the input signal SIN is transmitted to the first node N1 and the second node N2 through the turned-on input unit 11 (which can be the sixth transistor T1). The fourth output unit 22 (which can be the fifth transistor T6) and the second output unit 32 (which can be the second transistor T10) are turned off. The second potential signal VGL is transmitted to the third node N3 and the fourth node N4 through the turned-on eighth transistor T5. The third output unit 21 (which can be the fourth transistor T7) and the first output unit 31 (which can be the first transistor T9) are turned on. The output terminal Carry of the stage output module 20 and the output terminal Sout of the gate output module 30 output a high level.

[0144] Figure 7 The timing waveform diagram of another shift register provided in the embodiments of this application. Figure 7 Applicable to Figure 5 Shift registers. Figure 5 , Figure 6 Corresponding technical solutions and Figure 5 , Figure 7 The working principles of the corresponding technical solutions are similar, and will not be elaborated here. The difference lies in... Figure 5 , Figure 7In the corresponding technical solution, the display frame may not include the first sub-stage t0, that is... Figure 5 , Figure 6 Corresponding technical solutions and Figure 5 , Figure 7 In the corresponding technical solution, the pulse mode control signal RST has a different level at the beginning of the display frame. That is, by changing the pulse mode control signal RST, an inverted pulse signal can be generated, fulfilling the multi-functional requirements of the gate drive circuit.

[0145] In the fifth stage t5, the input signal SIN is high, the voltages of the first node N1 and the second node N2 remain high, the third node N3 and the fourth node N4 remain low, and the output terminal Carry of the stage output module 20 outputs the first potential signal VGH, for example, high. As the pulse mode control signal RST jumps to low, it boots up through the first coupling module 33 (which can be the first capacitor C2), and the output terminal Sout of the gate output module 30 outputs a low level.

[0146] The fifth stage t5 can be the second sub-stage t1 of the next display frame. The display frame Frame can include the second sub-stage t1, the second stage t2, the third stage t3, and the fourth stage t4.

[0147] Figure 8 A schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 8 The shift register 401 also includes a second coupling module 24, which is connected between the second terminal of the second output unit 32 and the control terminal of the second output unit 32. In the third stage t3, when the second output unit 32 is turned on, and the first clock signal SCK1 transitions to a low level, the voltage at the control terminal of the second output unit 32 can be pulled down to an extremely low level through the coupling effect of the second coupling module 24. This allows the second output unit 32 to conduct more fully, and the output terminal Sout of the gate output module 30 can output the first clock signal SCK1 without loss.

[0148] For example, the second coupling module 24 includes a second capacitor C2, which is connected between the second terminal of the second output unit 32 and the control terminal of the second output unit 32.

[0149] Figure 8 Technical solutions and Figure 5 The working principle of the technical solution is similar, so it will not be elaborated here. Figure 6 and Figure 7 Applicable to Figure 8 Shift registers.

[0150] Figure 9This is a timing waveform diagram of another shift register provided in an embodiment of this application. For example, in at least a portion of the first output mode, the voltage of the pulse mode control signal RST is a first level V1. In the second output mode, the voltage of the pulse mode control signal RST is a second level V2. One of the first level V1 and the second level V2 is low, and the other is high. When the voltage of the pulse mode control signal RST jumps from the second level V2 to the first level V1 (e.g., at time t11), one of the first clock signal SCK1 and the second clock signal SCK2 is high, and the other is low, i.e., a non-intermediate state.

[0151] In the intermediate state tx, when both the first clock signal SCK1 and the second clock signal SCK2 are high, for example, see... Figure 6 , Figure 8 and Figure 9 When the pulse mode control signal RST transitions from the second level V2 to the first level V1, for example, during a down-jump, the first node N1 and the second node N2 are pulled low through the coupling of the first coupling module 33 and the second coupling module 24. This causes the gate voltages of the second transistor T10 and the seventh transistor T4 to be pulled low, potentially leading to a risk of conduction. Therefore, if both the first clock signal SCK1 and the second clock signal SCK2 are high, the third node N3 and the fourth node N4 are charged to a positive voltage through the seventh transistor T4, resulting in abnormal output and an inability to replicate the pulse mode control signal RST waveform. The conduction of the second transistor T10 may also pose a risk of a short circuit between the pulse mode control signal RST input terminal and the first clock signal SCK1. Therefore, compared to the intermediate state, in the non-intermediate state, when the voltage of the pulse mode control signal RST transitions from the second level V2 to the first level V1, one of the first clock signals SCK1 and SCK2 is low, and the third node N3 and the fourth node N4 are charged to a negative voltage through the seventh transistor T4, which helps improve signal reliability.

[0152] In some embodiments, see Figure 5 No coupling module or capacitor may be provided between the second terminal of the second output unit 32 and the control terminal of the second output unit 32. A second coupling module 24 is provided between the second terminal of the fourth output unit 22 and the control terminal of the fourth output unit 22, which is beneficial to improving the reliability of the signal.

[0153] For example, see Figure 8 The shift register 401 also includes a voltage regulator module 26. The first end of the voltage regulator module 26 is connected to the output end Carry of the stage output module 20, and the second end of the voltage regulator module 26 is connected to a DC potential or a first potential signal VGH.

[0154] For example, see Figure 8The voltage regulator module 26 includes a fourth capacitor C4. The first terminal of the fourth capacitor C4 is connected to the output terminal Carry of the stage output module 20, and the second terminal of the fourth capacitor C4 is connected to a DC potential or a first potential signal VGH. This configuration stabilizes the signal output from the output terminal Carry of the stage output module 20, preventing the output terminal Carry of the stage output module 20 from being coupled by clock signals or other signals.

[0155] Figure 10 A schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 10 No coupling module or capacitor needs to be provided between the first terminal of the first output unit 31 and the control terminal of the first output unit 31. When the pulse mode control signal RST goes low, the third node N3 is coupled to a low level by the capacitance of the first transistor T9 in the first output unit 31, so that the output terminal Sout of the gate output module 30 outputs a low level.

[0156] In some embodiments, see Figure 10 The first protection module 34 may not be provided between the control terminal of the first output unit 31 and the first output terminal out1 of the control module 10, and / or the first protection module 34 may not be provided between the control terminal of the first output unit 31 and the control terminal of the third output unit 21.

[0157] Figures 1 to 10 The P-type transistors can be replaced with N-type transistors, with the high and low levels interchanged; the principle is similar and will not be elaborated further here. The channel type of each transistor can be set as needed, which will also not be elaborated further here.

[0158] Figure 11 This is a schematic diagram of another gate drive circuit provided in an embodiment of this application. For example, see... Figure 11 The first clock signal SCK1 of the i-th level shift register (or the (2k-1)-th level shift register, such as the odd-numbered level shift register) is provided through the first clock line L1, and the second clock signal SCK2 of the i-th level shift register (or the (2k-1)-th level shift register, such as the odd-numbered level shift register) is provided through the second clock line L2; the first clock signal SCK1 of the (i+1)-th level shift register (or the 2k-th level shift register, such as the even-numbered level shift register) is provided through the second clock line L2, and the second clock signal SCK2 of the (i+1)-th level shift register (or the 2k-th level shift register, such as the even-numbered level shift register) is provided through the first clock line L1. k can be an integer greater than or equal to 1.

[0159] Figure 12 This is a schematic diagram of another shift register provided in an embodiment of this application. Figure 13A schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 12 or Figure 13 The shift register 401 also includes a first inverter 35. The first output terminal out1 of the control module 10 is connected to the control terminal of the second output unit 32 via the first inverter 35. The voltages of the first output terminal out1 and the second output terminal out2 of the control module 10 are opposite. For example, when the first output terminal out1 of the control module 10 jumps to a high level, the second output terminal out2 of the control module 10 jumps to a low level; when the first output terminal out1 of the control module 10 jumps to a low level, the second output terminal out2 of the control module 10 jumps to a high level. This configuration reduces the load on the second output terminal out2 of the control module 10 and improves the reliability of the output signal of the fourth output unit 32. For example, the first output terminal out1 of the control module 10 is connected to the control terminal of the first output unit 31 via the first protection module 34. For example, the first output terminal out1 of the control module 10 is connected to the input terminal of the first inverter 35, and the output terminal of the first inverter 35 is connected to the control terminal of the second output unit 32. The first inverter 35 can invert the level of the input terminal of the first inverter 35 and output it to the output terminal of the first inverter 35. That is, when the input terminal of the first inverter 35 is high, the output terminal of the first inverter 35 outputs a low level; when the input terminal of the first inverter 35 is low, the output terminal of the first inverter 35 outputs a high level.

[0160] In some embodiments, the second output terminal out2 of the control module 10 is connected to the control terminal of the second output unit 32, and the second output terminal out2 of the control module 10 is connected to the control terminal of the first output unit 31 via the first inverter 35. For example, the second output terminal out2 of the control module 10 is connected to the input terminal of the first inverter 35, and the output terminal of the first inverter 35 is connected to the control terminal of the first output unit 31.

[0161] Figure 2 , Figure 4 Applicable to Figure 12 and Figure 13 The shift register in the middle. Figure 12 and Figure 13 Technical solutions and Figure 5 The technical solutions are similar, and will not be described in detail here. The difference lies in the specific structure of the control module 10. The specific structure of the control module 10 can be set as needed.

[0162] For example, see Figure 13The control module 10 may include a first transmission unit 14, a second transmission unit 17, a second inverter 15, a third inverter 16, and a fourth inverter 18. The control module 10 may include transistors T20 to T29. The pulse signal P4 of the input signal (e.g., a high-level pulse) may overlap with the effective level pulse (e.g., a low-level pulse) of the first clock signal SCK1.

[0163] Figure 14 This is a schematic diagram of another shift register provided in an embodiment of this application. Figure 15 The timing waveform diagram is provided for another gate drive circuit according to an embodiment of this application. Figure 16 The timing waveform diagram is provided for another gate drive circuit according to an embodiment of this application. Figure 15 , Figure 16 Applicable to Figure 14 Shift registers. For example, see [link to example]. Figure 14 The first terminal of the second output unit 32 can be connected to a power signal or a DC potential, such as a first potential signal VGH, for example, a high level. The first terminal of the fourth output unit 22 can be connected to a power signal or a DC potential, such as a first potential signal VGH, for example, a high level. The first terminal of the third output unit 21 can be connected to a power signal or a DC potential, such as a second potential signal VGL, for example, a low level. The effective level of the first pulse P1 can be a high level, that is, the first level V1 can be a high level. The effective level of the second pulse P2 can be a high level, that is, the first level V1 can be a high level. The second level V2 can be a low level.

[0164] Figure 1 , Figures 14 to 16 Technical solutions and Figures 1 to 5 The technical solutions are similar and will not be described in detail here. The differences lie in the input signals at the first end of the second output unit 32, the first end of the fourth output unit 22, and the first end of the third output unit 21; the specific structure of the control module 10; the effective level of the first pulse P1; and the effective level of the second pulse P2. The specific structure of the control module 10 can be set as needed.

[0165] For example, see Figure 14 The control module 10 may include transistors T1 to T5 and transistors T12 to T15.

[0166] This application provides a display panel. Figure 17This is a schematic diagram of a display panel provided in an embodiment of this application. The display panel 300 includes at least one gate driving circuit 400 provided in any of the above embodiments, and possesses the beneficial effects of the gate driving circuit 400 in any of the embodiments of this application, which will not be described again here. This embodiment can be combined with some or all of the features in the above embodiments, which will not be described again here.

[0167] For example, the display panel 300 may include a display area 301 and a non-display area 302. The gate driving circuit 400 may be located in the non-display area 302.

[0168] For example, the display panel 300 may include a light-emitting element 100, which may be located in the display area 301.

[0169] For example, see Figures 1 to 13 , Figure 17 The display panel 300 includes a pixel circuit 200. The pixel circuit 200 may be located in the display area 301. The pixel circuit 200 includes a driving transistor M1 and a switching transistor M2. The switching transistor M2 is connected to the driving transistor M1, for example, the switching transistor M2 is connected to the gate of the driving transistor M1. At least one gate driving circuit 400 may include a first gate driving circuit 410, which is connected to the gate of the switching transistor M2. For example, the first gate driving circuit 410 may be connected to the gate of the switching transistor M2 via a first gate line L4. For example, the first terminal of the switching transistor M2 is connected to a data line Data, and the second terminal of the switching transistor M2 is connected to the gate of the driving transistor M1. For example, the data line Data may time-division multiplex the initialization voltage Vini and the data voltage Vdata.

[0170] In the first time period, the switching transistors M2 of the multi-row pixel circuit 200 are simultaneously turned on, and the initialization voltage Vini is simultaneously applied to the switching transistors M2 of the multi-row pixel circuit 200. This initialization voltage Vini can be transmitted to the driving transistor M1 (e.g., the gate of the driving transistor M1) to initialize the driving transistor M1 (e.g., the gate of the driving transistor M1). That is, the gates of the driving transistors M1 of the multi-row (e.g., all rows, including the first and last rows) pixel circuits 200 are initialized simultaneously. In the first time period, the first gate driving circuit 410 operates in the first output mode Z1. The first time period can be a second sub-stage t1. For example, in the first time period, the data line Data can transmit the initialization voltage Vini.

[0171] During the second time period, the switching transistors M2 of the multi-row pixel circuit 200 are turned on row by row. The switching transistors M2 of the multi-row pixel circuit 200 are connected to the data voltage Vdata, which can be transmitted to the driving transistor M1 (e.g., the gate of the driving transistor M1) to realize the row-by-row data writing of the multi-row (e.g., all rows, including the first and last rows) pixel circuit 200. During the second time period, the first gate driving circuit 410 operates in the second output mode Z2. The second time period can be the third stage t3. For example, during the second time period, the data line Data can transmit the data voltage Vdata. For example, corresponding to the first gate driving circuit 410, in the second output mode Z2, the second pulse P2 output by the output terminal Sout of the gate output module 30 of the (i+1)th stage shift register 401 does not overlap with the second pulse P2 output by the output terminal Sout of the gate output module 30 of the i-th stage shift register 401.

[0172] In some embodiments, the shift register 401 in the first gate drive circuit 410 may be Figure 5 , Figure 8 , Figure 10 , Figure 13 Structures or similar structures.

[0173] For example, the pixel circuit 200 may also include a storage capacitor Cst. For example, the storage capacitor Cst is connected between the gate and the first terminal of the driving transistor M1. The pixel circuit 200 may also include more transistors and / or capacitors, or may adopt other connection relationships, which can be set as needed, and the embodiments of this application are not limited in this regard.

[0174] For example, pixel circuit 200 may also include a fifth capacitor C0. For example, the fifth capacitor C0 is connected in series with storage capacitor Cst. The first terminal of the fifth capacitor C0 is connected to the first terminal of driving transistor M1, and for example, the second terminal of the fifth capacitor C0 is connected to a DC voltage or a reference voltage V3. For example, switching transistor M2 may include a P-type transistor (see...). Figure 3 ) or N-type transistor.

[0175] For example, the driving transistor M1 may include an N-type transistor (see...). Figure 3 (or P-type transistor)

[0176] For example, see Figure 3 , Figure 17The display panel 300 also includes a selection circuit 500, which is electrically connected to the first terminal of the switching transistor M2 via a data line Data. For example, the selection circuit 500 includes a first switching transistor M4 and a second switching transistor M5. The first terminal of the first switching transistor M4 is connected to a data voltage Vdata, and the first terminal of the second switching transistor M5 is connected to an initialization voltage Vini. The second terminals of both the first and second switching transistors are electrically connected to the data line Data. The first switching transistor M4 and the second switching transistor M5 are time-division multiplexed; for example, in a first time period, the second switching transistor M5 is on and the first switching transistor M4 is off; in a second time period, the second switching transistor M5 is off and the first switching transistor M4 is on.

[0177] The selection circuit 500 can be located in the non-display area 302. For example, multiple pixel circuits located in the same column can share the same selection circuit 500. The switching transistor M2 can transmit the initialization voltage Vini and the data voltage Vdata in a time-division multiplexing manner, thereby reducing the number of transistors in the pixel circuit, which helps to simplify the pixel circuit and improve the pixel resolution (PPI).

[0178] Figure 18 This is a schematic diagram of another display panel structure provided in an embodiment of this application. Figure 19 This is a timing waveform diagram of a first type of display frame provided in an embodiment of this application. Figure 20 This is a timing waveform diagram of a second type of display frame provided in an embodiment of this application. For example, see... Figure 1 , Figure 3 , Figure 14 , Figure 15 , Figure 16 , Figure 18 , Figure 19 , Figure 20 The display panel includes pixel circuitry 200 and light-emitting elements 100. Pixel circuitry 200 includes a driving transistor M1 and a light-emitting control transistor M3. The driving transistor M1, the light-emitting control transistor M3, and the light-emitting element 100 are connected in series between a first power line VDD and a second power line VSS. At least one gate driving circuit 400 may include a second gate driving circuit 420, which is connected to the gate of the light-emitting control transistor M3. The second gate driving circuit 420 can be connected to the gate of the light-emitting control transistor M3 via a second gate line L5. The display frame may include a first type display frame Frame1 and / or a second type display frame Frame1.

[0179] In the first type of display frame Frame1, the light-emitting control transistors M3 of the multi-row pixel circuit 200 are simultaneously turned on, and the multi-row light-emitting elements 100 emit light simultaneously, i.e., in the simultaneous light-emitting mode, which enables the light-emitting elements connected in the multi-row pixel circuit to emit light simultaneously. During at least a portion of the time period of the first type of display frame Frame1, the second gate driving circuit 420 operates in the first output mode Z1.

[0180] For example, the first type of display frame Frame1 may include a non-light-emitting phase t1' and a light-emitting phase t2'. For example, the first pulse P1 corresponds to the non-light-emitting phase t1', and the operating state of the second gate driving circuit 420 in the non-light-emitting phase t1' is the same as or similar to the operating state of the second sub-phase t1, and the operating state of the second gate driving circuit 420 in the light-emitting phase t2' is the same as or similar to the operating state of the first sub-phase t0 or the second phase t2, which will not be elaborated here. For example, the light-emitting control transistor M3 is a P-type transistor.

[0181] In the second type of display frame Frame2, the light-emitting control transistors M3 of the multi-row pixel circuit 200 are turned on row by row, and the multi-row light-emitting elements 100 emit light row by row, that is, the row-by-row light-emitting mode, which enables the light-emitting elements connected by the multi-row pixel circuit to emit light row by row. During at least a portion of the time period of the second type of display frame Frame2, the second gate driving circuit 420 operates in the second output mode Z2. For example, the second pulse P2 corresponds to the non-light-emitting stage. For example, corresponding to the second gate driving circuit 420, in the second output mode Z2, the second pulse P2 output by the output terminal Sout of the gate output module 30 of the (i+1)th stage shift register 401 overlaps with the second pulse P2 output by the output terminal Sout of the gate output module 30 of the i-th stage shift register 401.

[0182] For example, the light-emitting control transistor M3 is connected between the first power line VDD and the second terminal of the driving transistor M1.

[0183] For example, the light-emitting control transistor M3 may include a P-type transistor (see...) Figure 3 ) or N-type transistor.

[0184] The channel type of the switching transistor M2 or the light-emitting control transistor M3 and the matching gate drive circuit 400 can be set as needed.

[0185] For example, during the light-emitting phase, the driving module 10 can generate a driving current to drive the light-emitting element 100 to emit light. A first power line VDD can be used to transmit a first power supply voltage. A second power line VSS can be used to transmit a second power supply voltage. For example, one of the first and second power supply voltages may be a high voltage, and the other a low voltage. For example, the first power supply voltage may be a high voltage (e.g., a positive voltage), and the second power supply voltage may be a low voltage (e.g., a negative voltage).

[0186] For example, the light-emitting element 100 may include a light-emitting diode, such as an organic light-emitting diode. For example, one of the first and second ends of the light-emitting element 100 may be an anode, and the other may be a cathode. For example, the first end of the light-emitting element 100 may be an anode, and the second end of the light-emitting element 100 may be a cathode. The second end of the light-emitting element 100 may be connected to a second power supply voltage and / or a second power supply line.

[0187] For example, the display panel includes a plurality of pixel circuits 200 arranged in an array. For example, each column of pixel circuits 200 includes a plurality of pixel circuits 200 arranged along a second direction Y.

[0188] For example, the multiple rows of pixel circuits 200 are arranged along the second direction Y. For example, each row of pixel circuits 200 includes a plurality of pixel circuits 200 arranged along the first direction X.

[0189] Optionally, the display panel 300 includes gate lines (e.g., L4, L5), and the pixel circuit 200 is connected to the gate lines, which extend along a first direction X. For example, multiple gate lines are arranged along a second direction Y. The first direction X and the second direction Y intersect, for example, perpendicularly. For example, multiple data lines (Data) may extend along the second direction Y and be arranged along the first direction X.

[0190] Figure 21 This is a schematic diagram of another display panel structure provided in an embodiment of this application. For example, the display panel may include a first gate driving circuit 410 and a second gate driving circuit 420.

[0191] This application provides a driving method. Figure 22 This is a schematic flowchart illustrating a driving method provided in an embodiment of this application. This driving method can be applied to the gate driving circuit 400 provided in an embodiment of this application. See also... Figure 22 The driving method includes: Step S110: In the first output mode, control the gate output modules of multiple shift registers to simultaneously output the first pulse.

[0192] Step S120: In the second output mode, the gate output modules of multiple shift registers sequentially output the second pulse.

[0193] For example, in at least a portion of the first output mode Z1, the pulse mode control signal is at a first level. In the second output mode, the pulse mode control signal is at a second level. One of the first level V1 and the second level V2 is low, and the other is high.

[0194] The driving method of this application embodiment can be applied to the gate driving circuit 400 of any embodiment of this application or to the display panel 300 of any embodiment of this application, and has the beneficial effects of the gate driving circuit 400 of any embodiment of this application, which will not be described again here. This embodiment can be combined with some or all of the features in the above embodiments, which will not be described again here.

[0195] Figure 23 This is a schematic diagram of a display device provided in an embodiment of this application. This application also provides a display device 1, including the display panel 300 provided in any embodiment of this application.

[0196] For example, the display device includes a photosensitive element and a display panel provided in any embodiment of this application. The photosensitive element is used to receive light transmitted through the light-transmitting area. The photosensitive element may include one or more of a camera, a fingerprint recognition module, an ambient light sensor, an infrared sensor, etc.

[0197] Display devices include, but are not limited to, mobile phones, personal digital assistants (PDAs), tablets, e-books, televisions, access control systems, smart landlines, consoles, laptops, wearable devices, in-vehicle displays, virtual reality (VR) and augmented reality (AR) and other near-eye display devices with display functions.

[0198] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0199] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0200] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A gate driving circuit, characterized in that, include: Multiple cascaded shift registers, The shift register includes: a control module, a stage output module, and a gate output module; The control module is connected to the stage output module and the gate output module. The gate output module receives a pulse mode control signal. The control module is used to control the output terminal of the stage transmission module to output a stage transmission signal based on at least the input signal and at least one clock signal. The multiple shift registers are used to control the output terminals of the gate output modules of the multiple shift registers to simultaneously output a first pulse in a first output mode, and in a second output mode, the output terminals of the gate output modules of the multiple shift registers to sequentially output a second pulse.

2. The gate driving circuit according to claim 1, characterized in that, In the first output mode, the first pulses output by the gate output modules of the multiple shift registers have the same start time and the same end time. In the second output mode, the second pulse output by the gate output module of the shift register of the (i+1)th stage lags behind the second pulse output by the gate output module of the shift register of the i-th stage, where i is an integer greater than or equal to 1; Preferably, the effective level of the first pulse and the effective level of the second pulse are the same; Preferably, in the same display frame, the pulse mode control signal includes one transition edge or at least two transition edges; Preferably, during at least a portion of the first output mode, the voltage of the pulse mode control signal is a first level, and during the second output mode, the voltage of the pulse mode control signal is a second level, wherein one of the first level and the second level is a low level and the other is a high level; In the same display frame, the voltage of the pulse mode control signal starts at the first level and then jumps to the second level; or, in the same display frame, the voltage of the pulse mode control signal starts at the second level, then jumps to the first level, and then jumps to the second level. Preferably, the width of the first pulse is greater than the width of the second pulse; Preferably, in the second output mode, the width of the second pulse output by the output terminals of the gate output modules of the plurality of shift registers is the same; Preferably, the effective level of the first pulse and the effective level of the second pulse are the first level; Preferably, in the first output mode, the voltage output by the gate output modules of the plurality of shift registers simultaneously changes from high level to low level, and / or simultaneously changes from low level to high level; Preferably, in the first output mode, the input signal is at a second level, and / or the voltage of the input signal remains unchanged; In the second output mode, the voltage of the pulse mode control signal is equal to the voltage of the first potential signal, and / or the voltage of the pulse mode control signal remains unchanged.

3. The gate driving circuit according to claim 1, characterized in that, The gate output module includes a first output unit and a second output unit. The first terminal of the first output unit is connected to the pulse mode control signal, and the second terminals of the first and second output units are connected to the output terminal of the gate output module. The first terminal of the second output unit is connected to a first clock signal, a power supply signal, or a DC potential. The control terminal of the first output unit is connected to the first output terminal of the control module; The control terminal of the second output unit is connected to the second output terminal of the control module; or, the shift register further includes a first inverter, and the first output terminal of the control module is connected to the control terminal of the second output unit via the first inverter. The first output unit is used to output the pulse mode control signal to the output terminal of the gate output module when the first output mode is turned on. The second output unit is used to turn off in the first output mode; The second output units of the plurality of shift registers are used to be turned on sequentially in the second output mode; Preferably, the shift register further includes a first coupling module and / or a second coupling module, wherein the first coupling module is connected between a first terminal of the first output unit and a control terminal of the first output unit; and the second coupling module is connected between a second terminal of the second output unit and a control terminal of the second output unit. Preferably, the shift register further includes a first protection module, and the first output terminal of the control module is connected to the control terminal of the first output unit via the first protection module; the control terminal of the first protection module is connected to a conduction level, a DC potential, or a second potential signal. Preferably, the first output unit includes a first transistor, the first electrode of the first transistor is the first terminal of the first output unit, the second electrode of the first transistor is the second terminal of the first output unit, and the gate of the first transistor is the control terminal of the first output unit; And / or, the second output unit includes a second transistor, the first electrode of the second transistor is the first terminal of the second output unit, the second electrode of the second transistor is the second terminal of the second output unit, and the gate of the second transistor is the control terminal of the second output unit; And / or, the first coupling module includes a first capacitor, which is connected between a first terminal of the first output unit and a control terminal of the first output unit; And / or, the second coupling module includes a second capacitor, which is connected between the second terminal of the second output unit and the control terminal of the second output unit; And / or, the first protection module includes a third transistor, and the first output terminal of the control module is connected to the control terminal of the first output unit via the third transistor; the gate of the third transistor is connected to a conduction level, a DC potential, or a second potential signal.

4. The gate driving circuit according to claim 3, characterized in that, During at least a portion of the time in the first output mode, the gate output module and the stage output module in the same shift register output different values; In the second output mode, the output terminal of the gate output module in the same shift register outputs the second pulse while the output terminal of the stage transmission output module outputs the stage transmission signal, and the pulse widths of the second pulse and the stage transmission signal are the same. Preferably, during at least a portion of the time period of the first output mode, one of the gate output module and the stage output module in the same shift register outputs a high level, while the other outputs a low level; Preferably, the output terminal of the stage output module of the i-th stage shift register is connected to the input terminal of the control module of the (i+1)-th stage shift register; The stage transmission signal output from the stage transmission output module of the i-th stage shift register is used as the input signal input to the control module of the (i+1)-th stage shift register; where i is an integer greater than or equal to 1. Preferably, the stage output module includes a third output unit and a fourth output unit. The first terminal of the third output unit is connected to a power signal, a DC potential, or a first potential signal. The second terminals of the third output unit and the fourth output unit are connected to the output terminals of the stage transmission module. The first terminal of the fourth output unit is connected to a first clock signal, a power signal, or a DC potential. The control terminal of the third output unit is connected to the first output terminal of the control module; the control terminal of the fourth output unit is connected to the second output terminal of the control module. Preferably, the first terminal of the second output unit and the first terminal of the fourth output unit are connected to the same signal, and / or the first terminal of the second output unit and the first terminal of the fourth output unit are electrically connected; Preferably, the shift register further includes a third coupling module, which is connected between the first terminal of the third output unit and the control terminal of the third output unit; Preferably, the shift register further includes a second coupling module, which is connected between the second terminal of the fourth output unit and the control terminal of the fourth output unit; Preferably, the third output unit includes a fourth transistor, the first terminal of the fourth transistor is the first terminal of the third output unit, the second terminal of the fourth transistor is the second terminal of the third output unit, and the gate of the fourth transistor is the control terminal of the third output unit; And / or, the fourth output unit includes a fifth transistor, the first electrode of the fifth transistor is the first terminal of the fourth output unit, the second electrode of the fifth transistor is the second terminal of the fourth output unit, and the gate of the fifth transistor is the control terminal of the fourth output unit; And / or, the third coupling module includes a third capacitor, which is connected between the first terminal of the third output unit and the control terminal of the third output unit; And / or, the second coupling module includes a second capacitor connected between the second terminal of the fourth output unit and the control terminal of the fourth output unit.

5. The gate driving circuit according to claim 1, characterized in that, The shift register also includes a voltage regulator module, the first end of which is connected to the output end of the stage output module, and the second end of which is connected to a DC potential or a first potential signal. Preferably, the voltage regulator module includes a fourth capacitor.

6. The gate driving circuit according to claim 3, characterized in that, The control module includes an input unit, a first control unit, and a second control unit. The input unit is used to control the second control signal output by the second output terminal of the control module according to the input signal and the second clock signal; The first control unit is used to control the first control signal output by the first output terminal of the control module according to the second clock signal and the second control signal; The second control unit is used to control the second control signal output by the second output terminal of the control module according to the first clock signal and the first control signal; Preferably, during at least a portion of the first output mode, the voltage of the pulse mode control signal is a first level; in the second output mode, the voltage of the pulse mode control signal is a second level, wherein one of the first level and the second level is low and the other is high; when the voltage of the pulse mode control signal transitions from the second level to the first level, one of the first clock signal and the second clock signal is high and the other is low. Preferably, the input unit includes a sixth transistor, the first terminal of the sixth transistor is connected to the input signal, the second terminal of the sixth transistor is connected to the second output terminal of the control module, and the gate of the sixth transistor is connected to the second clock signal; The first control unit includes a seventh transistor and an eighth transistor. The first terminal of the seventh transistor is connected to the second clock signal, the second terminal of the seventh transistor is connected to the first output terminal of the control module, and the gate of the seventh transistor is connected to the second output terminal of the control module. The first terminal of the eighth transistor is connected to the second potential signal, the second terminal of the eighth transistor is connected to the first output terminal of the control module, and the gate of the eighth transistor is connected to the second clock signal. The second control unit includes a ninth transistor and a tenth transistor. The second terminals of the ninth transistor and the tenth transistor are connected. One of the first terminals of the ninth transistor and the tenth transistor is connected to the second output terminal of the control module, and the other is connected to a first potential signal. One of the gates of the ninth transistor and the tenth transistor is connected to the first output terminal of the control module, and the other is connected to the first clock signal. One of the first potential signal and the second potential signal is at a high level, and the other is at a low level; the first clock signal and the second clock signal have the same frequency but different phases; Preferably, the first potential signal is at a high level, and the second potential signal is at a low level; Preferably, the shift register further includes a second protection module; the second output terminal of the control module is connected to the control terminal of the second output unit via the second protection module; the second output terminal of the control module is connected to the control terminal of the fourth output unit via the second protection module; the control terminal of the second protection module is connected to a conduction level, a DC potential, or a second potential signal. Preferably, the second protection module includes an eleventh transistor.

7. A display panel, characterized in that, include: At least one gate drive circuit as described in any one of claims 1-6.

8. The display panel according to claim 7, characterized in that, The display panel includes a pixel circuit, which includes a driving transistor and a switching transistor, with the switching transistor connected to the driving transistor. At least one of the gate driving circuits includes a first gate driving circuit, which is connected to the gate of the switching transistor. During the first time period, the switching transistors of the multiple rows of pixel circuits are simultaneously turned on, the switching transistors of the multiple rows of pixel circuits are simultaneously connected to the initialization voltage, and the first gate driving circuit operates in the first output mode. During the second time period, the switching transistors of the multiple rows of pixel circuits are turned on row by row, the switching transistors of the multiple rows of pixel circuits are connected to the data voltage, and the first gate driving circuit operates in the second output mode. Preferably, the switching transistor is connected to the gate of the driving transistor.

9. The display panel according to claim 7, characterized in that, The display panel includes pixel circuitry and light-emitting elements. The pixel circuitry includes driving transistors and light-emitting control transistors. The driving transistors, the light-emitting control transistors, and the light-emitting elements are connected in series between a first power line and a second power line. At least one of the gate driving circuits includes a second gate driving circuit, the second gate driving circuit being connected to the gate of the light-emitting control transistor. In the first type of display frame, the light-emitting control transistors of the multiple rows of pixel circuits are simultaneously turned on, and the light-emitting elements connected to the multiple rows of pixel circuits emit light simultaneously. During at least a portion of the time period of the first type of display frame, the second gate driving circuit operates in the first output mode. In the second type of display frame, the light-emitting control transistors of the multiple rows of pixel circuits are turned on row by row, and the light-emitting elements connected to the multiple rows of pixel circuits emit light row by row. During at least a portion of the time period of the second type of display frame, the second gate driving circuit operates in the second output mode.

10. A driving method, characterized in that, The driving method, applied to the gate driving circuit as described in any one of claims 1-6, comprises: In the first output mode, the gate output modules of the multiple shift registers are controlled to simultaneously output a first pulse; In the second output mode, the gate output modules of the multiple shift registers sequentially output the second pulse.

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