Pixel circuit, driving method thereof and display panel

Abstract

The application discloses a pixel circuit, a driving method thereof and a display panel. The pixel circuit comprises a writing module connected with a data voltage end and a first node; the first node is electrically connected with a gate of a driving transistor; the driving transistor is an N-type transistor; an initialization module connected with a first reference voltage end and a second node; an isolation module connected with the second node and the first node; a first capacitor connected with the first node and a third node; a second capacitor connected with the second node and the third node; a first light-emitting control module connected in series with the driving transistor between a first power supply end and the third node; a second light-emitting control module connected with the third node and a fourth node; the fourth node is electrically connected with a light-emitting element; and a reset module connected with a second reference voltage end, the third node or the fourth node. The above technical scheme can improve display quality.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel circuit and its driving method, and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently the mainstream technology for displays in mobile phones, televisions, computers, and other devices. Compared with traditional liquid crystal displays (LCDs), OLED displays have advantages such as low energy consumption, low cost, self-illumination, wide viewing angle, and fast response speed.

[0003] However, due to process deviations, usage time, and changes in the usage environment, the threshold voltage of the driving transistor in the pixel circuit may change, affecting the display quality. Summary of the Invention

[0004] This application provides a pixel circuit and its driving method, as well as a display panel, to improve display quality.

[0005] According to one aspect of this application, a pixel circuit is provided, comprising: The write module is connected to a data voltage terminal, a first node, and a first enable terminal, and is used to transmit the signal from the data voltage terminal to the first node in response to a first scan signal from the first enable terminal; the first node is electrically connected to the gate of a driving transistor, and the driving transistor is an N-type transistor; An initialization module is connected to a first reference voltage terminal, a second node, and a second enable terminal, and is used to transmit the signal from the first reference voltage terminal to the second node in response to the second scan signal from the second enable terminal. An isolation module, connecting the second node, the first node, and the third enable terminal, is used to transmit the signal of the second node to the first node in response to the third scan signal of the third enable terminal; The first capacitor is connected to the first node and the third node; The second capacitor is connected to the second node and the third node; The first light-emitting control module is connected in series with the driving transistor between the first power supply terminal and the third node, and the control terminal of the first light-emitting control module is electrically connected to the fourth enable terminal. The second light-emitting control module is connected to the third node, the fourth node, and the fifth enable terminal, and is used to transmit the signal of the third node to the fourth node in response to the fifth scan signal of the fifth enable terminal; the fourth node is electrically connected to the light-emitting element. A reset module is connected to a second reference voltage terminal, the third or fourth node, and a sixth enable terminal, and is used to transmit the signal from the second reference voltage terminal to the third or fourth node in response to the sixth scan signal of the sixth enable terminal.

[0006] According to another aspect of this application, a driving method for a pixel circuit is provided, for driving the aforementioned pixel circuit; the driving method includes: During the initialization phase, the first reference voltage terminal and the second node, the second node and the first node, and the second reference voltage terminal and the third node are connected; During the compensation phase, the first reference voltage terminal and the second node, the second node and the first node, and the first power supply terminal and the third node are connected; During the data writing phase, the data voltage terminal is connected to the first node and the first reference voltage terminal is connected to the second node; During the light-emitting phase, the first power supply terminal and the third node, as well as the third node and the fourth node, are connected.

[0007] According to another aspect of this application, a display panel is provided, comprising: a plurality of the aforementioned pixel circuits arranged in an array.

[0008] The technical solution of this application, by setting the driving transistor as an N-type transistor, on the one hand, makes the gate-source voltage of the driving transistor independent of the voltage of the first power supply terminal, compensating for the influence of the voltage drop of the first power supply terminal on the conduction current of the driving transistor DT; on the other hand, it makes the charge carriers in the driving transistor electrons, reducing the sensitivity to the threshold voltage and improving the hysteresis and threshold voltage drift of the driving transistor. By setting the write module electrically connected to the gate of the driving transistor, and the initialization module electrically connected to the gate of the driving transistor through the isolation module, the connection between the data voltage terminal and the gate of the driving transistor, the connection between the first reference voltage terminal and the second node, and the connection and isolation between the second node and the gate of the driving transistor can be realized. By designing the timing sequence of the first, second, and third scan signals, the working principle of the pixel circuit can be flexibly designed, and the working process of the pixel circuit can be adjusted. This allows the first light-emitting control module to conduct and change the voltage of the third node N3 to compensate for the threshold voltage of the driving transistor DT. This not only relies on the writing module to stabilize the voltage of the first node N1, but also utilizes the initialization module and the isolation module to stabilize the voltage of the first node N1. In this way, the threshold voltage compensation process is no longer limited by the conduction time of the writing module, which is beneficial to increase the duration of the threshold voltage compensation process and improve the charging rate during the threshold voltage compensation process. This enables the light-emitting element to accurately display grayscale, thereby improving the display quality when the pixel circuit is applied to the display panel.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the circuit structure of the first pixel circuit provided in the embodiments of this application; Figure 2 This is a top view of the structure of the first type of display panel provided in this application embodiment; Figure 3 This is a schematic diagram of the circuit structure of the second pixel circuit provided in the embodiments of this application; Figure 4 This is the first timing diagram provided in the embodiments of this application; Figure 5 This is a schematic diagram of the circuit structure of the third pixel circuit provided in the embodiments of this application; Figure 6 This is a second timing diagram provided in the embodiments of this application; Figure 7 This is a schematic diagram of the circuit structure of the fourth pixel circuit provided in the embodiments of this application; Figure 8 This is a third timing diagram provided in the embodiments of this application; Figure 9 This is a schematic diagram of the circuit structure of the fifth pixel circuit provided in the embodiments of this application; Figure 10 This is the fourth timing diagram provided in the embodiments of this application; Figure 11 This is the fifth timing diagram provided in the embodiments of this application; Figure 12 This is the sixth timing diagram provided in the embodiments of this application; Figure 13 This is a schematic diagram of the circuit structure of the sixth pixel circuit provided in the embodiments of this application; Figure 14 This is a schematic diagram of the circuit structure of the seventh pixel circuit provided in the embodiments of this application; Figure 15 This is the seventh timing diagram provided in the embodiments of this application; Figure 16 This is a schematic diagram of the circuit structure of the eighth pixel circuit provided in the embodiments of this application; Figure 17 This is the eighth timing diagram provided in the embodiments of this application; Figure 18 This is a schematic diagram of the circuit structure of the ninth pixel circuit provided in the embodiments of this application; Figure 19 This is the ninth timing diagram provided in the embodiments of this application; Figure 20 This is a schematic diagram of the circuit structure of the tenth pixel circuit provided in the embodiments of this application; Figure 21 This is the tenth timing diagram provided in the embodiments of this application; Figure 22 This is a flowchart of a pixel circuit driving method provided in an embodiment of this application; Figure 23 This is a top view of the structure of the second type of display panel provided in this application embodiment; Figure 24 This is a top view of the third type of display panel provided in the embodiments of this application; Figure 25 This is a schematic diagram of the circuit structure of the eleventh pixel circuit provided in the embodiments of this application; Figure 26 This is the eleventh timing diagram provided in the embodiments of this application; Figure 27 This is a top view of the fourth type of display panel provided in the embodiments of this application; Figure 28 This is a schematic diagram of the circuit structure of the twelfth pixel circuit provided in the embodiments of this application; Figure 29 This is the twelfth timing diagram provided in the embodiments of this application; Figure 30 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0012] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application.

[0013] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0014] It should be noted that the implementation methods provided in this application can be combined with each other without contradiction.

[0015] Figure 1 This is a schematic diagram of the circuit structure of the first pixel circuit provided in the embodiments of this application. (Reference) Figure 1 The pixel circuit 10 includes a driving transistor DT, a light-emitting element D1, a writing module 11, an initialization module 12, an isolation module 13, a first capacitor C1, a second capacitor C2, a first light-emitting control module 14, a second light-emitting control module 15, and a reset module 16; wherein, the driving transistor DT is an N-type transistor.

[0016] The first end of the write module 11 is connected to the data voltage terminal Vdata, the second end of the write module 11 is connected to the gate of the driving transistor DT at the first node N1, the control terminal of the write module 11 is connected to the first enable terminal SP, and the write module 11 is used to transmit the signal of the data voltage terminal Vdata to the first node N1 in response to the first scan signal of the first enable terminal SP.

[0017] The first terminal of the initialization module 12 is connected to the first reference voltage terminal Vref1, the second terminal of the initialization module 12 is connected to the second node N2, and the control terminal of the initialization module 12 is connected to the second enable terminal S1N. The initialization module 12 is used to transmit the signal of the first reference voltage terminal Vref1 to the second node N2 in response to the second scan signal of the second enable terminal S1N.

[0018] The first end of the isolation module 13 is connected to the second node N2, the second end of the isolation module 13 is connected to the first node N1, and the control connection of the isolation module 13 is the third enable terminal S2N. The isolation module 13 is used to transmit the signal of the second node N2 to the first node N1 in response to the third scan signal of the third enable terminal S2N.

[0019] The first plate of the first capacitor C1 is connected to the first node N1, and the second plate of the first capacitor C1 is connected to the third node N3; the first plate of the second capacitor C2 is connected to the second node N2, and the second plate of the second capacitor C2 is connected to the third node N3.

[0020] The first light-emitting control module 14 is connected in series with the driving transistor DT between the first power supply terminal PV1 and the third node N3. The control terminal of the first light-emitting control module 14 is electrically connected to the fourth enable terminal EM1. In a feasible embodiment, the first light-emitting control module 14 can be used to transmit the signal of the first power supply terminal to the third node in response to the fourth scan signal of the fourth enable terminal EM1.

[0021] The first end of the second light-emitting control module 15 is connected to the third node N3, and the second end of the second light-emitting control module 15 is connected to the light-emitting element D1 at the fourth node N4. The control end of the second light-emitting control module 15 is connected to the fifth enable end EM2, and is used to transmit the signal of the third node N3 to the fourth node N4 in response to the fifth scan signal of the fifth enable end EM2. In an optional embodiment, the light-emitting element D1 is also electrically connected to the second power supply end PV2. During the light-emitting stage of the pixel circuit 10, the fourth node N4 and the second power supply end PV2 can form a current to drive the light-emitting element D1 to emit light for display.

[0022] The first terminal of the reset module 16 is connected to the second reference voltage terminal Vref2, the second terminal of the reset module 16 is connected to the third node N3 or the fourth node N4, the control terminal of the reset module 16 is connected to the sixth enable terminal SPX, and the reset module 16 is used to transmit the signal of the second reference voltage terminal Vref2 to the third node N3 or the fourth node N4 in response to the sixth scan signal of the sixth enable terminal SPX.

[0023] Specifically, the write module 11 can transmit the signal of the data voltage terminal Vdata to the gate of the driving transistor DT when the first scan signal of the first enable terminal SP is at the enable level, and can control the gate voltage of the driving transistor DT by adjusting the voltage of the data voltage terminal Vdata; the initialization module 12 can transmit the signal of the first reference voltage Vref1 to the second node N2 when the second scan signal of the second enable terminal S1N is at the enable level; the isolation module 13 can transmit the signal of the second node N2 to the gate of the driving transistor DT when the third scan signal of the third enable terminal S2N is at the enable level, and can also control the gate voltage of the driving transistor DT by adjusting the voltage of the first reference voltage Vref1.

[0024] In an optional implementation, the third node N3 is electrically connected to the source of the driving transistor DT, and the first capacitor C1 is connected between the gate and the source of the driving transistor DT. The first capacitor C1 can realize the voltage coupling between the gate and the source of the driving transistor DT. When the source voltage changes, the gate voltage can also change synchronously, which is beneficial to maintain the stability of the gate-source voltage of the driving transistor DT and enable the light-emitting element D1 to accurately display light emission. Meanwhile, the second capacitor C2 is connected between the source of the driving transistor DT and the second node N3. The second capacitor C2 can stabilize the source voltage of the driving transistor DT, and when the gate voltage changes, it can change the coupling ratio of the source voltage and adjust the coupling coefficient. For example, when the signal of the data voltage terminal Vdata is written to the gate of the driving transistor DT, the change in the gate is ΔVN1, and the change in the source voltage can be ΔVN3=[C1 / (C1+C2)]×ΔVN1. At this time, the change in the gate-source voltage is ΔVGS=ΔVN1-ΔVN3=[C2 / (C1+C2)]×ΔVN1, so as to change the gate-source voltage and adjust the display grayscale of the light-emitting element D1.

[0025] The first light-emitting control module 14 can be turned on when the fourth scan signal of the fourth enable terminal EM1 is at the enable level, so that the signal of the first power supply terminal PV1 can be transmitted to the third node N3 through the first light-emitting control module 14 and the driving transistor DT, thereby changing the voltage of the third node N3. When the voltage of the third node N3 changes, if the first node N1 can simultaneously write an active signal, such as the signal of the first reference voltage terminal Vref1, so that the voltage of the first node N1 remains stable, the gate-source voltage VGS of the driving transistor DT can be changed when the voltage of the third node N3 changes, so that the gate-source voltage VGS of the driving transistor DT gradually approaches the threshold voltage VTH. The first capacitor C1 can store the threshold voltage VTH between the gate and source of the driving transistor DT. That is, no matter how the coupling between the gate and source of the driving transistor DT changes, the gate-source voltage VGS includes the threshold voltage VTH, so that VGS-VTH is almost independent of the threshold voltage VTH, compensating for the influence of the threshold voltage of the driving transistor DT on the conduction current of the driving transistor DT, and reducing the influence of the threshold voltage on the conduction current of the driving transistor DT. When the voltage of the third node N3 changes, if the first node N1 is floating and no active signal is written, the voltage of the first node N1 can be coupled by the first capacitor C1. When the voltage of the third node N3 changes, the gate-source voltage of the driving transistor DT will not change, thus stabilizing the gate-source voltage of the driving transistor DT and enabling the light-emitting element D1 to accurately display light emission.

[0026] The second light-emitting control module 15 is activated when the fifth scan signal at the fifth enable terminal EM2 is at the enable level, transmitting the signal from the third node N3 to the fourth node N4. When both the fourth scan signal at the fourth enable terminal EM1 and the fifth scan signal at the fifth enable terminal EM2 are at the enable level, the signal at the first power supply terminal PV1 can be transmitted to the fourth node N4, creating a voltage difference across the light-emitting element D1, thus enabling light emission. The light-emitting element D1 can be driven by current. A driving current can be formed between the first power supply terminal PV1 and the second power supply terminal PV2 through the first light-emitting control module 14, the driving transistor DT, the second light-emitting control module 15, and the light-emitting element D1. The driving current can be Id = k × (VGS - VTH). 2 Where k is the current coefficient of the driving transistor DT, which is related to the material properties and size parameters of the driving transistor DT; VGS is the gate-source voltage of the driving transistor DT; and VTH is the threshold voltage of the driving transistor DT. Simultaneously, the driving transistor DT is an N-type transistor, allowing its drain to be electrically connected to the first power supply terminal PV1 (including direct and indirect connections), and its source to be electrically connected to the third node N3 (including direct and indirect connections). Furthermore, the gate and source of the driving transistor DT can be coupled through the first capacitor C1. The gate-source voltage of the driving transistor DT can be independent of the voltage of the first power supply terminal PV1, thus compensating for the influence of the voltage drop of the first power supply terminal PV1 on the conduction current of the driving transistor DT.

[0027] The reset module 16 can transmit the signal of the second reference voltage terminal Vref2 to the third node N3 or the fourth node N4 when the sixth scan signal of the sixth enable terminal SPX is at the enable level. When the second terminal of the reset module 16 is directly electrically connected to the third node N3, the sixth scan signal of the sixth enable terminal SPX being at the enable level can make the voltage of the third node N3 equal to the voltage of the second reference voltage terminal Vref2, thereby resetting the third node N3; the fifth scan signal of the fifth enable terminal EM2 and the sixth scan signal of the sixth enable terminal SPX being at the same enable level can also make the voltage of the fourth node N4 equal to the voltage of the second reference voltage terminal Vref2, thereby resetting the fourth node N4; conversely, when the second terminal of the reset module 16 is directly electrically connected to the fourth node N4, the sixth scan signal of the sixth enable terminal SPX being at the enable level can reset the fourth node N4, and the fifth scan signal of the fifth enable terminal EM2 and the sixth scan signal of the sixth enable terminal SPX being at the same enable level can reset the third node N3.

[0028] It is understood that the scanning signal described above includes an enable level. When the scanning signal is at the enable level, it can control the conduction between the first and second terminals of the module and enable signal transmission. The scanning signal described above can also be at the disable level. When the scanning signal is at the disable level, it can control the cutoff between the first and second terminals of the module, thereby stopping signal transmission.

[0029] In one embodiment, the enable level can be high and the disable level can be low; in another embodiment, the enable level can be low and the disable level can be high; in yet another embodiment, the enable level of a portion of the scan signal can be high and the disable level can be low, and the enable level of a portion of the scan signal can be low and the disable level can be high. This application does not specifically limit the high / low of the enable and disable levels; the high / low of the enable and disable levels are related to the specific structure of the module it controls. For example, when the controlled module includes transistors and the transistors are P-channel transistors, the enable level is low and the disable level is high; while when the controlled module includes transistors and the transistors are N-channel transistors, the enable level is high and the disable level is low. In this application, the high / low of the enable and disable levels can be defined according to actual needs.

[0030] It should be noted that high level and low level refer to the voltage used to control the module to turn on or off, but are not limited to a certain fixed voltage. For example, voltages from +15V to +30V that can control the module to be in the same state can all be high level, and voltages from -10V to -5V that can control the module to be in the same state can all be low level.

[0031] For example, the pixel circuit 10 provided in this application embodiment can be applied to a display panel. Figure 2 This is a top view structural diagram of the first type of display panel provided in this application embodiment. (Reference) Figure 2 The display area AA of the display panel 01 can be configured with multiple pixel circuits 10 arranged in an array, multiple first scan lines SL1, multiple second scan lines SL2, multiple third scan lines SL3, multiple fourth scan lines SL4, multiple fifth scan lines SL5, and multiple sixth scan lines SL6. The non-display area NA of the display panel 01 can be configured with a first driving circuit 20, which includes a first shift register VSR1, a second shift register VSR2, a third shift register VSR3, a fourth shift register VSR4, a fifth shift register VSR5, and a sixth shift register VSR6. Each of the first shift register VSR1, second shift register VSR2, third shift register VSR3, fourth shift register VSR4, fifth shift register VSR5, and sixth shift register VSR6 includes multiple cascaded shift register units.

[0032] refer to Figure 1 and Figure 2 The shift register unit of the first shift register VSR1 can be electrically connected to the first enable terminal SP of the pixel circuit 10 through the first scan line SL1, providing a first scan signal to the control terminal of the writing module 11; the shift register unit of the second shift register VSR2 can be electrically connected to the second enable terminal S1N of the pixel circuit 10 through the second scan line SL2, providing a second scan signal to the control terminal of the initialization module 12; the shift register unit of the third shift register VSR3 can be electrically connected to the third enable terminal S2N of the pixel circuit 10 through the third scan line SL3, providing a third scan signal to the control terminal of the isolation module 13; the fourth shift register... The shift register unit of bit register VSR4 can be electrically connected to the fourth enable terminal EM1 of pixel circuit 10 through the fourth scan line SL4, providing a fourth scan signal to the control terminal of the first light-emitting control module 14; the shift register unit of fifth shift register VSR5 can be electrically connected to the fifth enable terminal EM2 of pixel circuit 10 through the fifth scan line SL5, providing a fifth scan signal to the control terminal of the second light-emitting control module 15; the shift register unit of sixth shift register VSR6 can be electrically connected to the sixth enable terminal SPX of pixel circuit 10 through the sixth scan line SL6, providing a sixth scan signal to the control terminal of reset module 16. Pixel circuit 10 can receive scan signals output from multiple shift registers in the first driving circuit 20 to control the working state of each module in pixel circuit 10, enabling pixel circuit 10 to provide corresponding driving current to light-emitting element D1 based on the signal of data voltage terminal Vdata, driving light-emitting element D1 to display corresponding gray levels. Multiple light-emitting elements D1 arranged in display area AA all display corresponding gray levels, forming a display image.

[0033] Continue to refer to Figure 1 and Figure 2 The display area AA of the display panel 01 can also be provided with multiple data lines DL, and the non-display area NA can also be provided with a second driving circuit 30. The second driving circuit 30 includes multiple data voltage terminals Do. The data voltage terminals Do can be electrically connected to the data voltage terminal Vdata of the pixel circuit 10 through the data lines DL, providing data signals to the first terminal of the writing module 11. In addition, the display panel 01 can also include a first common voltage terminal, a second common voltage terminal, a third common voltage terminal, and a fourth common voltage terminal (…). Figure 2 (Not shown in the image), the display area AA of the display panel 01 can also be configured with multiple first reference lines VL1, multiple second reference lines VL2, multiple first power lines PL1, and multiple second power lines PL2 (not shown in the image). Figure 2(Not shown in the image), the first common voltage terminal, the second common voltage terminal, the third common voltage terminal, and the fourth common voltage terminal can be electrically connected to the first reference voltage terminal Vref1, the second reference voltage terminal Vref2, the first power supply terminal PV1, and the second power supply terminal PV2 of the pixel circuit 10 through the first reference line VL1, the second reference line VL2, the first power supply line PL1, and the second power supply line PL2, respectively, to provide the first reference signal, the second reference signal, the first power supply signal, and the second power supply signal, respectively.

[0034] It should be noted that the figure only exemplarily shows that the shift register unit in the shift register is electrically connected to only one scan line, and the data voltage terminal is electrically connected to only one data line. In other embodiments, at least some of the shift register units in the shift register may also be electrically connected to multiple scan lines, and the data voltage terminal may be electrically connected to multiple data lines through a gating switch. Figure 2 (Not shown in the text).

[0035] It should also be noted that the figure only exemplarily shows that all shift registers are located on one side of the display area; the embodiments of this application do not limit the location of the shift registers. In optional embodiments, at least some shift registers may be located on both sides, three sides, or four sides of the display area. Figure 2 (Not shown in the image). In other alternative implementations, at least a portion of the shift register may also be located in the display area (…). Figure 2 (Not shown in the image).

[0036] The pixel circuit provided in this application embodiment, by setting the driving transistor to an N-type transistor, can, on the one hand, make the gate-source voltage of the driving transistor independent of the voltage of the first power supply terminal, compensating for the influence of the voltage drop of the first power supply terminal on the conduction current of the driving transistor DT; on the other hand, make the charge carriers in the driving transistor electrons, reducing the sensitivity to the threshold voltage and improving the hysteresis and threshold voltage drift of the driving transistor. By setting the write module electrically connected to the gate of the driving transistor, and the initialization module electrically connected to the gate of the driving transistor through the isolation module, the connection between the data voltage terminal and the gate of the driving transistor, the connection between the first reference voltage terminal and the second node, and the connection between the second node and the gate of the driving transistor can be realized. The isolation mechanism allows for flexible design of the pixel circuit's operating principle by adjusting the timing of the first, second, and third scan signals. This enables the pixel circuit to adjust its operation, allowing the first light-emitting control module to change the voltage of the third node N3 to compensate for the threshold voltage of the driving transistor DT. This not only relies on the writing module to stabilize the voltage of the first node N1 but also utilizes the initialization and isolation modules. Consequently, the threshold voltage compensation process is no longer limited by the writing module's conduction time, increasing the duration of the threshold voltage compensation process and improving the charging rate. This allows the light-emitting element to accurately display grayscale, thereby improving display quality when the pixel circuit is applied to a display panel.

[0037] In an alternative embodiment, reference continues. Figure 1 The first light-emitting control module 14 is connected to the first power supply terminal PV1, the fifth node N5, and the fourth enable terminal EM1. It is used to transmit the signal of the first power supply terminal PV1 to the fifth node N5 in response to the fourth scan signal of the fourth enable terminal EM1. The fifth node N5 is electrically connected to the first terminal of the driving transistor DT, and the second terminal of the driving transistor DT is electrically connected to the third node N3.

[0038] Specifically, the first terminal of the first light-emitting control module 14 is connected to the first power supply terminal PV1, the second terminal is connected to the fifth node N5, and the control terminal is connected to the fourth enable terminal EM1. When the fourth scan signal of the fourth enable terminal EM1 is at the enable level, the first light-emitting control module 14 can transmit the signal of the first power supply terminal PV1 to the fifth node N5. When the driving transistor DT is turned on, the signal of the first power supply terminal PV1 can be transmitted to the third node N3, changing the voltage of the third node N3. When the voltage of the third node N3 changes, if the first node N1 can simultaneously write an active signal, the first capacitor C1 can store the threshold voltage VTH between the gate and source of the driving transistor DT, compensating for the influence of the threshold voltage of the driving transistor DT on the conduction current of the driving transistor DT.

[0039] In another alternative embodiment, Figure 3This is a schematic diagram of the circuit structure of the second pixel circuit provided in an embodiment of this application. (Reference) Figure 3 The first terminal of the driving transistor DT is electrically connected to the first power supply terminal PV1, and the second terminal of the driving transistor DT is electrically connected to the fifth node N5. The first light-emitting control module 14 is connected to the fifth node N5, the third node N3, and the fourth enable terminal EM1, and is used to transmit the signal of the fifth node N5 to the third node N3 in response to the fourth scan signal of the fourth enable terminal EM1.

[0040] Specifically, the first terminal of the first light-emitting control module 14 is connected to the fifth node N5, the second terminal is connected to the third node N3, and the control terminal is connected to the fourth enable terminal EM1. When the fourth scan signal of the fourth enable terminal EM1 is at the enable level, the first light-emitting control module 14 can transmit the signal of the fifth node N5 to the third node N3. When the driving transistor DT is turned on, the signal of the first power supply terminal PV1 can be transmitted to the fifth node N5 and the third node N3, changing the voltage of the third node N3. When the voltage of the third node N3 changes, if the first node N1 can simultaneously write an active signal, the first capacitor C1 can store the threshold voltage VTH between the gate of the driving transistor DT and the third node N3. When a driving current is formed in the driving transistor DT, the first light-emitting control module 14 is turned on, making the voltage of the fifth node N5 the same as the voltage of the third node N3. This allows the gate-source voltage VGS of the driving transistor DT to include the threshold voltage VTH, compensating for the influence of the threshold voltage VTH of the driving transistor DT on the conduction current of the driving transistor DT.

[0041] Regardless of whether the first light-emitting control module 14 is connected between the first power supply terminal PV1 and the driving transistor DT, or between the driving transistor DT and the third node N3, when the first light-emitting control module 14 is turned on, the first capacitor C1 can store the threshold voltage VTH of the driving transistor DT, thereby compensating for the influence of the threshold voltage VTH on the driving current. For ease of explanation and understanding, unless otherwise specified, the embodiments of this application will be illustrated by the example of the first light-emitting control module 14 being connected between the first power supply terminal PV1 and the driving transistor DT.

[0042] The working principle of the pixel circuit 10 provided in this application embodiment will be explained below in conjunction with the timing of the working period of the pixel circuit 10.

[0043] Optionally, the working period of the pixel circuit 10 includes a compensation phase t1 and a data writing phase t2; in the compensation phase t1, the second scan signal of the second enable terminal S1N and the third scan signal of the third enable terminal S2N are both at the enable level; in the data writing phase t2, the third scan signal of the third enable terminal S2N is at the disable level.

[0044] For example, taking the case where the enable level of the scan signal is always high and the disable level is always low, Figure 4 This is a first timing diagram provided in the embodiments of this application, wherein, Figure 4 Specifically, it can be corresponding to Figure 1 or Figure 3 The driving timing diagram of the pixel circuit is shown. (Reference) Figure 1 and Figure 4 During the compensation phase t1, the second scan signal of the second enable terminal S1N and the third scan signal of the third enable terminal S2N are both at the enable level, which enables the initialization module 12 and the isolation module 13 to be turned on. That is, the first reference voltage terminal Vref1 and the second node N2, as well as the second node N2 and the first node N1, are connected. The signal of the first reference voltage terminal Vref1 can be transmitted to the first node N1, which initializes the gate of the driving transistor DT to the voltage of the first reference voltage terminal Vref1.

[0045] During the data writing phase t2, the first scan signal of the first enable terminal SP is at the enable level, the writing module 11 is turned on, and the gate of the driving transistor DT can write the signal of the data voltage terminal Vdata. At this time, the third scan signal of the third enable terminal S2N is at the disable level, the isolation module 13 is turned off, and the second node N2 and the first node N1 are cut off, which can realize the isolation between the second node N2 and the first node N1, so that the first node N1 is stable at the voltage of the data voltage terminal Vdata, and avoid the signal of the second node N2 from interfering with the first node N1.

[0046] Thus, the isolation module 13 enables the connection between the first reference voltage terminal Vref1 and the first node N1, as well as the isolation between the first node N1 and the second node N2. Furthermore, connecting the first reference voltage terminal Vref1 and the first node N1 during the compensation phase t1 stabilizes the gate of the driving transistor DT at the voltage of the first reference voltage terminal Vref1. Isolating the first node N1 and the second node N2 during the data writing phase t2 stabilizes the gate of the driving transistor DT at the voltage of the data voltage terminal Vdata. Additionally, during the compensation phase t1 and the data writing phase t2, the first reference voltage terminal Vref1 and the gate of the driving transistor DT, as well as the data voltage terminal Vdaat and the gate of the driving transistor DT, are time-divisionally conducted. This separates the compensation phase t1 from the data writing phase t2, allowing the compensation process of the compensation phase t1 to be unaffected by the data writing phase t2. This increases the compensation time of the compensation phase t1, improves the charging rate during the compensation process, and thus improves the accuracy of the driving current. When the pixel circuit is applied to the display panel, this effectively improves the display quality.

[0047] In an alternative embodiment, reference continues. Figure 1 and Figure 4 When the reset module 16 is connected to the second reference voltage terminal Vref2, the fourth node N4, and the sixth enable terminal SPX, during the compensation phase t1, the fourth scan signal of the fourth enable terminal EM1 is at the enable level, and the fifth scan signal of the fifth enable terminal EM2 is at the disable level.

[0048] For example, taking the case where the enable level of the scan signal is all high and the disable level is all low, refer to... Figure 1 and Figure 4 During the compensation phase t1, the first scan signal of the first enable terminal SP is at a disabled level, while the second scan signal of the second enable terminal S1N and the third scan signal of the third enable terminal S2N are both at enabled levels, driving the gate of the transistor DT to write the signal of the first reference voltage terminal Vref1. The fourth scan signal of the fourth enable terminal EM1 is at an enabled level, and the first light-emitting control module 14 is turned on, enabling the first power supply terminal PV1 and the third node N3 to conduct. The signal of the first power supply terminal PV1 can be transmitted to the third node N3, changing the signal of the third node N3 to compensate the threshold voltage VTH of the driving transistor DT. At the same time, the fifth scan signal of the fifth enable terminal EM2 is at a disabled level, and the second light-emitting control module 15 is turned off, which can cut off the connection between the fourth node N4 and the third node N3, so as to prevent the signal of the second reference voltage terminal Vref2 and / or the signal of the fourth node N4 from being transmitted to the third node N3 through the second light-emitting control module, affecting the threshold voltage VTH compensation process.

[0049] It is understandable that when the second terminal of the reset module 16 is directly connected to the fourth node N4, during the compensation phase t1, the second light-emitting control module 15 is turned off, and the reset module 16 can be turned on or off. That is, the sixth scan signal of the sixth enable terminal SPX can be either enabled or disabled, neither of which will affect the potential of the third node N3, nor will it affect the threshold voltage VTH compensation process (as long as the fifth scan signal of the fifth enable terminal EM2 is disabled during the compensation phase t1, the second light-emitting control module 15 can be turned off). Here, "the second terminal of the reset module 16 is directly connected to the fourth node N4" means that no device or component is placed between the second terminal of the reset module 16 and the fourth node N4, but conductive structures such as metal wires, lap holes, and lap electrodes can be used. Figure 1 Electrical connection (not shown in the image).

[0050] In another alternative embodiment, Figure 5 This is a schematic diagram of the circuit structure of the third pixel circuit provided in the embodiments of this application. Figure 6 This is a second timing diagram provided in the embodiments of this application, wherein, Figure 6 Specifically, it can be corresponding to Figure 5 The driving timing diagram of the pixel circuit is shown. (Reference) Figure 5 and Figure 6 When the reset module 16 is connected to the second reference voltage terminal Vref2, the third node N3, and the sixth enable terminal SPX, during the compensation phase t1, the fourth scan signal of the fourth enable terminal EM1 is at the enable level, while the fifth scan signal of the fifth enable terminal EM2 and the sixth scan signal of the sixth enable terminal SPX are both at the disable level.

[0051] For example, continuing with the case where the enable level of the scan signal is always high and the disable level is always low, refer to... Figure 5 and Figure 6 ,and Figure 1 , Figure 4 The similarities will not be repeated; only the differences will be explained. During the compensation phase t1, the fifth scan signal of the fifth enable terminal EM2 and the sixth scan signal of the sixth enable terminal SPX are both at a disabled level. The second light emission control module 15 and the reset module 16 are both turned off to cut off the signal transmission between the second reference voltage terminal Vref2 and the third node N3, as well as between the fourth node N4 and the third node N3. This prevents the signal transmission of the second reference voltage terminal Vref2 and / or the fourth node N4 to the third node N3, which would affect the threshold voltage VTH compensation process.

[0052] It is understandable that when the second terminal of the reset module 16 is directly connected to the third node N3, both the second light-emitting control module 15 and the reset module 16 are turned off during the compensation phase t1. That is, the sixth scan signal of the sixth enable terminal SPX must also be at a non-enable level. This avoids the reset module 16 affecting the potential of the third node N3 and also prevents the reset module 16 from affecting the threshold voltage VTH compensation process. Here, "the second terminal of the reset module 16 is directly connected to the third node N3" means that no device or component is placed between the second terminal of the reset module 16 and the third node N3, but conductive structures such as metal wires, lap holes, and lap electrodes can be used. Figure 1 Electrical connection (not shown in the image).

[0053] In yet another alternative embodiment, reference continues to... Figure 1 and Figure 4 When the reset module 16 is connected to the second reference voltage terminal Vref2, the fourth node N4, and the sixth enable terminal SPX, during the data writing stage t2, the second scan signal of the second enable terminal S1N is at the enable level, and the third scan signal of the third enable terminal S2N, the fourth scan signal of the fourth enable terminal EM1, and the fifth scan signal of the fifth enable terminal EM2 are all at the disable level.

[0054] For example, taking the case where the enable level of the scan signal is all high and the disable level is all low, continue to refer to... Figure 1 and Figure 4During the data writing phase t2, the first scan signal of the first enable terminal SP is at the enable level, the writing module 11 is turned on, and the first node N1 can write the signal of the data voltage terminal Vdata. When the voltage of the first node N1 changes, the voltage of the third node N3 can also change through the first capacitor C1. At the same time, the second scan signal of the second enable terminal S1N is at the enable level, the third scan signal of the third enable terminal S2N is a non-enable signal, the initialization module 12 is turned on, the isolation module 13 is turned off, the second node N2 writes the signal of the first reference voltage terminal Vref1, and the second node N2 is isolated from the first node N1, which can avoid a short circuit between the first reference voltage terminal Vref1 and the data voltage terminal Vdaat. Through the initialization module 12 and the second capacitor C2, the coupling coefficient of the third node N3 can be adjusted so that the voltage change of the third node N3 is not equal to the voltage change of the first node N1. In this way, the gate-source voltage VGS of the driving transistor DT can be changed, and the data signal of the data voltage terminal Vdata is written to the gate-source voltage VGS of the driving transistor DT.

[0055] In addition, continue to refer to Figure 1 and Figure 4 During the data writing phase t2, the fourth scan signal of the fourth enable terminal EM1 and the fifth scan signal of the fifth enable terminal EM2 are both at a disabled level. The first light-emitting control module 14 and the second light-emitting control module 15 are both turned off, thus cutting off the connection between the first power supply terminal PV1 and the third node N3, and between the fourth node N4 and the third node N3. This prevents the signal from the first power supply terminal PV1 from affecting the signal of the third node N3 through the first light-emitting control module 14, and the signal from the second reference voltage terminal Vref2 and / or the signal from the fourth node N4 from affecting the signal of the third node N3 through the second light-emitting control module, thereby affecting the data writing process. During the data writing phase t2, the reset module 16 can be either turned on or off; that is, the sixth scan signal of the sixth enable terminal SPX can be at an enabled level or a disabled level, neither of which will affect the potential of the third node N3 or the data writing process.

[0056] In yet another alternative embodiment, reference continues to... Figure 5 and Figure 6 When the reset module 16 is connected to the second reference voltage terminal Vref2, the fourth node N4, and the sixth enable terminal SPX, during the data writing stage t2, the second scan signal of the second enable terminal S1N is at the enable level, and the third scan signal of the third enable terminal S2N, the fourth scan signal of the fourth enable terminal EM1, the fifth scan signal of the fifth enable terminal EM2, and the sixth scan signal of the sixth enable terminal SPX are all at the disable level.

[0057] For example, continuing with the case where the enable level of the scan signal is always high and the disable level is always low, refer to... Figure 5 and Figure 6 ,and Figure 1 , Figure 4 The similarities will not be repeated; only the differences will be explained. During the data writing phase t2, the sixth scan signal of the sixth enable terminal SPX is also at a disabled level, and the reset module 16 is turned off to cut off the connection between the second reference voltage terminal Vref2 and the third node N3. This prevents the second reference voltage terminal Vref2 from affecting the potential of the third node N3 through the reset module 16, thus affecting the data writing process.

[0058] Based on the above embodiments, the operating period of the pixel circuit 10 also includes an initialization phase t0. Continuing with the example where all enable levels of the scan signals are high and all disable levels are low, refer to... Figure 1 and Figure 4 When the reset module 16 is connected to the second reference voltage terminal Vref2, the fourth node N4, and the sixth enable terminal SPX, during the initialization phase t0, the second scan signal of the second enable terminal S1N, the third scan signal of the third enable terminal S2N, the fifth scan signal of the fifth enable terminal EM2, and the sixth scan signal of the sixth enable terminal SPX all include an enable level. The initialization module 12, the isolation module 13, the second light-emitting control module 15, and the reset module 16 are all turned on, enabling the voltage of the first node N1 to be initialized to the voltage of the first reference voltage terminal Vref1, and the voltage of the third node N3 to be initialized to the voltage of the second reference voltage terminal Vref2. At this time, the first scan signal of the first enable terminal SP and the fourth scan signal of the fourth enable terminal EM1 are both disabled signals. That is, during the initialization phase t0, the write module 11 and the first light-emitting control module 14 are both turned off. In one embodiment, the first reference voltage terminal Vref1 is greater than the second reference voltage terminal Vref2+VTH, and during the initialization phase t0, the driving transistor DT can be fully turned on.

[0059] Based on the above embodiments, Figure 5 and Figure 6 When the reset module 16 is connected to the second reference voltage terminal Vref2, the third node N3, and the sixth enable terminal SPX, during the initialization phase t0, the second scan signal of the second enable terminal S1N, the third scan signal of the third enable terminal S2N, and the sixth scan signal of the sixth enable terminal SPX all include an enable level. The initialization module 12, the isolation module 13, and the reset module 16 are all turned on, which enables the voltage of the first node N1 to be initialized to the voltage of the first reference voltage terminal Vref1, and the voltage of the third node N3 to be initialized to the voltage of the second reference voltage terminal Vref2. In one embodiment, the first reference voltage terminal Vref1 is greater than the second reference voltage terminal Vref2+VTH. During the initialization phase t0, the driving transistor DT can be fully turned on.

[0060] It is understandable that when the second terminal of the reset module 16 is directly connected to the fourth node N4, both the second light-emitting control module 15 and the reset module 16 are turned on during the initialization phase t0. That is, the fifth scan signal of the fifth enable terminal EM2 and the sixth scan signal of the sixth enable terminal SPX both include the enable level. When the second terminal of the reset module 16 is directly connected to the third node N3, the reset module 16 is turned on during the initialization phase t0. The second light-emitting control module 15 can be turned on or off. That is, the sixth scan signal of the sixth enable terminal SPX includes the enable level. The fifth scan signal of the fifth enable terminal EM2 can be either the enable level or the disable level. Neither of these conditions affects the initialization of the voltage of the third node N3 to the voltage of the second reference voltage terminal Vref2.

[0061] Taking the example where the enable level of the scan signal is always high and the disable level is always low, Figure 7 This is a schematic diagram of the circuit structure of the fourth pixel circuit provided in the embodiments of this application, wherein, Figure 7 The driving timing of the pixel circuit shown can be Figure 4 The timing diagram is shown below. (Followed by...) Figure 4 and Figure 7 The working process of the pixel circuit provided in the embodiments of this application will be described in detail.

[0062] For example, refer to Figure 7 The writing module 11 includes a writing transistor M2, the initialization module 12 includes an initialization transistor M5, the isolation module 13 includes an isolation transistor M4, the first light-emitting control module 14 includes a first light-emitting control transistor M1, the second light-emitting control module 15 includes a second light-emitting control transistor M6, and the reset module 16 includes a reset transistor M7. In one embodiment, the writing transistor M2, the initialization transistor M5, the isolation transistor M4, the first light-emitting control transistor M1, the second light-emitting control transistor M6, and the reset transistor M7 are all N-type transistors. In other embodiments, the writing transistor M2, the initialization transistor M5, the isolation transistor M4, the first light-emitting control transistor M1, the second light-emitting control transistor M6, and the reset transistor M7 may also all be P-type transistors, or some may be P-type transistors and some may be N-type transistors.

[0063] The operating period of the pixel circuit 10 may include multiple display cycles, which may include an initialization phase t0, a compensation phase t1, a data compensation phase t2, and a light emission phase t3. Taking the example that all transistors in the pixel circuit 10 are N-type transistors, the following description, in conjunction with the potentials of each scanning signal, provides an exemplary illustration of this embodiment.

[0064] During the initialization phase t0, the first scan signal of the first enable terminal SP and the fourth scan signal of the fourth enable terminal EM1 are both at a low level (disabled). The second scan signal of the second enable terminal S1N, the third scan signal of the third enable terminal S2N, the fifth scan signal of the fifth enable terminal EM2, and the sixth scan signal of the sixth enable terminal SPX are all at a high level (enabled). The write transistor M2 and the first light-emitting control transistor M1 are both turned off, while the initialization transistor M5, the isolation transistor M4, the second light-emitting control transistor M6, and the reset transistor M7 are all turned on. The voltages of the first node N1 and the second node N2 are both equal to the voltage of the first reference voltage terminal Vref1, i.e., VN1=VN2=Vref1; the voltages of the third node N3 and the fourth node N4 are both equal to the voltage of the second reference voltage terminal Vref2, i.e., VN3=VN4=Vref2. In one embodiment, Vref1 > Vref2 + VTH, which makes the gate-source voltage VGS = VN1 - VN3 = Vref1 - Vref2 > VTH of the driving transistor DT, so that the driving transistor DT is fully turned on.

[0065] During the compensation phase t1, the first scan signal of the first enable terminal SP and the fifth scan signal of the fifth enable terminal EM2 are both at a low level and are not enabled. The second scan signal of the second enable terminal S1N, the third scan signal of the third enable terminal S2N, and the fourth scan signal of the fourth enable terminal EM1 are all at a high level and are enabled. The write transistor M2 and the second light-emitting control transistor M6 are both turned off, and the initialization transistor M5, the isolation transistor M4, and the first light-emitting control transistor M1 are all turned on. The voltages of the first node N1 and the second node N2 remain at the voltage of the first reference voltage terminal Vref1, i.e., VN1=VN2=Vref1; the signal of the first power supply terminal PV1 is transmitted to the third node N3 through the first light-emitting control transistor M1 and the driving transistor DT until VN3=Vref1-VTH, the gate-source voltage VGS of the driving transistor DT=VN1-VN3=Vref1-Vref2=VTH, the driving transistor DT stops conducting, and the threshold voltage VTH of the driving transistor DT can be compensated and stored between the gate and source of the driving transistor DT; the voltage of the fourth node N4 can continue to remain at the voltage of the second reference voltage terminal Vref2, i.e., VN4=Vref2.

[0066] When the reset transistor M7 is connected to the fourth node N4, during the compensation phase t1, the reset transistor M7 can be turned on or off. That is, the sixth scan signal of the sixth enable terminal SPX can be at an enabled level or a disabled level. In either case, the voltage of the fourth node N4 is VN4 = Vref2. Taking the sixth scan signal of the sixth enable terminal SPX at an enabled level and the reset transistor M7 being turned on during the compensation phase t1 as an example, before the fourth scan signal of the fourth enable terminal EM1 changes from a disabled low level to an enabled high level, the fifth scan signal of the fifth enable terminal EM2 first changes from an enabled high level to a disabled low level. That is, before the first light-emitting control transistor M1 is turned on, the second light-emitting control transistor M6 is turned off to avoid a short circuit between the first power supply terminal PV1 and the second reference voltage terminal Vref2.

[0067] During the data writing phase t2, the third scan signal of the third enable terminal S2N and the fourth scan signal of the fourth enable terminal EM1 are both enabled at a high level, and the fifth scan signal of the fifth enable terminal EM2 is both disabled at a low level. The first scan signal of the first enable terminal SP and the second scan signal of the second enable terminal S1N are both enabled at a high level. The isolation transistor M4, the first light-emitting control transistor M1, and the second light-emitting control transistor M6 are turned off, and the writing transistor M2 and the initialization transistor M5 are turned on. The voltage change of the first node N1 is the voltage of the data voltage terminal Vdata, that is, it changes from VN1=Vref1 to VN1=Vdata, and the voltage change of the first node N1 is ΔVN1=Vdata-Vref1; the voltage of the second node N2 continues to be the voltage of the first reference voltage terminal Vref1, that is, VN2=Vref1; the second node N3 is coupled by the first capacitor C1 and the second capacitor C2, and the voltage change of the third node N3 is ΔVN3=[C1 / (C1+C2)]×ΔVN1=[C1 / (C1+C2)]×(Vdata-Vref1), that is, VN3=Vref1-VTH+ΔVN3=Vref1-VTH+[C1 / (C1+C2)]×(Vdata-Vref1); the voltage of the fourth node N4 can continue to be the voltage of the second reference voltage terminal Vref2, that is, VN4=Vref2.

[0068] When the reset transistor M7 is connected to the fourth node N4, during the data writing phase t2, the reset transistor M7 can be turned on or off. That is, the sixth scan signal of the sixth enable terminal SPX can be either enabled or disabled. In either case, the voltage of the fourth node N4 is VN4 = Vref2. Furthermore, before the third scan signal of the third enable terminal S2N transitions from an enabled high level to a disabled low level, the fourth scan signal of the fourth enable terminal EM1 first transitions from an enabled high level to a disabled low level. That is, before the isolation transistor M4 is turned off, the first light-emitting control transistor M1 is turned off first. This helps maintain the stability of the first node N1 and avoids voltage fluctuations in the first node N1 or the voltage fluctuations in the third node N3 coupled with voltage fluctuations in the first node N1 when the isolation transistor M4 is turned off first. This is detrimental to writing accurate data signals between the gate and source of the driving transistor DT.

[0069] During the light-emitting stage t3, the first scan signal of the first enable terminal SP, the second scan signal of the second enable terminal S1N, the third scan signal of the third enable terminal S2N, and the sixth scan signal of the sixth enable terminal SPX are all at a low level and are not enabled. The fourth scan signal of the fourth enable terminal EM1 is at a high level and the fifth scan signal of the fifth enable terminal EM2 is at a high level and is enabled. The write transistor M2, the initialization transistor M5, the isolation transistor M4, and the reset transistor M7 are turned off, and the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are turned on. The voltage at the third node N3 can be pulled low by the second power supply terminal PV2 through the second light-emitting control transistor M6 and the light-emitting element D1. Under the coupling effect of the first capacitor C1, the voltage at the first node N1 also decreases synchronously, ΔVN1=ΔVN3, so that the gate-source voltage VGS of the driving transistor DT can be kept consistent with the previous extreme, which is VGS=VN1-VN3=Vdata-Vref1+VTH-[C1 / (C1+C2)]×(Vdata-Vref1)=[C2 / (C1+C2)]×(Vdata-Vref1)+VTH; both the driving transistor DT and the light-emitting element D1 can form a driving current, which is Id=k×(VGS-VTH). 2 =k×[(Data-VREF1)×C2 / (C1+C2)] 2 The light-emitting element D1 can display the corresponding brightness according to the driving current Id. By controlling the brightness and light emission duration of the light-emitting element OLED, the display grayscale of the pixel circuit 10 can be controlled. Here, k is the current coefficient of the driving transistor DT, which is related to the material properties and size parameters of the driving transistor DT.

[0070] In an alternative embodiment, Figure 8 This is a third timing diagram provided in the embodiments of this application, wherein, Figure 8 Specifically, it can be corresponding to Figure 7 The driving timing diagram of the pixel circuit is shown. (Reference) Figure 7 and Figure 8 The working period of the pixel circuit 10 includes a data writing phase t2, a reset phase t0', and a light emission phase t3. The reset phase t0' is located after the data writing phase t2 and before the light emission phase t3. When the reset module 16 is connected to the second reference voltage terminal Vref2, the fourth node N4, and the sixth enable terminal SPX, in the reset phase t0', the fourth scan signal of the fourth enable terminal EM1 is at a non-enable level, while the fifth scan signal of the fifth enable terminal EM2 and the sixth scan signal of the sixth enable terminal SPX are both at an enable level.

[0071] For example, taking the case where the enable level of the scan signal is all high and the disable level is all low, refer to... Figure 7 and Figure 8 During the reset phase t0', the fourth scan signal of the fourth enable terminal EM1 is at a low level and is disabled, while the fifth scan signal of the fifth enable terminal EM2 and the sixth scan signal of the sixth enable terminal SPX are both at a high level and are enabled. The first light-emitting control transistor M1 is turned off, and the second light-emitting control transistor M6 and the reset transistor M7 are turned on, cutting off the connection between the first power supply terminal PV1 and the third node N3. The connection between the second reference voltage terminal Vref2 and the fourth node N4, as well as between the fourth node N4 and the third node N3, is established. The signal of the second reference voltage terminal Vref2 can be transmitted to the third node N3 to reset the third node N3. During the data writing phase t2, the voltage of the third node N3 can be VN3 = Vref1 - VTH + [C1 / (C1 + C2)] × (Vdata - Vref1). By resetting the third node N3 to the voltage of the second reference voltage terminal Vref2 after the data writing phase t2 and before the light emission phase t3, on the one hand, the third node N3 in the pixel circuit 10 can be uniformly reset to the same voltage before the light-emitting element D1 emits light. On the other hand, this can reduce the fluctuation of the fourth node N4 when the driving current is formed, which is beneficial to the stable light emission of the light-emitting element D1. When applied to display panel 01, it improves the display uniformity of display panel 01; on the other hand, the voltage of the second reference voltage terminal Vref2 is usually close to that of the second power supply terminal PV2. Before the light-emitting element D1 emits light, the third node N3 in the pixel circuit 10 can be uniformly reset to a voltage close to that of the second power supply terminal PV2 to improve the accuracy of display light emission and avoid the voltage of the third node N3 being too high or too low before the light-emitting element D1 emits light, which would cause the voltage of the fourth node N4 to fluctuate downward when the driving current is formed, resulting in the dimming of light under low grayscale display or affecting the charging speed of the light-emitting element D1.

[0072] In another alternative embodiment, Figure 9This is a schematic diagram of the circuit structure of the fifth pixel circuit provided in the embodiments of this application. Figure 10 This is the fourth timing diagram provided in the embodiments of this application, wherein, Figure 10 Specifically, it can be corresponding to Figure 9 The driving timing diagram of the pixel circuit is shown. (Reference) Figure 9 and Figure 10 When the reset module 16 is connected to the second reference voltage terminal Vref2, the third node N3, and the sixth enable terminal SPX, during the reset phase t0', the fourth scan signal of the fourth enable terminal EM1 is at a disabled level, and the sixth scan signal of the sixth enable terminal SPX is at an enabled level.

[0073] For example, taking the case where the enable level of the scan signal is all high and the disable level is all low, refer to... Figure 9 and Figure 10 During the reset phase t0', the fourth scan signal of the fourth enable terminal EM1 is at a low level (disabled), and the sixth scan signal of the sixth enable terminal SPX is at a high level (enabled). The first light-emitting control transistor M1 is turned off, and the reset transistor M7 is turned on, cutting off the connection between the first power supply terminal PV1 and the third node N3. The second reference voltage terminal Vref2 is then connected to the third node N3, and the signal from the second reference voltage terminal Vref2 can also be transmitted to the third node N3 to reset the third node N3. This is beneficial for accurate light emission and improves display uniformity.

[0074] It is understandable that when the second end of the reset module 16 is directly connected to the fourth node N4, during the reset phase t0', the reset module 1 is turned on, and the second light-emitting control module 15 can be turned on or off. That is, the fifth scan signal of the fifth enable terminal EM2 can be either an enable level or a non-enable level, neither of which will affect the reset of the third node N3, nor will it affect the reset process.

[0075] Based on the above embodiments, in an optional implementation, during the reset phase t0', the first scan signal of the first enable terminal SP and the second scan signal of the second enable terminal S1N are both at a non-enable level.

[0076] For example, taking the case where the enable level of the scan signal is all high and the disable level is all low, refer to... Figures 7-10During the reset phase t0', the first scan signal at the first enable terminal SP and the second scan signal at the second enable terminal S1N are both at a disabled level. The write transistor M2 and the initialization transistor M5 are both turned off, which cuts off the connection between the data voltage terminal Vdata and the first node N1, as well as between the first reference voltage terminal Vref1 and the first node N1. The first node N1 is floating (no active signal is written). When the third node N3 is reset to the voltage of the second reference voltage terminal Vref2, the coupling effect of the first capacitor C1 allows the first node N1 to change synchronously, keeping the gate-source voltage of the driving transistor DT unchanged, which is beneficial for the accurate display of the light-emitting element D1. Furthermore, during the reset phase t0', when the third node N3 is reset to the voltage of the second reference voltage terminal Vref2, the initialization transistor M5 is turned off, which helps reduce power consumption and avoids a brief short circuit between the first reference voltage terminal Vref1 and the third node N3, preventing current formation and increasing the load on the second reference voltage terminal Vref1.

[0077] In the reset phase t0', when both the write transistor M2 and the initialization transistor M5 are turned off, the isolation transistor M4 can be turned on or off. In this embodiment, the third scan signal of the third enable terminal S2N is not limited.

[0078] In another alternative implementation, Figure 11 This is the fifth timing diagram provided in the embodiments of this application. Figure 12 This is the sixth timing diagram provided in the embodiments of this application, wherein, Figure 11 Specifically, it can be corresponding to Figure 7 The driving timing of the pixel circuit shown is as follows: Figure 12 Specifically, it can be corresponding to Figure 9 The driving timing diagram of the pixel circuit is shown. (Reference) Figure 11 and Figure 12 During the reset phase t0', the first scan signal of the first enable terminal SP and the third scan signal of the third enable terminal S2N are both at a disabled level, while the second scan signal of the second enable terminal S1N is at an enabled level.

[0079] For example, taking the case where the enable level of the scan signal is all high and the disable level is all low, refer to... Figure 11 and Figure 12During the reset phase t0', both the write transistor M2 and the isolation transistor M4 are turned off, which also cuts off the connection between the data voltage terminal Vdata and the first node N1, as well as between the first reference voltage terminal Vref1 and the first node N1. The first node N1 is floating (no active signal is written), which is beneficial for the accurate display of the light-emitting element D1. In addition, during the reset phase t0', when the third node N3 is reset to the voltage of the second reference voltage terminal Vref2, the initialization transistor M5 is turned on, and the voltage of the second node N2 is stabilized at the voltage of the first reference voltage terminal Vref1. The storage effect of the second capacitor C2 can be used to maintain the stability of the third node N3, avoiding noise interference and transient interference that could cause voltage jitter in the third node N3, which is not conducive to accurate display. During the reset phase t0', the fifth scan signal of the fifth enable terminal EM2 can be at the enable level, and the second light-emitting control transistor M6 is turned on. Maintaining the stability of the third node N3 is beneficial to the stability of the fourth node N4, which can effectively prevent the light-emitting element D1 from emitting light erroneously.

[0080] Optional, Figure 13 This is a schematic diagram of the circuit structure of the sixth pixel circuit provided in the embodiments of this application, for reference. Figure 13 The reset module 16 is connected to the second reference voltage terminal Vref2, the fourth node N4, and the sixth enable terminal SPX. In the same pixel circuit 10, the conduction periods of the initialization module 12 and the reset module 16 overlap, and the second scan signal of the second enable terminal S1N is multiplexed with the sixth scan signal of the sixth enable terminal SPX.

[0081] For example, refer to Figure 11 and Figure 13 In the initialization phase t0, compensation phase t1, data writing phase t2, and reset phase t0' of the pixel circuit 10, both the second scan signal of the second enable terminal S1N and the sixth scan signal of the sixth enable terminal SPX can be at the enable level; in the light emission phase t3, both the second scan signal of the second enable terminal S1N and the sixth scan signal of the sixth enable terminal SPX can be at the disable level. The initialization transistor M5 in the initialization module 12 and the reset transistor M7 in the reset module 16 can have the same channel type, for example, both are N-type transistors or both are P-type transistors. The enable level of the second scan signal of the second enable terminal S1N and the enable level of the sixth scan signal of the sixth enable terminal SPX can be the same. In the same pixel circuit 10, the gate of the initialization transistor M5 and the gate of the reset transistor M7 can be electrically connected. In this way, the number of scan signals required by the pixel circuit 10 can be reduced. When applied to the display panel 01, the number of scan lines and shift registers connected to the pixel circuit 10 can be reduced, which is beneficial to achieving a narrow bezel of the display panel 01.

[0082] Optional, Figure 14 This is a schematic diagram of the circuit structure of the seventh pixel circuit provided in the embodiments of this application. Figure 15 This is the seventh timing diagram provided in the embodiments of this application, wherein, Figure 15 Specifically, it can be corresponding to Figure 14 The driving timing diagram of the pixel circuit is shown. (Reference) Figure 14 and Figure 15 The reset module 16 is connected to the second reference voltage terminal Vref2, the fourth node N4, and the sixth enable terminal SPX. In the same pixel circuit 10, the conduction periods of the first light emission control module 14 and the reset module 14 do not overlap, and the fourth scan signal of the fourth enable terminal EM1 is multiplexed with the sixth scan signal of the sixth enable terminal SPX.

[0083] For example, refer to Figure 14 and Figure 15 In the initialization phase t0, data writing phase t2, and reset phase t0' of the pixel circuit 10, the fourth scan signal of the fourth enable terminal EM1 can be at a disabled level, and the sixth scan signal of the sixth enable terminal SPX can be at an enabled level. In the compensation phase t1 and light emission phase t3, the fourth scan signal of the fourth enable terminal EM1 can be at an enabled level, and the sixth scan signal of the sixth enable terminal SPX can be at a disabled level. The channel types of the first light emission control transistor M1 in the first light emission control module 14 and the reset transistor M7 in the reset module 16 can be different, for example, one is an N-type transistor and the other is a P-type transistor. The enable level of the fourth scan signal of the fourth enable terminal EM1 and the enable level of the sixth scan signal of the sixth enable terminal SPX can be different. In the same pixel circuit 10, the gate of the first light emission control transistor M1 and the gate of the reset transistor M7 can be electrically connected. In this way, the number of scan signals required by the pixel circuit 10 can be reduced. When applied to the display panel 01, the number of scan lines and shift registers connected to the pixel circuit 10 can be reduced, which is beneficial to achieving a narrow bezel of the display panel 01.

[0084] In optional embodiments, continue to refer to Figure 14 The second light-emitting control module 15 includes a second light-emitting control transistor M6; wherein the second light-emitting control transistor M6 and the first light-emitting control transistor M1 have the same channel type. The second light-emitting control transistor M6 and the first light-emitting control transistor M1 have the same current path, and their identical channel type facilitates symmetrical design, improves matching and aging consistency, thereby precisely controlling the drive current and enhancing brightness uniformity and long-term stability. It is understood that in other optional embodiments, the second light-emitting control transistor M6 and the first light-emitting control transistor M1 may have different channel types.

[0085] Optional, Figure 16 This is a schematic diagram of the circuit structure of the eighth pixel circuit provided in the embodiments of this application, for reference. Figure 16The pixel circuit 10 also includes an auxiliary module 17, which is connected to the third reference voltage terminal Vref3, the third node N3, and the seventh enable terminal SPX', and is used to transmit the signal of the third reference voltage terminal Vref3 to the third node N3 in response to the seventh scan signal of the seventh enable terminal SPX'.

[0086] Specifically, when the seventh scan signal of the seventh enable terminal SPX' is at the enable level, the auxiliary module 17 can transmit the signal of the third reference voltage terminal Vref3 to the third node N3.

[0087] For example, when the pixel circuit 10 is applied to the display panel 01, the display panel 01 may also include a seventh shift register ( Figure 2 (not shown in the image), the seventh shift register includes multiple shift register units, and the shift register of the seventh shift register can be electrically connected to the seventh enable terminal SPX' of the pixel circuit through the seventh scan line.

[0088] In an optional embodiment, the voltage of the first reference voltage terminal Vref1 is greater than the voltage of the third reference voltage terminal Vref3.

[0089] For example, the signal at the first reference voltage terminal Vref3 can be used to initialize the voltage of the first node N1, the signal at the second reference voltage terminal Vref2 can be used to reset the voltage of the fourth node N4, and the signal at the third reference voltage terminal Vref3 can be used to reset the voltage of the third node N3. By setting the voltage at the first reference voltage terminal Vref1 to be greater than the voltage at the third reference voltage terminal Vref3, the driving transistor DT can be fully turned on when VN1=Vref1 and VN3=Vref3, thus initializing the driving transistor DT.

[0090] In one embodiment, Vref1 > Vref3 + VTH, where VTH is the threshold voltage of the driving transistor DT; in another embodiment, the voltage of the second reference voltage terminal Vref2 is close to the voltage of the second power supply terminal PV2; in yet another embodiment, the voltage of the first reference voltage terminal Vref1 can be greater than, equal to, or less than the voltage of the second reference voltage terminal Vref2, that is, the voltage of the first reference voltage terminal Vref1 can be flexibly set and is not easily affected or limited by the voltage of the second reference voltage terminal Vref2.

[0091] In another alternative embodiment, Figure 17 This is the eighth timing diagram provided in the embodiments of this application, wherein, Figure 17 Specifically, it can be corresponding to Figure 16 The driving timing diagram of the pixel circuit is shown. (Reference) Figure 16 and Figure 17The working period of the pixel circuit 10 includes the initialization phase t0. When the reset module 16 is connected to the second reference voltage terminal Vref2, the fourth node N4, and the sixth enable terminal SPX, during the initialization phase t0, the fourth scan signal of the fourth enable terminal EM1 and the fifth scan signal of the fifth enable terminal EM2 are both at the disabled level, and the seventh scan signal of the seventh enable terminal SPX' is at the enabled level.

[0092] For example, refer to Figure 16 and Figure 17 During the initialization phase t0, both the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are turned off, and the auxiliary transistor M8 of the auxiliary module 17 is turned on, so that the voltage of the third node N3 can be initialized using the signal of the first reference voltage terminal Vref3; at the same time, during the initialization phase t0, the reset transistor M7 is also turned on, so that the voltage of the fourth node N4 can be reset using the signal of the second reference voltage terminal Vref2.

[0093] In other embodiments, when the reset module 16 is connected to the second reference voltage terminal Vref2, the third node N3, and the sixth enable terminal SPX, during the initialization phase t0, the fourth scan signal of the fourth enable terminal EM1, the fifth scan signal of the fifth enable terminal EM2, and the sixth scan signal of the sixth enable terminal SPX are all at a disabled level, while the seventh scan signal of the seventh enable terminal SPX' is at an enabled level. Figure 16 and Figure 17 (not shown in the image), that is, the first light-emitting control transistor M1, the second light-emitting control transistor M6 and the reset transistor M7 are all turned off, and the auxiliary transistor M8 is turned on, so as to initialize the voltage of the third node N3 using the signal of the first reference voltage terminal Vref3, while avoiding a short circuit between the second reference voltage terminal Vref2 and the third reference voltage terminal Vref3.

[0094] In yet another alternative embodiment, Figure 18 This is a schematic diagram of the circuit structure of the ninth pixel circuit provided in the embodiments of this application. Figure 19 This is the ninth timing diagram provided in the embodiments of this application, wherein, Figure 19 Specifically, it can be corresponding to Figure 18 The driving timing diagram of the pixel circuit is shown. (Reference) Figure 18 and Figure 19 The reset module 16 is connected to the second reference voltage terminal Vref2, the fourth node N4, and the sixth enable terminal SPX. In the same pixel circuit 10, the conduction periods of the second light emission control module 15 and the reset module 16 do not overlap, and the fifth scan signal of the fifth enable terminal EM2 is multiplexed with the sixth scan signal of the sixth enable terminal SPX.

[0095] For example, refer to Figure 18 and Figure 19In the initialization phase t0, compensation phase t1, data writing phase t2, and reset phase t0' of the pixel circuit 10, the fifth scan signal of the fifth enable terminal EM2 can be at a disabled level, and the sixth scan signal of the sixth enable terminal SPX can be at an enabled level. In the light emission phase t3, the fifth scan signal of the fifth enable terminal EM2 can be at an enabled level, and the sixth scan signal of the sixth enable terminal SPX can be at a disabled level. The channel types of the second light emission control transistor M6 in the second light emission control module 15 and the reset transistor M7 in the reset module 16 can be different, for example, one is an N-type transistor and the other is a P-type transistor. The enable level of the fifth scan signal of the fifth enable terminal EM2 and the enable level of the sixth scan signal of the sixth enable terminal SPX can be different. In the same pixel circuit 10, the gate of the second light emission control transistor M6 and the gate of the reset transistor M7 can be electrically connected. In this way, the number of scan signals required by the pixel circuit 10 can be reduced. When applied to the display panel 01, the number of scan lines and shift registers connected to the pixel circuit 10 can be reduced, which is beneficial for achieving a narrow bezel of the display panel 01.

[0096] In yet another alternative embodiment, Figure 20 This is a schematic diagram of the circuit structure of the tenth pixel circuit provided in the embodiments of this application. Figure 21 This is the tenth timing diagram provided in the embodiments of this application, wherein, Figure 21 Specifically, it can be corresponding to Figure 20 The driving timing diagram of the pixel circuit is shown. (Reference) Figure 20 and Figure 21 The reset module 16 is connected to the second reference voltage terminal Vref2, the fourth node N4, and the sixth enable terminal SPX. In the same pixel circuit 10, the conduction periods of the initialization module 12 and the reset module 16 overlap, while the conduction periods of the second light emission control module 15 and the reset module 16 do not overlap. The second scan signal of the second enable terminal S1N, the fifth scan signal of the fifth enable terminal EM2, and the sixth scan signal of the sixth enable terminal SPX are multiplexed.

[0097] For example, refer to Figure 20 and Figure 21In the initialization phase t0, compensation phase t1, data writing phase t2, and reset phase t0' of the pixel circuit 10, the fifth scan signal of the fifth enable terminal EM2 can be at a disabled level, while the second scan signal of the second enable terminal S1N and the sixth scan signal of the sixth enable terminal SPX can be at an enabled level. In the light emission phase t3, the fifth scan signal of the fifth enable terminal EM2 can be at an enabled level, while the second scan signal of the second enable terminal S1N and the sixth scan signal of the sixth enable terminal SPX can be at a disabled level. The initialization transistor M5 in the initialization module 15 and the reset transistor M7 in the reset module 16 can have the same channel type, while the second light emission control transistor M6 in the second light emission control module 15 and the reset transistor M7 in the reset module 16 can have different channel types. In the same pixel circuit 10, the gates of the initialization transistor M5, the second light emission control transistor M6, and the reset transistor M7 can be electrically connected. This further reduces the scanning signal required by the pixel circuit 10. When applied to the display panel 01, it further reduces the number of scan lines and shift registers connected to the pixel circuit 10, which is beneficial for achieving a narrow bezel on the display panel 01.

[0098] Based on the above embodiments, refer to Figures 18-21 The working period of the pixel circuit 10 includes a data writing phase t2, a reset phase t0', and an emission phase t3. The reset phase t0' is located after the data writing phase t2 and before the emission phase t3. During the reset phase t0', the fourth scan signal of the fourth enable terminal EM1 and the fifth scan signal of the fifth enable terminal EM2 are both at a disabled level, while the seventh scan signal of the seventh enable terminal SPX' is at an enabled level.

[0099] For example, refer to Figure 18 and Figure 19 During the reset phase t0', both the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are turned off, while the auxiliary transistor M8 is turned on. This cuts off the connection between the first power supply terminal PV1 and the third node N3, as well as between the second reference voltage terminal Vref2 and the third node N3. Conduction occurs between the third reference voltage terminal Vref3 and the third node N3, allowing the signal from the third reference voltage terminal Vref3 to be transmitted to the third node N3, resetting it. This facilitates accurate light emission and improves display uniformity. During the reset phase t0', the reset transistor M7 can be either turned on or off. This embodiment does not limit the sixth scan signal of the sixth enable terminal SPX.

[0100] Based on the above, refer to Figure 14 , Figure 16 , Figure 18 , Figure 20In some embodiments, the reset transistor M7, the first light-emitting control transistor M1, and the second light-emitting control transistor M6 have different channel types. In optional embodiments, the other transistors in the pixel circuit 10 can all be N-type transistors, which helps to reduce the off-state current.

[0101] Optional, continue to refer to Figure 20 The driving transistor DT includes a first gate and a second gate. The first gate of the driving transistor DT is electrically connected to a first node N1, and the second gate of the driving transistor DT is electrically connected to a third node N3.

[0102] Specifically, the driving transistor DT is a dual-gate transistor. The first gate is the driving gate of the driving transistor DT, and the voltage between the first gate and the source can control the on / off state of the driving transistor DT. The second gate is an additional gate of the driving transistor DT. By setting the second gate, the driving transistor DT can have better channel charge control capability. The second gate of the driving transistor DT is electrically connected to the third node N3, which can make the voltage of the second gate of the driving transistor DT the same as the voltage of the source of the second gate of the driving transistor DT. This helps to suppress the threshold voltage drift of the driving transistor DT, improve its working stability, extend its service life, and thus improve the display effect and reliability of the display panel 01.

[0103] Optional, continue to refer to Figure 20 The write module 11 includes a write transistor M2, which has a first gate and a second gate. The first gate and the second gate of the write transistor M2 are electrically connected. Specifically, the write transistor M2 is a dual-gate transistor, and the voltages of the first gate and the second gate are the same, which helps to increase the on-state current of the write transistor M2 and improve the switching speed.

[0104] In an optional implementation, the initialization transistor M5, isolation transistor M4, reset transistor M7, and auxiliary transistor M8 in the pixel circuit 10 can also be dual-gate transistors, and the voltages of the two gates are the same, which is beneficial to increase the on-state current and improve the switching speed.

[0105] In an optional implementation, the first light-emitting control transistor M1 and the second light-emitting control transistor M6 in the pixel circuit 10 can also be dual-gate transistors. The newly added gate can be connected to a fixed voltage terminal, which can adjust the threshold voltage of the first light-emitting control transistor M1 and the second light-emitting control transistor M6.

[0106] Based on the same inventive concept, this application also provides a pixel circuit driving method for driving the pixel circuit 10 provided in any embodiment of this application. Figure 22This is a flowchart of a pixel circuit driving method provided in an embodiment of this application, see reference. Figure 22 The driving methods include: S110, Initialization phase: The first reference voltage terminal is connected to the second node, the second node is connected to the first node, and the second reference voltage terminal is connected to the third node.

[0107] S120, during the compensation phase, the first reference voltage terminal is connected to the second node, the second node is connected to the first node, and the first power supply terminal is connected to the third node.

[0108] S130, during the data writing phase, the data voltage terminal is connected to the first node, and the first reference voltage terminal is connected to the second node.

[0109] S140, Light-emitting stage, conduction is achieved between the first power supply terminal and the third node, as well as between the third node and the fourth node.

[0110] For example, refer to Figure 1 and Figure 22 During the initialization phase, the initialization module, isolation module, second light-emitting control module, and reset module can be controlled to conduct via the second scan signal of the second enable terminal, the third scan signal of the third enable terminal, the fifth scan signal of the fifth enable terminal, and the sixth scan signal of the sixth enable terminal. The signal of the first reference voltage terminal can be input to the first node through the initialization module and the isolation module to initialize the voltage of the first node. The signal of the second reference voltage terminal can be transmitted to the third node through the reset module and the second light-emitting control module to initialize the third node N3 and make the control drive transistor in the conducting state. During the compensation phase, the initialization module can be controlled via the second scan signal of the second enable terminal, the third scan signal of the third enable terminal, and the fourth scan signal of the fourth enable terminal. The first light-emitting control module, isolation module, and first light-emitting control module are turned on, compensating the threshold voltage of the driving transistor. During the data writing phase, the writing module and initialization module can be turned on via the first scan signal at the first enable terminal and the second scan signal at the second enable terminal. The data signal at the data voltage terminal can be transmitted to the first node through the writing module. Under the action of the first capacitor and the second capacitor, the third node is partially coupled. The first capacitor can also store the gate-source voltage of the driving transistor. During the light-emitting phase, the first light-emitting control module and the second light-emitting control module can be turned on via the fourth scan signal at the fourth enable terminal and the fifth scan signal at the fifth enable terminal. The driving current of the pixel circuit can be provided to the light-emitting element, causing the light-emitting element to emit light. When this pixel circuit is applied to a display panel, the display quality of the display panel can be improved.

[0111] The pixel circuit driving method provided in this application embodiment can drive the pixel circuit provided in any embodiment of this application, and has the corresponding technical features and beneficial effects of the pixel circuit. For the contents not described in detail in the embodiments of the pixel circuit driving method, please refer to the description of the pixel circuit above, and will not be repeated here. Similarly, the pixel circuit of this application embodiment also has functional modules and beneficial effects that can execute the pixel circuit driving method provided in this application embodiment. For the contents not described in detail in the embodiments of the pixel circuit, please refer to the description of the pixel circuit driving method above, and will not be repeated here.

[0112] Based on the same inventive concept, this application also provides a display panel. Figure 23 This is a top view structural diagram of the second type of display panel provided in the embodiments of this application, with reference to... Figure 23 The display panel 01 includes a plurality of pixel circuits 10 arranged in an array. The pixel circuits 10 can be the pixel circuits 10 provided in any embodiment of this application.

[0113] For example, refer to Figure 1 Substitution Figure 23 The display panel 01 also includes multiple first scan lines SL1, multiple second scan lines SL2, multiple third scan lines SL3, multiple fourth scan lines SL4, multiple fifth scan lines SL5, multiple sixth scan lines SL6, and multiple data lines DL connected to multiple pixel circuits 10. Furthermore, it may include multiple first reference lines, multiple second reference lines, multiple first power lines, multiple second power lines, etc. Figure 23 (Not shown in the image). The first scan line SL1 can be connected to the first enable terminal SP in the pixel circuit 10, the second scan line SL2 can be connected to the second enable terminal S1N in the pixel circuit 10, the third scan line SL3 can be connected to the third enable terminal S2N in the pixel circuit 10, the fourth scan line SL4 can be connected to the fourth enable terminal EM1 in the pixel circuit 10, the fifth scan line SL5 can be connected to the fifth enable terminal EM2 in the pixel circuit 10, and the sixth scan line SL6 can be connected to the sixth enable terminal SPX in the pixel circuit 10. The first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the fifth scan line SL5, and the sixth scan line SL6 can be electrically connected to the first shift register, the second shift register, the third shift register, the fourth shift register, the fifth shift register, and the sixth shift register located in the non-display area NA, respectively. Figure 23 (Not shown in the image).

[0114] Optionally, the display panel 01 includes multiple pixel circuit rows, which extend along a first direction X and are arranged along a second direction Y; each pixel circuit row includes multiple pixel circuits 10, and the scan signals of the corresponding enable terminals of the multiple pixel circuits 10 located in the same pixel circuit row are the same; along the second direction Y, the second scan signal of the i-th row pixel circuit 10 is multiplexed with the third scan signal of the (i+m)-th row pixel circuit 10, where i and m are both positive integers.

[0115] For example, taking m=2 as an example, Figure 24 This is a top view structural diagram of the third type of display panel provided in the embodiments of this application, with reference to... Figure 1 and reference Figure 24 In pixel circuits 10 located in the same row, corresponding enable terminals can be connected to the same scan line and receive the same scan signal. Specifically, the second enable terminal S1N in the i-th row pixel circuit 10 can be connected to the i-th second scan line SL2. This second scan line SL2 can be connected to the (i+2)-th third scan line SL3. The (i+2)-th third scan line SL3 can be connected to the third enable terminal S2N in the (i+2)-th row pixel circuit 10. This allows the second scan signal of the second enable terminal S1N in the i-th row pixel circuit 10 to be the same as the third scan signal of the third enable terminal S2N in the (i+2)-th row pixel circuit 10. Within the same pixel circuit 10, the period during which the second scan signal of the second enable terminal S1N is at the enable level lags behind the period during which the third enable terminal S2N is at the enable level. For example... Figure 25 , Figure 26 As shown. In this way, the scanning signals of different rows can be multiplexed, which helps to reduce the shift registers used to provide the scanning signals and achieve a narrow bezel for the display panel 10.

[0116] Optionally, the display panel 01 includes multiple pixel circuit rows, which extend along a first direction X and are arranged along a second direction Y; each pixel circuit row includes multiple pixel circuits 10, and the scan signals of the corresponding enable terminals of the multiple pixel circuits 10 located in the same pixel circuit row are the same; in the same pixel circuit 10, the conduction periods of the first light-emitting control module and the reset module do not overlap; along the second direction, the fifth scan signal of the j-th row pixel circuit multiplexes the second scan signal of the j+n-th row pixel circuit, where j and n are both positive integers.

[0117] For example, taking n=1 as an example, Figure 27 This is a top view structural diagram of the fourth type of display panel provided in the embodiments of this application, with reference to... Figure 1 and reference Figure 27In pixel circuits 10 located in the same row, corresponding enable terminals can be connected to the same scan line and receive the same scan signal. Specifically, the fifth enable terminal EM2 in the j-th row pixel circuit 10 can be connected to the j-th fifth scan line SL5, which can be connected to the (j+n)-th second scan line SL2. The (j+1)-th second scan line SL2 can be connected to the second enable terminal S1N in the (j+1)-th row pixel circuit 10. This allows the fifth scan signal of the fifth enable terminal EM2 in the j-th row pixel circuit 10 to be the same as the second scan signal of the second enable terminal S1N in the (j+1)-th row pixel circuit 10. Within the same pixel circuit 10, the period during which the fifth scan signal of the fifth enable terminal EM2 is at the enable level lags behind the period during which the second scan signal of the second enable terminal S1N is at the enable level. For example... Figure 28 , Figure 29 As shown. In this way, the scanning signals of different rows can be multiplexed, which helps to reduce the shift registers used to provide the scanning signals and achieve a narrow bezel for the display panel 10.

[0118] The display panel provided in this application includes multiple pixel circuits arranged in an array as provided in any embodiment of this application. It has the corresponding technical features and beneficial effects of pixel circuits. For the contents not described in detail in the embodiments of the display panel, please refer to the description of the pixel circuit above, and will not be repeated here.

[0119] Based on the same inventive concept, embodiments of this application also provide a display device. Figure 30 This is a schematic diagram of the structure of a display device provided in an embodiment of this application, such as... Figure 30 As shown, the display device 02 includes the display panel 01 provided in any embodiment of this application. The display device 02 provided in the embodiments of this application can be... Figure 30 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet, digital camera, smart bracelet, smart glasses, in-vehicle display, medical device, industrial control equipment, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0120] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that, include: The write module is connected to the data voltage terminal, the first node, and the first enable terminal, and is used to transmit the signal from the data voltage terminal to the first node in response to the first scan signal from the first enable terminal. The first node is electrically connected to the gate of the driving transistor, which is an N-type transistor; An initialization module is connected to a first reference voltage terminal, a second node, and a second enable terminal, and is used to transmit the signal from the first reference voltage terminal to the second node in response to the second scan signal from the second enable terminal. An isolation module, connecting the second node, the first node, and the third enable terminal, is used to transmit the signal of the second node to the first node in response to the third scan signal of the third enable terminal; The first capacitor is connected to the first node and the third node; The second capacitor is connected to the second node and the third node; The first light-emitting control module is connected in series with the driving transistor between the first power supply terminal and the third node, and the control terminal of the first light-emitting control module is electrically connected to the fourth enable terminal. The second light-emitting control module is connected to the third node, the fourth node, and the fifth enable terminal, and is used to transmit the signal of the third node to the fourth node in response to the fifth scan signal of the fifth enable terminal; the fourth node is electrically connected to the light-emitting element. A reset module is connected to a second reference voltage terminal, the third or fourth node, and a sixth enable terminal, and is used to transmit the signal from the second reference voltage terminal to the third or fourth node in response to the sixth scan signal of the sixth enable terminal.

2. The pixel circuit according to claim 1, characterized in that, The first light-emitting control module is connected to the first power supply terminal, the fifth node, and the fourth enable terminal, and is used to transmit the signal from the first power supply terminal to the fifth node in response to the fourth scan signal of the fourth enable terminal. The fifth node is electrically connected to the first terminal of the driving transistor, and the second terminal of the driving transistor is electrically connected to the third node.

3. The pixel circuit according to claim 1, characterized in that, The first terminal of the driving transistor is electrically connected to the first power supply terminal, and the second terminal of the driving transistor is electrically connected to the fifth node; The first light emission control module is connected to the fifth node, the third node, and the fourth enable terminal, and is used to transmit the signal of the fifth node to the third node in response to the fourth scan signal of the fourth enable terminal.

4. The pixel circuit according to claim 1, characterized in that, The pixel circuit includes a compensation stage and a data writing stage; During the compensation phase, both the second scan signal of the second enable terminal and the third scan signal of the third enable terminal are at the enable level. During the data writing phase, the third scan signal of the third enable terminal is at a disabled level.

5. The pixel circuit according to claim 1, characterized in that, The pixel circuit includes a compensation phase; When the reset module is connected to the second reference voltage terminal, the third node, and the sixth enable terminal, during the compensation phase, the fourth scan signal of the fourth enable terminal is at an enable level, and the fifth scan signal of the fifth enable terminal and the sixth scan signal of the sixth enable terminal are both at a non-enable level. When the reset module is connected to the second reference voltage terminal, the fourth node, and the sixth enable terminal, during the compensation phase, the fourth scan signal of the fourth enable terminal is at an enable level, and the fifth scan signal of the fifth enable terminal is at a non-enable level.

6. The pixel circuit according to claim 1, characterized in that, The pixel circuit includes a data writing stage; When the reset module is connected to the second reference voltage terminal, the third node, and the sixth enable terminal, during the data writing phase, the second scan signal of the second enable terminal is at an enable level, and the third scan signal of the third enable terminal, the fourth scan signal of the fourth enable terminal, the fifth scan signal of the fifth enable terminal, and the sixth scan signal of the sixth enable terminal are all at a non-enable level. When the reset module is connected to the second reference voltage terminal, the fourth node, and the sixth enable terminal, during the data writing phase, the second scan signal of the second enable terminal is at an enable level, and the third scan signal of the third enable terminal, the fourth scan signal of the fourth enable terminal, and the fifth scan signal of the fifth enable terminal are all at a non-enable level.

7. The pixel circuit according to claim 1, characterized in that, The pixel circuit includes an initialization phase; When the reset module is connected to the second reference voltage terminal, the third node, and the sixth enable terminal, during the initialization phase, the second scan signal of the second enable terminal, the third scan signal of the third enable terminal, and the sixth scan signal of the sixth enable terminal all include an enable level. When the reset module is connected to the second reference voltage terminal, the fourth node, and the sixth enable terminal, during the initialization phase, the second scan signal of the second enable terminal, the third scan signal of the third enable terminal, the fifth scan signal of the fifth enable terminal, and the sixth scan signal of the sixth enable terminal all include an enable level.

8. The pixel circuit according to claim 1, characterized in that, The pixel circuit includes a data writing stage, a reset stage, and a light-emitting stage; the reset stage is located after the data writing stage and before the light-emitting stage. When the reset module is connected to the second reference voltage terminal, the third node, and the sixth enable terminal, during the reset phase, the fourth scan signal of the fourth enable terminal is at a disabled level, and the sixth scan signal of the sixth enable terminal is at an enabled level. When the reset module is connected to the second reference voltage terminal, the fourth node, and the sixth enable terminal, during the reset phase, the fourth scan signal of the fourth enable terminal is at a non-enable level, while the fifth scan signal of the fifth enable terminal and the sixth scan signal of the sixth enable terminal are both at an enable level.

9. The pixel circuit according to claim 8, characterized in that, During the reset phase, the first scan signal of the first enable terminal and the second scan signal of the second enable terminal are both at a non-enable level.

10. The pixel circuit according to claim 8, characterized in that, During the reset phase, the first scan signal of the first enable terminal and the third scan signal of the third enable terminal are both at a disabled level, while the second scan signal of the second enable terminal is at an enabled level.

11. The pixel circuit according to claim 1, characterized in that, The reset module is connected to the second reference voltage terminal, the fourth node, and the sixth enable terminal; In the same pixel circuit, the conduction periods of the initialization module and the reset module overlap, and the second scan signal of the second enable terminal is multiplexed with the sixth scan signal of the sixth enable terminal.

12. The pixel circuit according to claim 1, characterized in that, The reset module is connected to the second reference voltage terminal, the fourth node, and the sixth enable terminal; In the same pixel circuit, the conduction periods of the first light-emitting control module and the reset module do not overlap, and the fourth scan signal of the fourth enable terminal is multiplexed with the sixth scan signal of the sixth enable terminal.

13. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes an auxiliary module connected to the third reference voltage terminal, the third node, and the seventh enable terminal, for transmitting the signal from the third reference voltage terminal to the third node in response to the seventh scan signal from the seventh enable terminal.

14. The pixel circuit according to claim 13, characterized in that, The voltage at the first reference voltage terminal is greater than the voltage at the third reference voltage terminal.

15. The pixel circuit according to claim 13, characterized in that, The pixel circuit includes an initialization phase; When the reset module is connected to the second reference voltage terminal, the third node, and the sixth enable terminal, during the initialization phase, the fourth scan signal of the fourth enable terminal, the fifth scan signal of the fifth enable terminal, and the sixth scan signal of the sixth enable terminal are all at a disabled level, and the seventh scan signal of the seventh enable terminal is at an enabled level. When the reset module is connected to the second reference voltage terminal, the fourth node, and the sixth enable terminal, during the initialization phase, the fourth scan signal of the fourth enable terminal and the fifth scan signal of the fifth enable terminal are both at a disabled level, and the seventh scan signal of the seventh enable terminal is at an enabled level.

16. The pixel circuit according to claim 13, characterized in that, The reset module is connected to the second reference voltage terminal, the fourth node, and the sixth enable terminal; In the same pixel circuit, the conduction periods of the second light-emitting control module and the reset module do not overlap, and the fifth scan signal of the fifth enable terminal is multiplexed with the sixth scan signal of the sixth enable terminal.

17. The pixel circuit according to claim 16, characterized in that, The pixel circuit includes a data writing stage, a reset stage, and a light-emitting stage; the reset stage is located after the data writing stage and before the light-emitting stage. During the reset phase, the fourth scan signal of the fourth enable terminal and the fifth scan signal of the fifth enable terminal are both at a disabled level, while the seventh scan signal of the seventh enable terminal is at an enabled level.

18. The pixel circuit according to claim 1, characterized in that, The driving transistor includes a first gate and a second gate; the first gate of the driving transistor is electrically connected to the first node, and the second gate of the driving transistor is electrically connected to the third node.

19. The pixel circuit according to claim 1, characterized in that, The writing module includes a writing transistor, and the writing transistor includes a first gate and a second gate; The first gate and the second gate of the write transistor are electrically connected.

20. A driving method for a pixel circuit, characterized in that, For driving the pixel circuit according to any one of claims 1-19; The driving method includes: During the initialization phase, the first reference voltage terminal and the second node, the second node and the first node, and the second reference voltage terminal and the third node are connected; During the compensation phase, the first reference voltage terminal and the second node, the second node and the first node, and the first power supply terminal and the third node are connected; During the data writing phase, the data voltage terminal is connected to the first node and the first reference voltage terminal is connected to the second node; During the light-emitting phase, the first power supply terminal and the third node, as well as the third node and the fourth node, are connected.

21. A display panel, characterized in that, include: Multiple pixel circuits arranged in an array as described in any one of claims 1-19.

22. The display panel according to claim 21, characterized in that, The display panel includes multiple pixel circuit rows, which extend along a first direction and are arranged along a second direction. The pixel circuit row includes a plurality of pixel circuits, and the scan signals of the corresponding enable terminals of the plurality of pixel circuits located in the same pixel circuit row are the same; Along the second direction, the second scan signal of the pixel circuit in the i-th row multiplexes the third scan signal of the pixel circuit in the (i+m)-th row, where i and m are both positive integers.

23. The display panel according to claim 21, characterized in that, The display panel includes multiple pixel circuit rows, which extend along a first direction and are arranged along a second direction. The pixel circuit row includes a plurality of pixel circuits, and the scan signals of the corresponding enable terminals of the plurality of pixel circuits located in the same pixel circuit row are the same; In the same pixel circuit, the conduction periods of the first light-emitting control module and the reset module do not overlap; along the second direction, the fifth scan signal of the pixel circuit in the j-th row multiplexes the second scan signal of the pixel circuit in the (j+n)-th row, where j and n are both positive integers.

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