Pixel driving circuit and display panel

Abstract

The application provides a pixel driving circuit and a display panel, wherein the pixel driving circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a driving transistor, a light emitting diode and a first capacitor. The eighth transistor inputs a third reference voltage to a first electrode of the driving transistor before the light emitting diode emits light, so as to improve the driving current difference caused by the hysteresis effect of the driving transistor. In addition, the third transistor and the fifth transistor are simultaneously turned on, so that a direct current voltage is continuously provided to the fourth node by a fourth reference voltage line in the light emitting stage, so as to stabilize the potential of the fourth node and prevent display problems caused by the floating of the fourth node in the light emitting stage. The application can improve the flicker problem at a low refresh rate and improve the overall display effect.

Description

Technical Field

[0001] This invention relates to the field of display panels, and more specifically, to a pixel driving circuit and a display panel. Background Technology

[0002] Compared with traditional display technologies, OLED (Organic Light-Emitting Diode) display technology has advantages such as being thinner and lighter, having a wider viewing angle, and being more energy-efficient.

[0003] However, at low refresh rates, the pixel driving circuits of existing OLED display panels can cause screen flickering due to the hysteresis effect of the driving transistors, thus affecting the display effect. Summary of the Invention

[0004] In view of this, the present invention provides a pixel driving circuit and a display panel to at least solve the problem of screen flickering under low refresh rates in existing display panels.

[0005] In one aspect, embodiments of the present invention provide a pixel driving circuit, including a plurality of pixel driving units arranged in an array, wherein the pixel driving unit includes:

[0006] The first transistor has its first terminal connected to the data signal line, its second terminal connected to the fourth node, and its gate connected to the second scan signal line.

[0007] The second transistor has its first terminal connected to the second node, its second terminal connected to the third node, and its gate connected to the second scan signal line.

[0008] The third transistor has its first terminal connected to the third node, its second terminal connected to the fifth node, and its gate connected to the first light-emitting signal line.

[0009] The fourth transistor has its first terminal connected to the second node, its second terminal connected to the first reference voltage line, and its gate connected to the first scan signal line.

[0010] The fifth transistor has its first terminal connected to the fourth node, its second terminal connected to the fourth reference voltage line, and its gate connected to the first light-emitting signal line.

[0011] The sixth transistor has its first terminal connected to the first power supply voltage line, its second terminal connected to the first node, and its gate connected to the second light-emitting signal line.

[0012] The seventh transistor has its first terminal connected to the fifth node, its second terminal connected to the second reference voltage line, and its gate connected to the third scan signal line.

[0013] The eighth transistor has its first terminal connected to the first node, its second terminal connected to the third reference voltage line, and its gate connected to the third scan signal line.

[0014] A driving transistor is used, with its first terminal connected to the first node, its second terminal connected to the third node, and its gate connected to the second node.

[0015] The first capacitor has its first terminal connected to the fourth node and its second terminal connected to the second node.

[0016] The light-emitting diode (LED) has its first electrode connected to the fifth node and its second electrode connected to the second power supply voltage line.

[0017] In some embodiments, the pixel driving unit further includes:

[0018] The second capacitor has its first terminal connected to the first power supply voltage line and its second terminal connected to the fourth node.

[0019] In some embodiments, the first to eighth transistors are all dual-gate transistors.

[0020] In some embodiments, the first to eighth transistors and the driving transistor are all P-type MOS transistors.

[0021] In some embodiments, the output signals of the first scan signal line, the second scan signal line, the third scan signal line, the first light emission signal line, and the second light emission signal line have the same frequency.

[0022] In some embodiments, within one frame time, the times when the first scan signal line, the second scan signal line, and the third scan signal line input low potentials to the pixel driving circuit do not overlap, while the times when the first light-emitting signal line and the second light-emitting signal line input high potentials to the pixel driving circuit partially overlap.

[0023] In some embodiments, within one frame time, the first scan signal line, the second scan signal line, and the third scan signal line sequentially input low potentials to the pixel driving circuit in chronological order.

[0024] In some embodiments, within one frame time, the rising edge of the first light-emitting signal line is earlier than the rising edge of the second light-emitting signal line, and the falling edge times of the first light-emitting signal line and the second light-emitting signal line are the same.

[0025] In some embodiments, within one frame time, the rising edge of the first light-emitting signal line is earlier than the falling edge of the first scan signal line, the rising edge of the second scan signal line is earlier than the rising edge of the second light-emitting signal line, the falling edge of the third scan signal is later than the rising edge of the second light-emitting signal line, and the rising edge of the third scan signal is earlier than the falling edge of the second light-emitting signal line.

[0026] On the other hand, embodiments of the present invention also provide a display panel including the pixel driving circuit described above.

[0027] The pixel driving circuit and display panel of the present invention, by inputting a third reference voltage to the first terminal of the driving transistor before the light-emitting diode emits light through the eighth transistor, improves the difference in driving current caused by the hysteresis effect of the driving transistor, and improves the flicker problem at the low refresh rate of the display panel; in addition, the third transistor and the fifth transistor are turned on at the same time, so that the fourth node is continuously supplied with DC voltage by the fourth reference voltage line during the light-emitting stage, thereby stabilizing the potential of the fourth node, preventing display problems caused by the floating connection of the fourth node during the light-emitting stage, and improving the overall display effect. Attached Figure Description

[0028] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0029] Figure 1 This is a circuit diagram of a pixel driving unit in a related technology;

[0030] Figure 2 yes Figure 1 Waveform diagram of the middle pixel driving unit during operation;

[0031] Figure 3 This is an overall schematic diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0032] Figure 4 This is an overall schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0033] Figure 5 This is a circuit diagram of a pixel driving unit provided in an embodiment of the present invention;

[0034] Figure 6 yes Figure 4 or Figure 5 Waveform diagram of the middle pixel driving unit during operation;

[0035] Figure 7 yes Figure 5 The pixel driving unit in Figure 6 A schematic diagram of the working status in stage t1;

[0036] Figure 8 yes Figure 5 The pixel driving unit in Figure 6 A schematic diagram of the working status in stage t2;

[0037] Figure 9 yes Figure 5 The pixel driving unit in Figure 6A schematic diagram of the working status in stage t3;

[0038] Figure 10 yes Figure 5 The pixel driving unit in Figure 6 A schematic diagram of the working status in stage t4;

[0039] Figure 11 This is a schematic diagram of a display panel provided in an embodiment of the present invention.

[0040] Figure label:

[0041] 10-pixel driving circuit

[0042] 11-pixel driving unit

[0043] T1 First Transistor

[0044] T2 second transistor

[0045] T3 Third Transistor

[0046] T4 fourth transistor

[0047] T5 fifth transistor

[0048] T6 sixth transistor

[0049] T7 Seventh Transistor

[0050] T8 Eighth Transistor

[0051] DTFT driving transistor

[0052] C1 First capacitor

[0053] C2, the second capacitor

[0054] N1 First Node

[0055] N2 Second Node

[0056] N3 Third Node

[0057] N4 Fourth Node

[0058] N5 Fifth Node

[0059] Sn-1 First Scan Signal Line

[0060] Sn Second Scan Signal Line

[0061] Sn+1 Third scan signal line

[0062] En_a First LED signal line

[0063] En_b Second LED Signal Line

[0064] Vint1 First Reference Voltage Line

[0065] Vint2 Second Reference Voltage Line

[0066] Vint3 Third Reference Voltage Line

[0067] Vint4 Fourth Reference Voltage Line

[0068] Data signal line

[0069] ELVDD First power supply voltage line

[0070] ELVSS Second Power Supply Voltage Line

[0071] 20 Display Panel Detailed Implementation

[0072] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted.

[0073] The use of terms such as "first," "second," and similar terms in the specific description does not indicate any order, quantity, or importance, but is merely used to distinguish different components. Furthermore, in the description of this invention, terms such as "upper," "lower," etc., indicate orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings. These are merely for ease of description and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on the invention.

[0074] It should be noted that, unless otherwise specified, the embodiments of the present invention and the features in different embodiments can be combined with each other.

[0075] like Figure 1 and Figure 2 As shown, US Patent 9418595B2 discloses a pixel driving circuit, wherein the circuit of the pixel driving unit is as follows: Figure 1 As shown. At low refresh rates of the display panel, the hysteresis effect of the driving transistor DTFT of the pixel driving unit causes the brightness of the light-emitting diode OLED to flicker during the light-emitting stage t3, which in turn causes the screen brightness of the display panel to flicker and affects the display effect of the display panel.

[0076] like Figure 3 and Figure 4 As shown, in one aspect, embodiments of the present invention provide a pixel driving circuit 10, including a plurality of pixel driving units 11 arranged in an array. The pixel driving circuit 10 includes: a first transistor T1 to an eighth transistor T8, a driving transistor DTFT, a light-emitting diode, and a first capacitor C1.

[0077] In this configuration, the first transistor T1 has its first terminal connected to the data signal line Data, its second terminal connected to the fourth node N4, and its gate connected to the second scan signal line Sn. The second transistor T2 has its first terminal connected to the second node N2, its second terminal connected to the third node N3, and its gate connected to the second scan signal line Sn. The third transistor T3 has its first terminal connected to the third node N3, its second terminal connected to the fifth node N5, and its gate connected to the first light-emitting signal line En_a. The fourth transistor T4 has its first terminal connected to the second node N2, its second terminal connected to the first reference voltage line Vint1, and its gate connected to the first scan signal line Sn-1. The fifth transistor T5 has its first terminal connected to the fourth node N4, its second terminal connected to the fourth reference voltage line Vint4, and its gate connected to the first light-emitting signal line En_a. The sixth transistor T6 has its first terminal connected to the first power supply voltage line ELVDD, its second terminal connected to the first node N1, and its gate connected to the second light-emitting signal line En_b. The seventh transistor T7 has its first terminal connected to the fifth node N5, its second terminal connected to the second reference voltage line Vint2, and its gate connected to the third scan signal line Sn+1. The eighth transistor T8 has its first terminal connected to the first node N1, its second terminal connected to the third reference voltage line Vint3, and its gate connected to the third scan signal line Sn+1. The driving transistor DTFT has its first terminal connected to the first node N1, its second terminal connected to the third node N3, and its gate connected to the second node N2. The light-emitting diode (LED) has its first terminal connected to the fifth node N5 and its second terminal connected to the second power supply voltage line ELVSS. The first capacitor C1 has its first terminal connected to the fourth node N4 and its second terminal connected to the second node N2. The first terminal of the first capacitor C1 is connected to the data signal line Data through the first transistor T1, and its second terminal is connected to the gate of the driving transistor DTFT, thus transmitting the data signal from the data signal line Data to the gate of the driving transistor DTFT via capacitive coupling.

[0078] Specifically, transistors T1 to T8 are switching transistors, and the driving transistor DTFT is a transistor that directly drives the light-emitting diode to emit light. The first electrode of transistors T1 to T8 and the driving transistor DTFT is the source, the second electrode is the drain, and the control terminal is the gate; or the first electrode of transistors T1 to T8 and the driving transistor DTFT is the source, the second electrode is the drain, and the control terminal is the gate.

[0079] In the above configuration, the eighth transistor T8 inputs a third reference voltage to the first terminal of the driving transistor DTFT before the LED emits light. This mitigates the difference in driving current caused by the hysteresis effect of the driving transistor DTFT, thus reducing flicker at low refresh rates. Furthermore, the third transistor T3 and the fifth transistor T5 are simultaneously activated, ensuring that the fourth node N4 receives a continuous DC voltage from the fourth reference voltage line during the light-emitting phase. This stabilizes the potential of the fourth node N4, preventing display problems caused by floating during the light-emitting phase and improving the overall display effect. In addition, this configuration reduces the power consumption of the display chip; including only one capacitor also saves space in the pixel driving circuitry.

[0080] like Figure 5 As shown, in some embodiments, the pixel driving unit 11 further includes a second capacitor C2. The first terminal of the second capacitor C2 is connected to the first power supply voltage line ELVDD, and the second terminal is connected to the fourth node N4. It should be noted that when the third transistor T3 and the fifth transistor T5 are simultaneously turned on, allowing the fourth node N4 to continuously receive DC voltage from the fourth reference voltage line during the light-emitting phase, the second capacitor C2 further stabilizes the potential of the fourth node N4, preventing display problems caused by the fourth node N4 floating during the light-emitting phase, and further improving the overall display effect.

[0081] Continue to refer to Figure 4 or Figure 5 In some embodiments, the first transistor T1 to the eighth transistor T8 are all single-gate transistors or dual-gate transistors. Dual-gate transistors can reduce leakage current in the first transistor T1 to the eighth transistor T8, further reducing the low refresh rate flicker problem of the display panel and improving the display effect.

[0082] Continue to refer to Figure 4 or Figure 5 In some embodiments, the first transistor T1 to the eighth transistor T8 and the driving transistor DTFT are all P-type MOS transistors. A P-type MOS transistor, also called a PMOS transistor, is short for P-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The on-state level of a PMOS transistor is low, and its off-state level is high. In other embodiments, those skilled in the art will readily recognize that the pixel driving unit 11 provided by this invention can be easily modified to consist entirely of N-type MOS transistors or hybrid CMOS transistors. It should be noted that the high and low voltage levels during transistor on- and off-state operations described below are based on PMOS transistors. When other appropriate transistor types are selected according to design requirements, their on- and off-state high and low voltage levels will also change accordingly.

[0083] like Figure 6 As shown, in some embodiments, the output signals of the first scan signal line Sn-1, the second scan signal line Sn, the third scan signal line Sn+1, the first light emission signal line En_a, and the second light emission signal line En_b have the same frequency. Specifically, the first scan signal line Sn-1, the second scan signal line Sn, and the third scan signal line Sn+1 respectively input a first scan signal, a second scan signal, and a third scan signal to the pixel driving circuit 10. Furthermore, within the same cycle, each of the first scan signal, the second scan signal, and the third scan signal has only one low-level period. The first scan signal, the second scan signal, and the third scan signal are emitted by the scan driving circuit and input to the pixel driving circuit 10. Simultaneously, the first light emission signal line En_a and the second light emission signal line En_b respectively input a first light emission signal and a second light emission signal to the pixel driving circuit 10. Furthermore, within the same cycle, each of the first light emission signal and the second light emission signal has only one high-level period. The first light emission signal and the second light emission signal are emitted by the light emission driving circuit and input to the pixel driving circuit 10.

[0084] Continue to refer to Figure 6 In some embodiments, during one frame of a picture, the times when the first scan signal line Sn-1, the second scan signal line Sn, and the third scan signal line Sn+1 input low potentials to the pixel driving circuit 10 do not coincide, while the times when the first light-emitting signal line En_a and the second light-emitting signal line En_b input high potentials to the pixel driving circuit 10 partially coincide. During the remaining time of one frame of a picture, the first scan signal line Sn-1, the second scan signal line Sn, and the third scan signal line Sn+1 all output high levels, while the first light-emitting signal line En_a and the second light-emitting signal line En_b both output low levels.

[0085] Continue to refer to Figure 6 In some embodiments, within one frame, the first scan signal line Sn-1, the second scan signal line Sn, and the third scan signal line Sn+1 sequentially input low potentials to the pixel driving circuit 10 in chronological order. Furthermore, the low potential times of the three lines do not overlap and the intervals between them are the same.

[0086] Continue to refer to Figure 6 In some embodiments, within one frame, the rising edge of the first light-emitting signal line En_a precedes the rising edge of the second light-emitting signal line En_b, and the falling edges of the first light-emitting signal line En_a and the second light-emitting signal line En_b occur at the same time. That is, within one frame, the high-level duration of the first light-emitting signal line En_a is longer than that of the second light-emitting signal line En_b, and their high-level states end simultaneously.

[0087] Continue to refer to Figure 6In some embodiments, within one frame, the rising edge of the first light-emitting signal line En_a is earlier than the falling edge of the first scan signal line Sn-1, the rising edge of the second scan signal line Sn is earlier than the rising edge of the second light-emitting signal line En_b, the falling edge of the third scan signal is later than the rising edge of the second light-emitting signal line En_b, and the rising edge of the third scan signal is earlier than the falling edge of the second light-emitting signal line En_b.

[0088] In some embodiments, the light-emitting diode can be an OLED or an AMOLED (Active-Matrix Organic Light-Emitting Diode). The first electrode of the light-emitting diode is the anode, and the second electrode is the cathode.

[0089] In some embodiments, the first power supply voltage line ELVDD provides a positive power supply voltage to the pixel driving circuit 10, and the second power supply voltage line ELVSS provides a negative power supply voltage to the pixel driving circuit 10.

[0090] In some embodiments, the first reference voltage line Vint1, the second reference voltage line Vint2, the third reference voltage line Vint3, and the fourth reference voltage line Vint4 provide a first reference voltage, a second reference voltage, a third reference voltage, and a fourth reference voltage to the pixel driving circuit 10, respectively. Furthermore, the first initial voltage, the second initial voltage, the third initial voltage, and the fourth initial voltage are constant. Specifically, the first initial voltage, the second initial voltage, the third initial voltage, and the fourth initial voltage can be selected by the pixel driving circuit 10 to meet different display requirements; this application does not impose any limitations on this.

[0091] Specifically, the pixel driving circuit 10 can operate at a low frequency, where low frequency means that the refresh rate of the display panel is less than 60Hz, but the minimum operating frequency is 1Hz, and this application does not limit this.

[0092] Continue to refer to Figure 6 In this embodiment, the operation of the pixel driving unit 11 is divided into four stages, t1 to t4, during the time it takes for the display panel to display one frame. During these four stages, the light-emitting diode in the pixel driving unit 11 completes one cycle from black insertion to light emission.

[0093] The following is combined Figure 6 waveform diagram and Figure 5 The circuit diagram is used to analyze the relationship between the input / output and light emission of the pixel driving unit 11 in the above four processes. Figure 4 The analysis process for the circuit diagram is the same, and will not be repeated below:

[0094] like Figure 6 and Figure 7 As shown, in stage t1, the first light-emitting signal line En_a, the second scan signal line Sn, and the third scan signal line Sn+1 are input at high level; the second light-emitting signal line En_b and the first scan signal line Sn-1 are input at low level. The first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off, while the fourth transistor T4 and the sixth transistor T6 are turned on. During this stage, the fourth node N4 maintains the potential from the end of the previous frame's display, i.e., the voltage V of the fourth node N4. N4 =Vint4, where Vint4 is the voltage of the fourth reference voltage line Vint4. The first reference voltage line Vint1 writes a potential to the second node N2 through the fourth transistor T4, that is, the voltage V of the second node N2. N2 =Vint1, where Vint1 is the voltage of the first reference voltage line Vint1. This stage can be regarded as the reset stage of the pixel driving unit 11. The first reference voltage line Vint1 writes a potential to the second node N2 through the fourth transistor T4 to reset the driving transistor DTFT. In addition, in this stage, since the third transistor T3 is turned off, the light-emitting diode does not emit light.

[0095] like Figure 6 and Figure 8 As shown, in stage t2, the first light-emitting signal line En_a, the first scan signal line Sn-1, and the third scan signal line Sn+1 are input at a high level; the second scan signal line Sn and the second light-emitting signal line En_b are input at a low level. The third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off, while the first transistor T1, the second transistor T2, and the sixth transistor T6 are turned on. In this stage, the data signal line Data writes a data signal to the fourth node N4 through the first transistor T1, i.e., the voltage V of the fourth node N4... N4 =V Data , where V Data This refers to the voltage of the data signal line Data. The first power supply voltage line ELVDD controls the potential of the second node N2 through the sixth transistor T6 and the driving transistor DTFT, that is, the potential of the second node N2 VN2 = V ELVDD +Vth, where V ELVDD The first power supply voltage is ELVDD, and Vth is the threshold voltage of the driving transistor DTFT. This stage can be considered as the compensation stage of the pixel driving unit 11, where the driving transistor DTFT is compensated using the first power supply voltage. Furthermore, in this stage, since the third transistor T3 is turned off, the light-emitting diode remains non-emitting.

[0096] like Figure 6 and Figure 9 As shown, in stage t3, the first light-emitting signal line En_a, the second light-emitting signal line En_b, the first scan signal line Sn-1, and the second scan signal line Sn are input at high level; the third scan signal line Sn+1 is input at low level. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off, while the seventh transistor T7 and the eighth transistor T8 are turned on. In this stage, the fourth node N4 maintains the potential written to the data signal line Data in the previous stage, i.e., the voltage V of the fourth node N4. N4 =V Data From stage t1 to stage t2, the potential change at the fourth node N4 is V. Data -Vint4. At this point, due to the presence of the first capacitor C1, the potential of the second node N2 is the potential at stage t2 minus the potential change at the fourth node N4, which is V. N2 =V ELVDD +Vth-V Data +Vint4. The third reference voltage line Vint3 writes a potential to the first node N1 through the eighth transistor T8, that is, the voltage V of the first node N1. N1 =Vint3, where Vint3 is the voltage of the third reference voltage line Vint3. The second reference voltage line Vint2 writes a potential to the fifth node N5 through the seventh transistor T7, that is, the voltage V of the fifth node N5. N5 =Vint2, where Vint2 is the voltage of the second reference voltage line Vint2. This stage can be regarded as the reset stage of the pixel driving unit 11. The first node N1, i.e., the source of the driving transistor DTFT, is written with a potential through the third reference voltage line Vint3 to reset the driving transistor DTFT. In addition, in this stage, since the third transistor T3 and the sixth transistor T6 are turned off, the light-emitting diode still does not emit light. With the above settings, the eighth transistor T8 inputs the third reference voltage to the first terminal (i.e., the source) of the driving transistor DTFT in this stage, i.e., before the light-emitting diode emits light, to improve the difference in driving current caused by the hysteresis effect of the driving transistor DTFT, and improve the flicker problem at low refresh rates of the display panel.

[0097] like Figure 6 and Figure 10As shown, in stage t4, the first scan signal line Sn-1, the second scan signal line Sn, and the third scan signal line Sn+1 are input at high level; the first light emission signal line En_a and the second light emission signal line En_b are input at low level. The first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off, while the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are turned on. In this stage, the fourth reference voltage line Vint4 writes a potential to the fourth node N4 through the fifth transistor T5, that is, the voltage V of the fourth node N4. N4 =Vint4. The potential of the second node N2 maintains the voltage of stage t3, that is, V. N2 =V ELVDD +Vth-V Data +Vint4. Furthermore, in this stage, since both the third transistor T3 and the sixth transistor T6 are turned on, the LED emits light. At this time, the LED current I = k(Vint4 - V Data 2, where k is the current calculation coefficient for the driving transistor DTFT. The above setup, by simultaneously turning on the third transistor T3 and the fifth transistor T5, ensures that the fourth node N4 receives a continuous DC voltage from the fourth reference voltage line during the light-emitting phase. This stabilizes the potential of the fourth node N4, preventing display problems caused by floating during the light-emitting phase and improving the overall display effect. It should be noted that, in the above process, the second capacitor C2 further stabilizes the potential of the fourth node N4, preventing display problems caused by floating during the light-emitting phase and further improving the overall display effect.

[0098] The pixel driving circuit 10 of the present invention provides a third reference voltage to the first electrode of the driving transistor DTFT before the light-emitting diode emits light through the eighth transistor T8, so as to improve the difference in driving current caused by the hysteresis effect of the driving transistor DTFT and improve the flicker problem at low refresh rates of the display panel. In addition, the third transistor T3 and the fifth transistor T5 are turned on at the same time, so that the fourth node N4 is continuously supplied with DC voltage by the fourth reference voltage line during the light-emitting stage, so as to stabilize the potential of the fourth node N4, prevent the display problem caused by the floating connection of the fourth node N4 during the light-emitting stage, and improve the overall display effect.

[0099] like Figure 11 As shown, in another aspect, embodiments of the present invention also provide a display panel 20, including the pixel driving circuit described above. This display panel 20 can be applied to any product or component with display functionality, such as mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, and navigators. Specific implementations of this display panel 20 can be found in the embodiments of the pixel driving circuit described above; details will not be repeated.

[0100] In summary, the pixel driving circuit and display panel of the present invention improve the difference in driving current caused by the hysteresis effect of the driving transistor by inputting a third reference voltage to the first terminal of the driving transistor before the light-emitting diode emits light through the eighth transistor, thereby reducing the flicker problem at low refresh rates of the display panel; in addition, the third transistor and the fifth transistor are turned on at the same time, so that the fourth node is continuously supplied with DC voltage by the fourth reference voltage line during the light-emitting stage, thereby stabilizing the potential of the fourth node, preventing display problems caused by the fourth node floating during the light-emitting stage, and improving the overall display effect.

[0101] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A pixel driving circuit, comprising a plurality of pixel driving units arranged in an array, characterized in that, The pixel driving unit includes: The first transistor has its first terminal connected to a data signal line, its second terminal connected to a fourth node, and its gate connected to a second scan signal line. The second transistor has its first terminal connected to the second node, its second terminal connected to the third node, and its gate connected to the second scan signal line; The third transistor has its first terminal connected to the third node, its second terminal connected to the fifth node, and its gate connected to the first light-emitting signal line; The fourth transistor has its first terminal connected to the second node, its second terminal connected to the first reference voltage line, and its gate connected to the first scan signal line; The fifth transistor has its first terminal connected to the fourth node, its second terminal connected to the fourth reference voltage line, and its gate connected to the first light-emitting signal line. The sixth transistor has its first terminal connected to the first power supply voltage line, its second terminal connected to the first node, and its gate connected to the second light-emitting signal line. The seventh transistor has its first terminal connected to the fifth node, its second terminal connected to the second reference voltage line, and its gate connected to the third scan signal line; The eighth transistor has its first terminal connected to the first node, its second terminal connected to the third reference voltage line, and its gate connected to the third scan signal line. A driving transistor, wherein a first terminal of the driving transistor is connected to the first node, a second terminal is connected to the third node, and a gate is connected to the second node; A first capacitor, wherein the first terminal of the first capacitor is connected to the fourth node, and the second terminal is connected to the second node; A light-emitting diode, wherein the first electrode of the light-emitting diode is connected to the fifth node, and the second electrode is connected to the second power supply voltage line.

2. The pixel driving circuit according to claim 1, characterized in that, The pixel driving unit further includes: The second capacitor has its first terminal connected to the first power supply voltage line and its second terminal connected to the fourth node.

3. The pixel driving circuit according to claim 1, characterized in that, The first transistor through the eighth transistor are all dual-gate transistors.

4. The pixel driving circuit according to claim 1, characterized in that, The first transistor through the eighth transistor and the driving transistor are all P-type MOS transistors.

5. The pixel driving circuit according to claim 1, characterized in that, The first scan signal line, the second scan signal line, the third scan signal line, the first light-emitting signal line, and the second light-emitting signal line all output signals with the same frequency.

6. The pixel driving circuit according to claim 5, characterized in that, Within one frame, the times when the first scan signal line, the second scan signal line, and the third scan signal line input low potentials to the pixel driving circuit do not overlap, while the times when the first light-emitting signal line and the second light-emitting signal line input high potentials to the pixel driving circuit partially overlap.

7. The pixel driving circuit according to claim 6, characterized in that, Within one frame, the first scan signal line, the second scan signal line, and the third scan signal line sequentially input a low potential to the pixel driving circuit in chronological order.

8. The pixel driving circuit according to claim 7, characterized in that, Within one frame, the rising edge of the first light-emitting signal line is earlier than the rising edge of the second light-emitting signal line, and the falling edges of the first and second light-emitting signal lines occur at the same time.

9. The pixel driving circuit according to claim 8, characterized in that, Within one frame, the rising edge of the first light-emitting signal line is earlier than the falling edge of the first scan signal line, the rising edge of the second scan signal line is earlier than the rising edge of the second light-emitting signal line, the falling edge of the third scan signal is later than the rising edge of the second light-emitting signal line, and the rising edge of the third scan signal is earlier than the falling edge of the second light-emitting signal line.

10. A display panel, characterized in that, Includes the pixel driving circuit according to any one of claims 1 to 9.

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