Display device, backlight control circuit, and backlight control method

Abstract

The application relates to a display device, a backlight control circuit and a backlight control method, and relates to the technical field of display devices. The display device comprises a display screen, at least two parallel driving circuit assemblies, a backlight assembly, a connection module and a main control circuit. The driving circuit assembly comprises at least two driving circuits connected in series. The backlight assembly comprises a plurality of backlight sub-zones, and each backlight sub-zone comprises a plurality of backlight sources. At least two output ends of the connection module are coupled with the at least two driving circuit assemblies in one-to-one correspondence. The main control circuit is coupled with the display screen and the input end of the connection module, and is configured to acquire a luminance data signal, send the luminance data signal to the corresponding driving circuit assembly through the connection module, and enable the driving circuit in the corresponding driving circuit assembly to control the luminance of the backlight source in the corresponding backlight sub-zone based on the corresponding sub-luminance data signal in the luminance data signal. The application can improve the backlight luminance regulation effect.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202511882906.5, filed on December 12, 2025, entitled “Display Device and Backlight Control Method”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display device technology, and in particular to a display device, a backlight control circuit, and a backlight control method. Background Technology

[0004] The driving circuit in display devices such as smart TVs is mainly used to control the brightness of the corresponding backlight based on the brightness data signal.

[0005] In traditional technology, the main control circuit in a display device sends a brightness data signal to the first driver circuit component. This signal is then transmitted sequentially among the driver circuit components connected in series. Each driver circuit controls the brightness of its corresponding backlight zone based on the received brightness data signal. However, this sequential transmission of the brightness data signal leads to significant cumulative signal loss in later driver circuit components. Furthermore, if a driver circuit component fails, the brightness data signal is interrupted, preventing subsequent components from receiving it. This hinders effective control of the backlight brightness in the backlight zones, resulting in poor backlight brightness regulation.

[0006] Therefore, traditional technologies suffer from poor backlight brightness control. Summary of the Invention

[0007] This application provides a display device, a backlight control circuit, and a backlight control method to solve the technical problem of poor backlight brightness regulation.

[0008] In a first aspect, some embodiments provide a display device, including: a display screen, at least two parallel driving circuit components, a backlight component, a connection module, and a main control circuit. The driving circuit components include at least two driving circuits connected in series; the backlight component includes multiple backlight zones, each backlight zone including multiple backlight sources; at least two output terminals of the connection module are coupled one-to-one with the at least two driving circuit components; the main control circuit is coupled to the input terminals of the display screen and the connection module, respectively, and is configured to:

[0009] Acquire brightness data signals;

[0010] The brightness data signal is sent to the corresponding driving circuit component through the connection module, so that the driving circuit in the corresponding driving circuit component controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the brightness data signal.

[0011] Technical Effect: By sending the brightness data signal to the corresponding drive circuit component through at least two output terminals of the connection module via the main control circuit, each drive circuit component can control the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the received brightness data signal. This achieves the goal of sending the brightness data signal to the corresponding drive circuit component via the connection module, avoiding the drawback of the main control circuit sending a brightness data signal to the first drive circuit component, causing the brightness data signal to be transmitted sequentially between drive circuit components, resulting in significant cumulative signal loss for later drive circuit components. By eliminating redundant brightness data signal transmission processes, the signal loss of the brightness data signal received by each drive circuit component is effectively reduced, improving the efficiency of each drive circuit component. The improved signal quality of the brightness data signal received by each driving circuit component facilitates effective control of the backlight brightness of the backlight zone corresponding to the driving circuit in each component. Furthermore, it avoids the problem of a malfunction in one driving circuit component causing a break in the brightness data signal, which could prevent other driving circuit components downstream from receiving the signal and thus hinder the normal control of the backlight in the corresponding backlight zone. This ensures that even if one driving circuit component fails, the backlight in the corresponding backlight zone of other driving circuit components can still be normally controlled, effectively improving the backlight control effect of the backlight in the subsequent driving circuit components when one component fails, thereby significantly enhancing the backlight brightness control effect.

[0012] Secondly, some embodiments also provide another display device, including: a display screen, at least two parallel driving circuit components, a backlight component, an analog multiplexer, and a main control circuit. The driving circuit components include at least two driving circuits connected in series; the backlight component includes multiple backlight zones, each backlight zone including multiple backlight sources; the analog multiplexer includes at least two analog switches, each of which is coupled to one of the at least two driving circuit components; the main control circuit is coupled to the brightness data signal input terminal and control signal input terminal of the display screen and the analog multiplexer, respectively, and is configured to:

[0013] Acquire the target brightness data signal of the driving circuit component and the target analog switch control signal of the driving circuit component;

[0014] The target brightness data signal and the target analog switch control signal are sent to the analog multiplexer;

[0015] The analog multiplexer is configured as follows:

[0016] Control the target analog switch corresponding to the target analog switch control signal to open, and control the non-target analog switch that does not correspond to the target analog switch control signal to close;

[0017] The target brightness data signal is sent to the corresponding driving circuit component through the target analog switch, so that the driving circuit in the corresponding driving circuit component controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the target brightness data signal.

[0018] Technical Effect: The main control circuit sends the target brightness data signal and target analog switch control signal of each drive circuit component to an analog multiplexer. This allows the analog multiplexer to control the target analog switch corresponding to the target analog switch control signal to open, and to control non-target analog switches not corresponding to the target analog switch control signal to close. The target brightness data signal is then sent to the corresponding drive circuit component via the target analog switch. Each drive circuit in the corresponding drive circuit component controls the brightness of the backlight in its corresponding backlight zone based on the corresponding sub-brightness data signal in the target brightness data signal. This achieves the goal of accurately sending the target brightness data signal of each drive circuit component to its corresponding drive circuit component via the analog multiplexer. It avoids the main control circuit sending a brightness data signal to the first drive circuit component, preventing the brightness data signal from being transmitted sequentially between drive circuit components and causing cumulative loss of brightness data signal received by later drive circuit components. The significant drawback is that by eliminating the need for redundant brightness data signal transmission, the signal loss of the brightness data signal received by each drive circuit component is effectively reduced, improving the signal quality of the brightness data signal received by each drive circuit component. This facilitates effective control of the backlight brightness of the backlight zone corresponding to the drive circuit in each drive circuit component. Moreover, it avoids the defect that if a drive circuit component fails, the brightness data signal will be interrupted, causing subsequent drive circuit components to be unable to receive normal brightness data signals, which could easily lead to the backlight of the corresponding backlight zone in the subsequent drive circuit components being unable to be properly controlled. This ensures that the backlight of the corresponding backlight zone in the subsequent drive circuit components can be normally controlled even if a drive circuit component fails, effectively improving the backlight control effect of the backlight zone in the subsequent drive circuit components when a drive circuit component fails, thereby effectively improving the backlight brightness control effect.

[0019] Thirdly, some embodiments also provide another display device, including: a display screen, at least two parallel driving circuit components, a backlight assembly, an adapter board, and a main control circuit. The driving circuit components include at least two driving circuits connected in series; the backlight assembly includes multiple backlight zones, each backlight zone including multiple backlight sources; at least two output terminals of the adapter board are coupled one-to-one with at least two driving circuit components; the main control circuit is coupled to at least two input terminals of the display screen and the adapter board, respectively, and is configured to:

[0020] Acquire target brightness data signals for the at least two driving circuit components;

[0021] The target brightness data signal is sent to the adapter board;

[0022] The adapter board is configured as follows:

[0023] The target brightness data signal is forwarded to the driving circuit assembly, so that the driving circuit in the driving circuit assembly controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the target brightness data signal.

[0024] Technical Effect: The main control circuit sends target brightness data signals for at least two drive circuit components to the adapter board. The adapter board then forwards the target brightness data signals to each drive circuit component. Each drive circuit in each drive circuit component controls the brightness of the backlight in its corresponding backlight zone based on the corresponding sub-brightness data signal within the target brightness data signal. This achieves the goal of forwarding target brightness data signals for all drive circuit components to each drive circuit component via the adapter board. This avoids the drawback of the main control circuit sending a brightness data signal to the first drive circuit component, causing the brightness data signal to be transmitted sequentially between drive circuit components, resulting in significant cumulative loss of brightness data signal received by later drive circuit components. By eliminating redundant brightness data signal transmission processes, the brightness data received by each drive circuit component can be effectively reduced. The reduced signal loss improves the signal quality of the brightness data signal received by each driving circuit component, which is beneficial for effectively controlling the backlight brightness of the backlight zone corresponding to each driving circuit in each driving circuit component. Moreover, it avoids the problem of the brightness data signal being interrupted when a certain driving circuit component fails, causing subsequent driving circuit components to be unable to receive normal brightness data signals, which could easily lead to the backlight of the driving circuit corresponding to the subsequent driving circuit components not being properly controlled. This ensures that when a certain driving circuit component fails, the backlight of the driving circuit corresponding to the driving circuit in other driving circuit components located after that driving circuit component can be normally controlled, effectively improving the backlight control effect of the backlight zone corresponding to the driving circuit in the subsequent driving circuit components when a certain driving circuit component fails, thereby effectively improving the backlight brightness control effect.

[0025] Fourthly, some embodiments also provide a backlight control circuit, including: a main control unit; a plurality of driving units, each of the driving units being used to drive at least one light-emitting device; the main control unit sending control data to the plurality of driving units via a data signal line; wherein the main control unit is connected to the plurality of driving units via a single data signal line, and the plurality of driving units are configured in parallel on the single data signal line; the backlight control circuit further includes a selection switch unit, the common terminal of the selection switch unit being connected to the single data signal line of the main control unit, and the plurality of selection terminals of the selection switch unit being respectively connected one-to-one to the data input terminals of the plurality of driving units;

[0026] The main control unit is further configured to: output a switch control signal to the selection switch unit to control the plurality of selection terminals to alternately connect with the common terminal in different time segments; and,

[0027] A timing signal containing address data sub-packets and luminance data sub-packets corresponding to each time segment is output to the single data signal line, such that within each time segment, the timing signal is transmitted through the selection switch unit to a drive unit connected to the currently active selection terminal.

[0028] Technical Effects: Breaking away from the conventional thinking that "simplified wiring must be achieved by sharing signal paths in series," this solution cleverly utilizes the condition of selecting the switching unit to allocate the path of a single data signal in the time dimension. It adopts time-division multiplexing and data sub-packet matching techniques, which solves the technical problem of ensuring that the signal path of each drive unit is independent and the load is single while maintaining low wiring complexity at the main control end. This achieves the technical effect of avoiding the cumulative attenuation and distortion of the signal on the long link and eliminating the failure of all subsequent units due to the failure of a single link.

[0029] Fifthly, some embodiments also provide another backlight control circuit, including: a main control unit; multiple driving branches, each driving branch including at least one driving unit connected in series for driving at least one light-emitting device; the main control unit sends control data to the multiple driving branches through a data signal line; wherein, the main control unit is simultaneously connected to the data input terminal of the first-end driving unit of each of the multiple driving branches through a single data signal line, forming a broadcast connection topology, and the first-end driving unit of each driving branch is provided with a hardware code recognition unit, and the hardware code recognition units of the first-end driving units of different driving branches are configured to have different hardware code states;

[0030] The driving unit is configured to: during power-on initialization, detect the hardware coding status of the hardware coding identification unit of its branch, and based on the detected hardware coding status, allocate a unique logical address range for itself and subsequent driving units in its branch.

[0031] The main control unit is configured to output a broadcast signal containing a target logical address and brightness data to the single data signal line, and the driving unit matches the target logical address in the broadcast signal with its own address and responds with the matched brightness data.

[0032] Technical Effects: Breaking away from the conventional thinking that "simplified wiring must be achieved through serial sharing of signal paths," this solution cleverly utilizes the condition of assigning different hardware coding states to the first unit of each branch under a physical parallel topology. It adopts a technical means of power-on self-identification and allocation of independent logical address segments accordingly. This solves the technical problem of ensuring that each drive unit can be uniquely addressed and accurately respond to commands while maintaining low wiring complexity at the master control end and broadcast signal transmission. As a result, all drive units can directly obtain the original signal without attenuation from the master control end, and achieve the technical effect of fault isolation between physical branches.

[0033] Sixthly, some embodiments also provide a backlight control method applied to a display device, the display device including a display screen, at least two parallel driving circuit components, a backlight component, a connection module, and a main control circuit; the driving circuit component includes at least two driving circuits connected in series; the backlight component includes multiple backlight zones, each backlight zone including multiple backlight sources; multiple output terminals of the connection module are coupled one-to-one with the at least two driving circuit components; the main control circuit is coupled to the input terminals of the display screen and the connection module respectively; the method includes:

[0034] Acquire brightness data signals;

[0035] The brightness data signal is sent to the corresponding driving circuit component through the connection module, so that the driving circuit in the corresponding driving circuit component controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the brightness data signal.

[0036] Technical Effect: By sending the brightness data signal to the corresponding drive circuit component through at least two output terminals of the connection module via the main control circuit, each drive circuit component can control the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the received brightness data signal. This achieves the goal of sending the brightness data signal to the corresponding drive circuit component via the connection module, avoiding the drawback of the main control circuit sending a brightness data signal to the first drive circuit component, causing the brightness data signal to be transmitted sequentially between drive circuit components, resulting in significant cumulative signal loss for later drive circuit components. By eliminating redundant brightness data signal transmission processes, the signal loss of the brightness data signal received by each drive circuit component is effectively reduced, improving the efficiency of each drive circuit component. The improved signal quality of the brightness data signal received by each driving circuit component facilitates effective control of the backlight brightness of the backlight zone corresponding to the driving circuit in each component. Furthermore, it avoids the problem of a malfunction in one driving circuit component causing a break in the brightness data signal, which could prevent other driving circuit components downstream from receiving the signal and thus hinder the normal control of the backlight in the corresponding backlight zone. This ensures that even if one driving circuit component fails, the backlight in the corresponding backlight zone of other driving circuit components can still be normally controlled, effectively improving the backlight control effect of the backlight in the subsequent driving circuit components when one component fails, thereby significantly enhancing the backlight brightness control effect. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the driver architecture of a display device provided in some embodiments of this application;

[0039] Figure 2 A schematic flowchart illustrating a backlight control method provided in some embodiments of this application;

[0040] Figure 3 This is a connection diagram of a multi-channel data signal control multi-channel driver IC (drive circuit) provided in some embodiments of this application;

[0041] Figure 4This application provides a schematic diagram illustrating the connection of a multi-channel driver IC controlled by the same data signal in some embodiments.

[0042] Figure 5 This is a schematic diagram of the driving architecture of a display device provided in other embodiments of this application;

[0043] Figure 6 A schematic flowchart illustrating a backlight control method provided in other embodiments of this application;

[0044] Figure 7 This application provides schematic diagrams illustrating driver IC data signal control based on analog multiplexers in some embodiments.

[0045] Figure 8 This is a schematic diagram illustrating the transmission of brightness data and readback data provided in some embodiments of this application;

[0046] Figure 9 This application provides schematic diagrams of the driver architecture of a display device for some embodiments thereof;

[0047] Figure 10 A schematic flowchart illustrating a backlight control method provided in some embodiments of this application;

[0048] Figure 11 A schematic diagram of driver IC data signal control based on an adapter board is provided for some embodiments of this application;

[0049] Figure 12 This is a schematic diagram illustrating the data signal provided in some embodiments of this application passing through the main control IC (main control circuit), adapter board, and driver IC (driver circuit);

[0050] Figure 13 Signaling interaction diagrams for a backlight control method for a display device provided in some embodiments of this application;

[0051] Figure 14 Structural block diagrams of backlight control devices provided in some embodiments of this application;

[0052] Figure 15 Structural block diagrams of backlight control devices provided in other embodiments of this application;

[0053] Figure 16 Structural block diagram of a backlight control device provided in some embodiments of this application;

[0054] Figure 17 A framework diagram of the main technical system of the backlight control circuit provided in some embodiments of this application;

[0055] Figure 18This application provides structural block diagrams of backlight control circuits in some embodiments.

[0056] Figure 19 The following is a structural block diagram of a backlight control circuit provided in some other embodiments of this application. Detailed Implementation

[0057] The embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described below do not represent all embodiments consistent with this application. They are merely examples of systems and methods consistent with some aspects of this application as detailed in the claims.

[0058] It should be noted that the brief descriptions of terms in this application are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0059] The terms "first," "second," "third," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar or related objects or entities, and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms are interchangeable where appropriate.

[0060] The terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclude inclusion, for example, a product or device that includes a range of components is not necessarily limited to all of the components that are clearly listed, but may include other components that are not clearly listed or that are inherent to such product or device.

[0061] The term "module" refers to any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code that is capable of performing the functions associated with that element.

[0062] In the field of LCD technology, local dimming has become a mainstream feature in high-end display devices to improve image contrast, reduce energy consumption, and achieve a superior visual experience. This technology independently controls the backlight module in separate zones, making bright areas brighter and dark areas darker. In this technological context, the core components typically consist of a main control integrated circuit, multiple driver integrated circuits, and an array of light-emitting devices. As market demands for display quality continue to rise, the number of backlight zones is rapidly increasing, from dozens to hundreds or even thousands. This trend places more stringent demands on the precision, real-time performance, and system complexity of the drive control. Given the need to balance display performance with hardware costs, building a backlight driver architecture that achieves precise zone control, high reliability, and cost-effectiveness has become a key challenge for the industry.

[0063] To address the increased control complexity resulting from the increased number of partitions, the industry has explored various technical approaches. One mainstream solution involves using multiple independent data signal lines, with the main control unit connecting to and controlling each driver IC. While this approach achieves independent control, it significantly increases the number of pins on the main control unit, the number of connectors, and PCB traces, thereby increasing system material costs and design complexity. To simplify the system and reduce costs, another considered and adopted solution is to use a single data signal line to control multiple driver ICs in series. In this solution, multiple driver ICs are connected in series on the same data signal path, and the data signal from the main control unit flows sequentially through each driver unit. However, this series architecture has inherent performance drawbacks. First, as the signal passes through the input / output interfaces of multiple driver units, it experiences cumulative attenuation and waveform distortion due to interface impedance and parasitic parameters. By the time the signal reaches the driver unit at the end of the link, its quality may have severely deteriorated, leading to inaccurate or even failed control of the backlight in the final partition, failing to achieve the expected local dimming effect. Second, this architecture places multiple driver units on the same physical link, creating a cascaded dependency. When any drive unit or its connecting node on the link fails, all drive units after the failure point cannot receive a valid control signal, resulting in large-area backlight failure and a significant weakness in system reliability. The root cause of these defects lies in the serial topology itself, whose indivisible signal path and fault propagation are difficult to overcome within the existing technological framework.

[0064] Therefore, a new backlight driving control scheme is urgently needed to effectively overcome signal attenuation and single-point failure problems while maintaining low wiring complexity and cost advantages, thereby meeting the dual requirements of signal quality and system reliability under a high number of zones. Based on this, this application proposes a display device, a backlight control circuit, and a backlight control method.

[0065] In this application embodiment, "display device" generally refers to a device with screen display and data processing capabilities. For example, display devices include, but are not limited to, smart TVs, mobile terminals, computers, monitors, advertising screens, wearable devices, virtual reality devices, and augmented reality devices. Furthermore, display devices can provide broadcast television reception functions and may also include, additionally, smart network TV functions with computer support, including but not limited to, network TV, smart TVs, and Internet Protocol TV (IPTV).

[0066] Figure 1 This is a schematic diagram of the driver architecture of a display device provided in some embodiments of this application. For example... Figure 1 The diagram shows that the driving architecture of the display device includes a display screen 110, at least two parallel driving circuit components 140, a backlight component 150, a connection module 130, and a main control circuit 120. Each driving circuit component 140 includes at least two driving circuits connected in series, such as five driving circuits connected in series. The backlight component 150 includes multiple backlight zones, each backlight zone including multiple backlight sources. At least two output terminals of the connection module 130 are coupled one-to-one with at least two driving circuit components 140. The main control circuit 120 is coupled to the input terminals of both the display screen 110 and the connection module 130.

[0067] In some embodiments, the display screen 110 includes display function components for presenting images and driving components for driving image display. The display screen 110 is used to receive and display image signals originating from the main control circuit 120. For example, the display screen 110 can be used to display video content, image content, menu control interface components, and user control UI interfaces, etc. For example, the display screen 110 is used to receive and display images or processed images sent by the main control circuit 120.

[0068] In some embodiments, the main control circuit 120 may include at least one of a central processing unit, a video processor, an audio processor, a graphics processor, and a power processor, and provide input / output interfaces from the first to the nth interface. The main control circuit 120 controls the operation of the display device and responds to user operations through various software control programs stored in memory. The main control circuit 120 controls the overall operation of the display device. Furthermore, the main control circuit 120 can also process images and audio. For example, the main control circuit 120 may refer to a main control IC (Integrated Circuit) used to generate a brightness data signal and send this brightness data signal to the corresponding drive circuit component 140 through the connection module 130, so that each drive circuit in the corresponding drive circuit component 140 controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the brightness data signal.

[0069] In some embodiments, the connection module 130 refers to a module connecting the main control circuit 120 and the drive circuit assembly 140, used to forward the brightness data signal sent by the main control circuit 120 to the corresponding drive circuit assembly 140. For example, the connection module 130 may refer to an analog multiplexer, used to receive the target brightness data signal of each drive circuit assembly sent by the main control circuit 120, as well as the target analog switch control signal of each drive circuit assembly, then control the target analog switch corresponding to the target analog switch control signal to open, and control the non-target analog switch not corresponding to the target analog switch control signal to close, and finally send the target brightness data signal to the corresponding drive circuit assembly 140 through the target analog switch, so that each drive circuit in the corresponding drive circuit assembly 140 controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the target brightness data signal. For example, the connection module 130 may refer to an adapter board, which is used to receive target brightness data signals for at least two drive circuit components sent by the main control circuit 120, and then forward the target brightness data signals to each drive circuit component 140, so that each drive circuit in each drive circuit component 140 controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the target brightness data signal.

[0070] In some embodiments, the driving circuit component 140 refers to a component used to control the corresponding backlight component 150 based on the received brightness data signal, such as a Driver IC (Driver Integrated Circuit) component. Each driving circuit component 140 includes multiple driving circuits, such as Driver ICs, connected in series. Each driving circuit is used to control the brightness of the backlight in a corresponding backlight zone based on a corresponding sub-brightness data signal in the received brightness data signal; for example, each driving circuit is used to convert the sub-brightness data signal into a backlight driving signal and control the brightness of the backlight in the corresponding backlight zone based on the backlight driving signal. For instance, each driving circuit in the driving circuit component 140 that receives the brightness data signal is used to control the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the brightness data signal.

[0071] In some embodiments, the backlight assembly 150 refers to an assembly that includes multiple backlight zones, and each backlight zone includes multiple backlight sources (such as red backlights, green backlights, and blue backlights), such as a color backlight module. The backlight source of each backlight zone in the backlight assembly 150 is used to adjust its current brightness to a corresponding brightness based on the sub-brightness data signal of each driving circuit in the driving circuit assembly 140. For example, driven by the backlight driving signal corresponding to the sub-brightness data signal of each driving circuit in the driving circuit assembly 140, the backlight source of each backlight zone in the backlight assembly 150 can adjust its current brightness to a corresponding brightness.

[0072] In some embodiments, such as Figure 1 As shown, this application provides a display device, which may include a display screen 110, at least two parallel driving circuit components 140, a backlight component 150, a connection module 130, and a main control circuit 120. The driving circuit component 140 includes at least two driving circuits connected in series; the backlight component 150 includes multiple backlight zones, each including multiple backlight sources; at least two output terminals of the connection module 130 are coupled to at least two driving circuit components in a one-to-one correspondence; and the main control circuit 120 is coupled to the input terminals of the display screen 110 and the connection module 130, respectively.

[0073] like Figure 2 As shown, the main control circuit 120 is configured as follows:

[0074] Step S201: Acquire brightness data signal.

[0075] In step S202, the brightness data signal is sent to the corresponding drive circuit component 140 through the connection module 130, so that the drive circuit in the corresponding drive circuit component 140 controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the brightness data signal.

[0076] The drive circuit components 140 are connected in parallel; for example, the reference... Figure 1 The drive circuit components 1, 2, 3, ... n are connected in parallel; for example, refer to Figure 7 and Figure 11 The drive circuit components of Lane 1, Lane 2, Lane 3, and Lane 4 are connected in parallel.

[0077] Each drive circuit assembly 140 includes multiple drive circuits connected in series; for example, reference Figure 1In drive circuit assembly 1, drive circuit 1, drive circuit 2, drive circuit 3... drive circuit N-1, drive circuit N are connected in series. A drive circuit refers to a Driver IC, which includes DIP terminals (input terminals) and DOS terminals (output terminals). For example, refer to... Figure 1 In drive circuit assembly 1, the DIP terminal of drive circuit 1 is used to receive the brightness data signal sent by connection module 130; the DOS terminal of drive circuit 1 is connected to the DIP terminal of drive circuit 2 and is used to send the brightness data signal to drive circuit 2; the DOS terminal of drive circuit 2 is connected to the DIP terminal of drive circuit 3 and is used to send the brightness data signal to drive circuit 3... The DOS terminal of drive circuit N-1 is connected to the DIP terminal of drive circuit N and is used to send the brightness data signal to drive circuit N. Each drive circuit corresponds to a backlight zone, specifically used to control the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal. For example, drive circuit 1 in drive circuit assembly 1 controls the brightness of the backlight in backlight zone 1 in backlight assembly 150 based on the corresponding sub-brightness data signal; drive circuit 2 in drive circuit assembly 1 controls the brightness of the backlight in backlight zone 2 in backlight assembly 150 based on the corresponding sub-brightness data signal.

[0078] Each backlight zone in the backlight assembly 150 includes multiple backlight sources, such as LEDs (Light Emitting Diodes). Each driving circuit drives the brightness of the LEDs in its corresponding backlight zone. The input terminal of the connection module 130 is coupled to the main control circuit 120 to receive brightness data signals sent by the main control circuit 120. The connection module 130 includes multiple output terminals, each coupled to a corresponding driving circuit assembly 140, for forwarding the brightness data signals to the corresponding driving circuit assembly 140, such as forwarding the brightness data signals to the driving circuit 1 in the driving circuit assembly 1. For example, the connection module 130 could refer to... Figure 5 The analog multiplexer in the text can also refer to... Figure 9 The adapter board in the middle.

[0079] The brightness data signal refers to the data signal used to control the brightness of the backlight in each backlight zone of the backlight assembly 150. Specifically, it includes sub-brightness data signals corresponding to multiple driving circuits, which can be determined based on the input image. For example, the main control circuit 120 determines, based on the received input image, which backlight zones need to have their backlight brightness increased and which need to have their backlight brightness decreased. Furthermore, refer to... Figure 1The brightness data signal can refer to the brightness data signal of a specific driving circuit component, such as the brightness data signal of driving circuit component 1. The brightness data signal of each driving circuit component includes the sub-brightness data signals corresponding to each driving circuit within that component. For example, the brightness data signal of driving circuit component 1 includes the sub-brightness data signals corresponding to driving circuit 1, driving circuit 2, driving circuit 3, ..., driving circuit N-1, and driving circuit N. Furthermore, refer to... Figure 1 Brightness data signal can also refer to brightness data signal for all driving circuit components, such as brightness data signal for driving circuit component 1, brightness data signal for driving circuit component 2, brightness data signal for driving circuit component 3, and so on, brightness data signal for driving circuit component n.

[0080] Sending the brightness data signal to the corresponding drive circuit component 140 via the connection module 130 can mean sending the brightness data signal of a certain drive circuit component 140 to that drive circuit component 140 via the connection module 130 (such as drive circuit component 1); or it can mean sending the brightness data signals for all drive circuit components 140 to each drive circuit component 140 separately via the connection module 130 (such as drive circuit component 1, drive circuit component 2, drive circuit component 3... drive circuit component n).

[0081] The brightness data signal includes a sub-brightness data signal corresponding to the address bit of each driving circuit. Each driving circuit in the driving circuit assembly 140 can identify the sub-brightness data signal corresponding to the address bit of each driving circuit from the received brightness data signal, and convert it into a backlight driving signal. The backlight driving signal is used to control the brightness of the backlight in the corresponding backlight zone, such as increasing or decreasing the brightness of the backlight in the corresponding backlight zone to a specified brightness.

[0082] It should be noted that local dimming technology uses a main control IC to control a driver IC to independently switch the backlight of different zones, resulting in a cleaner picture and higher contrast. It is currently widely used in LCD displays. As the number of backlight zones in LCD TVs increases daily, higher demands are placed on the finer control of these zones. Therefore, AM (Active Matrix) driving solutions have become the mainstream for backlight control. Currently, most AM driving solutions use multiple data signals to control multiple driver ICs, and their connection method is as follows: Figure 3As shown, the driver ICs are distributed in series on the LED board or LED strip. The main control IC achieves precise control of the driver ICs through data signals. After the main control IC sends data signals to address the driver ICs sequentially, each driver IC receives corresponding brightness data to control the brightness of the LEDs, achieving area-based light control. Furthermore, the transmission direction of the data signals is controllable; the data signals can be output from the driver ICs to the main control IC, which analyzes the state of the driver ICs based on this data and allocates VLED (Voltage for LED) to the LEDs in real time. To save hardware resources, reduce BOM (Bill of Materials) costs, and minimize wiring and connectors, using the same data signal to control multiple driver ICs is a major trend. When the same data signal controls multiple driver ICs, the multiple driver ICs are connected in series, as shown in the diagram. Figure 4 As shown, data signals are transmitted between multiple driver ICs, resulting in significant signal loss. This connection method has two drawbacks: when one lane fails, all subsequent lanes will fail to light up; when the data signal is transmitted to lane 3 or lane 4, energy attenuation and waveform distortion are highly likely to occur, making it difficult to guarantee signal quality. This can lead to the driver ICs in lane 3 or lane 4 becoming uncontrollable or even failing to light up, thus preventing the realization of local dimming control for the corresponding zone. Therefore, improving signal distortion and ensuring signal quality for all lanes is crucial. Based on this, the display device proposed in this application connects the various driving circuit components in parallel, with each driving circuit component receiving the brightness data signal independently. This eliminates the need for redundant brightness data signal transmission, effectively reducing signal loss in the brightness data signal received by each driving circuit component. Furthermore, it avoids the defect that a failure in one driving circuit component interrupts the brightness data signal, causing other driving circuit components downstream of that component to be unable to receive the brightness data signal.

[0083] Specifically, refer to Figure 1The main control circuit 120 analyzes and processes the received input image to obtain the brightness requirement information of each backlight zone in the backlight assembly. Based on the brightness requirement information of each backlight zone in the backlight assembly, it obtains the sub-brightness data signal of each driving circuit. The sub-brightness data signals of each driving circuit are combined to obtain the brightness data signal. Then, the main control circuit 120 sends the brightness data signal to the connection module 130. The connection module 130 receives the brightness data signal through its input terminal and then sends the brightness data signal through its output terminal to the corresponding driving circuit component 140. If the brightness data signal is for a certain driving circuit component 140, the brightness data signal is sent to the corresponding driving circuit component 140. If the brightness data signal is for all driving circuit components 140, the brightness data signal is sent to each driving circuit component 140 respectively. Each driving circuit in the driving circuit assembly 140 identifies the sub-brightness data signal corresponding to its address bit from the received brightness data signal, and then converts it into a backlight driving signal. The backlight driving signal is used to control the brightness of the backlight in the corresponding backlight zone, for example, increasing the brightness of the backlight in the corresponding backlight zone to a specified brightness to match the display of the input image. For example, in driving circuit assembly 1, driving circuit 1 identifies the sub-brightness data signal 1 corresponding to its address bit from the received brightness data signal, uses sub-brightness data signal 1 to control the brightness of the backlight in the corresponding backlight zone, and simultaneously sends the received brightness data signal to driving circuit assembly 2; driving circuit assembly 2 identifies the sub-brightness data signal 2 corresponding to its address bit from the received brightness data signal, uses sub-brightness data signal 2 to control the brightness of the backlight in the corresponding backlight zone, and simultaneously sends the received brightness data signal to driving circuit assembly 3, and so on, until the brightness data signal is transmitted to the last driving circuit in driving circuit assembly 1, i.e., driving circuit N. Furthermore, the main control circuit 120 also sends the input image to the display screen 110, and displays the received input image on the display screen 110.

[0084] The technical solution provided in this embodiment achieves the purpose of sending brightness data signals to the corresponding driving circuit components through the connection module, without the need for an extra brightness data signal transmission process. This effectively reduces the signal loss of the brightness data signals received by each driving circuit component, improves the signal quality of the brightness data signals received by each driving circuit component, and facilitates the effective control of the backlight brightness of the backlight zone corresponding to the driving circuit in each driving circuit component, thereby effectively improving the backlight brightness control effect.

[0085] In some embodiments, reference Figure 5The connection module is an analog multiplexer 530, which includes at least two analog switches, each of which is coupled to at least two drive circuit components 140 in a one-to-one correspondence; and a main control circuit 120 is coupled to the brightness data signal input terminal and the control signal input terminal of the analog multiplexer 530, respectively.

[0086] like Figure 6 As shown, the main control circuit 120 is configured as follows:

[0087] Step S601: Acquire the target brightness data signal of the driving circuit component 140 and the target analog switch control signal of the driving circuit component 140.

[0088] In step S602, the target brightness data signal and the target analog switch control signal are sent to the analog multiplexer 530.

[0089] The analog multiplexer 530 is configured to: control the target analog switch corresponding to the target analog switch control signal to open, and control the non-target analog switch that does not correspond to the target analog switch control signal to close; send the target brightness data signal through the target analog switch to the corresponding drive circuit component 140, so that the drive circuit in the corresponding drive circuit component 140 controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the target brightness data signal.

[0090] The analog multiplexer 530 includes multiple analog switches, each connected to a corresponding drive circuit component 140. The analog multiplexer 530 also includes a brightness data signal input terminal and a control signal input terminal. The brightness data signal input terminal receives the target brightness data signal sent by the main control circuit 120, and the control signal input terminal receives the target analog switch control signal sent by the main control circuit 120, such as multiple sub-analog switch control signals sent by the main control circuit 120.

[0091] The target brightness data signal refers to the brightness data signal corresponding to each driving circuit component, including the sub-brightness data signals of each driving circuit in the driving circuit component, such as the target brightness data signal 1 of driving circuit component 1, the target brightness data signal 2 of driving circuit component 2, and the target brightness data signal 3 of driving circuit component 3.

[0092] The target analog switch control signal refers to the analog switch control signal corresponding to each drive circuit component. It is used to control the analog switch corresponding to each drive circuit component to open and other analog switches to close. Specifically, it controls the target analog switch (e.g., analog switch S1) corresponding to the target analog switch control signal to open, and controls non-target analog switches (e.g., analog switches S2, S3, S4) that do not correspond to the target analog switch control signal to close; for example, target analog switch control signal 1 for drive circuit component 1, target analog switch control signal 2 for drive circuit component 2, target analog switch control signal 3 for drive circuit component 3, etc. Furthermore, the target analog switch control signal specifically includes multiple sub-analog switch control signals, such as... Figure 7 The control signals A and B are shown. (Reference) Figure 7 When control signal A is 0 and control signal B is 0, analog switch S1 is open, and analog switches S2, S3, and S4 are closed; when control signal A is 0 and control signal B is 1, analog switch S2 is open, and analog switches S1, S3, and S4 are closed; when control signal A is 1 and control signal B is 0, analog switch S3 is open, and analog switches S1, S2, and S4 are closed; when control signal A is 1 and control signal B is 1, analog switch S4 is open, and analog switches S1, S2, and S3 are closed. It should be noted that the number N of sub-analog switch control signals included in the target analog switch control signal has a preset correspondence with the number of drive circuit components 140, i.e., the number of drive circuit components 140 = 2. N For example, the number of sub-analog switch control signals is 2, and the number of drive circuit components 140 is 4; the number of sub-analog switch control signals is 3, and the number of drive circuit components 140 is 8; the number of sub-analog switch control signals is 4, and the number of drive circuit components 140 is 16.

[0093] Among them, the target analog switch refers to the analog switch that corresponds to the target analog switch control signal, such as analog switch S1; the non-target analog switch refers to the analog switch that does not correspond to the target analog switch control signal, such as analog switches S2, S3 and S4.

[0094] Specifically, refer to Figure 5The main control circuit 120 analyzes and processes the received input image to obtain the brightness requirement information of each backlight zone in the backlight assembly. Based on the brightness requirement information of each backlight zone in the backlight assembly, it obtains the sub-brightness data signal of each driving circuit. Based on the sub-brightness data signal of each driving circuit, it obtains the target brightness data signal of each driving circuit assembly 140. Then, the main control circuit 120 generates the target analog switch control signal of each driving circuit assembly 140 and, according to the transmission timing information of the target brightness data signal of each driving circuit assembly 140, combines the target brightness data signal and the target analog switch control signal of each driving circuit assembly 140. The signals are sent to the analog multiplexer 530. For example, in the first time period, the target brightness data signal and the target analog switch control signal of the drive circuit component 1 are sent to the analog multiplexer 530; in the second time period, the target brightness data signal and the target analog switch control signal of the drive circuit component 2 are sent to the analog multiplexer 530; in the third time period, the target brightness data signal and the target analog switch control signal of the drive circuit component 3 are sent to the analog multiplexer 530... and in the nth time period, the target brightness data signal and the target analog switch control signal of the drive circuit component n are sent to the analog multiplexer 530. The analog multiplexer 530 receives the target brightness data signal from the corresponding drive circuit component 140 through the brightness data signal input terminal and the target analog switch control signal from the corresponding drive circuit component 140 through the control signal input terminal. It then controls the target analog switch (e.g., analog switch S1) corresponding to the target analog switch control signal to open, and controls the non-target analog switches (e.g., analog switches S2, S3, and S4) not corresponding to the target analog switch control signal to close. The target brightness data signal is then sent to the corresponding drive circuit component 140 (e.g., drive circuit component 1) through the target analog switch. Each drive circuit in the corresponding drive circuit component 140 identifies the sub-brightness data signal corresponding to the address bit of each drive circuit from the received target brightness data signal, converts it into a backlight drive signal, and uses the backlight drive signal to control the brightness of the backlight in the corresponding backlight zone to match the display of the input image.

[0095] For example, see reference. Figure 7 and Figure 8In the first time cycle, the main control IC sends the brightness data signal, control signal A (0), and control signal B (0) of the drive circuit component of Lane 1 to the analog multiplexer. Based on control signal A (0) and control signal B (0), the analog multiplexer controls analog switch S1 to open and analog switches S2, S3, and S4 to close. Then, the analog multiplexer sends the brightness data signal of the drive circuit component of Lane 1 to Driver IC 1 in the drive circuit component of Lane 1 through analog switch S1. Driver IC 1 in the drive circuit component of Lane 1 identifies the sub-brightness data signal corresponding to the address bit of Driver IC 1 from the received brightness data signal, and uses the sub-brightness data signal to control the brightness of the backlight in the corresponding backlight zone. At the same time, it sends the received brightness data signal to Driver IC 2. Driver IC 2 identifies the sub-brightness data signal corresponding to the address bit of Driver IC 1 from the received brightness data signal. The address bit of 2 corresponds to the sub-brightness data signal, which is used to control the brightness of the backlight in the corresponding backlight zone. At the same time, the received brightness data signal is sent to Driver IC 3. This process continues until Driver IC N identifies the sub-brightness data signal corresponding to the address bit of Driver IC N from the received brightness data signal and uses the sub-brightness data signal to control the brightness of the backlight in the corresponding backlight zone.

[0096] The technical solution provided in this embodiment achieves the goal of accurately sending the target brightness data signal of each driving circuit component to the corresponding driving circuit component through an analog multiplexer, without the need for an extra brightness data signal transmission process. This can effectively reduce the signal loss of the brightness data signal received by each driving circuit component, which is beneficial for effectively controlling the backlight brightness of the backlight zone corresponding to the driving circuit in each driving circuit component, thereby effectively improving the backlight brightness control effect.

[0097] In some embodiments, reference Figure 5 The main control circuit 120 is also configured to: acquire the address signal of each drive circuit component 140; and send the address signal to the corresponding drive circuit component through the corresponding analog switch on the analog multiplexer 530.

[0098] The first driving circuit in the corresponding driving circuit assembly 140 is configured to: confirm the address bit of the first driving circuit as 1 based on the addressing signal; generate an address increment signal and send the address increment signal to the next driving circuit of the first driving circuit in the corresponding driving circuit assembly until the address bits of the driving circuits in the corresponding driving circuit assembly are confirmed.

[0099] The addressing signal is the signal used to determine the address bits of the driving circuit.

[0100] Specifically, refer to Figure 5 Before controlling the brightness of the backlight in the backlight zone, the main control circuit 120 acquires the addressing signal of each driving circuit component 140, and then sends the addressing signal of each driving circuit component 140 and the target analog switch control signal to the analog multiplexer 530. The analog multiplexer 530 controls the target analog switch (such as analog switch S1) corresponding to the target analog switch control signal to open, and controls the non-target analog switches (such as analog switches S2, S3 and S4) that do not correspond to the target analog switch control signal to close, and sends the addressing signal to the corresponding driving circuit component 140 (such as driving circuit component 1) through the target analog switch. The first driving circuit in the corresponding driving circuit component 140 confirms its own address bit as 1 based on the addressing signal, then generates an address increment signal, and sends the address increment signal to the second driving circuit in the driving circuit component 140. The second driving circuit confirms its own address bit as 2 based on the address increment signal, then generates a new address increment signal and sends the new address increment signal to the third driving circuit in the driving circuit component 140, and so on, until the address bit of each driving circuit in the corresponding driving circuit component 140 has been confirmed.

[0101] The technical solution provided in this embodiment generates an address signal for each driving circuit component and sends the address signal to the corresponding driving circuit component through the corresponding analog switch on the analog multiplexer. This enables each driving circuit in the corresponding driving circuit component to complete the address bit confirmation, which is beneficial for subsequent precise control of the backlight brightness in the backlight zone corresponding to each driving circuit through the address bit, further improving the backlight brightness control effect.

[0102] In some embodiments, reference Figure 5 The target brightness data signal of the driving circuit assembly 140 includes a sub-brightness data signal corresponding to the address bit of the driving circuit in the driving circuit assembly 140. The driving circuit in the driving circuit assembly 140 is configured to: obtain the sub-brightness data signal corresponding to the address bit of the driving circuit from the target brightness data signal; and control the brightness of the backlight in the corresponding backlight zone according to the sub-brightness data signal.

[0103] Each address bit of the driving circuit corresponds to a sub-brightness data signal; for example, address bit 1 corresponds to sub-brightness data signal 1, and address bit 2 corresponds to sub-brightness data signal 2.

[0104] The target brightness data signal is formatted as address bit + sub-brightness data signal, for example (address bit 1, sub-brightness data signal 1; address bit 2, sub-brightness data signal 2; address bit 3, sub-brightness data signal 3... address bit N, sub-brightness data signal N).

[0105] Specifically, refer to Figure 5 Each driving circuit in each driving circuit assembly 140 (e.g., driving circuit assembly 1) identifies a sub-brightness data signal that is the same as the address bit of each driving circuit from the received target brightness data signal (e.g., the target brightness data signal of driving circuit assembly 1), and uses it as the sub-brightness data signal corresponding to the address bit of each driving circuit. For example, it identifies the sub-brightness data signal 1 corresponding to address bit 1 of driving circuit 1. Then, it converts the corresponding sub-brightness data signal into a backlight driving signal, and finally uses the backlight driving signal to control the brightness of the backlight in the corresponding backlight zone, for example, adjusting the brightness of the backlight in the corresponding backlight zone to a specified brightness.

[0106] The technical solution provided in this embodiment achieves the goal of controlling the brightness of the backlight in the corresponding backlight zone based on the sub-brightness data signal corresponding to the address bit. This is beneficial for accurately controlling the brightness of the backlight in the backlight zone corresponding to each driving circuit, and further improves the backlight brightness control effect.

[0107] In some embodiments, reference Figure 5 The main control circuit 120 is also configured to: receive status data signals sent by the corresponding drive circuit component 140 through the target analog switch on the analog multiplexer 530; and determine the status of the drive circuit in the corresponding drive circuit component 140 through the status data signals.

[0108] The status data signals include the sub-status data signals of each drive circuit in the corresponding drive circuit assembly. The sub-status data signals of each drive circuit are used to reflect the status of each drive circuit, specifically the operating status, such as low supply voltage or high supply voltage.

[0109] Specifically, refer to Figure 5The corresponding driving circuit component 140 acquires the sub-state data signal of each driving circuit in the corresponding driving circuit component 140. Based on the sub-state data signal of each driving circuit in the corresponding driving circuit component 140, it obtains the state data signal of the corresponding driving circuit component 140. Then, through the target analog switch on the analog multiplexer 530, the state data signal is sent to the main control circuit 120. The main control circuit 120 parses the state data signal to obtain the sub-state data signal of each driving circuit in the corresponding driving circuit component 140. It analyzes the sub-state data signal of each driving circuit to obtain the state of each driving circuit. Based on the state of each driving circuit, it determines the target supply voltage of each driving circuit. Finally, it allocates the corresponding target supply voltage to each driving circuit to precisely control the brightness of the backlight of the corresponding backlight zone.

[0110] The technical solution provided in this embodiment determines the state of each driving circuit in the corresponding driving circuit component based on the state data signal sent by the target analog switch on the analog multiplexer. This facilitates precise control of the backlight brightness of the backlight zone corresponding to each driving circuit based on the state of each driving circuit, further improving the backlight brightness control effect.

[0111] In some embodiments, reference Figure 9 The connection module is an adapter board 930; at least two output terminals of the adapter board 930 are coupled to at least two drive circuit components 140 in a one-to-one correspondence; the main control circuit 120 is coupled to at least two input terminals of the adapter board 930.

[0112] like Figure 10 As shown, the main control circuit 120 is configured as follows:

[0113] Step S1001: Acquire target brightness data signals for at least two drive circuit components 140.

[0114] Step S1002: Send the target brightness data signal to the adapter board 930.

[0115] The adapter board 930 is configured to forward the target brightness data signal to the drive circuit assembly 140, so that the drive circuit in the drive circuit assembly 140 controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the target brightness data signal.

[0116] The adapter board 930 includes multiple output terminals, each of which is connected to a corresponding drive circuit component 140. The number of input terminals of the adapter board 930 is the same as the number of output terminals, and each input terminal receives the same target brightness data signal.

[0117] The target brightness data signal for at least two driving circuit components 140 refers to the target brightness data signal for all driving circuit components 140, specifically including the brightness data signals of driving circuit component 1, driving circuit component 2, driving circuit component 3... driving circuit component n. Its format is address bit + sub-brightness data signal, for example: (address bit 1 of driving circuit component 1, sub-brightness data signal 11; address bit 2 of driving circuit component 1, sub-brightness data signal 12; address bit 3 of driving circuit component 1, sub-brightness data signal 13... address bit N of driving circuit component 1). Sub-brightness data signal 1N; address bit 1 of driving circuit component 2, sub-brightness data signal 21; address bit 2 of driving circuit component 2, sub-brightness data signal 22; address bit 3 of driving circuit component 2, sub-brightness data signal 23... address bit N of driving circuit component 2, sub-brightness data signal 2N... address bit 1 of driving circuit component N, sub-brightness data signal N1; address bit 2 of driving circuit component N, sub-brightness data signal N2; address bit 3 of driving circuit component N, sub-brightness data signal N3... address bit N of driving circuit component N, sub-brightness data signal NN).

[0118] Specifically, refer to Figure 9 The main control circuit 120 analyzes and processes the received input image to obtain the brightness requirement information of each backlight zone in the backlight assembly. Based on the brightness requirement information of each backlight zone in the backlight assembly, it obtains the sub-brightness data signal of each driving circuit. Based on the sub-brightness data signal of each driving circuit, it obtains the brightness data signal of each driving circuit assembly 140. The brightness data signals of each driving circuit assembly 140 are combined to obtain the target brightness data signal for all driving circuit assemblies 140. Then, the main control circuit 120 sends the target brightness data signal to the adapter board 930. The adapter board 930 receives the same target brightness data signal through each input terminal and then forwards the target brightness data signal to each driving circuit assembly 140 through each output terminal. Each driving circuit in each driving circuit assembly 140 identifies the sub-brightness data signal corresponding to the address bit of each driving circuit from the received target brightness data signal, and then converts the corresponding sub-brightness data signal into a backlight driving signal. The backlight driving signal is used to control the brightness of the backlight in the corresponding backlight zone to match the display of the input image. Furthermore, the main control circuit 120 can also receive the corresponding status data signal sent by each drive circuit component 140 through the adapter board 930, determine the status of each drive circuit in each drive circuit component 140 through the status data signal; determine the target power supply voltage of each drive circuit based on the status of each drive circuit, and allocate the corresponding target power supply voltage to each drive circuit in order to precisely control the brightness of the backlight of the corresponding backlight zone.

[0119] For example, see reference. Figure 11 and Figure 12 The main control IC sends the target brightness data signals for the drive circuit components of Lane 1, Lane 2, Lane 3, and Lane 4 to the adapter board. The adapter board receives the same target brightness data signals through four input terminals and forwards them to Driver IC 1 in the drive circuit components of Lane 1, Lane 2, Lane 3, and Lane 4, respectively, through four output terminals. Driver IC 1 in the drive circuit component of Lane 1 identifies the sub-brightness data signal corresponding to the address bit of Driver IC 1 from the received target brightness data signals, and uses this sub-brightness data signal to control the brightness of the backlight in the corresponding backlight zone. At the same time, it sends the received brightness data signals to Driver IC 2 in the drive circuit component of Lane 1. Driver IC 2 identifies the sub-brightness data signal corresponding to the address bit of Driver IC 1 from the received brightness data signals. The sub-brightness data signal corresponding to address bit 2 is used to control the brightness of the backlight in the corresponding backlight zone. Simultaneously, the received brightness data signal is sent to Driver IC 3 in the driver circuit assembly of Lane 1. This process continues until Driver IC N in the driver circuit assembly of Lane 1 identifies the sub-brightness data signal corresponding to the address bit of Driver IC N from the received brightness data signal and uses this sub-brightness data signal to control the brightness of the backlight in the corresponding backlight zone. The execution process of the driver circuit assemblies of Lane 2, Lane 3, and Lane 4 is the same as that of Lane 1 and will not be described further.

[0120] The technical solution provided in this embodiment achieves the purpose of forwarding the target brightness data signals for all driving circuit components to each driving circuit component through the adapter board. This can effectively reduce the signal loss of the brightness data signals received by each driving circuit component, which is beneficial to effectively control the backlight brightness of the backlight zone corresponding to the driving circuit in each driving circuit component, thereby effectively improving the backlight brightness control effect.

[0121] In some embodiments, reference Figure 9 The signal input terminal of the first drive circuit in the drive circuit assembly 140 is connected to the corresponding signal terminal on the adapter board 930.

[0122] The first drive circuit in the drive circuit assembly 140 is configured to: detect the signal connection status of the signal input terminal of the first drive circuit when the main control circuit 120 is powered on; confirm the address bit of the first drive circuit as a preset value when the signal input terminal of the first drive circuit is detected to be connected to the corresponding signal terminal on the adapter board 930; generate an address increment signal and send the address increment signal to the next drive circuit in the drive circuit assembly 140 until the address bits of all drive circuits in the drive circuit assembly 140 are confirmed.

[0123] The corresponding signal terminals on the adapter board 930 include a VCC signal terminal, a GND terminal, a 1.5V signal terminal, and a floating terminal. It should be noted that the signal input terminal of the first drive circuit in each drive circuit assembly 140 is connected to the corresponding output terminal of the adapter board 930, as well as the corresponding signal terminal on the adapter board 930.

[0124] Specifically, refer to Figure 9 When the main control circuit 120 is powered on, the first drive circuit in each drive circuit assembly 140 detects the signal connection status of its own signal input terminal. If it detects that its own signal input terminal is connected to the corresponding signal terminal on the adapter board 930, it sets the address bit of the first drive circuit to a preset value. For example, if it detects a connection to the VCC signal terminal on the adapter board 930, it sets the address bit of the first drive circuit to 1; if it detects a connection to the GND terminal on the adapter board 930, it sets the address bit of the first drive circuit to 0; if it detects a connection to the 1.5V signal terminal on the adapter board 930, it sets the address bit of the first drive circuit to Q; if it detects a connection to a floating terminal on the adapter board 930, it sets the address bit of the first drive circuit to S. Next, the first drive circuit in each drive circuit assembly 140 generates an address increment signal and sends the address increment signal to the second drive circuit in each drive circuit assembly 140. The second driving circuit confirms its own address bit as 2, 0+1, Q+1, or S+1 based on the address increment signal, then generates a new address increment signal and sends the new address increment signal to the third driving circuit in each driving circuit component 140, and so on, until the address bit of each driving circuit in each driving circuit component 140 has been confirmed.

[0125] The technical solution provided in this embodiment, when it is detected that the signal input terminal of the first driving circuit is connected to the corresponding signal terminal on the adapter board, confirms the address bit of the first driving circuit as a preset value, and sends the address increment signal to the next driving circuit of the first driving circuit in each driving circuit assembly until each driving circuit in each driving circuit assembly has completed the address bit confirmation. This is beneficial for subsequent precise control of the backlight brightness of the backlight zone corresponding to each driving circuit through the address bit, further improving the backlight brightness control effect.

[0126] In some embodiments, such as Figure 5 As shown, this application also provides another display device, which may include a display screen 110, at least two parallel driving circuit components 140, a backlight component 150, an analog multiplexer 530, and a main control circuit 120. The driving circuit component 140 includes at least two driving circuits connected in series; the backlight component 150 includes multiple backlight zones, each including multiple backlight sources; the analog multiplexer 530 includes at least two analog switches, each of which is coupled to one of the at least two driving circuit components 140; the main control circuit 120 is coupled to the brightness data signal input terminal and the control signal input terminal of the display screen 110 and the analog multiplexer 530, respectively.

[0127] like Figure 6 As shown, the main control circuit 120 is configured as follows:

[0128] Step S601: Acquire the target brightness data signal of the driving circuit component 140 and the target analog switch control signal of the driving circuit component 140.

[0129] In step S602, the target brightness data signal and the target analog switch control signal are sent to the analog multiplexer 530.

[0130] The analog multiplexer 530 is configured to: control the target analog switch corresponding to the target analog switch control signal to open, and control the non-target analog switch not corresponding to the target analog switch control signal to close; send the target brightness data signal through the target analog switch to the corresponding drive circuit component 140, so that the drive circuit in the corresponding drive circuit component 140 controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the target brightness data signal.

[0131] It should be noted that for a description of another type of display device, please refer to [link / reference]. Figure 5 and Figure 6 The relevant embodiments are not described in detail here.

[0132] The technical solution provided in this embodiment achieves the goal of accurately sending the target brightness data signal of each driving circuit component to the corresponding driving circuit component through an analog multiplexer, without the need for an extra brightness data signal transmission process. This can effectively reduce the signal loss of the brightness data signal received by each driving circuit component, which is beneficial for effectively controlling the backlight brightness of the backlight zone corresponding to the driving circuit in each driving circuit component, thereby effectively improving the backlight brightness control effect.

[0133] In some embodiments, such as Figure 9 As shown, this application also provides another display device, which may include a display screen 110, at least two parallel driving circuit components 140, a backlight component 150, an adapter board 930, and a main control circuit 120. The driving circuit component 140 includes at least two driving circuits connected in series; the backlight component 150 includes multiple backlight zones, each including multiple backlight sources; at least two output terminals of the adapter board 930 are coupled one-to-one with at least two driving circuit components 140; and the main control circuit 120 is coupled to at least two input terminals of the display screen 110 and the adapter board 930, respectively.

[0134] like Figure 10 As shown, the main control circuit 120 is configured as follows:

[0135] Step S1001: Acquire target brightness data signals for at least two drive circuit components 140.

[0136] Step S1002: Send the target brightness data signal to the adapter board 930.

[0137] The adapter board 930 is configured to forward the target brightness data signal to the drive circuit assembly 140, so that the drive circuit in the drive circuit assembly 140 controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the target brightness data signal.

[0138] It should be noted that for a description of another type of display device, please refer to [link / reference]. Figure 9 and Figure 10 The relevant embodiments are not described in detail here.

[0139] The technical solution provided in this embodiment achieves the purpose of forwarding the target brightness data signals for all driving circuit components to each driving circuit component through the adapter board, without going through an extra brightness data signal transmission process. This can effectively reduce the signal loss of the brightness data signals received by each driving circuit component, which is conducive to the effective control of the backlight brightness of the backlight zone corresponding to each driving circuit in each driving circuit component, thereby effectively improving the backlight brightness control effect.

[0140] In some embodiments, such as Figure 2 As shown, a backlight control method is provided, which can be applied to, for example... Figure 1 The display device shown, such as Figure 1 As shown, the display device may include a display screen 110, at least two parallel driving circuit components 140, a backlight component 150, a connection module 130, and a main control circuit 120; the driving circuit component 140 includes at least two driving circuits connected in series; the backlight component 150 includes multiple backlight zones, and each backlight zone includes multiple backlight sources; at least two output terminals of the connection module 130 are coupled one-to-one with at least two driving circuit components 140; the main control circuit 120 is coupled to the input terminals of the display screen 110 and the connection module 130 respectively; the method may include the following steps:

[0141] Step S201: Acquire brightness data signal.

[0142] In step S202, the brightness data signal is sent to the corresponding driving circuit component through the connection module, so that the driving circuit in the corresponding driving circuit component controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the brightness data signal.

[0143] It should be noted that the specific implementation process of the above backlight control method can be found in [reference needed]. Figure 1 The embodiments of the display device shown are not described in detail here. It should be noted that the above-described backlight control method may also include... Figure 1 The implementation steps for the display device shown are not described in detail here.

[0144] The technical solution provided in this embodiment can effectively reduce the signal loss of the brightness data signal received by each driving circuit component, improve the signal quality of the brightness data signal received by each driving circuit component, and facilitate the effective control of the backlight brightness of the backlight zone corresponding to the driving circuit in each driving circuit component, thereby effectively improving the backlight brightness control effect.

[0145] In some embodiments, such as Figure 13 As shown, to more clearly describe the signaling interaction process between the modules of the display device, this application also provides another backlight control method, which may include the following steps:

[0146] Step S1301: The main control circuit receives the input image.

[0147] In step S1302, the main control circuit analyzes and processes the input image to obtain the brightness requirement information of each backlight zone in the backlight assembly. Based on the brightness requirement information of each backlight zone in the backlight assembly, the sub-brightness data signal of each driving circuit is obtained. The sub-brightness data signals of each driving circuit are combined to obtain the brightness data signal.

[0148] In step S1303, the main control circuit sends the brightness data signal to the connection module.

[0149] In step S1304, the connection module sends the brightness data signal to the corresponding drive circuit component.

[0150] In step S1305, each driving circuit in the driving circuit assembly converts the corresponding sub-brightness data signal in the brightness data signal into a backlight driving signal.

[0151] In step S1306, each driving circuit in the driving circuit assembly controls the brightness of the backlight in the corresponding backlight zone of the backlight assembly based on the corresponding backlight driving signal.

[0152] In step S1307, the main control circuit controls the display screen to display the input image or a compensated image of the input image.

[0153] The technical solution provided in this embodiment can effectively reduce the signal loss of the brightness data signal received by each driving circuit component, improve the signal quality of the brightness data signal received by each driving circuit component, and facilitate the effective control of the backlight brightness of the backlight zone corresponding to the driving circuit in each driving circuit component, thereby effectively improving the backlight brightness control effect.

[0154] In some embodiments, to more clearly illustrate the display device provided in the present application, the following specific embodiment will be used to describe the display device in detail. This application belongs to the field of LCD TV backlight zoning control, and in particular to a novel Driver IC data signal control technology. This technology can optimize the connection method of multiple Driver ICs, changing the series connection to a parallel connection, optimizing the data signal transmission method, ensuring the signal quality of all lanes, and achieving precise local dimming zoning control.

[0155] This application designs a novel driver IC data signal control method that ensures signal quality for each lane and achieves precise control without altering the communication protocol. The hardware connection method is optimized by changing the series connection to a parallel connection. Addressing and brightness data transmission are achieved using data signals. Two implementation schemes are detailed below:

[0156] The first approach: This approach uses a 4-lane configuration as an example. Additional control signals can be added as needed to control more lanes with the driver IC. The main control IC uses an analog multiplexer to control the opening and closing of multiple analog switches via control signals, while simultaneously adjusting the timing of data signals to achieve multi-channel driver IC control. For example... Figure 7 As shown, the main control IC outputs one data signal, which is connected to four driver ICs via four analog switches. The main control IC sends the data signal to initialize and address the driver ICs. During addressing, each driver IC in each lane is addressed separately, meaning the address of the first driver IC in each lane is always one. The data signal is as follows: Figure 8 As shown, both the brightness data packet and the readback packet consist of 4 packets. When transmitting brightness data, all switches are off, except for S1, which is on. The Driver IC on Lane 1 receives the brightness data from Lane 1 to control the brightness of the corresponding LED. Similarly, only S2 is on, and the Driver IC on Lane 2 receives the brightness data from Lane 2 to control the brightness of the corresponding LED. This process continues to achieve data reception for all lanes and local dimming control for all zones.

[0157] When the master control IC reads back the state of the driver IC, it reverses the data signal transmission direction, sending the data signal from the driver IC to the master control IC. Similarly, during readback, all switches are closed, except for S1, which is open. The master control IC reads the driver IC state on Lane 1 via the data signal; only S2 is open, and the master control IC reads the driver IC state on Lane 2 via the data signal. This process continues to achieve driver IC state readback for all lanes. For example, the master control IC outputs two control signals to control the opening and closing of analog switches. When control signal A is 0 and B is 0, switch S1 is open; when control signal A is 0 and B is 1, switch S2 is open; when control signal A is 1 and B is 0, switch S3 is open; and when control signal A is 1 and B is 1, switch S4 is open. This ensures that data from each lane is accurately transmitted to the master control IC and the driver IC. Based on the above scheme, the number of lanes can be increased as needed. For example, a control signal can be added to the main control IC to control the 8 lane signals to achieve the Local Dimming function.

[0158] The second approach: The main control IC sends one data signal to the 4-lane Driver IC. The DIP signal of the first Driver IC in each lane, besides being connected to the data signal sent by the main control IC via an adapter board, is also connected to VCC, GND, 1.5V, and a floating signal, respectively. Figure 11 As shown. When the Driver IC is powered on, each Driver IC checks its own DIP signal connection status. When a DIP signal is detected to be connected to the VCC signal, the Driver IC is determined to be the first IC in Lane 1, addressed as 1, and so on, until the last IC is addressed as N; when a DIP signal is detected to be connected to the GND signal, the Driver IC is determined to be the first IC in Lane 2, addressed as 0, and so on, until the last IC is addressed as P; when a DIP signal is detected to be connected to the 1.5V signal, the Driver IC is determined to be the first IC in Lane 3, addressed as Q, and so on, until the last IC is addressed as R; when a DIP signal is detected to be floating, the Driver IC is determined to be the first IC in Lane 4, addressed as S, and so on, until the last IC is addressed as T, where T > S > R > Q > P > O > N.

[0159] After the Driver IC has been successfully addressed, the Master Control IC sends a data signal to the Driver IC. This signal is in the format of address bits + brightness data, such as... Figure 12 As shown, the data signal is transmitted to the Driver IC via the adapter board. Each Driver IC in each lane receives specific brightness data based on its address bits to control the LEDs. When the main control IC reads back the status of the Driver IC, it reverses the data signal transmission direction, and the data signal is sent from the Driver IC to the main control IC. The main control IC then receives the status of each Driver IC.

[0160] The technical solution provided in this embodiment can achieve the following technical effects: (1) Optimize the connection method of multiple driver ICs, change from series connection to parallel connection, reduce the load on each path, thereby reducing signal attenuation and electromagnetic interference. (2) Improve system reliability and redundancy. The parallel structure allows the signal to be transmitted through multiple paths. When one path fails, the other paths can still maintain signal transmission.

[0161] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0162] Based on the same inventive concept, this application also provides a backlight control device for implementing the backlight control method described above. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more backlight control device embodiments provided below can be found in the limitations of the backlight control method described above, and will not be repeated here.

[0163] In some embodiments, such as Figure 14 As shown, a backlight control device 1400 is provided, which can be applied to applications such as... Figure 1 The display device shown, such as Figure 1 As shown, the display device may include a display screen 110, at least two parallel driving circuit assemblies 140, a backlight assembly 150, a connection module 130, and a main control circuit 120; the driving circuit assembly 140 includes at least two driving circuits connected in series; the backlight assembly 150 includes multiple backlight zones, and each backlight zone includes multiple backlight sources; at least two output terminals of the connection module 130 are coupled one-to-one with at least two driving circuit assemblies; the main control circuit 120 is coupled to the input terminals of the display screen 110 and the connection module 130 respectively; the device may include:

[0164] The first acquisition module 1410 is used to acquire brightness data signals.

[0165] The first transmitting module 1420 is used to transmit the brightness data signal to the corresponding driving circuit component through the connection module, so that the driving circuit in the corresponding driving circuit component controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the brightness data signal.

[0166] In some embodiments, such as Figure 15As shown, another backlight control device 1500 is provided, which can be applied to applications such as... Figure 5 The display device shown, such as Figure 5 As shown, the display device may include a display screen 110, at least two parallel drive circuit components 140, a backlight assembly 150, an analog multiplexer 530, and a main control circuit 120. The drive circuit component 140 includes at least two drive circuits connected in series; the backlight assembly 150 includes multiple backlight zones, each including multiple backlight sources; the analog multiplexer 530 includes at least two analog switches, each coupled to one of the at least two drive circuit components 140; the main control circuit 120 is coupled to the brightness data signal input terminal and control signal input terminal of the display screen 110 and the analog multiplexer 530, respectively. This device may include:

[0167] The second acquisition module 1510 is used to acquire the target brightness data signal of the driving circuit component and the target analog switch control signal of the driving circuit component.

[0168] The second transmitting module 1520 is used to transmit the target brightness data signal and the target analog switch control signal to an analog multiplexer. The analog multiplexer is configured to: control the target analog switch corresponding to the target analog switch control signal to open, and control the non-target analog switch not corresponding to the target analog switch control signal to close; transmit the target brightness data signal through the target analog switch to the corresponding driving circuit component, so that the driving circuit in the corresponding driving circuit component controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the target brightness data signal.

[0169] In some embodiments, such as Figure 16 As shown, another backlight control device 1600 is provided, which can be applied to, for example... Figure 9 The display device shown, such as Figure 9 As shown, the display device may include a display screen 110, at least two parallel driving circuit assemblies 140, a backlight assembly 150, an adapter board 930, and a main control circuit 120. The driving circuit assembly 140 includes at least two driving circuits connected in series; the backlight assembly 150 includes multiple backlight zones, each including multiple backlight sources; at least two output terminals of the adapter board 930 are coupled one-to-one with at least two driving circuit assemblies; the main control circuit 120 is coupled to at least two input terminals of the display screen 110 and the adapter board 930, respectively. This device may include:

[0170] The third acquisition module 1610 is used to acquire target brightness data signals for at least two drive circuit components.

[0171] The third transmitting module 1620 is used to transmit the target brightness data signal to the adapter board; the adapter board is configured to forward the target brightness data signal to the driving circuit assembly, so that the driving circuit in the driving circuit assembly controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the target brightness data signal.

[0172] Each module in the aforementioned backlight control device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0173] The technical concept of this solution is as follows: In the backlight control system of a liquid crystal display device, the main body of the technology typically consists of a main control integrated circuit and multiple backlight driver integrated circuits. The operational scenario of its technical functional modules is as follows: the main control unit needs to send precise brightness control signals to the driver units distributed in different physical locations to achieve high-contrast local dimming. With the increasing demands for image quality in display devices, the number of backlight zones has increased dramatically, which in turn increases the number of driver units. Under these conditions, a core technical obstacle lies in how to ensure that the control signals can be transmitted to each driver unit with high quality and high reliability within limited hardware complexity and cost constraints.

[0174] A common technological inertia exists in existing technologies: to simplify the physical wiring from the main control unit to multiple drive units, the most direct approach is to use a single data signal and connect multiple drive units in a daisy-chain configuration along this signal path. This thinking stems from a naive understanding of "simplification," namely, reducing the number of connections equates to reducing complexity. However, this daisy-chain architecture has inherent mechanistic flaws. When a signal is transmitted in a daisy-chain link, it faces signal attenuation and waveform distortion due to interface impedance at each drive unit. When the number of drive units reaches a certain level (e.g., the third or fourth unit at the end of the link), signal integrity will be severely degraded, leading to incorrect or malfunctioning commands received by the end drive unit, thus failing to achieve precise brightness control. More seriously, this architecture places all drive units on the same physical link; the failure of any intermediate node will cause all subsequent nodes to malfunction, resulting in a single point of vulnerability in system reliability. Existing technologies typically focus on optimizing signal relay or protocol coding within a serial framework, but cannot fundamentally overcome the two inherent problems determined by the topology: excessively long signal paths and fault propagation.

[0175] To overcome the inherent signal attenuation and fault propagation problems of series topologies, this solution abandons the traditional approach of optimization within a predetermined framework and instead adopts a topology reconstruction mechanism. Specifically, this solution breaks with the conventional wisdom that "simplifying wiring necessitates series connection" and proposes a core technical approach that reconstructs the connection method of driver units from "sequential series" to "selective or broadcast parallel connection." This reconstruction is not simply a change in connection method, but rather includes entirely new signal distribution and unit addressing logic to address the new problems arising from the topology change, thereby achieving the goal of thoroughly resolving signal quality and system reliability issues while maintaining low wiring complexity.

[0176] This solution achieves the aforementioned reconstruction through two collaborative technical approaches: Approach 1 introduces a controlled selection switch unit to alternately guide the single-channel output signal of the main control unit to each parallel branch within different time segments. The key to this approach is that, through time-dimensional multiplexing, a single physical signal is logically transformed into multiple independent virtual channels, each directly reaching the target driver unit. The path is extremely short and the load is singular, thus eliminating the cumulative attenuation of the signal over long links. Approach 2 employs broadcast parallel connection, where the main control signal is simultaneously sent to all branches, but each parallel branch is assigned a unique hardware code identity. When the driver unit powers on, it automatically assigns a globally unique logical address to itself and its affiliated branches by recognizing this hardware code. The main control unit broadcasts data packets containing the target address, and each driver unit only responds to instructions matching its own address. This mechanism allows all driver units to directly obtain the undegraded original signal from the source, while the electrical isolation between physical branches prevents fault propagation across branches.

[0177] Therefore, this solution first achieves the technical effect of ensuring that each drive unit, especially the end unit, receives a control signal of the same quality as the first unit, laying the physical foundation for achieving fine and uniform local dimming. Secondly, it achieves fault isolation between drive branches, ensuring that an anomaly in a single branch no longer affects the normal operation of other parts of the system, significantly improving the overall robustness of the system.

[0178] Furthermore, the "topology reconstruction and collaborative logic design" mechanism adopted in this solution breaks the traditional technical inertia of forcibly binding "wiring simplification" and "signal serialization" in the field of backlight control, thereby reconstructing the basic paradigm of signal distribution and unit addressing in multi-node control systems. This reconstruction is not an incremental improvement on existing solutions, but an architectural-level innovation. It decouples the coupling relationship between wiring complexity and signal path length, proving that through innovative logic control (time-division selection or hardware-coded addressing), efficient and reliable centralized control can be achieved on parallel physical topologies. Ultimately, this solution simplifies the physical layer design of the system (reducing wiring and connectors) while simultaneously achieving a leap in signal integrity, system reliability, and control accuracy, achieving comprehensive technical effects that are difficult to achieve under existing serial architectures.

[0179] Therefore, this solution, by reconstructing the interconnect topology and supporting control logic of the backlight driver unit, and employing either a parallel architecture combined with dynamic signal allocation or a parallel architecture combined with static identity encoding, solves the long-standing problem of signal attenuation and system reliability being mutually constrained under a high number of partitions. Furthermore, this solution breaks through the long-standing technical prejudice in the display driver industry that "single-channel signal control of multiple channels must use a series approach to save pins and wiring," providing a new and superior technical implementation path for high-partition backlight systems.

[0180] Before introducing the specific embodiments of this application, the constituent units involved in this application will be described first: main control unit (100); drive unit (200, each branch: 200_1, 200_2, ... 200_n), which integrates a hardware encoding recognition unit (600) and an address self-allocation logic module (700); data signal line (300); light-emitting device (400); selection switch unit (500), which integrates an analog switch array and decoding logic; adapter board (800), which integrates a hardware encoding configuration circuit.

[0181] In some embodiments, such as Figure 17 As shown, this application also provides a technical main system framework diagram of a backlight control circuit. The technical main system of the backlight control circuit includes: a main control unit (100); multiple driving units (200_1 to 200_n), each driving unit being used to drive at least one light-emitting device (400); the main control unit (100) sends control data to the multiple driving units (200_1 to 200_n) through a data signal line (300); wherein, the main control unit (100) is connected to the multiple driving units (200_1 to 200_n) through a single data signal line (300), and the multiple driving units (200_1 to 200_n) are configured in parallel on the single data signal line (300).

[0182] refer to Figure 17 The main technical system of the backlight control circuit includes: a main control unit (100), multiple driving units (200_1 to 200_n), a data signal line (300), and light-emitting devices (400) driven by the driving units. The cooperative relationship between each unit and other units is as follows: the main control unit (100) communicates with each driving unit (200_1 to 200_n) through the data signal line (300) and sends control data to them; each driving unit (200_1 to 200_n) independently controls the light-emitting state of its connected light-emitting device (400) according to the received control data; the light-emitting device (400) is driven by the driving unit (200_1 to 200_n) to emit light, forming the backlight of the display device (i.e., display equipment, such as a smart TV).

[0183] Here, the main control unit (100) refers to the main control circuit, such as the main control IC. The driving unit refers to the driving circuit, such as the Driver IC; each driving unit (200_1 to 200_n) includes at least two driving units connected in series in its driving branch, and each driving unit is used to independently control the light emission state of one or more light-emitting devices (400) connected to it. The driving branch refers to the driving circuit assembly, specifically including at least two driving units connected in series in its driving branch; each driving branch is configured in parallel on a single data signal line (300), and the main control unit (100) is connected in parallel with each driving branch through the single data signal line (300); for example, reference Figure 17 The drive branches 1, 2, 3, ..., n are connected in parallel. A single data signal line (300) is used to transmit control data (such as brightness data sub-packets) sent by the main control unit (100) to each drive unit (200_1 to 200_n). The light-emitting device (400) refers to the backlight, specifically the backlight in the backlight zone, such as an LED.

[0184] Specifically, refer to Figure 17The main control unit (100) analyzes and processes the received input image to obtain the brightness requirement information of the light-emitting device (400) controlled by each driving unit. Based on the brightness requirement information of the light-emitting device (400) controlled by each driving unit, it obtains the sub-brightness data signal of each driving unit. It combines the sub-brightness data signals of each driving unit to obtain control data (such as brightness data sub-packets). Then, the main control unit (100) sends the control data to each driving unit (200_1 to 200_n) through the data signal line (300), so that each driving unit (200_1 to 200_n) independently controls the light-emitting state of its connected light-emitting device (400) according to the received control data. For example, if the control data is for a specific drive branch, the main control unit (100) sends the control data to the corresponding drive branch via a selection switch unit (such as an analog multiplexer); if the control data is for all drive branches, the main control unit (100) sends the control data to each drive branch via an adapter board. Each drive unit in the drive branch identifies the sub-brightness data signal corresponding to the address bit of each drive unit from the received control data, then converts it into a backlight drive signal, and uses the backlight drive signal to independently control the light emission state of the corresponding light-emitting device (400), such as increasing the light emission brightness of the corresponding light-emitting device (400) to a specified brightness to match the display of the input image. For example, in drive branch 1, drive unit 1 identifies the sub-brightness data signal 1 corresponding to the address bit of drive unit 1 from the received control data, uses the sub-brightness data signal 1 to control the light emission state of the corresponding light-emitting device (400), and simultaneously sends the received control data to drive circuit assembly 2; drive circuit assembly 2 identifies the sub-brightness data signal 2 corresponding to the address bit of drive circuit 2 from the received control data, uses the sub-brightness data signal 2 to control the brightness of the backlight in the corresponding backlight zone, and simultaneously sends the received control data to drive circuit assembly 3, and so on, until the control data is transmitted to the last drive circuit in drive circuit assembly 1, i.e., drive circuit N. Further, the main control unit (100) can also send the input image to the display screen, and display the received input image on the display screen. In some embodiments, such as Figure 18As shown, this application also provides a backlight control circuit (using a time-division multiplexing selection mechanism), including: a main control unit (100); and multiple drive units (200_1 to 200_ ). Each driving unit is used to drive at least one light-emitting device (400); the main control unit (100) sends control data to multiple driving units (200_1 to 200_n) through a data signal line (300); wherein, the main control unit is connected to multiple driving units (200_1 to 200_n) through a single data signal line (300), and the multiple driving units (200_1 to 200_n) are configured in parallel on the single data signal line (300); the backlight control circuit also includes a selection switch unit (500), the common terminal of the selection switch unit (500) is connected to the single data signal line (300) of the main control unit (100), and the multiple selection terminals of the selection switch unit (500) are respectively connected to the data input terminals of the multiple driving units (200_1 to 200_n).

[0185] The main control unit (100) is also configured to: output a switch control signal to the selection switch unit (500) to control multiple selection terminals to alternately conduct with the common terminal in different time segments; and output a timing signal containing address data sub-packets and brightness data sub-packets corresponding to each time segment to a single data signal line (300), such that in each time segment, the timing signal is transmitted through the selection switch unit (500) to a drive unit connected to the currently conducting selection terminal.

[0186] The backlight control circuit refers to an electronic circuit system used in a display device to drive and control an array of light-emitting devices to achieve local brightness adjustment. It includes at least a main control unit (100), multiple driving units (200_1 to 200_n), data signal lines (300) connecting the main control unit (100) and the driving units (200_1 to 200_n), and light-emitting devices (400). In some embodiments, the backlight control circuit is applied to a direct-lit LCD TV backlight module with local dimming functionality.

[0187] Among them, the main control unit (100) refers to the central processing and control component in the backlight control circuit. It is usually an integrated circuit that is responsible for generating and outputting control data (i.e., control data signals) for controlling all driving units. The control data includes at least brightness control instructions and may include instructions such as addressing and status query.

[0188] In some embodiments, the main control unit (100) may be a main control integrated circuit in a liquid crystal display device, which typically integrates an image processing engine, a timing controller, and a backlight management module. In other embodiments, it may be a dedicated microcontroller or programmable logic device for backlight control.

[0189] The main control unit (100) can calculate the ideal brightness values ​​required for each backlight zone of the display panel based on the input image data, and then generate corresponding control data (such as brightness control data). This brightness control data, along with necessary control instructions, is encoded into a specific communication protocol format and output through its output pins. The output signal is typically a digital signal, possibly in single-ended or differential form. For example, the main control unit (100) receives brightness distribution information of a frame of image from the upstream video processing module, maps it to specific backlight zones using an internal algorithm, and calculates a grayscale control value of 0 to 255 levels for each zone. Then, the main control unit (100) packages these grayscale values, along with the address information of the target driving unit, into a data packet conforming to a preset communication protocol (such as SPI, I2C, or a custom serial protocol). In other embodiments, the main control unit (100) may not directly process the image, but instead receive and forward brightness instructions from an external processor.

[0190] The main control unit (100) is connected to other component units via data signal lines (300) in a unidirectional or bidirectional manner. For example, one or more data output pins of the main control unit (100) are connected to subsequent circuit nodes via data signal lines (300) formed by PCB (Printed Circuit Board) traces or flexible circuit boards. In unidirectional control scenarios, the data signal lines (300) are used only to send data from the main control unit (100) to the drive units (200_1 to 200_n). In scenarios requiring status readback, the data signal lines (300) must support bidirectional communication, and the corresponding pins of the main control unit (100) must be configured as bidirectional input / output ports, or the data transmission direction must be switched via additional direction control signals. In other embodiments, additional control signal lines may also exist between the main control unit (100) and the drive units (200_1 to 200_n) for transmitting clock, enable, or reset signals.

[0191] The main control unit (100) operates as follows: At the beginning of each display frame cycle, the main control unit (100) initiates the backlight control process. S101: The internal timing generator or processor core of the main control unit (100) generates the corresponding raw control data set according to the target brightness of each backlight partition in the current frame. S102: The protocol processing module of the main control unit (100) encodes and packages the raw control data set according to the preset communication protocol format. If a time-division multiplexing access mechanism is used, the packaging process needs to generate independent address data sub-packets and brightness data sub-packets for each target driving unit (200_1 to 200_n) and arrange them in the access order. If a broadcast addressing mechanism is used, the packaging process generates a complete data packet containing the target logical address and the corresponding brightness data. S103: The driving circuit of the main control unit (100) drives the packaged serial data stream to the data signal line (300) with a specific voltage level and timing. S104: After data transmission is completed or at a specific time, if it is necessary to read back the status of the drive unit, the main control unit (100) switches the transmission direction of the data signal line (300) (if bidirectional communication is supported) and sends a status query command, and then waits for and receives response data from the drive units (200_1 to 200_n). This signal (i.e., the response data) is used to monitor the health status of the backlight system or to perform closed-loop dimming control.

[0192] The internal signal processing, particularly the algorithmic or signal conversion processing, and the internal processing flow or mechanism, are as follows: The image mapping algorithm within the main control unit (100) converts the spatial brightness information of the input image onto a two-dimensional grid of the backlight partition. This algorithm may involve downsampling, filtering, and compensation calculations to determine the optimal drive value for each partition. The protocol packaging process involves converting digital brightness values ​​into binary sequences and adding synchronization headers, address fields, data fields, and check fields. For the time-sharing mechanism, a scheduling module is also required to determine the access time slice for each drive unit and control the generation of the switch control signal.

[0193] The main control unit sends control data to multiple drive units via a single data signal line. The main control unit is connected to multiple drive units via this single data signal line, and the drive units are configured in parallel on the single data signal line. The main control unit is also configured to: output switch control signals to a selection switch unit to control multiple selection terminals to alternately connect to a common terminal within different time segments; and output timing signals containing address data sub-packets and brightness data sub-packets corresponding to each time segment to the single data signal line.

[0194] Unlike other similar technologies (or existing technologies), the main control unit (100) in this solution is configured to generate control logic that matches the parallel topology, whether it is time-division selected switch control signals and timing sub-packets, or broadcast-addressed addressable data packets. In other similar technologies (or existing technologies), the main control unit is usually configured to generate a single data stream for sequential transmission suitable for serial links, which does not contain or contains very little independent addressing information to distinguish different physical branches, or relies on the sequential position on the link for addressing. Therefore, the two are fundamentally different in their control signal generation mechanisms. Consequently, this solution enables the main control unit to drive a physically parallel load network and ensure the independence and quality of signal transmission, avoiding signal attenuation and fault propagation in serial topologies.

[0195] The driving unit (200_1 to 200_n) refers to a circuit module that receives control data from the main control unit (100) and generates driving current or voltage according to the control data to control the luminous brightness of one or more light-emitting devices (400). In some embodiments, one driving unit can drive multiple light-emitting devices connected in series or in parallel.

[0196] In some embodiments, the driving unit (200, taking 200_1 as an example) can be a constant current driving integrated circuit specifically for driving LEDs, commonly referred to as a Driver IC. Internally, it includes a serial communication interface, data latch, decoding logic, and a constant current source output channel. In other embodiments, it can also be a driving circuit built with discrete components, but integrated ICs are the mainstream form.

[0197] The driving unit (200_1) can parse the received serial data to extract commands controlling its output channel, thereby adjusting the current flowing through the connected light-emitting device to control its brightness. It is used to convert digital brightness commands into analog driving current. Exemplarily, the driving unit (200_1) has a data input pin, a clock pin (if required by the protocol), and multiple constant current output pins. It receives serial data from the main control unit (100) or an upstream driving unit through the data input pin. Internal shift registers and latches convert the serial data into parallel data in coordination with the clock. The decoding logic determines whether the data belongs to this unit based on the address information in the data. If it does, it controls the corresponding pulse width modulator or digital-to-analog converter according to the value of the brightness data field, adjusting the duty cycle or amplitude of the constant current source's output current, thereby changing the LED brightness. In other embodiments, the driving unit (200_1) may also employ a voltage-driven mode.

[0198] In this design, the driving unit (200_1) receives control signals at its data input terminal via a data signal line (300) or a branch thereof. Its multiple output terminals are connected to one or more light-emitting devices (400). In the prior art of serial architecture, the driving unit (200_1) may also have a data output terminal for forwarding the received and processed data signal to the next serially connected driving unit. For example, within a branch, multiple driving units (200_1, 200_2…) may still be connected in series to save wiring within that branch; that is, the data output of 200_1 is connected to the data input of 200_2, and so on. In the parallel architecture of this solution, the data input terminals of the first driving unit in different branches are connected in parallel, jointly connected to the output of the main control unit (100) or the selection switch unit. In other embodiments, all driving units may also be connected in parallel.

[0199] The operating sequence of the driver unit (200_1) is as follows: S201: Power-on initialization. The driver unit (200_1) is powered on and reset, performing internal register configuration and status detection. In embodiments employing a hardware encoding scheme, this stage includes detecting the status of its hardware encoding identification unit to determine its own branch and basic logical address, and possibly assigning addresses to subsequent units within the branch. S202: Communication and data reception. The driver unit (200_1) continuously listens to its data input terminal. When a valid communication start condition (such as a specific synchronization header) is detected, it begins receiving the serial data stream. S203: Data parsing and address matching. The driver unit (200_1) parses the received data packets. If the data packet uses broadcast addressing and contains a destination address field, the driver unit (200_1) compares the destination address with its stored logical address. If the addresses match, or in a time-division multiplexing scheme where address matching is not required (data is directly sent to the correct branch), step S204 is executed; otherwise, the data packet is ignored or passed to subsequent units (when serially connected within a branch). S204: Instruction Execution and Drive Output. The drive unit (200_1) updates the control register of the corresponding output channel according to the brightness data field in the data packet, thereby immediately or in the next refresh cycle changing the output of the constant current source and adjusting the LED brightness. S205: Status Response (Optional). When the main control unit (100) initiates a status readback and the drive unit (200_1) is addressed, the drive unit (200_1) organizes the data in its internal status registers (such as temperature, open / short circuit flags, brightness readback values, etc.) into a response data packet, and after the data transmission direction is reversed, drives it to the data signal line and sends it back to the main control unit (100). This signal (i.e., the response data packet) is used to realize the system's monitoring and feedback control.

[0200] Specifically, regarding the driving unit, the internal signal processing, especially the algorithms or signal conversion processes, and the internal processing flow or mechanism, is as follows: Address matching is typically achieved through a digital comparator. The conversion from brightness data to driving current may involve mapping digital values ​​to PWM (Pulse Width Modulation) duty cycles via a lookup table, or generating a reference voltage to control the constant current source via a DAC (Digital-to-Analog Converter). The constant current source typically consists of an operational amplifier, a feedback resistor, and a power transistor to ensure that the load current does not fluctuate with changes in the LED forward voltage.

[0201] Each driving unit is used to drive at least one light-emitting device, such as driving one or more light-emitting devices.

[0202] In this solution, the driving unit (200) differs from other similar technologies (or existing technologies) in that, in some key embodiments, it is endowed with the ability to self-identify and assign addresses based on hardware physical states, or is designed to operate in a physically parallel topology. Its data input is directly or via a switch connected to the main control signal source, rather than being connected in series from the previous driving unit. In contrast, in the serial architecture of other similar technologies (or existing technologies), the driving unit typically lacks self-addressing functionality based on hardware coding. Its address is either externally configured or determined by its physical position order on the serial link, and its signal input depends on the output of the preceding driving unit. Therefore, there are significant differences in initialization behavior, address determination mechanism, and coupling relationship with the system topology. Consequently, the driving unit in this solution can adapt to parallel topologies, achieving more reliable signal reception and fault isolation.

[0203] Among them, the data signal line (300) refers to the physical wire or conductive trace used to transmit control data signals between the main control unit (100) and the drive unit. Its electrical characteristics (such as impedance and capacitance) will affect the signal transmission quality.

[0204] In some embodiments, the data signal line (300) can be a copper wire trace on a printed circuit board, the width and spacing of which are designed according to impedance control and current carrying capacity. In other embodiments, it can be a conductor in a flexible printed circuit or a wire in a cable.

[0205] The data signal line (300) can be a conductive path that transmits electrical signals generated by the main control unit (100) to one or more drive units (200). It is used to carry digitized control data. Example: On a PCB, a continuous conductive path extends from the DATA_OUT pin of the main control unit (100), passes through the board to the backlight module connector, then through the connector to the light strip or light board, and finally connects to the input terminals of each drive unit (200), forming the data signal line (300). Its characteristic impedance needs to be matched with the interfaces of the driver and receiver to reduce reflections. In other embodiments, differential pairs (such as DATA+ and DATA-) may be used for high-speed or long-distance transmission.

[0206] The relationship between the data signal line (300) and other components is as follows: one end of the data signal line (300) is connected to the data output terminal of the main control unit (100), and the other end (or after passing through an intermediate node) is connected to the data input terminal of the drive unit (200). In the parallel topology, the data signal line (300) may branch at a certain node (such as the common terminal of the selector switch unit, or a transition board node), forming multiple branches that lead to different drive branches.

[0207] The operating sequence of the data signal line (300) is as follows: As a passive transmission medium, the data signal line (300) does not operate actively but transmits voltage changes applied to it. S301: When the main control unit (100) drives its output pin, it switches the pin voltage to a low or high level according to the logic '0' or '1' to be sent. S302: This voltage change propagates along the data signal line (300) in the form of an electromagnetic wave, and the propagation speed depends on the dielectric constant of the surrounding medium. S303: The voltage waveform reaches the input pin of the drive unit (200) and is sampled and decoded by the receiving circuit. If there are branches and impedance discontinuities, signal reflection may occur, which needs to be considered in the design. This signal is used to transmit control information to the drive unit (200).

[0208] The internal signal processing of the data signal line (300) is as follows: The transmission behavior of the data signal line (300) can be described by transmission line theory, involving signal rise / fall time, propagation delay, impedance matching, etc.

[0209] Unlike other similar technologies (or existing technologies), in the parallel configuration of this scheme, the path length of the data signal line (300) or its branches to each drive unit (200) is usually designed to be shorter and more balanced (especially when using a radial layout). Furthermore, due to the parallel connection, the load capacitance of each branch is relatively independent and does not accumulate as in series. In the series configuration of other similar technologies (or existing technologies), the same data signal line needs to pass through all drive units sequentially, resulting in a long path, and the input capacitance of each drive unit is superimposed in series on this long path, leading to heavy load at the end and poor signal integrity. Therefore, the signal quality carried by the data signal line (300) in this scheme exhibits significantly reduced attenuation and distortion when transmitted to each terminal, providing a physical basis for reliable communication.

[0210] The light-emitting device (400) can be a light-emitting diode, specifically a white LED, Mini-LED, or Micro-LED. In other embodiments, it can also be other types of solid-state light-emitting devices, such as organic light-emitting diodes. The light-emitting device (400) can convert electrical energy into light energy based on the driving current provided by the driving unit (200). It is used to provide backlight illumination for the liquid crystal display panel. Example: Each light-emitting device (400) is an LED chip, whose anode and cathode are connected to the constant current output channel of the driving unit (200) and the power ground, respectively. When the driving unit (200) turns on the channel, a constant current flows through the LED, causing it to emit light. The brightness is controlled by adjusting the PWM duty cycle or amplitude of the current. In other embodiments, multiple LEDs may be connected in series or parallel together as a light-emitting unit, controlled by a single driving channel.

[0211] The relationship between the light-emitting device (400) and other components is as follows: its electrical connection is entirely controlled by the output channel of the connected driving unit (200). Multiple light-emitting devices (400) may be arranged in an array to form the light source part of the backlight module. Its optical characteristics (such as light emission angle and uniformity) are also affected by components such as light guide plates and optical films.

[0212] The operating sequence of the light-emitting device (400) is as follows: The light-emitting device (400) is a passively controlled element. Its operating timing depends entirely on the electrical signal applied to its two ends by the driving unit (200). S401: At the beginning of the control cycle of the driving unit (200), the driving unit (200) generates a PWM signal with a corresponding duty cycle or a current of a specific amplitude according to the received brightness data. S402: The electrical signal is applied to the light-emitting device (400). S403: Driven by the electrical signal, the light-emitting device (400) emits light during power-on and extinguishes or maintains low brightness during power-off (depending on the driving method). The average brightness is proportional to the effective value or duty cycle of the electrical signal. The light signal is used to penetrate the liquid crystal layer to form the backlight of the image that is finally seen. The internal signal processing of the light-emitting device (400) is as follows: The internal electroluminescence physical process of the light-emitting device (400) is a semiconductor PN junction, without digital processing flow.

[0213] In some embodiments, multiple light-emitting devices (400) are connected in series within a single drive branch. This means they share the same drive current. The advantage is high current consistency, but this requires the drive unit (200) to provide a sufficiently high output voltage to overcome the sum of the forward voltage drops of all the LEDs connected in series. For example, if each LED has a forward voltage drop of 3V, 12 LEDs connected in series would require a drive voltage of at least 36V. The constant current source of the drive unit (200) needs to be adapted to this voltage range. This connection method simplifies the wiring within the branch.

[0214] In this solution, the light-emitting device (400) differs from other similar technologies (or existing technologies) in that, due to the improved topology and control obtained by the driving unit (200) to achieve a higher quality driving signal, the light-emitting device (400) can obtain a more accurate and stable driving current, especially for those light-emitting devices located at the end of the series topology that might otherwise suffer from poor driving due to signal attenuation. In other similar technologies (or existing technologies), the end light-emitting devices may suffer from inaccurate brightness control, flickering, or response delay due to signal distortion. Therefore, although the physical properties of the light-emitting devices themselves are the same, their operating conditions (driving signal quality) are fundamentally improved in this solution, thereby enabling the entire backlight system to achieve a more uniform and accurate brightness control effect.

[0215] The address data sub-packet refers to a specific data sequence in the timing signal output by the main control unit (100) that is used to identify or determine the logical address of the target driving unit. Specifically, it includes the address bits of the driving unit, which are used to specify some driving units, or some or all driving units in the driving branch.

[0216] Among them, the brightness data sub-packet refers to a specific data sequence in the timing signal output by the main control unit (100) used to control the brightness information of the target light-emitting device, specifically including the target brightness information of the light-emitting device connected to the driving unit.

[0217] The selection switch unit (500) refers to an analog switch integrated circuit with one common terminal and multiple selection terminals. It selects the common terminal to be connected to one of the selection terminals through a digital control signal, such as an analog multiplexer. The common terminal is used to connect to the single data signal line (300) of the main control unit (100); each selection terminal is connected to the data input terminal of a drive unit or the drive branch where the drive unit is located.

[0218] In some embodiments, the selection switch unit (500) can be an integrated analog multiplexer integrated circuit. Its package type may be SOP, TSSOP, or QFN, etc. In other embodiments, it can be composed of multiple independent single-pole single-throw analog switch chips or transistor switch arrays.

[0219] The selection switch unit (500) can be a channel selector based on digital control signals. Based on the level combination of the received switch control signals, it electrically connects its common terminal (COM) to one and only one of a plurality of selection terminals (S1, S2, ... SN). The output signal on the selected terminal is consistent with the signal on the common terminal. For example, a 4-channel analog multiplexer (such as a 74HC4052 or similar functional device) internally contains an analog switch matrix and decoding logic. When the control terminal inputs a binary code "00", the internal switch connects channel 0 (corresponding to S1) to the common terminal; when "01" is input, channel 1 (corresponding to S2) is connected, and so on. In other embodiments, the selection switch unit (500) can also implement a multiplexed-to-one selection function, but in this scheme it is configured as a one-to-multiple allocation mode.

[0220] The relationship between the selection switch unit (500) and other components is as follows: its common terminal is connected to the data output of the main control unit (100) via a data signal line (300) or its branch. Its multiple selection terminals are connected to the data input terminals of the first-end drive units (200_1) of different drive branches via their respective branch data lines (300_1, 300_2, ...). Its control terminals (e.g., A, B) are connected to the general purpose input / output pins of the main control unit (100) via control signal lines (501, 502). For example, the DATA_OUT pin of the main control unit (100) is connected to the COM pin of the selection switch unit (500). The S1 pin of the selection switch unit (500) is connected to the DIN pin of the first driver IC on Lane 1, the S2 pin is connected to the DIN pin of the first driver IC on Lane 2, and so on. The GPIO1 and GPIO2 pins of the main control unit (100) are connected to the address control pins A and B of the selection switch unit (500), respectively.

[0221] During the operation of the selection switch unit (500), it receives a switch control signal from the main control unit (100) for switching signal paths. Throughout the period when the switch control signal level is stable and valid, internal decoding and physical on / off operations of the analog switch are performed. Then, the data signal applied by the main control unit (100) to the common terminal is transmitted almost losslessly to the currently selected terminal. This signal is used to transmit control data to a specific drive branch. For example, S501: The selection switch unit (500) continuously monitors the levels on its control pins A and B. S502: When the level changes from (1,0) to (1,1), the internal decoder recognizes the new code. S503: The control logic of the internal analog switch (such as a CMOS transmission gate) corresponding to the code (1,1) is activated, the switch changes from a high-impedance state to an on state, and the previously on switch is turned off. S504: The data signal is transmitted from the COM terminal to the S4 terminal through the on switch. The entire handover process has a finite setup time (Ton).

[0222] The selection switch unit (500) handles the internal signal processing, particularly the algorithm or signal conversion, and its internal processing flow or mechanism as follows: The core of the selection switch unit (500) is an analog switch array. After level conversion and decoding, the digital control signal generates the voltage driving the gates of each analog switch. An analog switch is essentially a voltage-controlled variable resistor. When the control voltage is active, the on-resistance (Ron) between the source and drain is very low, typically a few ohms to tens of ohms; when the control voltage is inactive, the on-resistance is extremely high, reaching megaohms. When a signal passes through, no active amplification or logic processing is performed except for the introduction of a small on-resistance and parasitic capacitance, aiming to achieve transparent signal transmission.

[0223] In some embodiments, the selection switch unit (500) is specifically implemented as an analog multiplexer. For example, a 16-channel analog multiplexer (such as ADG726) is used. It has 4 binary address lines (A0-A3) that can select one of 16 channels. The main control unit (100) uses 4 GPIO pins to output a 4-bit address code. The address code "0000" selects channel 0 corresponding to Lane 1, "0001" corresponds to Lane 2, ..., "1111" corresponds to Lane 16. This allows the system to be easily expanded to control 16 independent backlight drive branches. All switching and decoding logic is integrated internally in the analog multiplexer, simplifying the peripheral circuitry.

[0224] In other embodiments, the selection switch unit (500) consists of multiple independent analog switches. For example, four single-channel SPST analog switches (such as TS5A23157) are used. The control terminal of each switch is independently controlled by a GPIO pin of the main control unit (100). The software logic of the main control unit (100) ensures that at any given time, at most one GPIO outputs a high level (or a low level, depending on the switch enable logic) to turn on the corresponding switch, while the other switches are turned off. This approach provides greater wiring flexibility, as the switches can be distributed close to their respective drive branches, but requires more control lines.

[0225] The difference between the selection switch unit (500) and other similar technologies (or existing technologies) in this solution is that the selection switch unit (500) is introduced into the signal path between the main control unit (100) and multiple drive units (200), acting as an active and controlled signal routing node. In contrast, in the serial architecture of other similar technologies (or existing technologies), there is no such centralized routing switch. The signal path is fixed and serial, with the drive units acting as signal repeaters in sequence. Therefore, there is a fundamental difference in the controllability and dynamism of the signal path between the two. Furthermore, this solution, through the selection switch unit (500), enables multiplexing access of a single physical signal to multiple independent load branches in the time dimension, physically cutting off the cumulative path of signal attenuation and the transmission path of faults.

[0226] Parallel configuration refers to a circuit connection in which the data input terminals of multiple electronic components (such as drive units) are connected to the same signal node, or they share the same signal source through an equivalent switching network. The components are in parallel with respect to the signal source in the electrical path, rather than being connected in series.

[0227] The control data can refer to timing signals containing address data sub-packets and luminance data sub-packets corresponding to each time segment. A complete time period can be divided into multiple time segments, each with corresponding address data sub-packets and luminance data sub-packets, used to control the drive units in the corresponding drive branch.

[0228] The switch control signal is used by the selection switch unit (500) to control multiple selection terminals to alternately conduct with the common terminal in different time segments. Specifically, it controls the multiple selection terminals to alternately conduct with the common terminal in different time segments within a complete time period. For example, within the same complete time period, only the first selection terminal conducts with the common terminal in the first time segment; only the second selection terminal conducts with the common terminal in the second time segment; only the third selection terminal conducts with the common terminal in the third time segment; and only the fourth selection terminal conducts with the common terminal in the fourth time segment. Each time segment is provided with a corresponding switch control signal, so that the corresponding selection terminal conducts with the common terminal in the corresponding time segment, thereby enabling the addressing data sub-packet and brightness data sub-packet of the corresponding time segment to be transmitted to a driving unit or driving branch connected to the corresponding conducting selection terminal.

[0229] The timing signal includes address data sub-packets and luminance data sub-packets corresponding to each time segment. Within each time segment, the main control unit (100) outputs address data sub-packets and luminance data sub-packets corresponding to each time segment to a single data signal line (300), so that the address data sub-packets and luminance data sub-packets corresponding to each time segment are transmitted through the selection switch unit (500) to a driving unit or a driving branch connected to the corresponding active selection terminal.

[0230] Specifically, refer to Figure 18 The main control unit (100) analyzes and processes the received input image to obtain the brightness requirement information of the light-emitting device (400) controlled by each driving unit. Based on the brightness requirement information of the light-emitting device (400) controlled by each driving unit, the sub-brightness data signal of each driving unit is obtained. Based on the sub-brightness data signal of each driving unit, the addressing data sub-packet and brightness data sub-packet corresponding to each time segment within a time period are obtained. Alternatively, the main control unit (100) directly obtains the addressing data sub-packet and brightness data sub-packet corresponding to each time segment within a time period. Then, the main control unit (100) sends the addressing data sub-packet and brightness data sub-packet corresponding to each time segment to the selection switch unit (500) through a single data signal line (300), and sends the switch control signal corresponding to each time segment to the selection switch unit (500). The selection switch unit (500) controls multiple selection terminals to alternately connect to the common terminal in different time segments based on the switch control signal corresponding to each time segment. In each time segment, it sends the address data sub-packet and brightness data sub-packet corresponding to each time segment to a driving unit or driving branch connected to the corresponding connected selection terminal. Each driving unit in the driving branch determines whether it needs to participate in the control based on the received address data sub-packet and brightness data sub-packet, and identifies the sub-brightness data signal corresponding to its own address bit. Then, it converts it into a backlight driving signal and uses the backlight driving signal to independently control the light emission state of the corresponding light-emitting device (400), such as increasing the light emission brightness of the corresponding light-emitting device (400) to a specified brightness to match the display of the input image.

[0231] For example, see reference. Figure 18In the first time segment of a complete time cycle, the main control unit (100) sends the address data sub-packet and brightness data sub-packet corresponding to the first time segment to the selection switch unit (500), and sends the switch control signal corresponding to the first time segment to the selection switch unit (500). Based on the switch control signal corresponding to the first time segment, the selection switch unit (500) controls the analog switch S1 to open and the other analog switches to close, so that the selection terminal connected to the input terminal of the drive branch 1 is connected to the common terminal. Then, the address data sub-packet and brightness data sub-packet corresponding to the first time segment are sent to the drive branch 1 through the connected selection terminal. The drive unit in the drive branch 1 determines whether it needs to participate in the control from the received address data sub-packet and brightness data sub-packet, and identifies the sub-brightness data signal corresponding to its own address bit. Then, it converts it into a backlight drive signal and uses the backlight drive signal to independently control the light emission state of the corresponding light-emitting device (400). In the first time segment, the main control unit (100) sends the address data sub-packet and brightness data sub-packet corresponding to the second time segment to the selection switch unit (500), and sends the switch control signal corresponding to the second time segment to the selection switch unit (500); the selection switch unit (500) controls the analog switch S2 to open and the other analog switches to close based on the switch control signal corresponding to the second time segment, so that the selection terminal connected to the input terminal of the drive branch 2 is connected to the common terminal. Then, the address data sub-packet and brightness data sub-packet corresponding to the second time segment are sent to the drive branch 2 through the connected selection terminal; the drive unit in the drive branch 2 determines whether it needs to participate in the control from the received address data sub-packet and brightness data sub-packet, and identifies the sub-brightness data signal corresponding to its own address bit, and then converts it into a backlight drive signal, and uses the backlight drive signal to independently control the light emission state of the corresponding light-emitting device (400); and so on, until the address data sub-packet and brightness data sub-packet corresponding to the nth time segment are sent to the drive branch n.

[0232] In this embodiment, the conventional thinking that "simplified wiring must be achieved by sharing signal paths in series" is broken. This solution cleverly utilizes the condition of selecting the switching unit to allocate the path of a single data signal in the time dimension. It adopts time-division conduction and data sub-packet matching techniques to solve the technical problem of ensuring that the signal path of each drive unit is independent and the load is single while maintaining low wiring complexity at the main control end. This achieves the technical effect of avoiding the cumulative attenuation and distortion of the signal on the long link and eliminating the failure of all subsequent units due to the failure of a single link.

[0233] In some embodiments, the switch control signal includes at least a first control signal line and a second control signal line, and the selection switch unit is used to determine the currently active selection terminal based on the level combination of the first control signal line and the second control signal line.

[0234] The first control signal line is used to transmit control signal A, which has a value of 0 or 1. The first control signal line is also used to transmit control signal B, which has a value of 0 or 1.

[0235] The level combinations of the first control signal line and the second control signal line include: (0,0), (0,1), (1,0), and (1,1). (0,0) indicates that the first selection terminal is connected to the common terminal, that is, the currently connected selection terminal is the first selection terminal; (0,1) indicates that the second selection terminal is connected to the common terminal, that is, the currently connected selection terminal is the second selection terminal; (1,0) indicates that the third selection terminal is connected to the common terminal, that is, the currently connected selection terminal is the third selection terminal; and (1,1) indicates that the fourth selection terminal is connected to the common terminal, that is, the currently connected selection terminal is the fourth selection terminal.

[0236] Specifically, the main control unit (100) generates the switch control signal as follows: the internal state machine generates the corresponding binary code based on the index of the drive unit or drive branch to be accessed. For example, to control four branches, two binary bits are required (control signals A and B). When the index is 0, output (0, 0); when the index is 1, output (0, 1); when the index is 2, output (1, 0); when the index is 3, output (1, 1). These signals are output to the control terminal of the select switch unit through dedicated general-purpose input / output pins. At the same time, the data packetization module must ensure that during the time segment of the output (0, 0) signal, the data transmitted on the data signal line is the data packet of the drive unit corresponding to index 0. In other embodiments, the generation of the switch control signal can also be accomplished by an independent counter or decoder circuit.

[0237] In this embodiment, since the conduction path is uniquely determined by the level combination of at least two control signal lines, the problem of accurately selecting multiple selection terminals with the least amount of control line resources is solved, thereby simplifying the control logic and reducing the pin requirements of the main control unit.

[0238] In some embodiments, the switch control signal consists of N control signal lines to uniquely select 2. N There are 1 selection endpoints; where N is a positive integer greater than or equal to 1.

[0239] Each control signal line transmits a control signal, and each control signal has a value of either 0 or 1. N control signal lines correspond to N bits of binary code, which in turn correspond to 2... NThere are two selection options, corresponding to 2 N One drive branch.

[0240] Specifically, assuming there are three control signal lines, when the binary code is (0, 0, 0), it indicates that the first selection terminal is connected to the common terminal, and the first driving branch can receive the corresponding address data sub-packet and brightness data sub-packet. When the binary code is (0, 0, 1), it indicates that the second selection terminal is connected to the common terminal, and the second driving branch can receive the corresponding address data sub-packet and brightness data sub-packet. When the binary code is (0, 1, 0), it indicates that the first selection terminal is connected to the common terminal, and the third driving branch can receive the corresponding address data sub-packet and brightness data sub-packet, and so on. When the binary code is (1, 1, 1), it indicates that the eighth selection terminal is connected to the common terminal, and the eighth driving branch can receive the corresponding address data sub-packet and brightness data sub-packet.

[0241] In this embodiment, N control lines are used to encode and select 2. N The extended architecture of the path solves the scalability problem of linearly increasing the number of control lines as the number of drive units increases, thereby achieving the effect of managing exponentially growing drive paths using logarithmically growing control resources.

[0242] In some embodiments, the selection switch unit includes an analog multiplexer.

[0243] Among them, the selection switch unit can refer to an analog multiplexer; the analog multiplexer refers to an analog switch integrated circuit that includes a common terminal and multiple selection terminals. It selects to connect the common terminal to one of the selection terminals through digital control signals. Its specific function is the same as that of the selection switch unit, and will not be described in detail here.

[0244] In this embodiment, by using an integrated analog multiplexer as the selection switch unit, the circuit complexity and synchronization control problems caused by the need for multiple discrete switches to work together are solved, thereby achieving the effects of improving circuit integration, simplifying layout and wiring, and control timing.

[0245] In some embodiments, the selection switch unit includes a switch array consisting of a plurality of independently controlled analog switches.

[0246] The selection switch unit can refer to a switch array; the switch array includes multiple independently controlled analog switches, each of which is used to connect the corresponding selection terminal to the common terminal. The specific function is the same as that of the selection switch unit, and will not be described in detail here.

[0247] In this embodiment, the use of independently controlled analog switch arrays solves the problem of flexibility requirements for switch unit topology, thereby allowing non-standard multi-choice topologies or distributed layouts to adapt to different PCB design constraints.

[0248] In some embodiments, the master control unit is configured to address and write luminance data to each drive unit at least once during a complete cycle of the output timing signal.

[0249] Within a complete cycle of the output timing signal, each driving unit in the driving branch is addressed and written with luminance data once in the corresponding time segment to control the light emission state of its connected light-emitting device. For example, in the first time segment of a complete time cycle, each driving unit in driving branch 1 is addressed and written with luminance data at least once; in the second time segment of a complete time cycle, each driving unit in driving branch 2 is addressed and written with luminance data at least once, and so on, until the nth time segment of a complete time cycle, where each driving unit in driving branch n is addressed and written with luminance data at least once.

[0250] In this embodiment, since the main control unit completes the polling control of all driving units within a complete cycle, the problem of ensuring the synchronization and consistency of the refresh rate of all light-emitting zones is solved, thereby avoiding asynchronous updates of different partition screens due to time-sharing access, and thus achieving the effect of uniform visual performance.

[0251] In some embodiments, in the timing signal output by the main control unit to the single data signal line, the address data sub-packets and the brightness data sub-packets are arranged in a preset fixed order corresponding to each driving unit.

[0252] The addressing data sub-packets are arranged in a preset, fixed order corresponding to each driving unit, such as (address bit 1, address bit 2, ..., address bit N), so that the driving unit can identify its own data without complex protocol parsing.

[0253] Among them, the brightness data sub-packets are arranged in a preset fixed order corresponding to each driving unit, such as (brightness data 1, brightness data 2...brightness data N), so that the driving unit side can identify its own data without having to go through complex protocol parsing.

[0254] In this embodiment, by using a fixed order of data packets, the problem of the driver unit being able to identify its own data without complex protocol parsing is solved, thereby simplifying the logic design of the driver unit and reducing its power consumption and cost.

[0255] In some embodiments, the main control unit is further configured to: when it is necessary to read the status of the drive unit, control the data transmission direction of the single data signal line to reverse, and control the selection switch unit to turn on each selection terminal in a time-division manner, so as to read the status data returned by each drive unit in sequence.

[0256] Among them, the drive unit status is used to reflect the unit status of each drive unit, specifically the working status, such as the power supply voltage being too low or too high.

[0257] Specifically, when it is necessary to read the status of the driving unit, the main control unit reverses the data transmission direction of the single data signal line and controls the selection switch unit to make multiple selection terminals alternately connected to the common terminal in different time segments. In each time segment, the driving unit or driving branch connected to the currently connected selection terminal returns the driving unit status to the main control unit through the selection switch unit. The main control unit then reads the status data returned by each driving unit in sequence. For example, the main control unit parses the driving unit status to obtain the specific status data of each driving unit. Based on the specific status data of each driving unit, the main control unit determines the target power supply voltage of each driving unit and finally allocates the corresponding target power supply voltage to each driving unit to accurately control the luminous brightness of the corresponding light-emitting device.

[0258] In this embodiment, the use of direction reversal combined with time-division selection for status readback solves the problem of reusing the same data signal line to achieve bidirectional communication in a parallel topology, thereby achieving the effect of system status monitoring and diagnosis without adding extra signal lines.

[0259] In some embodiments, the driving unit is configured to drive its internal state data onto a single data signal line when its corresponding selection terminal is turned on and the data transmission direction is reversed.

[0260] Specifically, when the corresponding selection terminal of the drive unit in the drive branch is turned on and the data transmission direction is reversed, the drive unit acquires its internal status data and sends its internal status data to the single-channel data signal line through the selection switch unit. Then, it is transmitted to the main control unit through the single-channel data signal line. Finally, the main control unit reads the status data returned by each drive unit in sequence.

[0261] In this embodiment, since the driving unit drives the bus only under specific conditions (selection and reverse direction), the problem of bus conflict caused by the output competition of multiple driving units is solved, thereby ensuring the accuracy and reliability of the status readback data.

[0262] In some embodiments, the backlight control circuit is applied to a liquid crystal display device, the driving unit is a Driver IC for driving LEDs, and the light-emitting device is an LED.

[0263] Among them, the driving unit refers to the driver IC used to drive the light-emitting device (such as LED) connected to it, such as the driver IC.

[0264] In this embodiment, since it is specifically applied to the backlight driving scenario of liquid crystal display, the problem of anchoring a general parallel control scheme to a specific technical field is solved, thereby achieving the effect of more clearly defining the background of this application and the application scenarios of distinctive features.

[0265] In some embodiments, each driving unit is connected in series to multiple light-emitting devices on its branch.

[0266] Each driving unit is connected in series with one or more light-emitting devices, such as five light-emitting devices.

[0267] In this embodiment, since the driving unit drives multiple light-emitting devices in series, the problem of controlling multiple LEDs with a single driving channel to improve utilization and simplify cascade wiring is solved, and the typical connection relationship between the driving unit and the load is further defined.

[0268] In some embodiments, different time segments are divided by the main control unit according to a periodic clock signal generated by an internal timing generator, and each time segment corresponds to the access cycle of a drive unit.

[0269] The main control unit divides the time into multiple different time segments based on the periodic clock signal (i.e., the complete cycle) generated by an internal timing generator. Each time segment corresponds to the access cycle of a drive unit or drive branch.

[0270] Specifically, the main control unit (100) has an internal reference clock. Assuming the communication baud rate is 1MHz and each drive unit needs to transmit 256 bits of data, each time segment can be set to no less than 256 microseconds. The scheduling module of the main control unit (100) generates a time slice enable signal based on this clock to control the switching of the switch control signal and data transmission.

[0271] In this embodiment, by adopting periodic time segmentation based on an internal timing generator, the timing reference and synchronization problem of multiple driving units accessing the system in a time-sharing manner is solved, thereby ensuring strict synchronization between signal switching and data packet transmission and avoiding timing chaos.

[0272] In some embodiments, when switching time segments, the master control unit inserts a preset delay between the change of the switch control signal and the transmission of the corresponding sub-packet in the timing signal.

[0273] Specifically, after switching the switch control signal from (0,0) to (0,1), a fixed delay time, such as 100 nanoseconds, is waited to ensure that the analog switch is fully and stably conducting to the new branch before sending the next data sub-packet. This delay time needs to be determined based on the switching time (Ton / Toff) of the selected analog switch; for details, please refer to [reference needed]. Figure 8 .

[0274] In this embodiment, by inserting a preset delay between the control signal switching and the data transmission, the problem of errors caused by data transmission during the transient instability that may occur during the physical switching of the switching unit is solved, thereby improving the stability and reliability of signal transmission.

[0275] In some embodiments, the addressing data sub-packet in the timing signal includes a branch identifier code for indicating the target driving branch.

[0276] Among them, the branch identification code refers to the unique identification information of the driving branch, which is used to indicate the corresponding target driving branch.

[0277] Specifically, even with time-division multiplexing, to enhance the robustness of the protocol and the versatility of the driver units, a "Lane ID" field is still included in the data packet sent to a specific driver branch. Upon receiving data, the driver unit on that branch verifies whether this ID matches its own driver branch (this matching relationship may be set through other methods, such as hardwiring or configuration registers), thus providing double verification to prevent data write errors caused by switch malfunctions or timing discrepancies. Furthermore, if the driver unit on that branch identifies that the ID matches its own driver branch, it reads the corresponding address data sub-packet and brightness data sub-packet.

[0278] In this embodiment, by introducing a tributary identifier code into the addressing data sub-packet, the problem of providing a clear logical address identifier for the driver unit is solved even under a time-division multiplexing architecture, thereby enhancing protocol compatibility and driver unit identifiability.

[0279] In some embodiments, the master control unit is configured to dynamically adjust the duration of a time segment based on the total number of multiple drive units and the communication baud rate.

[0280] In serial communication, the communication baud rate refers to the number of symbol (signal state) changes transmitted per unit time (per second), and the unit is baud.

[0281] Specifically, the main control unit queries the correspondence between the driving unit, the communication baud rate, and the duration of the time segment based on the total number of multiple driving units and the communication baud rate, and obtains the duration of the corresponding time segment.

[0282] In this embodiment, since the time segment can be dynamically adjusted according to the number of driving units and the baud rate, the problem of balancing refresh rate and signal stability under different system configurations is solved, thereby achieving the effect of optimizing system performance adaptability.

[0283] In some embodiments, the backlight control circuit further includes a signal buffer unit disposed between the single-channel data signal line output terminal of the main control unit and the common terminal of the selection switch unit.

[0284] Among them, a signal buffer unit is set between the single-channel data signal line output terminal of the main control unit and the common terminal of the selection switch unit; the signal buffer unit refers to a functional module composed of a buffer, a driver, or an integrated circuit or discrete device with signal amplification / drive enhancement function. Its core function is to enhance signal driving capability, improve load capacity, and improve signal quality.

[0285] For example, a signal buffer unit can refer to a bus buffer or line driver integrated circuit. Its input is connected to the output of the main control unit (100), and its output is connected to the common terminal of the selection switch unit. This buffer provides high current drive capability and low output impedance, enabling it to better drive any subsequent capacitive loads (such as the input capacitance of multiple analog switches and PCB parasitic capacitance), helping to maintain steep signal edges and reduce signal degradation due to overload.

[0286] In this embodiment, by adding a signal buffer unit in the signal path, the problem of insufficient signal driving capability that may be caused by long-distance transmission or high-load switching is solved, thereby achieving the effect of further improving signal quality and enhancing system load capacity.

[0287] In some embodiments, the selection switch unit is integrated with multiple drive units on the same printed circuit board.

[0288] The selection switch unit and multiple drive units can be integrated on the same PCB.

[0289] In this embodiment, by integrating the selection switch unit and the drive unit on the same PCB, the problems of additional parasitic parameters and signal integrity introduced by the connection of discrete modules are solved, thereby simplifying the system structure and improving the overall reliability.

[0290] In some embodiments, the light-emitting device is a light-emitting diode, and the driving unit is a constant current driving integrated circuit.

[0291] Among them, the driving unit refers to the constant current driving integrated circuit that drives the connected light-emitting diode.

[0292] Specifically,

[0293] In this embodiment, since the driving object is clearly defined as the LED and its constant current driving IC, the specific load type and driving method of this application are further limited, thereby achieving the effect of anchoring the technical field and clarifying the signal distribution problem solved by this application in a specific scenario.

[0294] In some embodiments, such as Figure 19 As shown, this application also provides another backlight control circuit (using a hardware coding broadcast mechanism), including: multiple driving branches, each driving branch including at least one driving unit (200) connected in series for driving at least one light-emitting device (400); a main control unit (100) sends control data to multiple driving branches through a data signal line; wherein, the main control unit (100) is simultaneously connected to the data input terminal of the first driving unit of each of the multiple driving branches through a single data signal line (300) to form a broadcast connection topology, and the first driving unit of each driving branch is provided with a hardware coding identification unit (600), and the hardware coding identification units (600) of the first driving units of different driving branches are configured to have different hardware coding states.

[0295] The driver unit (200) is configured to: detect the hardware coding status of the hardware coding identification unit of its branch during power-on initialization, and allocate a unique logical address range for itself and subsequent driver units in its branch based on the detected hardware coding status.

[0296] The main control unit (100) is configured to output a broadcast signal containing a target logical address and brightness data to a single data signal line, and the drive unit matches the target logical address in the broadcast signal with its own address and responds with the matched brightness data.

[0297] Each driving branch (i.e., driving circuit assembly) includes a driving unit (i.e., driving circuit, such as DriverIC), or multiple driving units connected in series. Each driving unit is used to drive the light-emitting state of one or more light-emitting devices (400) connected to it.

[0298] Among them, the control data sent by the main control unit (100) to multiple drive branches through the data signal line can refer to a broadcast signal containing the target logical address and brightness data.

[0299] Specifically, the main control unit (100) is connected to the data input terminal of the first drive unit of each of the multiple drive branches through a single data signal line (300) and an adapter board (800).

[0300] The first-end driver unit of a driver branch refers to the first driver unit in that driver branch. Each first-end driver unit is equipped with a hardware encoding recognition unit (600) and an address self-allocation logic module (700).

[0301] The hardware coding state refers to the electrical state preset for an electronic component (such as a drive unit) through a physical connection method (such as connection to a specific voltage, grounding, or floating) to characterize its identity or category. For example, it may be connected to a first voltage (VCC), a second voltage (1.5V), grounding, or floating, and these states are all different. The hardware coding identification unit (600) of the first-end drive unit of the drive branch is configured to be connected to the first voltage (VCC), indicating that the drive branch is drive branch 1; the hardware coding identification unit (600) of the first-end drive unit of the drive branch is configured to be grounded, indicating that the drive branch is drive branch 2; the hardware coding identification unit (600) of the first-end drive unit of the drive branch is configured to be connected to the second voltage (1.5V), indicating that the drive branch is drive branch 3.

[0302] The first-end driver unit of a drive branch, during power-on initialization, allocates a unique logical address range to itself and subsequent driver units within its branch based on the hardware encoding status of the hardware encoding identification unit of that branch. This range could be (1 to N), (0 to P), (Q to R), or (S to T). For example, when the DIP signal of the first-end driver unit is detected to be connected to the VCC signal, it is determined that the first-end driver unit is the first driver unit of the first lane drive branch, addressed as 1, and so on sequentially until the last driver unit is addressed as N.

[0303] The target logical address refers to the address bits of the driving unit that needs to be referenced for control, used to specify the target driving unit participating in the control. The brightness data refers to the brightness data of the target driving unit participating in the control, used to control the luminous brightness of its connected light-emitting devices.

[0304] The broadcast signal contains a target logical address and brightness data, i.e., its signal format is target logical address + brightness data; specifically, it can include the target logical address and brightness data of the driving unit in one driving branch, or it can include the target logical address and brightness data of the driving units in all driving branches.

[0305] In some embodiments, the hardware encoding recognition unit detection process of the driver unit (200_1) is as follows: a dedicated encoding pin (DIP) is connected to a specific potential via an external circuit or directly. After the encoding pin is powered on, the analog-to-digital converter or voltage comparator inside the driver unit (200_1) measures its voltage; the measured value is compared with several preset threshold voltage ranges. For example, threshold one is set to 70% of the power supply voltage VCC, and threshold two is set to 30% of VCC. If the voltage is higher than threshold one, it is determined to be connected to VCC (state one); if the voltage is lower than threshold two, it is determined to be connected to GND (state two); if the voltage is between threshold one and threshold two, it is determined to be connected to an intermediate voltage such as 1.5V (state three); if the voltage is in a high-impedance state (measured by pull-up / pull-down resistors), it is determined to be floating (state four). Based on the determination result, the firmware of the driver unit (200_1) marks itself as Lane 1, Lane 2, Lane 3, or Lane 4.

[0306] In some embodiments, the hardware encoding identification unit (600) is not a separate integrated circuit, but a functional unit composed of a dedicated pin (DIP) of the driver unit (200_1) and its external connection circuit. The external circuit can be a simple pull-up resistor, pull-down resistor, resistor divider network, or a direct connection to the power supply, ground, or a specific voltage source.

[0307] The hardware encoding identification unit (600) can be a physical identification circuit. Based on its externally connected fixed electrical network, it provides a stable and detectable analog or digital voltage signal to the drive unit (200_1) upon power-up. It outputs a voltage value characterizing a specific hardware encoding state to the internal detection circuit of the drive unit (200_1). Exemplarily, the DIP pin of the drive unit (200_1) is connected to a power supply (VCC, such as 3.3V) via a 0-ohm resistor or directly. This represents hardware encoding state one. In other embodiments, the pin can also be pulled down to ground (GND) via a 10kΩ resistor, representing state two.

[0308] The hardware encoding and recognition unit (600) is related to other components as follows: its core is the connection between the encoding pin of the driver unit (200_1) and an external fixed potential point. This connection is usually determined during circuit board assembly by soldering or using a zero-ohm resistor jumper, and is a hardware configuration that cannot be changed during system operation. It does not have dynamic signal interaction with other units; its function is only to be sampled once by the driver unit (200_1) during the system power-on initialization phase.

[0309] The hardware encoding identification unit (600) is activated only during system power-on or hard reset. After detecting stable power supply, the power management or initialization logic inside the driver unit (200_1) applies a weak test current to the encoding pin or activates an internal ADC to sample the pin voltage. Then, the firmware or hardware logic of the driver unit (200_1) compares the sampled voltage value with several internally preset threshold voltage ranges. Finally, it outputs a digitized encoding identifier (e.g., a 2-bit binary number 00, 01, 10, 11) to the address allocation logic module of the driver unit (200_1). This signal uniquely identifies the driver unit (200_1) and its logical identity within the entire branch in the system.

[0310] The hardware encoding and recognition unit (600) handles the internal signal processing, especially the algorithm or signal conversion processing, and the internal processing flow or mechanism as follows: The driver unit (200_1) typically integrates a multi-channel analog-to-digital converter or several voltage comparators. The voltage of the encoding pin is connected to one input channel of the ADC. The ADC performs a conversion on this channel during initialization to obtain a digital value. Several threshold ranges are preset in the firmware. For example, if the ADC full scale is 3.3V, a value greater than 1020 (corresponding to approximately 3.2V) can be determined as connected to VCC; a value less than 100 (corresponding to approximately 0.1V) can be determined as connected to GND; a value between 450 and 550 (corresponding to approximately 1.45V-1.65V) can be determined as connected to 1.5V; if the value drifts or is in an unexpected intermediate value, it may be judged as floating or connected to a specific resistor.

[0311] Unlike other similar technologies (or existing technologies), the hardware coding identification unit (600) in this solution is integrated into the entry driver unit of each parallel branch as a static, hardware-based identity module, providing a distributed, self-identifying physical identity mechanism for the system. In other similar technologies (or existing technologies), whether in series or multi-channel independent signal control, the driver unit typically lacks this identity identification mechanism based on dedicated pin hardware connections to distinguish different physical groups. Its address is either configured by the main control unit through software or implicitly determined by its physical location in the communication link (such as the series order). Therefore, there is a fundamental difference between the two in terms of the autonomy and determinism of identity recognition and address allocation. Furthermore, this solution enables each driver unit to autonomously determine its globally unique logical address upon power-up in a physically parallel broadcast topology, without requiring complex individual configuration by the main control unit. This achieves plug-and-play functionality and automatic system topology discovery, simplifying production and maintenance processes.

[0312] In some embodiments, the driver unit also integrates an address self-allocation logic module (700), which can also be called the driver unit address self-allocation logic module. This is a functional logic module implemented by the firmware or hardware state machine inside the driver unit (200), and is not an independent physical component. However, it is crucial for understanding Scheme 2, and therefore is described as a logic sub-unit.

[0313] The address self-allocation logic module (700) can be a processor that calculates and allocates addresses based on the initial hardware coding state. Based on the coding identifier obtained from the hardware coding identification unit (600), it executes a predefined address mapping algorithm. The output is the logical address allocated to the driver unit itself, and (for the branch head unit) the address space range calculated for the branch it belongs to. For example, in the microcontroller firmware of the driver unit (200_1), there is a startup code section specifically responsible for address allocation. In other embodiments, it can also be implemented using dedicated hardware logic (such as state machines and registers).

[0314] The address self-assignment logic module (700) is related to the other components as follows: as part of the internal logic of the driver unit (200), it receives the sampling results (encoding identifiers) of the hardware encoding recognition unit (600) from the internal ADC or comparator. It may interact with non-volatile memory (such as EEPROM) to store or read addresses. It is also connected to the communication interface logic of the driver unit (200) to provide its finally determined address to the address matching comparator.

[0315] The address self-allocation logic module (700) operates as follows, taking the branch head driver unit (200_1) as an example: S701: After power-on reset, it obtains the encoding identifier Code_X (e.g., 00, 01, 10, 11) from the hardware encoding recognition unit (600). S702: According to the predefined mapping rules, it converts Code_X into a base logical address Base_Addr. For example, the mapping rules are: 00 -> 0x00; 01 -> 0x40; 10 -> 0x80; 11 -> 0xC0. This means that the base addresses of different branches are separated by 64 address units. S703: It assigns Base_Addr to its own logical address register. S704: If this driver unit is the first in the branch, it may need to notify the subsequent serially connected driver units (200_2, 200_3…) in this branch to start address allocation in some way (e.g., through a specific serial communication protocol). A common approach is that after the first unit completes its own addressing, it sends an address allocation instruction containing Base_Addr+1 to the next unit in the link via its data output pin. Upon receiving this instruction, the next unit sets its own address to Base_Addr+1 and continues to pass Base_Addr+2 to the next unit, and so on, until the end of the branch. S705: Optionally, the final allocated address is written to non-volatile memory for direct reading upon the next power-on.

[0316] The address self-allocation logic module (700) handles the internal signal processing, particularly the algorithm or signal conversion during the process, as well as the internal processing flow or mechanism. The mapping rule can be a simple lookup table. The address passing mechanism may rely on existing serial data paths between driver units. For example, in initialization mode, the first unit (200_1) can send a special "address increment" pulse sequence or data packet through its DOUT pin. Subsequent units, upon receiving a pulse or a specific instruction, increment an internal address counter and set that value to their own address. This requires the driver units to support this initialization protocol.

[0317] The address self-allocation logic module (700) differs from other similar technologies (or existing technologies) in that address allocation in this solution is a parallel and autonomous process completed by each drive branch, starting from the physical coding of the hardware. In other similar technologies (or existing technologies), address allocation is usually a serial configuration process dominated by the main control unit (such as sending address setting commands sequentially on the serial link), or it relies on manual settings such as external DIP switches. Therefore, there are significant differences between the two in terms of system-level concurrency, automation level, and dependence on the main control unit in address allocation. Consequently, this solution greatly simplifies the system initialization process, improves assembly and production efficiency, and enhances the system's adaptability to topology changes (such as replacing a light strip).

[0318] Specifically, refer to Figure 19 During power-on initialization, the first-end driver unit in each driver branch detects the hardware coding status of the hardware coding identification unit of its branch. For example, it measures the voltage signal value connected to the coding pin (DIP) in the first-end driver unit and compares it with several preset threshold voltage ranges. If the connected voltage signal value is the first voltage (VCC), the hardware coding status of the hardware coding identification unit is confirmed to be connected to the first voltage; if the connected voltage signal value is the second voltage (1.5V), the hardware coding status of the hardware coding identification unit is confirmed to be connected to the second voltage. Then, based on the hardware coding status of the hardware coding identification unit, the correspondence between the hardware coding status and the logical address range is queried. For example, if connected to the first voltage, the corresponding logical address range is (1 to N), such as the logical address range of the driver unit in driver branch 1 (1 to N); if grounded, the corresponding logical address range is (0 to P), such as the logical address range of the driver unit in driver branch 1 (0 to P). The logical address range corresponding to the driving unit in 2 is (0 to P); if connected to the second voltage, the corresponding logical address range is (Q to R), such as the logical address range corresponding to the driving unit in driving branch 3 is (Q to R); if floating, the corresponding logical address range is (S to T), such as the logical address range corresponding to the driving unit in driving branch n is (S to T). Then, according to the corresponding logical address range, a unique logical address range is allocated to itself and the subsequent driving units in its branch. For example, for the logical address range (1 to N), the first driving unit in the first driving branch sets its address bit (Base_Addr) to 1 and sends an address allocation instruction containing Base_Addr+1 to the next driving unit on the link through its data output pin; after receiving it, the next driving unit sets its own address to Base_Addr+1 (i.e., 2) and continues to pass Base_Addr+2 to the next driving unit, and so on, until the end of the driving branch.

[0319] Furthermore, after address allocation is completed, the main control unit (100) analyzes and processes the received input image to obtain the brightness requirement information of the light-emitting device (400) controlled by each driving unit. Based on the brightness requirement information of the light-emitting device (400) controlled by each driving unit, it obtains the brightness data of each driving unit; it acquires the target logical address of each driving unit, and generates a broadcast signal containing the target logical address and brightness data based on the target logical address and brightness data of each driving unit, or it directly acquires the broadcast signal containing the target logical address and brightness data without analyzing the input image; Then, the main control unit (100) outputs a broadcast signal containing the target logical address and brightness data to a single data signal line. The broadcast signal is transmitted to each driving branch through the adapter board. The driving unit in each driving branch matches the target logical address in the broadcast signal with its own address. If the match is successful, it obtains the brightness data that matches its own address from the brightness data and then converts it into a backlight driving signal. The backlight driving signal is used to independently control the light emission state of the corresponding light-emitting device (400). For example, the light emission brightness of the corresponding light-emitting device (400) is increased to a specified brightness to match the display of the input image.

[0320] For example, see reference. Figure 19 The main control unit (100) sends a broadcast signal containing the target logical address and brightness data to the adapter board (800) through a single data signal line. The adapter board (800) sends the broadcast signal to each driving branch. The driving unit in each driving branch matches the target logical address in the broadcast signal with its own address and responds to the matched brightness data. For example, the driving unit 1 in driving branch 1 matches the target logical address in the broadcast signal with its own address and responds to the matched brightness data, controls the brightness of the light-emitting device (400) connected to the driving unit 1, and transmits the broadcast signal to the driving unit 2 in driving branch 1. The driving unit 2 in driving branch 1 matches the target logical address in the broadcast signal with its own address and responds to the matched brightness data, controls the brightness of the light-emitting device (400) connected to the driving unit 2, and transmits the broadcast signal to the driving unit 3 in driving branch 1. This continues until the broadcast signal is transmitted to the driving unit N in driving branch 1.

[0321] In this embodiment, the conventional thinking that "simplified wiring must be achieved by sharing signal paths in series" is broken. This solution cleverly utilizes the condition of assigning different hardware coding states to the first unit of each branch under a physical parallel topology. It adopts the technical means of power-on self-identification and allocation of independent logical address segments accordingly. This solves the technical problem of ensuring that each drive unit can be uniquely addressed and accurately respond to commands while maintaining low wiring complexity at the master control end and signal broadcast transmission. In this way, all drive units can directly obtain the original signal without attenuation from the master control end and achieve the technical effect of fault isolation between physical branches.

[0322] In some embodiments, the hardware encoding state is manifested as the hardware encoding recognition unit being connected to a first voltage, connected to a second voltage, grounded, or floating.

[0323] The number of hardware coding states can be multiple, such as the hardware coding recognition unit being connected to the first voltage (VCC), the hardware coding recognition unit being connected to the second voltage (1.5V), the hardware coding recognition unit being grounded, or the hardware coding recognition unit being left floating.

[0324] Different hardware encoding states correspond to different logical address ranges.

[0325] In this embodiment, by using a simple and reliable hardware connection to different voltages or to be left floating to define the encoding state, the problem of branch identity differentiation without complex encoding circuits is solved, thereby achieving the effect of low cost and easy configuration and identification in production.

[0326] In some embodiments, the value of the second voltage is between the first voltage and the ground potential.

[0327] The second voltage can have multiple values, such as 1.5V, 1.4V, 1.3V, etc., to expand multiple drive branches.

[0328] In this embodiment, by using an intermediate voltage between the power supply and ground as one of the encoding states, the problem of adding more recognizable encoding states beyond the limited pin states (high, low, floating) is solved, thereby achieving the effect of expanding the number of supported drive branches with a small increase in cost.

[0329] In some embodiments, the value of the second voltage is a preset threshold voltage, and the driving unit is provided with a comparator to compare the voltage on the hardware encoding recognition unit with a reference voltage in order to identify the hardware encoding state.

[0330] The reference voltage can include multiple thresholds, such as 70% of the power supply voltage VCC, 30% of VCC, etc.

[0331] The comparator inside the driver unit compares the voltage on the hardware code recognition unit with a reference voltage. Based on the comparison result, it determines the magnitude of the voltage on the hardware code recognition unit, and thus determines the hardware code status of the hardware code recognition unit. For example, if the reference voltage is set to 70% of the power supply voltage VCC, and the voltage on the hardware code recognition unit is greater than 70% of the power supply voltage VCC, then the hardware code status of the hardware code recognition unit is determined to be connected to VCC.

[0332] For example, the reference voltage is set to 1.25V and 0.4V. When the voltage on the encoding pin is greater than 1.25V, it is identified as a high level (VCC); when it is less than 0.4V, it is identified as a low level (GND); and when it is between 0.4V and 1.25V, it is identified as an intermediate level (1.5V). If it cannot be stabilized in any of these ranges, it may be judged as floating or faulty.

[0333] In this embodiment, by using a comparator to identify the intermediate voltage threshold, the problem of accurately distinguishing the intermediate voltage from the power supply voltage or ground potential is solved, thereby improving the robustness and anti-interference ability of the encoded state recognition.

[0334] In some embodiments, the hardware encoding recognition unit includes a resistor network connected between the encoding pin of the driving unit and different potentials. Different resistor voltage division values ​​characterize different hardware encoding states, thereby expanding the driving branch and avoiding the shortcomings of a single intermediate voltage limitation.

[0335] The driver unit encoding pin is a DIP.

[0336] The different hardware coding identification units include resistor networks connected between the coding pins of the driving unit and different potentials, so that the coding pins of the driving unit are at different resistor voltage values, thus representing different hardware coding states. For example, the hardware coding identification unit in the first-end driving unit of driving branch 1 includes a resistor network connected between the coding pin of the first-end driving unit and the potential VCC, indicating that the hardware coding state is connected to VCC; the hardware coding identification unit in the first-end driving unit of driving branch 2 includes a resistor network connected between the coding pin of the first-end driving unit and the potential GND, indicating that the hardware coding state is connected to GND; the hardware coding identification unit in the first-end driving unit of driving branch 3 includes a resistor network connected between the coding pin of the first-end driving unit and the potential 1.5V, indicating that the hardware coding state is connected to 1.5V.

[0337] Specifically, the hardware encoding and identification unit (600) is implemented by connecting to different potentials. For example, in a system with four drive branches, the DIP pins of the first Driver IC for each branch on the adapter board or LED strip PCB are designed with different connection methods: the DIP of Lane 1 is connected to VCC (3.3V) through a 0-ohm resistor. The DIP of Lane 2 is connected to GND through a 0-ohm resistor. The DIP of Lane 3 is connected to 1.5V (which can be generated by an LDO regulator) through a voltage divider resistor network. The DIP of Lane 4 is kept floating (NC) and pulled to a certain level internally by a weak pull-up resistor, but not externally connected, leaving it in a floating high-impedance state. This design is extremely low-cost, requiring only changes to the traces or jumpers on the PCB.

[0338] Specifically, to support more branches, the hardware encoding and recognition unit (600) can employ a resistor network voltage divider. For example, a voltage divider circuit containing two fixed resistors can be designed for the encoding pin, connected between VCC and GND. By selecting resistors R1 and R2 with different values, different voltage division values ​​V_dip = VCC × R2 / (R1 + R2) can be generated on the encoding pin. The ADC inside the driver unit (200_1) has sufficient accuracy to distinguish these different voltage division values. Assuming VCC = 3.3V, R1 and R2 can be designed so that V_dip is 0.5V, 1.0V, 1.5V, 2.0V, 2.5V, etc., thereby encoding more states. The resistor accuracy can be selected as 1% to ensure recognition reliability.

[0339] In this embodiment, by using a resistor network to divide the voltage to generate multiple encoding voltages, the problem of limited encoding quantity when using a single intermediate voltage is solved. This achieves the effect of enabling more branch identity encoding by selecting different resistance value combinations, thereby improving the system's scalability.

[0340] In some embodiments, the logical address range allocated based on the hardware coding state is continuous and the branches do not overlap.

[0341] The logical address range allocated to each hardware coding state is continuous, and the logical address ranges corresponding to each driving branch are non-overlapping; for example, the logical address range corresponding to driving branch 1 is (1, 2, 3...N), the logical address range corresponding to driving branch 2 is (0, 0+1, 0+2...P), and the logical address range corresponding to driving branch 3 is (Q, Q+1, Q+2...R).

[0342] In this embodiment, by allocating continuous and non-overlapping logical address ranges, the problem of ensuring that each driver unit has a unique identifier in the global address space is solved, thereby enabling the main control unit to access any driver unit using a unified and simple address addressing protocol.

[0343] In some embodiments, the driving unit is configured such that: the first driving unit determines its own basic logic address based on the detected hardware coding state, and allocates the address of each driving unit connected in series thereafter by incrementing the address by a predetermined step.

[0344] Different hardware coding states correspond to different basic logic addresses; for example, if the hardware coding state is connected to VCC, the corresponding basic logic address is 1; if the hardware coding state is connected to GND, the corresponding basic logic address is 0; if the hardware coding state is connected to 1.5V, the corresponding basic logic address is Q.

[0345] The predetermined step size can be 1.

[0346] Specifically, assume the system has 4 branches, each with 8 cascaded drive units. The hardware encoding mapping is based on the following addresses: Lane 1: 0x00; Lane 2: 0x08; Lane 3: 0x10; Lane 4: 0x18 (the interval is set to 8, which is greater than or equal to the maximum number of units per branch, ensuring that the address space does not overlap). The first unit of Lane 1 (200_1) detects that the encoding is connected to VCC (state 00) and sets its own address to 0x00. Then it notifies the second drive unit through the internal cascaded link, the second drive unit sets its own address to 0x01, and notifies the third drive unit to set it to 0x02, ..., the eighth drive unit's address is 0x07. The first unit of Lane 2 detects that the encoding is connected to GND (state 01) and sets its own address to 0x08, and its subsequent unit addresses are 0x09 to 0x0F respectively. Ultimately, all 32 driver units in the system obtain globally unique addresses: 0x00-0x07, 0x08-0x0F, 0x10-0x17, and 0x18-0x1F. The master control unit (100) is aware of this mapping rule and can precisely control any driver unit by simply setting the target address to a value between 0x00 and 0x1F when sending data packets.

[0347] In this embodiment, by adopting the allocation rule of determining the base address of the first unit and incrementing it sequentially for subsequent units, the problem of automatic address allocation of multiple drive units within the branch is solved, thereby simplifying the address configuration logic of the drive unit and supporting the effect of "plug and play" expansion.

[0348] In some embodiments, the main control unit is further configured to: when it is necessary to read the status of the drive unit, control the data transmission direction of the single data signal line to reverse, and sequentially send a status read instruction containing its logical address to each drive unit, so as to receive the status data returned by each drive unit in the order of its logical address.

[0349] The drive unit status is used to reflect the working status of each drive unit, such as low power supply voltage or high power supply voltage.

[0350] The status read instruction includes the logical address of the driver unit to be read, so as to accurately read the unit status of the corresponding driver unit.

[0351] Specifically, when it is necessary to read the status of the driving unit, the main control unit reverses the data transmission direction of the single data signal line and sends status read instructions containing their logical addresses to each driving unit sequentially through the adapter board. Each driving unit obtains the corresponding driving unit status according to the corresponding status read instruction and returns the corresponding driving unit status to the main control unit in the order of its logical address through the adapter board. This allows the main control unit to receive the status data returned by each driving unit in the order of its logical address. For example, the main control unit parses the driving unit status to obtain the specific status data of each driving unit. Based on the specific status data of each driving unit, it determines the target power supply voltage of each driving unit and allocates the corresponding target power supply voltage to each driving unit to accurately control the luminous brightness of the corresponding light-emitting device.

[0352] In this embodiment, by using direction reversal and combining it with address instructions for status polling, the problem of reading the status of all drive units in an orderly manner without data conflict under a broadcast parallel topology is solved, thereby achieving the effect of reliable system monitoring and diagnosis.

[0353] In some embodiments, the master control unit is configured to send status read instructions in ascending order of logical addresses.

[0354] When the main control unit sends the status read command, it sends it in ascending order of logical address to accurately read the status of each driver unit and avoid the need to distinguish the status of each driver unit.

[0355] Specifically, the main control unit sends status read instructions containing the logical addresses of each driver unit in ascending order of logical addresses via an adapter board; each driver unit obtains the corresponding driver unit status according to the corresponding status read instruction and returns the corresponding driver unit status to the main control unit via the adapter board, so that the main control unit receives the status data returned by each driver unit in the order of its logical addresses.

[0356] In this embodiment, since polling is performed according to address order, the deterministic and predictable problem of status readback timing is solved, thereby simplifying the readback control logic of the main control unit and facilitating correspondence with address allocation rules.

[0357] In some embodiments, the backlight control circuit is applied to a liquid crystal display device, the driving unit is a Driver IC for driving LEDs, and the light-emitting device is an LED.

[0358] In this embodiment, since it is specifically applied to the backlight driving scenario of liquid crystal display, the problem of anchoring a general parallel control scheme to a specific technical field is solved, thereby achieving the effect of more clearly defining the background of this application and the application scenarios of distinctive features.

[0359] In some embodiments, a single data signal line is simultaneously connected to the data input terminal of the first-end drive unit of each drive branch via an adapter board.

[0360] In some embodiments, the adapter board is a separate PCB or connector module, which enables fan-out connections from a single output cable on the main control board (where the main control unit is located) to multiple drive branch input points on the backlight module. Internally, it may contain simple wire connections, or it may include the aforementioned signal buffer unit, ESD protection devices, etc.

[0361] In some embodiments, the adapter board (800) is an optional physical component, as mentioned in Scheme 2, used to realize the physical fan-out connection from a single data signal to a multi-drive branch.

[0362] The adapter board (800) can be a small printed circuit board with conductive lines and connectors. In other embodiments, it can also be a flexible circuit board or a wire harness connector assembly.

[0363] The adapter board (800) can be a signal distribution and hardware coding configuration board. Based on its internal fixed wiring, a single data signal line (300) for the future autonomous control unit (100) can be simultaneously connected to multiple output ports, each output port corresponding to a drive branch. Simultaneously, the board can also integrate a resistor network or jumpers for setting the status of the hardware coding identification unit (600) for each branch. The outputs are multiple physically independent but electrically parallel signal lines connected at the input.

[0364] The adapter board (800) is connected to other components as follows: its input connector receives a single data signal line (300) from the main control unit (100) via a cable. Its multiple output connectors are connected to the data input terminals of the head units of each drive branch via cables. Furthermore, its resistor network or jumpers directly constitute the external circuitry of each branch hardware encoding and identification unit (600).

[0365] During operation, the adapter board (800) is a passive connection component and does not involve dynamic timing. Its function is to complete the physical connection and hardware coding configuration in one go during system assembly. During operation, it simply transmits data signals transparently.

[0366] In some embodiments, the adapter board (800) has the following structure: It has one input interface (e.g., an FPC connector) to receive main control signals from the motherboard. It has four output interfaces (e.g., four FFC connectors) to connect to four LED strips respectively. The board's internal wiring directly connects the input signal lines in parallel to the corresponding pins of the four output interfaces. Simultaneously, different components are soldered onto the data line pins (corresponding to the DIP pins of the driver IC) of each output interface, according to their corresponding Lane number: for Lane 1 output, this pin is connected to 3.3V on the board via a 0-ohm resistor; for Lane 2 output, this pin is connected to GND on the board via a 0-ohm resistor; for Lane 3 output, this pin is connected to a 1.65V node generated by a 1kΩ and 1kΩ resistor divider on 3.3V; for Lane 4 output, this pin is not connected to any components and is left floating. Thus, when each LED strip is connected to the adapter board, the DIP pin of its first Driver IC is automatically configured with the corresponding hardware coding state.

[0367] Unlike other similar technologies (or existing technologies), the adapter board (800) in this solution, in addition to performing the conventional function of signal fan-out, also integrates a key configuration circuit for hardware identification encoding of each parallel branch. In other similar technologies (or existing technologies) with multiple independent signals, multiple adapter boards or complex wiring may be required to distribute multiple independent signals; in series schemes, such fan-out adapter boards are not needed, and signals are transmitted sequentially. Therefore, the adapter board (800) in this solution becomes the key physical carrier for realizing the innovative architecture of "single-channel signal broadcasting + hardware encoding". It centralizes the system-level encoding configuration from the scattered light strip design to a single board, which is beneficial for standardization and production management.

[0368] In this embodiment, the physical fan-out connection from single to multiple channels is achieved through the adapter board, thereby solving the problem of reliable physical interconnection between the output pins of the main control unit and the input terminals of multiple drive branches, thus achieving the effect of facilitating PCB layout and routing and improving the convenience of production and assembly.

[0369] In some embodiments, the hardware encoding recognition unit includes a dedicated encoding pin of the driving unit, and different hardware encoding states are achieved by connecting the dedicated encoding pin to different fixed potentials or by connecting it to a fixed potential through a resistor.

[0370] The hardware encoding recognition unit includes a dedicated encoding pin (DIP) of the driver unit. By connecting the dedicated encoding pin to different fixed potentials (such as VCC, GND, 1.5V, 2.5V, etc.), the dedicated encoding pin is at different voltage values, thereby realizing different hardware encoding states.

[0371] The hardware encoding recognition unit includes a dedicated encoding pin (DIP) of the driver unit. By connecting the dedicated encoding pin to different fixed potentials (such as VCC, GND, 1.5V, 2.5V, etc.) through a resistor, the dedicated encoding pin is at different voltage values, thereby realizing different hardware encoding states.

[0372] In this embodiment, by using dedicated encoding pins to connect to different potentials to achieve encoding, the problem of how to achieve hardware identification without affecting the function of data communication pins is solved, thereby achieving the effect of simple circuit design and stable encoding state.

[0373] In some embodiments, the fixed potential includes the power supply voltage, the ground potential, and one or more intermediate potentials generated by resistor voltage division.

[0374] The number of fixed potentials is multiple, including power supply voltage, ground potential, and one or more intermediate potentials generated by resistor voltage division (such as 1.6V, 1.7V, 1.8V, etc.), thereby realizing different hardware encoding states and expanding multiple drive branches; that is, the dedicated encoding pin (DIP) of the first drive unit in each drive branch is connected to the corresponding fixed potential. If the number of fixed potentials is M, then the number of drive branches is M.

[0375] In this embodiment, by incorporating the intermediate potential into the encoding potential selection, the problem of excessive limitation on the number of codes due to relying solely on power and ground potentials is solved, thereby achieving the effect of implementing more encoding states on a single pin and supporting more driving branches.

[0376] In some embodiments, the drive unit is configured to store the allocation result in a non-volatile memory after completing the logical address allocation during the power-on initialization phase.

[0377] Non-volatile memory can refer to registers.

[0378] Specifically, the drive unit (200_1) integrates a one-time programmable memory or an electrically erasable memory. After successfully completing the address self-allocation for the first time, it writes its calculated logical address into this memory. Upon subsequent power-ups, the stored address can be directly read without re-executing the detection and allocation process, thereby speeding up the startup process; this is especially important for display devices that require fast response.

[0379] In this embodiment, by storing the allocated logical address in non-volatile memory, the problem of address information loss and re-initialization after power failure is solved, thereby improving system startup speed and operational reliability.

[0380] In some embodiments, the drive unit is further configured to enter a preset fail-safe mode or report an error state when a hardware coding failure or anomaly is detected.

[0381] Entering the preset fault-safe mode means that the drive unit enters a pre-set safe working state to avoid system abnormalities or damage; for example, turning off the current light-emitting device (LED off), outputting a fixed low brightness, stopping the output drive current, remaining silent, not interfering with the bus, resetting its own internal state, etc.

[0382] Entering the error reporting state means that the drive unit feeds back the error state to the main control unit through the adapter board. For example, in the readback timing, it sets its own status to 1 (indicating an abnormality), sends a specific error code (such as check error, encoding error, over-temperature, over-current), and replies to the main control unit with a fixed abnormal identification sequence.

[0383] Specifically, if the driver unit (200_1) cannot classify its encoded pin voltage into any valid state range, it can set an internal error flag and set all its output channels to a safe low-brightness state or completely shut down to prevent unpredictable behavior. Simultaneously, during state readback, this error flag can be reported to the main control unit (100).

[0384] In this embodiment, by setting up a fault handling mechanism for encoding detection failure, the problem of the system failing to start normally or exhibiting uncertain behavior due to poor hardware connection is solved, thereby improving the robustness and maintainability of the system.

[0385] In some embodiments, the master control unit is configured to broadcast an address query instruction to all drive units after system startup in order to obtain all valid logical address mapping relationships in the current system.

[0386] Specifically, after the system starts, the main control unit broadcasts an address query command to all drive units through the adapter board; each drive unit obtains its own logical address according to the address query command, and sends its own logical address to the main control unit through the adapter board. Based on the logical addresses returned by each drive unit, the main control unit obtains all valid logical address mapping relationships in the current system, such as which drive unit corresponds to which logical address.

[0387] In this embodiment, since the main control unit actively queries the address mapping, the problem of the main control unit needing to know or store all driver unit address information in advance is solved, thereby achieving the effect of automatic system discovery and configuration, and enhancing flexibility.

[0388] In some embodiments, the broadcast signal adopts a data packet structure, and each data packet includes a header, a destination address field, a brightness data field, and a check field.

[0389] The packet header refers to the fixed data segment at the very beginning of the data packet, used to identify the start of the data.

[0390] The check field refers to the last segment of data in the data packet. Its function is to verify the integrity of the entire data packet, detect transmission errors, and after the driver IC receives the data, it compares the field it calculates with the check field. If they match, the data is valid; if they do not match, the data is discarded or an error is reported.

[0391] Broadcast signals refer to data packets that include a header, a destination address field, a brightness data field, and a checksum field.

[0392] In this embodiment, by adopting a complete data packet structure that includes a check field, the bit error problem that may occur during broadcast transmission is solved, thereby improving communication reliability and data integrity.

[0393] In some embodiments, a single data signal line uses a differential signal line pair.

[0394] Among them, the differential signal pair refers to a signal line structure consisting of two lines that form a pair to transmit electrical signals of equal magnitude but opposite phase. It is used to resist interference and transmit data over long distances and at high speeds, such as DATA+ and DATA-.

[0395] The main control unit can use differential signal pairs to transmit broadcast signals.

[0396] In this embodiment, differential signal transmission is used, which solves the problem that single-ended signals are susceptible to common-mode noise interference in long-distance broadcast transmission, thereby further improving signal transmission quality and anti-interference capability.

[0397] In some embodiments, multiple drive branches are physically arranged radially from the main control unit or a switching node.

[0398] Among them, multiple drive branches are arranged in a radial shape in terms of physical layout, and are led out from the main control unit or from the adapter node (such as the adapter board) connected to the main control unit.

[0399] In this embodiment, the use of a radial physical layout solves the problem of minimizing the difference in signal path length in actual PCB routing of parallel topologies, thereby achieving a more balanced signal transmission delay for each branch, which is beneficial for timing control.

[0400] In one specific embodiment, this application provides an improved backlight control circuit system. This system includes two core improved branches, corresponding to Scheme 1 (e.g., ...). Figure 18 ) and Option 2 (such as Figure 19 Common foundational components (see reference) Figure 17 The system includes: a main control unit (100), multiple drive units (200, which can be divided into multiple drive branches, each branch containing drive units 200_1, 200_2, ... in series), a data signal line (300), and a light-emitting device (400). In Scheme 1, the core improvement unit is the selection switch unit (500). In Scheme 2, the core improvement is reflected in the hardware encoding and identification unit (600) integrated in the first drive unit (200_1) of each drive branch and the address self-allocation logic module (700) it triggers. The two schemes share the "improved basic association feature": that is, the main control unit (100) is connected to multiple drive units (200) through a single data signal line (300), and these drive units (200) are configured in parallel on the single data signal line, rather than in a traditional series link. The collaborative relationship between the units is as follows: the main control unit (100) acts as the control source and issues global commands through the data signal line (300); in Scheme 1, the selection switch unit (500) acts as the controlled path selector and dynamically guides the main control signal to the target drive branch; in Scheme 2, all drive branches receive broadcast signals at the same time, but through the identity information pre-set by the hardware coding identification unit (600), each drive unit (200) autonomously completes logical addressing and realizes accurate response to commands; finally, all drive units (200) independently control the light-emitting devices (400) connected to them to emit light.

[0401] In some embodiments, the overall signal interaction process of Scheme 1 is as follows: S1000: System power-on initialization. S1001: The main control unit (100) enters the driver unit addressing stage. At this time, the main control unit (100) controls the selection switch unit (500) to sequentially turn on each branch (e.g., first S1, then S2, then S3, and finally S4). When each branch is turned on, the main control unit (100) sends a specific addressing data packet to the branch through the data signal line (300). The addressing data packet may command all Driver ICs on the branch to set their addresses to a sequence starting from 1 (e.g., the first address of each Lane is set to 1). S1002: After addressing is completed, the normal brightness data transmission cycle begins. In each cycle, the scheduling module of the main control unit (100) divides the cycle into N time segments (N is the number of branches). S1003: In the first time segment, the main control unit (100) sets the switch control signal to select the first branch (e.g., A=0, B=0) and sends a sub-packet containing the brightness data of Lane 1 (Data for Lane 1). This data is sent only to the drive unit of Lane 1 through the selection switch unit (500). S1004: In the second time segment, the main control unit (100) switches the switch control signal to select the second branch (A=0, B=1) and sends the brightness data sub-packet of Lane 2. This cycle continues until all branches have sent their data. S1005: After a complete brightness control cycle ends, the main control unit (100) can start the next cycle or enter the status readback stage as needed. S1006: In the status readback stage, the main control unit (100) first switches the drive direction of the data signal line (300) to input (or enables the bidirectional transceiver). Then, it controls the selection switch unit (500) again to time-divisionally activate each branch. When a branch is turned on, the drive unit on that branch drives its status data to the data signal line and sends it back to the main control unit (100) for reading.

[0402] In some embodiments, the overall signal interaction process of Scheme 2 is as follows: S2000: The system is powered on. S2001: All drive branches are powered on simultaneously. The first-end drive unit (200_1) of each branch detects its own encoding status through its hardware encoding recognition unit (600). S2002: Each first-end drive unit executes the address self-allocation logic in parallel according to the detection result, allocating a unique logical address to itself and the subsequent units in its branch. This process is completed entirely within the drive unit or branch, without the intervention of the main control unit. S2003: After the address allocation is completed, each drive unit enters the standby state and listens to the data signal line. S2004: The main control unit (100) starts working. It does not need to know the specific physical location of each drive unit, but only needs to organize the data according to the global address mapping table (which can be preset or obtained by querying in step S2005). The main control unit (100) packages the brightness data to be sent into consecutive data packets according to the format of the target address (Addr_X) and brightness value (PWM_X), and broadcasts them to the data signal line (300). S2005 (optional): The main control unit (100) may first broadcast an address query instruction packet (e.g., the target address is the broadcast address 0xFF). After all the drive units receive it, they send their addresses back to the main control unit in sequence (e.g., starting from address 0x00), so that the main control unit (100) can automatically construct the address topology of the system. S2006: During normal operation, the main control unit (100) sends a data packet for example {Addr: 0x05, PWM: 120}. All drive units on Lane 1 with addresses 0x00-0x07 receive the packet, but only the drive unit with address exactly 0x05 will respond to the brightness data and adjust its PWM output to a duty cycle of 120 / 255. Meanwhile, the driver unit at address 0x08 (belonging to Lane 2) ignores this packet. S2007: During status readback, the master control unit (100) reverses the data direction and sends a status request packet for a specific address (such as {Read_Addr: 0x05}). After receiving it, the driver unit at address 0x05 drives its status data onto the bus and sends it back.

[0403] In some embodiments, user configuration and diagnostic interaction scenarios are described. This backlight control circuit is usually an internal module of the display device and does not directly interact with end users. However, the "use scenarios" of production line engineers or maintenance personnel can be considered. Scenario 1: Production line configuration. The engineer runs a configuration tool through a debugging interface (such as UART or USB) connected to the main control unit (100). The tool interface displays "Backlight Topology Configuration". The engineer selects the "Automatic Scan" button. The tool sends the above address query command (S2005) through the main control unit (100), and then the interface graphically displays the number of detected drive branches (e.g., 4 Lanes) and the number of drive units on each branch (e.g., 8 per Lane), and lists all logical addresses. After the engineer confirms, this configuration is saved to the firmware of the main control unit (100). Scenario 2: Fault diagnosis. The device reports a backlight abnormality. The maintenance personnel open the diagnostic mode, and the interface displays a backlight partition status diagram. A certain partition (corresponding to the drive unit of a specific logical address) in the diagram is displayed as a red alarm. When a maintenance technician clicks on the partition, detailed information pops up: "Address 0x0A, Lane 2 - 3rd IC, Status: Open Circuit Fault." This helps the technician quickly locate the specific faulty light bar and LED. These interactions rely on the status readback capability obtained by the main control unit (100) through Scheme 1 or Scheme 2.

[0404] In some embodiments, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0405] In some embodiments, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0406] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0407] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0408] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0409] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A display device, characterized in that, include: Display screen; At least two drive circuit components connected in parallel; The drive circuit assembly includes: At least two drive circuits connected in series; Backlight assembly; the backlight assembly includes multiple backlight zones, the backlight zones including: Multiple backlights; A connection module; at least two output terminals of the connection module are coupled one-to-one with at least two drive circuit components; The main control circuit is coupled to the input terminals of the display screen and the connection module, respectively, and is configured as follows: Acquire brightness data signals; The brightness data signal is sent to the corresponding driving circuit component through the connection module, so that the driving circuit in the corresponding driving circuit component controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the brightness data signal.

2. The display device according to claim 1, characterized in that, The connection module is an analog multiplexer, which includes: At least two analog switches, wherein the at least two analog switches are coupled one-to-one with the at least two drive circuit components; The main control circuit is coupled to the brightness data signal input terminal and the control signal input terminal of the analog multiplexer, respectively, and is configured as follows: Acquire the target brightness data signal of the driving circuit component and the target analog switch control signal of the driving circuit component; The target brightness data signal and the target analog switch control signal are sent to the analog multiplexer; The analog multiplexer is configured as follows: Control the target analog switch corresponding to the target analog switch control signal to open, and control the non-target analog switch that does not correspond to the target analog switch control signal to close; The target brightness data signal is sent to the corresponding driving circuit component through the target analog switch, so that the driving circuit in the corresponding driving circuit component controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the target brightness data signal.

3. The display device according to claim 2, characterized in that, The main control circuit is further configured as follows: Obtain the address signal of each driving circuit component; The addressing signal is sent to the corresponding drive circuit component through the corresponding analog switch on the analog multiplexer; The first drive circuit in the corresponding drive circuit assembly is configured as follows: Based on the addressing signal, the address bit of the first driving circuit is set to 1; An address increment signal is generated and sent to the next driver circuit of the first driver circuit in the corresponding driver circuit assembly until all address bits of the driver circuits in the corresponding driver circuit assembly have been confirmed.

4. The display device according to claim 2, characterized in that, The target brightness data signal of the driving circuit assembly includes the sub-brightness data signal corresponding to the address bits of the driving circuit in the driving circuit assembly. The drive circuit in the drive circuit assembly is configured as follows: From the target brightness data signal, obtain the sub-brightness data signal corresponding to the address bit of the driving circuit; The brightness of the backlight in the corresponding backlight zone is controlled based on the sub-brightness data signal.

5. The display device according to claim 2, characterized in that, The main control circuit is further configured as follows: Receive the status data signal sent by the corresponding drive circuit component through the target analog switch on the analog multiplexer; The state of the drive circuit in the corresponding drive circuit component is determined by the state data signal.

6. The display device according to claim 1, characterized in that, The connection module is an adapter board; at least two output terminals of the adapter board are coupled one-to-one with the at least two drive circuit components; The main control circuit is coupled to at least two input terminals of the adapter board and is configured as follows: Acquire target brightness data signals for the at least two driving circuit components; The target brightness data signal is sent to the adapter board; The adapter board is configured as follows: The target brightness data signal is forwarded to the driving circuit assembly, so that the driving circuit in the driving circuit assembly controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the target brightness data signal.

7. The display device according to claim 6, characterized in that, The signal input terminal of the first drive circuit in the drive circuit assembly is connected to the corresponding signal terminal on the adapter board. The first drive circuit in the drive circuit assembly is configured as follows: When the main control circuit is powered on, the signal connection status of the signal input terminal of the first drive circuit is detected; When it is detected that the signal input terminal of the first driving circuit is connected to the corresponding signal terminal on the adapter board, the address bit of the first driving circuit is confirmed to a preset value. An address increment signal is generated and sent to the next drive circuit of the first drive circuit in the drive circuit assembly until all address bits of the drive circuits in the drive circuit assembly have been confirmed.

8. A display device, characterized in that, include: Display screen; At least two drive circuit components connected in parallel; The drive circuit assembly includes: At least two drive circuits connected in series; Backlight assembly; the backlight assembly includes multiple backlight zones, the backlight zones including: Multiple backlights; Analog multiplexer; the analog multiplexer includes: At least two analog switches, wherein the at least two analog switches are coupled one-to-one with at least two drive circuit components; The main control circuit is coupled to the brightness data signal input terminal and control signal input terminal of the display screen and the analog multiplexer, respectively, and is configured as follows: Acquire the target brightness data signal of the driving circuit component and the target analog switch control signal of the driving circuit component; The target brightness data signal and the target analog switch control signal are sent to the analog multiplexer; The analog multiplexer is configured as follows: Control the target analog switch corresponding to the target analog switch control signal to open, and control the non-target analog switch that does not correspond to the target analog switch control signal to close; The target brightness data signal is sent to the corresponding driving circuit component through the target analog switch, so that the driving circuit in the corresponding driving circuit component controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the target brightness data signal.

9. A display device, characterized in that, include: Display screen; At least two drive circuit components connected in parallel; The drive circuit assembly includes: At least two drive circuits connected in series; Backlight assembly; the backlight assembly includes multiple backlight zones, the backlight zones including: Multiple backlights; Adapter board; at least two output terminals of the adapter board are coupled one-to-one with at least two drive circuit components; The main control circuit is coupled to at least two input terminals of the display screen and the adapter board, respectively, and is configured as follows: Acquire target brightness data signals for the at least two driving circuit components; The target brightness data signal is sent to the adapter board; The adapter board is configured as follows: The target brightness data signal is forwarded to the driving circuit assembly, so that the driving circuit in the driving circuit assembly controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the target brightness data signal.

10. A backlight control circuit, comprising: Main control unit; Multiple driving units, each driving unit being used to drive at least one light-emitting device; The main control unit sends control data to the plurality of drive units via data signal lines; The main control unit is connected to the plurality of drive units via a single data signal line, and the plurality of drive units are configured in parallel on the single data signal line. The backlight control circuit also includes a selection switch unit. The common terminal of the selection switch unit is connected to the single-channel data signal line of the main control unit, and the multiple selection terminals of the selection switch unit are respectively connected to the data input terminals of the multiple driving units. The main control unit is further configured to: output a switch control signal to the selection switch unit to control the plurality of selection terminals to alternately connect with the common terminal in different time segments; and, A timing signal containing address data sub-packets and luminance data sub-packets corresponding to each time segment is output to the single data signal line, such that within each time segment, the timing signal is transmitted through the selection switch unit to a drive unit connected to the currently active selection terminal.

11. The backlight control circuit according to claim 10, characterized in that, The switch control signal includes at least a first control signal line and a second control signal line. The selection switch unit is used to determine the currently active selection terminal based on the level combination of the first control signal line and the second control signal line.

12. The backlight control circuit according to claim 11, characterized in that, The switch control signal consists of N control signal lines, with one line uniquely selecting 2. N The selection terminals are: N, where N is a positive integer greater than or equal to 1.

13. The backlight control circuit according to claim 10, characterized in that, The selection switch unit includes an analog multiplexer.

14. The backlight control circuit according to claim 10, characterized in that, The selection switch unit includes a switch array consisting of multiple independently controlled analog switches.

15. The backlight control circuit according to claim 10, characterized in that, The main control unit is configured to address and write brightness data to each drive unit at least once during a complete cycle of outputting the timing signal.

16. The backlight control circuit according to claim 15, characterized in that, In the timing signal output by the main control unit to the single data signal line, the address data sub-packet and the brightness data sub-packet are arranged in a preset fixed order corresponding to each of the driving units.

17. The backlight control circuit according to claim 10, characterized in that, The main control unit is also configured to: when it is necessary to read the status of the drive unit, control the data transmission direction of the single data signal line to reverse, and control the selection switch unit to turn on each selection terminal in a time-division manner, so as to read the status data returned by each drive unit in sequence.

18. The backlight control circuit according to claim 17, characterized in that, The driving unit is configured to drive its internal state data to the single data signal line when its corresponding selection terminal is turned on and the data transmission direction is reversed.

19. The backlight control circuit according to claim 10, characterized in that, The backlight control circuit is applied to the liquid crystal display device, the driving unit is a driver IC for driving LEDs, and the light-emitting device is an LED.

20. The backlight control circuit according to claim 19, characterized in that, Each of the driving units is connected in series to multiple light-emitting devices on its branch.

21. The backlight control circuit according to claim 10, characterized in that, The different time segments are divided by the main control unit according to the periodic clock signal generated by an internal timing generator, and each time segment corresponds to an access cycle of the drive unit.

22. The backlight control circuit according to claim 10 or 21, characterized in that, When switching the time segment, the main control unit inserts a preset delay between the change in the switch control signal and the transmission of the corresponding sub-packet in the timing signal.

23. The backlight control circuit according to claim 10, characterized in that, The addressing data sub-packet in the timing signal contains a branch identifier code for indicating the target driving branch.

24. The backlight control circuit according to claim 10, characterized in that, The main control unit is configured to dynamically adjust the duration of the time segment based on the total number of the plurality of drive units and the communication baud rate.

25. The backlight control circuit according to claim 10, characterized in that, The backlight control circuit also includes a signal buffer unit, which is disposed between the single-channel data signal line output terminal of the main control unit and the common terminal of the selection switch unit.

26. The backlight control circuit according to claim 10, characterized in that, The selection switch unit and the plurality of drive units are integrated on the same printed circuit board.

27. The backlight control circuit according to claim 10, characterized in that, The light-emitting device is a light-emitting diode, and the driving unit is a constant current driving integrated circuit.

28. A backlight control circuit, comprising: Main control unit; Multiple driving branches, each driving branch including at least one driving unit connected in series for driving at least one light-emitting device; The main control unit sends control data to the multiple drive branches via data signal lines; The main control unit is simultaneously connected to the data input terminal of the first-end drive unit of each of the multiple drive branches via a single data signal line, forming a broadcast connection topology. Its characteristic is that... Each of the driving branches has a hardware code recognition unit at its head end. The hardware code recognition units of the head end driving units of different driving branches are configured to have different hardware code states. The driving unit is configured to: during power-on initialization, detect the hardware coding status of the hardware coding identification unit of its branch, and based on the detected hardware coding status, allocate a unique logical address range for itself and subsequent driving units in its branch. The main control unit is configured to output a broadcast signal containing a target logical address and brightness data to the single data signal line, and the driving unit matches the target logical address in the broadcast signal with its own address and responds with the matched brightness data.

29. The backlight control circuit according to claim 28, characterized in that, The hardware encoding state is manifested as the hardware encoding recognition unit being connected to a first voltage, connected to a second voltage, grounded, or suspended in the air.

30. The backlight control circuit according to claim 29, characterized in that, The value of the second voltage is between the first voltage and the ground potential.

31. The backlight control circuit according to claim 30, characterized in that, The value of the second voltage is a preset threshold voltage. The driving unit is equipped with a comparator to compare the voltage on the hardware encoding recognition unit with a reference voltage in order to identify the hardware encoding state.

32. The backlight control circuit according to claim 28, characterized in that, The hardware encoding identification unit includes a resistor network connected between the encoding pin of the driving unit and different potentials, and different resistor voltage division values ​​characterize different hardware encoding states.

33. The backlight control circuit according to claim 28, characterized in that, The logical address range allocated based on the hardware encoding state is continuous and the branches do not overlap.

34. The backlight control circuit according to claim 33, characterized in that, The driving unit is configured such that: the first driving unit determines its own basic logic address based on the detected hardware coding state, and allocates the address of each driving unit connected in series thereafter by incrementing the address by a predetermined step.

35. The backlight control circuit according to claim 28, characterized in that, The main control unit is also configured to: when it is necessary to read the status of the driving unit, control the data transmission direction of the single data signal line to reverse, and send a status read instruction containing its logical address to each driving unit in sequence, so as to receive the status data returned by each driving unit in the order of its logical address.

36. The backlight control circuit according to claim 35, characterized in that, The main control unit is configured to send the status read instructions in ascending order of logical addresses.

37. The backlight control circuit according to claim 28, characterized in that, The backlight control circuit is applied to the liquid crystal display device, the driving unit is a driver IC for driving LEDs, and the light-emitting device is an LED.

38. The backlight control circuit according to claim 37, characterized in that, The single-channel data signal line is simultaneously connected to the data input terminal of the first-end drive unit of each of the drive branches via an adapter board.

39. The backlight control circuit according to claim 28, characterized in that, The hardware encoding recognition unit includes a dedicated encoding pin of the driving unit. The different hardware encoding states are achieved by connecting the dedicated encoding pin to different fixed potentials or by connecting it to a fixed potential through a resistor.

40. The backlight control circuit according to claim 39, characterized in that, The fixed potential includes the power supply voltage, the ground potential, and one or more intermediate potentials generated by resistor voltage division.

41. The backlight control circuit according to claim 28, characterized in that, The driving unit is configured to store the allocation result in a non-volatile memory after completing the logical address allocation during the power-on initialization phase.

42. The backlight control circuit according to claim 28, characterized in that, The drive unit is also configured to enter a preset fail-safe mode or report an error state when the hardware coding state fails or is abnormal.

43. The backlight control circuit according to claim 28, characterized in that, The main control unit is configured to broadcast an address query instruction to all drive units after the system starts up, in order to obtain all valid logical address mapping relationships in the current system.

44. The backlight control circuit according to claim 28, characterized in that, The broadcast signal adopts a data packet structure, and each data packet includes a header, a destination address field, a brightness data field, and a check field.

45. The backlight control circuit according to claim 28, characterized in that, The single-channel data signal line uses differential signal line pairs.

46. ​​The backlight control circuit according to claim 28, characterized in that, The multiple drive branches are physically arranged radially from the main control unit or a transfer node.

47. A backlight control method applied to a display device, the display device comprising a display screen, at least two parallel driving circuit components, a backlight component, a connection module, and a main control circuit; the driving circuit components comprising at least two driving circuits connected in series; the backlight component comprising multiple backlight zones, each backlight zone comprising multiple backlight sources; at least two output terminals of the connection module being coupled one-to-one with the at least two driving circuit components; the main control circuit being coupled to the input terminals of the display screen and the connection module respectively. The method includes: Acquire brightness data signals; The brightness data signal is sent to the corresponding driving circuit component through the connection module, so that the driving circuit in the corresponding driving circuit component controls the brightness of the backlight in the corresponding backlight zone based on the corresponding sub-brightness data signal in the brightness data signal.

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