Display control method, display chip and display device

Abstract

Provided are a display control method, a display chip and a display device, and the technical field belongs to display technology. In the display control method, the display chip can control the display driving circuit to perform a refresh rate switching operation in combination with the display refresh rate switching condition and the counting position of the counting module. Therefore, the counting position triggering condition can be flexibly configured, the display refresh rate is switched from one refresh rate to another refresh rate only at a specific position, different rows can have the same polarity, the brightness difference problem caused by different polarities of different rows is solved, the occurrence of display defects is avoided, and the display effect is ensured to be good.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display control method, a display chip, and a display device. Background Technology

[0002] Display chips are one of the essential circuits that drive display devices (such as liquid crystal displays) to display images.

[0003] Currently, taking LCD devices as an example, to balance display smoothness and power consumption, the display chip can control the display driver circuit to control different display zones of the display panel to refresh at different refresh rates. That is, it controls display zones displaying, for example, dynamic images to refresh at a higher refresh rate to ensure better display smoothness; and controls display zones displaying, for example, static images to refresh at a lower refresh rate to reduce power consumption. Furthermore, to avoid polarization of liquid crystal molecules, the display chip can also control the display driver circuit to drive the pixels of the display panel using a polarity reversal method, that is, periodically changing the polarity of the voltage applied to the pixels.

[0004] However, with the current driving method, under the polarity reversal driving method, when the refresh rate is switched (especially from high refresh to low refresh), there will be a phenomenon of different line polarities. Since the brightness of different polarities is different, it will eventually lead to a blocky display, resulting in poor display effect. Summary of the Invention

[0005] A display control method, a display chip, and a display device are provided, which can solve the technical problem in related technologies where the display effect is poor due to the existence of different line polarities in scenarios with switchable refresh rates. The technical solution is as follows: On one hand, a display control method is provided, applied to a display chip, wherein the display chip controls a display driving circuit to drive a display panel to display multiple rows of pixels using a polarity reversal method; the method includes: Receive display information and frame synchronization signals; Based on the display information, determine whether the display refresh rate of the display panel meets the refresh rate switching condition from the first refresh rate to the second refresh rate, wherein the first refresh rate and the second refresh rate have different values; The display frames of the display panel are counted based on the frame synchronization signal. When it is determined that the display refresh rate meets the refresh rate switching condition, a corresponding refresh rate switching control signal is generated and output to the display driver circuit according to the counting position, so as to control the display driver circuit to perform the refresh rate switching operation.

[0006] Optionally, counting the display frames of the display panel includes: cyclically counting the display frames of the display panel at a counting period greater than 1; and controlling the display driving circuit to perform a refresh rate switching operation, including: The display driving circuit controls the display refresh rate of the current row of pixels to switch to the second refresh rate at the current counting position, and controls the display refresh rate of the multiple rows of pixels to switch synchronously at the beginning frame of each counting cycle, starting from the end of the current counting cycle.

[0007] Optionally, counting the display frames of the display panel includes: cyclically counting the display frames of the display panel at a counting period greater than 1; and controlling the display driving circuit to perform a refresh rate switching operation includes: When the display driving circuit reaches the starting frame of the next counting cycle adjacent to the current counting cycle at the counting position, it controls the display refresh rate of the current row of pixels to switch to the second refresh rate. Starting from the next counting cycle after its end, at the beginning frame of each counting cycle, it controls the display refresh rate of the multiple rows of pixels to switch synchronously.

[0008] Optionally, counting the display frames of the display panel includes: cyclically counting the display frames of the display panel at a counting period greater than 1; and controlling the display driving circuit to perform a refresh rate switching operation includes: When the current counting position is an even frame or the counting position reaches the next even frame adjacent to the current odd frame, the display driving circuit controls the display refresh rate of the current row of pixels to switch to the second refresh rate. Starting from the counting period adjacent to the end of the counting period of the even frame, the display refresh rate of the multiple rows of pixels is controlled to switch synchronously at the beginning frame of each counting period.

[0009] Optionally, the display information includes multiple consecutive frames of image data; based on the display information, determining whether the display refresh rate of the display panel meets the refresh rate switching condition from the first refresh rate to the second refresh rate includes: Based on each adjacent frame of image data in the continuous multi-frame image data, determine the display refresh rate corresponding to the current moment of the image screen; Compare the display refresh rate at the current moment with the display refresh rate at the previous moment to determine the change in the display refresh rate; Based on the comparison results, it is determined whether the display refresh rate of the display panel meets the refresh rate switching condition for switching from the first refresh rate to the second refresh rate.

[0010] On the other hand, a display chip is provided for performing the display control method as described in the above aspect.

[0011] In another aspect, a display chip is provided, which is used to control a display driving circuit to drive a display panel to display multiple rows of pixels in a polarity-reversed manner; and the display chip includes: The counting module is configured to count the display frames of the display panel; The detection module is configured to detect whether the display refresh rate of the display panel meets the refresh rate switching condition from the first refresh rate to the second refresh rate, wherein the first refresh rate and the second refresh rate have different values; The control module is configured to control the display driver circuit to perform a refresh rate switching operation based on whether the display refresh rate meets the refresh rate switching conditions and the counting position.

[0012] Optionally, the counting module is configured to: cyclically count the display frames of the display panel according to a counting period greater than 1; The control module is configured to: when the display refresh rate meets the refresh rate switching condition, control the display driving circuit to perform the following refresh rate switching operation: control the display refresh rate of the current row of pixels to switch to the second refresh rate at the current counting position, and control the display refresh rate of the multiple rows of pixels to switch synchronously at the beginning frame of each counting period, starting from the adjacent counting period after the end of the current counting period.

[0013] Optionally, the counting module is configured to: cyclically count the display frames of the display panel according to a counting period greater than 1; The control module is configured to: when the display refresh rate meets the refresh rate switching condition, control the display driving circuit to perform the following refresh rate switching operation: when the counting position reaches the start frame of the next counting cycle adjacent to the current counting cycle, control the display refresh rate of the current row of pixels to switch to the second refresh rate, and from the end of the next counting cycle, start of the next counting cycle, control the display refresh rate of the multiple rows of pixels to switch synchronously at the start frame of each counting cycle.

[0014] Optionally, the counting module is configured to: cyclically count the display frames of the display panel according to a counting period greater than 1; The control module is configured to: when the display refresh rate meets the refresh rate switching condition, control the display driving circuit to perform the following refresh rate switching operation: when the current counting position is an even frame or the counting position reaches the next even frame adjacent to the current odd frame, control the display refresh rate of the current row of pixels to switch to the second refresh rate, and starting from the counting period adjacent to the end of the counting period of the even frame, control the display refresh rate of the multiple rows of pixels to switch synchronously at the beginning frame of each counting period.

[0015] Optionally, the detection module includes: The receiving unit is configured to receive display information; The detection unit is configured to: detect, based on the display information, whether the display refresh rate of the display panel meets the refresh rate switching condition for switching from the first refresh rate to the second refresh rate.

[0016] Optionally, the display information includes multiple consecutive frames of image data; the detection unit is configured to: Based on each adjacent frame of image data in the continuous multi-frame image data, determine the display refresh rate corresponding to the current moment of the image screen; Compare the display refresh rate at the current moment with the display refresh rate at the previous moment to determine the change in the display refresh rate; Based on the comparison results, it is determined whether the display refresh rate of the display panel meets the refresh rate switching condition for switching from the first refresh rate to the second refresh rate.

[0017] Optionally, the first refresh rate is greater than the second refresh rate.

[0018] Optionally, the second refresh rate is 1 / n of the first refresh rate, and the counting period is n, where n is an integer greater than 1.

[0019] Optionally, the display chip is used to control the display driving circuit to drive the display panel to display multiple rows of pixels in a manner that reverses the polarity of adjacent frames.

[0020] In another aspect, a display control method is provided, applied to a display chip, wherein the display chip controls a display driving circuit to drive the display panel to display multiple rows of pixels using a polarity reversal method; the method includes: Count the display frames of the display panel; The display panel is checked to see if its refresh rate meets the refresh rate switching condition from the first refresh rate to the second refresh rate, wherein the first refresh rate and the second refresh rate have different values; Based on whether the display refresh rate meets the refresh rate switching conditions and the counting position, the display driver circuit is controlled to perform a refresh rate switching operation.

[0021] In another aspect, a display device is provided, the display device comprising: a display panel, a display driving circuit, and a display chip as described in the other and yet another aspects above.

[0022] In summary, the technical solution provided in this application can bring at least the following beneficial effects: A display control method, a display chip, and a display device are provided. In this display control method, the display chip can control the display driver circuit to perform refresh rate switching operations by combining the display refresh rate switching status and the counting position of the counting module. Therefore, by flexibly configuring the counting position trigger conditions, the display refresh rate can be controlled to switch from one refresh rate to another only at a specific position. This ensures that different rows have the same polarity, solves the brightness difference problem caused by different polarities of different rows, and thus avoids display defects, ensuring better display effects. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the display state of a display chip provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a display chip provided in an embodiment of this application; Figure 3 This is a schematic diagram of the display state of another display chip provided in an embodiment of this application; Figure 4 Is Figure 3 The diagram shown is a signal timing diagram of a display chip. Figure 5 This is a schematic diagram of the display state of another display chip provided in an embodiment of this application; Figure 6 Is Figure 5 The diagram shown is a signal timing diagram of a display chip. Figure 7 This is a schematic diagram of the display state of another display chip provided in an embodiment of this application; Figure 8 Is Figure 7 The diagram shown is a signal timing diagram of a display chip. Figure 9 This is a schematic diagram of the display state of another display chip provided in an embodiment of this application; Figure 10 Is Figure 9 The diagram shown is a signal timing diagram of a display chip. Figure 11 This is a schematic diagram of another display chip structure provided in an embodiment of this application; Figure 12 This is a schematic diagram of another display chip structure provided in an embodiment of this application; Figure 13 This is a flowchart illustrating a display control method provided in an embodiment of this application; Figure 14 This is a flowchart illustrating another display control method provided in an embodiment of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0026] With the upgrading of comprehensive consumer demand, the decline in manufacturing costs, the improvement of interface transmission bandwidth, and the promotion of various emerging interactive scenarios such as Virtual Reality (VR) / Augmented Reality (AR), displays are still evolving towards higher refresh rates, especially in e-sports, mobile terminals and immersive devices.

[0027] As mentioned in the background, the core advantage of a high refresh rate lies in its ability to significantly improve image smoothness and reduce input lag and motion blur by increasing the number of image updates per second. This is particularly suitable for professional scenarios such as gaming, professional video editing, VR / AR, and displays of dynamic images requiring rapid interaction. However, a high refresh rate also comes with higher power consumption, and refresh rate and power consumption are generally positively correlated. Therefore, a trade-off must be made between device performance and battery life. The core advantage of a low refresh rate is that it maintains lower power consumption and lower manufacturing costs, and is sufficient for static or low-dynamic display scenarios such as daily office work, web browsing, and document reading. At the same time, low refresh rate displays still maintain a good level of resolution and color performance. The terms "high," "low," and "large" mentioned in the embodiments of this application are relative. A high refresh rate is generally about 120 Hz or even higher, and a low refresh rate is generally about 40 Hz or even lower. Of course, these parameters are only illustrative.

[0028] Therefore, in some embodiments, considering the balance between display smoothness and power consumption, the display chip can control the display driver circuit to control different display zones of the display panel to refresh at different refresh rates. For example, in the display driver circuit, the gate driver circuit (also called GOA circuit) that controls the pixel activation generally includes cascaded multi-level shift register units (also called GOA units), with each GOA unit connected to a corresponding row of pixels. Based on this structure, the display chip can flexibly control the activation frequency of each level of GOA unit to enable pixels in different display zones at different refresh rates, thereby controlling different display zones to refresh at different refresh rates. For example, the GOA unit can be configured to include two levels of driver units: the first-level driver unit is responsible for providing a unified gate drive signal for all row pixels based on the clock signals provided by multiple connected driver clock terminals CLKC (e.g., CLKC1 to CLKC6), ensuring the consistency of the basic switching timing of all row pixels. The second-level driver unit is responsible for providing independent enable control signals for different display zones, such as high refresh areas and low refresh areas, based on the clock signals provided by multiple connected enable clock terminals CLK (e.g., CLK1 to CLK6). Correspondingly, by flexibly setting the frequency of the clock signal provided by different enable clock terminals CLK in the display chip, it is possible to achieve differentiated refresh rate configurations for different display zones. In other words, the clock combination of the drive clock terminal CLKC and the enable clock terminal CLK can realize zoned refresh of the LCD screen.

[0029] However, in practical applications, it has been found that the control method using the above clock combination will introduce image quality loss in display scenarios with polarity reversal, which is often manifested as block abnormalities, screen flickering and other defects, affecting the user's visual experience.

[0030] The principle of polarity reversal is explained as follows: For liquid crystal display devices, the display driving circuit is typically used, under the control of the display chip, to apply a driving voltage to the liquid crystal molecules in the pixel. This drives the liquid crystal molecules to deflect, allowing light to pass through a color filter located on one side of the pixel and thus achieve display. Applying a driving voltage to the liquid crystal molecules in the pixel can mean applying voltages to the pixel electrode and the common electrode located at opposite ends of the liquid crystal molecules, creating a voltage difference between them. This voltage difference drives the liquid crystal molecules to deflect. Furthermore, the application of a unidirectional driving voltage over a long period means that the voltage difference between the voltage applied to the pixel electrode (also called the pixel voltage) and the voltage applied to the common electrode (i.e., the common voltage) remains positive for a long time (i.e., the pixel voltage is higher than the common voltage for a long time); or, the voltage difference between the pixel voltage and the common voltage remains negative for a long time (i.e., the pixel voltage is lower than the common voltage for a long time). This situation leads to polarization of the liquid crystal molecules. Polarization is a physical phenomenon where, under the influence of an electric field, the internal charge distribution of the liquid crystal molecules shifts, forming a dipole moment or causing existing dipole moments to align in an orientation. This polarization phenomenon also causes the liquid crystal molecules to slow down their response speed when switching between display images. The liquid crystal molecules cannot change their alignment in time, which further leads to the previous image remaining on the display panel, resulting in display defects such as image retention and ghosting. Furthermore, after prolonged use, the liquid crystal molecules may even struggle to regain their original response characteristics, causing permanent defects in the display panel and significantly shortening its lifespan.

[0031] Based on this, in some embodiments, the display chip is configured to control the display driving circuit to drive the liquid crystal molecules using a polarity reversal method. Polarity reversal refers to periodically changing the polarity of the driving voltage applied to the liquid crystal molecules, causing the driving voltage to continuously switch between a positive polarity voltage (i.e., voltage greater than 0, or pixel voltage greater than the common voltage) and a negative polarity voltage (i.e., voltage less than 0, or pixel voltage less than the common voltage). This ensures that the liquid crystal molecules do not become polarized due to the continuous action of a unidirectional electric field during long-term operation, while maintaining relatively stable polarization performance, thereby improving problems such as poor display quality and short lifespan. Generally, the common voltage is fixed, and the display chip can achieve polarity reversal by controlling the display driving circuit to change the magnitude of the pixel voltage. In addition, the display driving circuit generally includes a source driving circuit (Source IC), which can be connected to the pixel electrodes in multiple columns of pixels through multiple data lines to provide pixel voltages to each pixel electrode under the control of the display chip.

[0032] For example, in some embodiments, the display chip can control the display driving circuit to drive in a column-inverted manner: that is, during each frame display, the driving voltages applied to the liquid crystal molecules in any two adjacent columns of pixels have opposite polarities, and the driving voltages applied to the liquid crystal molecules in the same column of pixels have the same polarity. Accordingly, in the case of multiple rows and columns of pixels, the positive and negative polarity voltages can be switched periodically according to the frame. And, in two adjacent frames, the driving voltages applied to the same column of pixels have opposite polarities. For example, in combination with... Figure 1 This schematically illustrates the driving voltage polarity from frame 1 to frame 12. (Reference) Figure 1 As can be seen, odd-numbered frames (e.g., the first frame Frame1) have a positive polarity (marked as +); even-numbered frames (e.g., the second frame Frame2) have a negative polarity (marked as -). Of course, this is not limited to column reversal. In some embodiments, dot reversal can also be used: that is, during the display of each frame, the driving voltages applied to the liquid crystal molecules in any two adjacent (top, bottom, left, right) pixels have opposite polarities. Accordingly, in cases involving multiple rows and columns of pixels, the positive and negative polarity voltages can be switched according to the behavior cycle.

[0033] Understandable Figure 1 The horizontal axis represents time and records the polarity that the screen should exhibit at different frame positions. Figure 1 The vertical axis represents different rows, recording the different times when different rows transition from high refresh rate to low refresh rate. A high refresh rate is, for example, 120Hz, and a low refresh rate is, for example, 1 / 3 of the high refresh rate: 40Hz, corresponding to 1 frame refresh followed by 2 frames keep. Refresh refers to writing updated display data to the pixel, controlling the pixel to complete the screen update; keep refers to no longer writing display data to the pixel, but instead maintaining its display state after the last refresh, with the polarity unchanged. Figure 1 The illustration shows the transition from high refresh to low refresh for six lines (Line1 to Line6). For example, for the first line (Line1), it can enter low refresh in the first frame (Frame1), for the second line (Line2), it can enter low refresh in the second frame (Frame2), and so on.

[0034] However, in Figure 1Under the driving mode shown, it can be observed that in the seventh frame (Frame 7) and subsequent frames, different rows have different polarities. For example, taking the seventh frame (Frame 7) as an example: for the first row (Line 1), it is in a Refresh state with a + polarity; for the second row (Line 2), it is in a Keep state, maintaining the state after the refresh of the fifth frame (Frame 5) with a + polarity; for the third row (Line 3), it is in a Keep state, maintaining the state after the refresh of the sixth frame (Frame 6) with a - polarity; for the fourth row (Line 4), it is in a Refresh state with a + polarity; for the fifth row (Line 5), it is in a Keep state, maintaining the state after the refresh of the fifth frame (Frame 5) with a + polarity; and for the sixth row (Line 6), it is in a Keep state, maintaining the state after the refresh of the sixth frame (Frame 6) with a - polarity. This shows that the polarities of the second (Line 2) and third (Line 3) lines are different; the polarities of the third (Line 3) and fourth (Line 4) lines are different; and the polarities of the fifth (Line 5) and sixth (Line 6) lines are different. The same applies to other frames. Since brightness generally differs between lines with different polarities, it's understood that if multiple lines in each frame have different polarities, it will lead to significant differences in brightness, ultimately causing issues such as blocking and flickering. Understandably, this display problem also exists when switching from a low refresh rate to a high refresh rate using the polarity reversal driving method.

[0035] Based on this, the embodiments of this application provide a new technical solution that can control different display zones of the display panel to refresh at different refresh rates. That is, while realizing the display screen zone refresh control, it also solves problems such as blocking and flickering, ensuring better display effect, and improving power consumption performance.

[0036] Figure 2 This is a schematic diagram of a display chip provided in an embodiment of this application. The display chip is used to control the display driving circuit to drive the display panel to display multiple rows of pixels using a polarity reversal method, such as... Figure 1 The display chip is driven by a polarity reversal method as shown. Furthermore, the display chip includes: a counting module 01, a detection module 02, and a control module 03. Combined with... Figure 2 It can also be seen that both the counting module 01 and the detection module 02 are connected to the control module 03.

[0037] The counting module 01 is configured to count the display frames of the display panel.

[0038] That is, in this embodiment of the application, a counting module 01 can be set to count the display frames to determine the position of the current display frame. For example, starting from the first frame (Frame1), the count value can be incremented by 1 for each frame, thereby realizing the counting of display frames. Correspondingly, the counting module 01 can also be called a frame counter.

[0039] The detection module 02 is configured to detect whether the display refresh rate of the display panel meets the refresh rate switching condition from the first refresh rate to the second refresh rate.

[0040] The first refresh rate and the second refresh rate have different values. That is, the first refresh rate can be greater than the second refresh rate, corresponding to a switch from a high refresh rate to a low refresh rate; the first refresh rate is also called the high refresh rate, and the second refresh rate is also called the low refresh rate. Alternatively, the first refresh rate can be less than the second refresh rate, corresponding to a switch from a low refresh rate to a high refresh rate; the first refresh rate is also called the low refresh rate, and the second refresh rate is also called the high refresh rate. For example, combined with... Figure 3 The first refresh rate shown is greater than the second refresh rate, and the first refresh rate is 120Hz, while the second refresh rate is 40Hz.

[0041] That is, in this embodiment of the application, a detection module 02 can be set to detect the refresh rate to determine the refresh rate switching position, i.e., to determine the switching position from one refresh rate to another. For example, in combination with Figure 3 Taking the first line (Line1) as an example, the detection module 02 can be used to determine in which frame the low refresh rate occurred in that line. Furthermore, the detection module 02 can reliably detect the refresh rate based on, for example, the dynamic and static changes of the displayed content.

[0042] Control module 03 is configured to control the display driver circuit to perform a refresh rate switching operation based on whether the display refresh rate meets the refresh rate switching conditions and the counting position.

[0043] That is, in this embodiment, the control module 03 can combine the display refresh rate detection result of the detection module 02 and the counting position of the counting module 01 to control the display driving circuit to perform a refresh rate switching operation at a specific counting position. In this way, the counting position can be flexibly configured when the display refresh rate meets the refresh rate switching conditions, ensuring that after the refresh rate switching operation, different rows have as much the same polarity as possible and do not exhibit [unclear meaning]. Figure 1 This addresses the problem of brightness differences caused by different row polarities.

[0044] Optionally, in this embodiment, the counting module 01 can also transmit the counting result to the control module 03, and the detection module 02 can transmit the refresh rate detection result to the control module 03 for use by the control module 03. Alternatively, in some embodiments, the control module 03 can actively obtain the corresponding results from the counting module 01 and the detection module 02. This embodiment does not limit this aspect.

[0045] In summary, this application provides a display chip. Because the control module in this display chip can control the display driver circuit to perform refresh rate switching operations by combining the display refresh rate switching status and the counting position of the counting module, the counting position trigger conditions can be flexibly configured so that the display refresh rate is switched from one refresh rate to another only at a specific position. This ensures that different rows have the same polarity, solves the brightness difference problem caused by different polarities of different rows, and thus avoids display defects, ensuring better display effects.

[0046] Optionally, in this embodiment of the application, the counting module 01 can be configured to: cyclically count the display frames of the display panel according to a counting period greater than 1.

[0047] That is, in this embodiment of the application, the counting module 01 can be set to count the display frames cyclically according to a fixed counting period greater than 1. For example, starting from the first frame (Frame1), the count value can be incremented by 1 after each frame. When the count value reaches the counting period, it can be automatically reset to zero and the counting can start again. Thus, periodic monitoring of the display frames can be realized.

[0048] Optionally, the counting period can be determined based on the multiple relationship between the high refresh rate and the low refresh rate. For example, if the low refresh rate is 1 / 3 of the high refresh rate, the counting period could be 3. Figure 1 Based on the combination Figure 3 With a counting cycle of 3, the counting module 01 increments the count starting from the first frame (Frame1). When it counts to the third frame (Frame3), it can reset to zero and start counting the fourth frame (Frame4) as the first frame again, and so on. That is, taking the first frame (Frame1) to the twelfth frame (Frame12) as an example, starting from the first frame, every 3 frames can be considered as one cycle, and correspondingly, it can be divided into 4 cycles.

[0049] Optionally, based on cyclically counting the display frames of the display panel at a counting period greater than 1: In one alternative implementation: control module 03 can be configured as follows: When the display refresh rate meets the refresh rate switching conditions, the control display driver circuit performs the following refresh rate switching operation: at the current counting position, the display refresh rate of the current row of pixels is switched to the second refresh rate, and starting from the next counting cycle after the end of the current counting cycle, the display refresh rates of multiple rows of pixels are switched synchronously at the beginning frame of each counting cycle.

[0050] That is, in this implementation, the control module 03 can determine the position of the frame counter when it detects a refresh rate switch, and instruct the display drive circuit to control all row pixels to switch refresh rates synchronously according to the starting frame position of the counting period.

[0051] For example, combining Figure 3 In scenarios where the first refresh rate is greater than the second refresh rate, the display driver circuit can control the display refresh rate of multiple rows of pixels to switch from a high refresh rate to a low refresh rate at the beginning frame of a counting cycle, or the first frame. This can also be called entering low refresh by periodic position, thereby completing low refresh frame synchronization. The control method for switching the display refresh rate from low refresh rate to high refresh rate is similar and will not be repeated here.

[0052] For example, still combined Figure 3 When the counting period is 3, and the detection module 02 detects that the first line (Line1) enters a low refresh rate in the first frame (Frame1), the second line (Line2) enters a low refresh rate in the second frame (Frame2), the third line (Line3) enters a low refresh rate in the third frame (Frame3), the fourth line (Line4) enters a low refresh rate in the fourth frame (Frame4), the fifth line (Line5) enters a low refresh rate in the fifth frame (Frame5), and the sixth line (Line6) enters a low refresh rate in the sixth frame (Frame6), the control module 03 can control the display driver circuit to perform the following operations: For the first row (Line1), firstly, the pixels in the first row are controlled to switch from a first refresh rate of 120Hz to a second refresh rate of 40Hz in the first frame of the first counting cycle (Frame1), which is the first frame out of twelve frames, corresponding to the Refresh state. Then, in the second frame of the first counting cycle (Frame2), they switch to the Keep state, entering a low refresh rate. In the third frame of the first counting cycle (Frame3), they remain in the Keep state. Then, starting from the second counting cycle, in the first frame (Frame1) or starting frame of each counting cycle, all row pixels are controlled to synchronously switch refresh rates, cycling through the Refresh, Keep, and Keep states sequentially from the first frame (Frame1) to the third frame (Frame3) of each counting cycle.

[0053] For the second row (Line2), firstly, the pixels in the second row are controlled to switch to Keep state and enter low refresh rate at the current counting position "the second frame of the first counting cycle (Frame2)," which is the second frame out of twelve frames. Then, they remain in Keep state in the third frame (Frame3) of the first counting cycle. Then, starting from the second counting cycle, in the first frame (Frame1) or starting frame of each counting cycle, all row pixels are controlled to synchronously switch refresh rates, cycling through Refresh, Keep, Keep states sequentially from the first frame (Frame1) to the third frame (Frame3) of each counting cycle.

[0054] For the third line (Line3), firstly, control the pixels in the third line to switch to Keep state and enter low refresh rate at the current counting position "the third frame of the first counting cycle (Frame3)," which is the third frame out of twelve frames. Then, starting from the second counting cycle, in the first frame (Frame1) or starting frame of each counting cycle, control all line pixels to synchronously switch refresh rates, cycling through the Refresh, Keep, Keep states sequentially from the first frame (Frame1) to the third frame (Frame3) of each counting cycle.

[0055] For the fourth row (Line4), firstly, the pixels in the fourth row are controlled to switch from a first refresh rate of 120Hz to a second refresh rate of 40Hz in the current counting position, "the first frame of the second counting cycle (Frame1)," which is the fourth frame out of twelve frames, corresponding to the Refresh state. Then, in the second frame of the second counting cycle (Frame2), they switch to the Keep state; and in the third frame of the second counting cycle (Frame3), they remain in the Keep state. Then, starting from the third counting cycle, in the first frame (Frame1) or starting frame of each counting cycle, all row pixels are controlled to synchronously switch refresh rates, cycling through the Refresh, Keep, and Keep states sequentially from the first frame (Frame1) to the third frame (Frame3) of each counting cycle.

[0056] For the fifth row (Line 5), firstly, the pixels in the fifth row are controlled to switch to Keep state and enter low refresh rate at the current counting position "the second frame of the second counting cycle (Frame 2)," which is the fifth frame out of twelve frames. Then, they remain in Keep state in the third frame of the second counting cycle (Frame 3). Then, starting from the third counting cycle, in the first frame (Frame 1) or starting frame of each counting cycle, all row pixels are controlled to synchronously switch refresh rates, cycling through Refresh, Keep, Keep states sequentially from the first frame (Frame 1) to the third frame (Frame 3) of each counting cycle.

[0057] For the sixth row (Line6), firstly, control the pixels in the sixth row to switch to Keep state and enter low refresh rate at the current counting position "the third frame of the second counting cycle (Frame3)," which is the sixth frame out of twelve frames. Then, starting from the third counting cycle, in the first frame (Frame1) or starting frame of each counting cycle, control all row pixels to synchronously switch refresh rates, cycling through the Refresh, Keep, Keep states sequentially from the first frame (Frame1) to the third frame (Frame3) of each counting cycle.

[0058] Thus, in comparison Figure 1 and Figure 3 It can be seen that by entering low refresh rate according to the periodic position, in frames such as the seventh frame (Frame 7) and subsequent frames, different rows can have the same polarity, meaning the problem of different rows having different polarities no longer exists. That is, in Figure 3 As shown in the driving mode, taking the seventh frame (Frame 7) as an example, it can be seen that for the first line (Line 1) to the sixth line (Line 6), all can be in the Refresh state, with the polarity all being +. The same applies to other frames, so it will not be repeated here. In this way, polarity balance can be achieved, improving undesirable phenomena such as blocking and flickering, and ensuring better display effects.

[0059] For example, Figure 4 It also schematically shows Figure 3 The timing diagram corresponding to the scheme shown is shown. Figure 4The diagram illustrates: (1) Total frame count results: from frame 1 to frame 9; (2) Periodic frame count results with 3 frames as a cycle; (3) Polarity change: from frame 1 to frame 9, the polarity of each adjacent frame is opposite, odd-numbered frames are positive polarity, and even-numbered frames are negative polarity; (4) Changes in the display content of the third line: from frame 1 to frame 9, the order is: dynamic, dynamic, static, static, static, static, static, static, static, static, static, satisfying that the third line enters low refresh in the third frame and enters low refresh according to the periodic position; (5) High and low refresh flags, the flag is high when it is in dynamic high refresh state, the flag is... When the voltage is low, it is in a static low refresh state. Of course, it is not limited to the high and low voltage limit. (6) The clock signal provided by the driving clock terminal CLKC satisfies that it is in a high voltage valid state in each frame. (7) The clock signal provided by the enable clock terminal CLK satisfies that in the third frame (Frame3) of the first counting cycle, that is, the third frame from the first frame (Frame1) to the ninth frame (Frame9), it is in a low voltage invalid state, that is, in a Keep state, thereby ensuring that the third line (Line3) enters a low refresh in the third frame (Frame3); and in the first frame of each subsequent counting cycle, it is in a high voltage valid state, that is, in a Refresh state, and in the other frames of each subsequent counting cycle, it is in a low voltage invalid state, that is, in a Keep state, and so on. (8) The corresponding refresh state satisfies that from the first frame (Frame1) to the ninth frame (Frame9), it is refresh, refresh, hold, refresh, hold, hold, refresh, hold, hold. (9) The corresponding high and low refresh rates satisfy the following: from the first frame (Frame1) to the ninth frame (Frame9), the refresh rates are high, high, low, low, low, low, low, low, low, low, low, low. This further demonstrates that by arranging the Refresh operation to be executed in the first frame of each counting cycle, and entering a Keep state for the rest of the cycle, once a line of image content becomes static (e.g., Line 3 in Frame3), the display chip can control the display driver circuit to safely and synchronously switch the refresh rate of all row pixels to low refresh mode in the first frame of the next counting cycle, and maintain this low refresh state during the static content period. This improves issues such as blocking and flickering, ensuring better display performance.

[0060] However, combined Figure 3It can also be seen that while the above solutions address the issues, display anomalies still exist. For example, regarding the third line (Line 3), as indicated by the dashed box, it is in a Refresh state in the second frame (Frame 2) of the first counting cycle, with a negative polarity (-); in the third frame (Frame 3) of the first counting cycle, it is in a Keep state, maintaining the negative polarity of the second frame (Frame 2) of the current counting cycle (-); and in the first frame (Frame 1) of the second counting cycle, it is in a Refresh state, with a negative polarity (-). That is, there is a phenomenon of continuously refreshing frames with negative polarity. Regarding the sixth line (Line 6), as indicated by the dashed box, it is in a Refresh state in the second frame (Frame 2) of the second counting cycle, with a positive polarity (+); in the third frame (Frame 3) of the second counting cycle, it is in a Keep state, maintaining the positive polarity of the second frame (Frame 2) of the current counting cycle (+); and in the first frame (Frame 1) of the third counting cycle, it is in a Refresh state, with a positive polarity (+). That is, there is a phenomenon of continuously refreshing frames with positive polarity. In other words, Figure 3 The proposed solution can cause the display to show consecutive refresh frames with the same polarity, which can lead to significant brightness variations and flickering.

[0061] Based on this, in another alternative implementation, control module 03 can be configured as follows: When the display refresh rate meets the refresh rate switching conditions, the display driver circuit is controlled to perform the following refresh rate switching operation: when the counting position reaches the start frame of the next counting cycle adjacent to the current counting cycle, the display refresh rate of the current row of pixels is controlled to switch to the second refresh rate, and starting from the next counting cycle after the end of the next counting cycle, the display refresh rates of multiple rows of pixels are controlled to switch synchronously at the start frame of each counting cycle.

[0062] That is, in the above Figure 3 Based on the illustrated scheme, a synchronization cycle design is added. Specifically, when the detection module 02 detects a switch from one refresh rate to another (e.g., from a high refresh rate to a low refresh rate), the control module 03 does not immediately control the switch to the other refresh rate (e.g., a low refresh rate). Instead, it first enters a polarity synchronization cycle and determines the counting position of the current counting module 01. Only when the counting position of the counting module 01 cycles to the starting frame of the next counting cycle is the refresh rate switching operation officially executed. During the polarity synchronization cycle, the refresh rate can remain at the first refresh rate, i.e., it remains in the Refresh state.

[0063] For example, combining Figure 5Still with a counting cycle of 3, and with detection module 02 detecting that the first line (Line1) enters low refresh in the first frame (Frame1), the second line (Line2) enters low refresh in the second frame (Frame2), the third line (Line3) enters low refresh in the third frame (Frame3), the fourth line (Line4) enters low refresh in the fourth frame (Frame4), the fifth line (Line5) enters low refresh in the fifth frame (Frame5), and the sixth line (Line6) enters low refresh in the sixth frame (Frame6), the comparison... Figure 3 The control module 03 can control the display driver circuit to perform the following operations: For the first row (Line 1), firstly, the display refresh rate of the first row of pixels is controlled to be in Refresh state within the first counting cycle of the current counting position "the first frame of the first counting cycle (Frame 1)," i.e., entering the polarity synchronization cycle. Then, when the counting position reaches the first frame of the adjacent second counting cycle (Frame 1), i.e., the fourth frame out of twelve frames, it prepares to switch from the first refresh rate of 120Hz to the second refresh rate of 40Hz, corresponding to the Refresh state; then, in the second frame of the second counting cycle (Frame 2), it switches to Keep state, entering low refresh; and in the third frame of the second counting cycle (Frame 3), it remains in Keep state. Next, starting from the third counting cycle, in the first frame (Frame 1) of each counting cycle, or the starting frame, all row pixels are controlled to synchronously switch refresh rates, cycling through Refresh, Keep, Keep states sequentially from the first frame (Frame 1) to the third frame (Frame 3) of each counting cycle. That is, if it is not in the current counting position "the first frame of the first counting cycle (Frame 1), i.e., the first frame out of twelve frames," it immediately enters low refresh.

[0064] For the second row (Line 2), firstly, the display refresh rate of the pixels in the second row is controlled to be in Refresh state within the first counting cycle, i.e., entering the polarity synchronization cycle, at the current counting position "the second frame of the first counting cycle (Frame 2)". Then, when the counting position reaches the first frame of the adjacent second counting cycle (Frame 1), i.e., the fourth frame out of twelve frames, it prepares to switch from the first refresh rate of 120Hz to the second refresh rate of 40Hz, corresponding to the Refresh state; then, in the second frame of the second counting cycle (Frame 2), it switches to Keep state, entering low refresh; and in the third frame of the second counting cycle (Frame 3), it remains in Keep state. Next, starting from the third counting cycle, in the first frame (Frame 1) or starting frame of each counting cycle, all row pixels are controlled to synchronously switch refresh rates, cycling through Refresh, Keep, Keep states sequentially from the first frame (Frame 1) to the third frame (Frame 3) of each counting cycle. That is, if it is not in the current counting position "the second frame of the first counting cycle (Frame 2), i.e., the second frame out of twelve frames", it immediately enters low refresh.

[0065] For the third row (Line 3), firstly, the display refresh rate of the third row's pixels is controlled to be in Refresh state within the first counting cycle, i.e., entering the polarity synchronization cycle, during the first counting cycle of the current counting position "the third frame of the first counting cycle (Frame 3)". Then, when the counting position reaches the first frame of the adjacent second counting cycle (Frame 1), i.e., the fourth frame out of twelve frames, it prepares to switch from the first refresh rate of 120Hz to the second refresh rate of 40Hz, corresponding to the Refresh state; then, in the second frame of the second counting cycle (Frame 2), it switches to Keep state, entering low refresh; and in the third frame of the second counting cycle (Frame 3), it remains in Keep state. Next, starting from the third counting cycle, in the first frame (Frame 1) or starting frame of each counting cycle, all row pixels are controlled to synchronously switch refresh rates, cycling through Refresh, Keep, Keep states sequentially from the first frame (Frame 1) to the third frame (Frame 3) of each counting cycle. That is, if it is not in the third frame of the first counting cycle (Frame 3), i.e., the third frame out of twelve frames, it immediately enters low refresh.

[0066] For the fourth row (Line4), firstly, the display refresh rate of the pixels in the fourth row is controlled to be in Refresh state within the second counting cycle, which is the first frame (Frame1) of the second counting cycle, i.e., entering the polarity synchronization cycle. Then, when the counting position reaches the first frame (Frame1) of the adjacent third counting cycle, i.e., the seventh frame out of twelve frames, it prepares to switch from the first refresh rate of 120Hz to the second refresh rate of 40Hz, corresponding to the Refresh state; then, in the second frame (Frame2) of the third counting cycle, it switches to Keep state, entering low refresh; and in the third frame (Frame3) of the third counting cycle, it remains in Keep state. Next, starting from the fourth counting cycle, in the first frame (Frame1) or starting frame of each counting cycle, all row pixels are controlled to synchronously switch refresh rates, cycling through Refresh, Keep, Keep states sequentially from the first frame (Frame1) to the third frame (Frame3) of each counting cycle. That is, it immediately enters low refresh when it is not in the first frame (Frame1) of the second counting cycle, i.e., the fourth frame out of twelve frames.

[0067] For the fifth row (Line 5), firstly, the display refresh rate of the pixels in the fifth row is controlled to be in Refresh state within the second counting cycle, which is the second frame (Frame 2) of the second counting cycle, i.e., entering the polarity synchronization cycle. Then, when the counting position reaches the first frame (Frame 1) of the adjacent third counting cycle, i.e., the seventh frame out of twelve frames, it prepares to switch from the first refresh rate of 120Hz to the second refresh rate of 40Hz, corresponding to the Refresh state; then, in the second frame (Frame 2) of the third counting cycle, it switches to Keep state, entering low refresh; and in the third frame (Frame 3) of the third counting cycle, it remains in Keep state. Next, starting from the second counting cycle, in the first frame (Frame 1) or starting frame of each counting cycle, all row pixels are controlled to synchronously switch refresh rates, cycling through Refresh, Keep, Keep states sequentially from the first frame (Frame 1) to the third frame (Frame 3) of each counting cycle. That is, it immediately enters low refresh when it is not in the second frame (Frame 1) of the second counting cycle, i.e., the fifth frame out of twelve frames.

[0068] For the sixth row (Line 6), firstly, the display refresh rate of the sixth row's pixels is controlled to be in Refresh state throughout the second counting cycle, specifically the third frame (Frame 3) of the second counting cycle, i.e., entering the polarity synchronization cycle. Then, when the counting position reaches the first frame (Frame 1) of the adjacent third counting cycle (i.e., the seventh frame out of twelve frames), it prepares to switch from the first refresh rate of 120Hz to the second refresh rate of 40Hz, corresponding to Refresh state. Afterward, it switches to Keep state in the second frame (Frame 2) of the third counting cycle, entering low refresh; and remains in Keep state in the third frame (Frame 3) of the third counting cycle. Next, starting from the second counting cycle, in the first frame (Frame 1) or starting frame of each counting cycle, all row pixels are controlled to synchronously switch refresh rates, cycling through Refresh, Keep, Keep states sequentially from the first frame (Frame 1) to the third frame (Frame 3) of each counting cycle. That is, if the current counting position is not in the third frame (Frame 3) of the second counting cycle (i.e., the sixth frame out of twelve frames), it immediately enters low refresh.

[0069] Thus, in comparison Figure 3 and Figure 5 It can also be seen that by increasing the synchronization cycle design and delaying the entry into low refresh by one counting cycle, not only can different rows in frames such as the seventh frame (Frame 7) and subsequent frames have the same polarity, thus eliminating the problem of different rows having different polarities, but it can also avoid the occurrence of... Figure 3 The dashed box shows the phenomenon of continuously refreshing frames with either negative or positive polarity, which can solve the problem of large brightness variations and improve flickering. For example, in designs that increase the synchronization cycle, combined with... Figure 5 As can be seen, for the third line (Line3), as indicated by the dashed box, it is in the Refresh state in the second frame (Frame2) of the first counting cycle, with a negative polarity (-); it is also in the Refresh state in the third frame (Frame3) of the first counting cycle, with a positive polarity (+); and it is also in the Refresh state in the first frame (Frame1) of the second counting cycle, with a negative polarity (-), rather than continuously positive or negative polarity.

[0070] For example, Figure 6 It also schematically shows Figure 5 The timing diagram corresponding to the scheme shown is shown. Figure 6The diagram illustrates: (1) Total frame count results: from frame 1 to frame 9; (2) Frame count results with 3 frames as a cycle; (3) Polarity change: from frame 1 to frame 9, the polarity of each adjacent frame is opposite, odd-numbered frames are positive polarity, and even-numbered frames are negative polarity; (4) Changes in the display content of the second line: from frame 1 to frame 9, the order is: dynamic, static, static, static, static, static, static, static, static, static, static, static, satisfying that the second line enters low refresh in the second frame; (5) High and low refresh flags: when the flag is high, it is in dynamic high refresh state, and when the flag is low, it is in static low refresh state; (6) The clock signal provided by the driving clock terminal CLKC satisfies: it is at a high level in each frame. Valid state; (7) The clock signal provided by the enable clock terminal CLK satisfies the following: In the first frame (Frame1) to the third frame (Frame3) of the first counting cycle, it is in a high-level valid state, that is, in the Refresh state. In the first frame (Frame1) of the second counting cycle after a delay of one counting cycle, that is, in the fourth frame of the first frame (Frame1) to the ninth frame (Frame9), it is in a high-level valid state, that is, in the Refresh state. In the second frame (Frame2) and the third frame (Frame3) of the second counting cycle, it is in a low-level invalid state, that is, in the Keep state. In the first frame of each subsequent counting cycle, it is in a high-level valid state, that is, in the Refresh state. In the other frames of each subsequent counting cycle, it is in a low-level invalid state, that is, in the Keep state. This cycle repeats. (8) The corresponding refresh state satisfies the following: From the first frame (Frame1) to the ninth frame (Frame9), it is refresh, refresh, refresh, refresh, keep, keep, refresh, keep, keep. (9) The corresponding high and low refresh rates are: from the first frame (Frame1) to the ninth frame (Frame9), the refresh rates are high, high, high, low, low, low, low, low, low, low, low.

[0071] However, Figure 5 The extended high refresh rate duration in the illustrated embodiment hinders power consumption reduction. Therefore, in another alternative implementation, the control module 03 can be configured as follows: When the display refresh rate meets the refresh rate switching conditions, the control display driver circuit performs the following refresh rate switching operation: when the current counting position is an even frame or the counting position reaches the next even frame adjacent to the current odd frame, the display refresh rate of the current row of pixels is switched to the second refresh rate, and starting from the counting period adjacent to the end of the even frame, the display refresh rate of multiple rows of pixels is switched synchronously at the beginning of each counting period.

[0072] That is, in the above Figure 3 Based on the scheme shown, a synchronization frame design is added. Specifically, when the detection module 02 detects a switch from one refresh rate to another (e.g., from a high refresh rate to a low refresh rate), the control module 03 does not immediately control the switch to the other refresh rate (e.g., a low refresh rate). Instead, it first determines the counting position. If the current counting position is an even-numbered frame, the refresh rate is switched; if the current counting position is an odd-numbered frame, the refresh rate is not switched.

[0073] For example, combining Figure 7 Still with a counting cycle of 3, and with detection module 02 detecting that the first line (Line1) enters low refresh in the first frame (Frame1), the second line (Line2) enters low refresh in the second frame (Frame2), the third line (Line3) enters low refresh in the third frame (Frame3), the fourth line (Line4) enters low refresh in the fourth frame (Frame4), the fifth line (Line5) enters low refresh in the fifth frame (Frame5), and the sixth line (Line6) enters low refresh in the sixth frame (Frame6), the comparison... Figure 5 The control module 03 can control the display driver circuit to perform the following operations: For the first row (Line 1), firstly, the display refresh rate of the first row's pixels is controlled to switch from a 120Hz first refresh rate to a 40Hz second refresh rate in the first frame (Frame 1) of the first counting cycle (i.e., the first of twelve frames), corresponding to the Refresh state. Then, in the second frame (Frame 2) of the first counting cycle, it switches to the Keep state, entering a low refresh rate; and in the third frame (Frame 3) of the first counting cycle, it remains in the Keep state. Then, starting from the second counting cycle, in the first frame (Frame 1) or starting frame of each counting cycle, all row pixels are controlled to synchronously switch refresh rates, cycling through Refresh, Keep, Keep states sequentially from the first frame (Frame 1) to the third frame (Frame 3) of each counting cycle. This can also be understood as reliably entering a low refresh rate only in even-numbered frames—the second frame of the first counting cycle.

[0074] For the second line (Line 2), firstly, the display refresh rate of the second line's pixels is switched to Keep state and enters low refresh rate in the second frame (Frame 2) of the first counting cycle, which is the second frame out of twelve frames. Then, it remains in Keep state in the third frame (Frame 3) of the first counting cycle. Next, starting from the second counting cycle, in the first frame (Frame 1), or the starting frame, the refresh rate of all line pixels is switched synchronously, cycling through Refresh, Keep, Keep states from the first frame (Frame 1) to the third frame (Frame 3) of each counting cycle. This can also be understood as reliably entering low refresh rate only in even-numbered frames—the second frame of the first counting cycle.

[0075] For the third row (Line 3), firstly, the display refresh rate of the third row's pixels is controlled to switch from a 120Hz first refresh rate to a 40Hz second refresh rate in the first frame (Frame 1) of the second counting cycle, which is the fourth frame out of twelve frames, corresponding to the Refresh state. Then, in the second frame (Frame 2) of the second counting cycle, it switches to the Keep state, entering a low refresh rate. It remains in the Keep state in the third frame (Frame 3) of the first counting cycle. Then, starting from the third counting cycle, in the first frame (Frame 1), or the starting frame, all row pixels are controlled to synchronously switch refresh rates, cycling through Refresh, Keep, and Keep states from the first frame (Frame 1) to the third frame (Frame 3) of each counting cycle. In the current counting cycle, "the third frame (Frame 3) of the first counting cycle, which is the third frame out of twelve frames," it remains in the Refresh state and does not immediately enter a low refresh rate. This can also be understood as reliably entering a low refresh rate only in an even-numbered frame—the second frame of the second counting cycle.

[0076] For the fourth row (Line4), firstly, the display refresh rate of the fourth row's pixels is controlled to switch from a 120Hz first refresh rate to a 40Hz second refresh rate in the first frame (Frame1) of the second counting cycle (the fourth frame out of twelve frames), corresponding to the Refresh state. Then, in the second frame (Frame2) of the second counting cycle, it switches to the Keep state; and in the third frame (Frame3) of the second counting cycle, it remains in the Keep state. Then, starting from the third counting cycle, in the first frame (Frame1), or the starting frame, all row pixels are controlled to synchronously switch refresh rates, cycling through Refresh, Keep, and Keep states sequentially from the first frame (Frame1) to the third frame (Frame3) of each counting cycle. This can also be understood as reliably entering the low refresh rate only in even-numbered frames—the second frame of the second counting cycle.

[0077] For the fifth row (Line 5), firstly, the display refresh rate of the fifth row's pixels is switched to Keep state and enters low refresh rate in the second frame (Frame 2) of the second counting cycle, which is the fifth frame out of twelve frames. Then, it remains in Keep state in the third frame (Frame 3) of the second counting cycle. Then, starting from the third counting cycle, in the first frame (Frame 1), or the starting frame, the refresh rate of all row pixels is switched synchronously, cycling through Refresh, Keep, Keep states from the first frame (Frame 1) to the third frame (Frame 3) of each counting cycle. This can be understood as reliably entering low refresh rate only in even-numbered frames—the second frame of the second counting cycle.

[0078] For the sixth row (Line 6), firstly, the display refresh rate of the sixth row's pixels is controlled to switch from a 120Hz first refresh rate to a 40Hz second refresh rate in the first frame (Frame 1) of the third counting cycle (the seventh frame out of twelve frames), corresponding to the Refresh state. Then, in the second frame (Frame 2) of the third counting cycle, it switches to the Keep state, entering a low refresh rate. In the third frame (Frame 3) of the third counting cycle, it remains in the Keep state. Then, starting from the fourth counting cycle, in the first frame (Frame 1) or starting frame of each counting cycle, all row pixels are controlled to synchronously switch refresh rates, cycling through Refresh, Keep, and Keep states sequentially from the first frame (Frame 1) to the third frame (Frame 3) of each counting cycle. In the current counting cycle, "the third frame (Frame 3) of the second counting cycle (the sixth frame out of twelve frames)," it remains in the Refresh state and does not immediately enter a low refresh rate. This can also be understood as reliably entering a low refresh rate only in even-numbered frames—the second frame of the third counting cycle.

[0079] Thus, in comparison Figure 5 and Figure 7 It can also be seen that by adding a synchronization frame design, the low refresh rate can be adjusted to be delayed by one frame instead of one counting cycle. This not only ensures that different rows have the same polarity in frames such as the seventh frame (Frame 7) and subsequent frames, thus eliminating the problem of different rows having different polarities, but also avoids the occurrence of... Figure 3 Within the dashed box shown, the phenomenon of continuously refreshing frames with negative or positive polarity can solve the problem of large brightness changes, improve flickering, and ensure faster entry into low refresh rates, thereby better reducing display power consumption, which can generally reduce power consumption by about 8.5% to 20%.

[0080] For example, Figure 8 It also schematically shows Figure 7The timing diagram corresponding to the scheme shown is shown. Figure 8 The diagram illustrates: (1) Total frame count results: from frame 1 to frame 9; (2) Periodic frame count results with 3 frames as a cycle; (3) Polarity changes: from frame 1 to frame 9, the polarity of each adjacent frame is opposite, odd-numbered frames are positive polarity, and even-numbered frames are negative polarity; (4) Changes in the display content of the second line: from frame 1 to frame 9, the order is: dynamic, static, static, static, static, static, static, static, static, static, static, static, satisfying the second Line 2 enters low refresh in the second frame (Frame 2); (5) High and low refresh flags: when the flag is high, it is in dynamic high refresh state; when the flag is low, it is in static low refresh state; (6) The clock signal provided by the driving clock terminal CLKC satisfies: it is in a high-level valid state in each frame; (7) The clock signal provided by the enable clock terminal CLK satisfies: in the first frame of each counting cycle, it is in a high-level valid state, i.e., in the Refresh state, and in the other frames of each counting cycle, it is in a low-level invalid state, i.e., in the Keep state, and so on. (8) The corresponding refresh state satisfies: from the first frame (Frame 1) to the ninth frame (Frame 9), it is refresh, keep, keep, refresh, keep, keep, refresh, keep, keep. (9) The corresponding high and low refresh situations satisfy: from the first frame (Frame 1) to the ninth frame (Frame 9), it is high refresh, low refresh, low refresh, low refresh, low refresh, low refresh, low refresh, low refresh, low refresh.

[0081] For example, combining Figure 9 If, with a counting cycle of 3, the detection module 02 detects that the first line (Line 1) enters a high refresh rate in the fourth frame (Frame 4), the second line (Line 2) enters a high refresh rate in the fifth frame (Frame 5), the third line (Line 3) enters a high refresh rate in the sixth frame (Frame 6), the fourth line (Line 4) enters a high refresh rate in the seventh frame (Frame 7), the fifth line (Line 5) enters a high refresh rate in the eighth frame (Frame 8), and the sixth line (Line 6) enters a high refresh rate in the ninth frame (Frame 9), the control module 03 can control the display driver circuit to perform the following operations: For the first row (Line 1), firstly, the display refresh rate of the first row's pixels is controlled to switch from a 40Hz first refresh rate to a 120Hz second refresh rate in the first frame (Frame 1) of the second counting cycle (the fourth frame out of twelve frames), corresponding to the Refresh state. Then, in the second frame (Frame 2) of the second counting cycle, it switches to the Refresh state, entering high refresh; and in the third frame (Frame 3) of the second counting cycle, it remains in the Refresh state. Next, starting from the second counting cycle, in the first frame (Frame 1) or starting frame of each counting cycle, all row pixels are controlled to synchronously switch refresh rates. In subsequent counting cycles, the first frame (Frame 1) to the third frame (Frame 3) cycle through the Refresh, Refresh, Refresh states sequentially. This can also be understood as entering high refresh only in even-numbered frames—the second frame of the second counting cycle.

[0082] For the second line (Line 2), firstly, the display refresh rate of the second line's pixels switches to Refresh state and enters high refresh mode in the second frame (Frame 2) of the second counting cycle, which is the fifth frame out of twelve frames. Then, it remains in Refresh state in the third frame (Frame 3) of the second counting cycle. Next, starting from the second counting cycle, in the first frame (Frame 1) or starting frame of each counting cycle, all line pixels are controlled to synchronously switch refresh rates. In subsequent counting cycles, the first frame (Frame 1) to the third frame (Frame 3) cycle through Refresh, Refresh, Refresh states. This can also be understood as entering high refresh mode only in even-numbered frames—the second frame of the second counting cycle.

[0083] For the third row (Line 3), firstly, the display refresh rate of the third row's pixels is controlled to switch from a 40Hz first refresh rate to a 120Hz second refresh rate in the first frame (Frame 1) of the third counting cycle (the seventh frame out of twelve frames), corresponding to the Refresh state. Then, in the second frame (Frame 2) of the third counting cycle, it switches to the Refresh state, entering high refresh. In the third frame (Frame 3) of the third counting cycle, it remains in the Refresh state. Next, starting from the fourth counting cycle, in the first frame (Frame 1) or starting frame of each counting cycle, all row pixels are controlled to synchronously switch refresh rates. In subsequent counting cycles, the first frame (Frame 1) to the third frame (Frame 3) cycle through the Refresh, Refresh, Refresh states sequentially. In the third frame (Frame 3) of the second counting cycle (the sixth frame out of twelve frames), it remains in the Keep state and does not immediately enter high refresh. This can also be understood as entering high refresh only in even-numbered frames—the second frame of the third counting cycle.

[0084] For the fourth row (Line4), firstly, the display refresh rate of the fourth row's pixels is controlled to switch from a 40Hz first refresh rate to a 120Hz second refresh rate in the first frame (Frame1) of the third counting cycle, which is the seventh frame out of twelve frames, corresponding to the Refresh state. Then, in the second frame (Frame2) of the third counting cycle, it switches to the Refresh state; and in the third frame (Frame3) of the third counting cycle, it remains in the Refresh state. Next, starting from the fourth counting cycle, in the first frame (Frame1) or starting frame of each counting cycle, all row pixels are controlled to synchronously switch refresh rates. In subsequent counting cycles, the first frame (Frame1) to the third frame (Frame3) cycle in a Refresh, Refresh, Refresh state. This can also be understood as entering high refresh rate only in even-numbered frames—the second frame of the third counting cycle.

[0085] For the fifth row (Line 5), firstly, the display refresh rate of the fifth row's pixels switches to Refresh state and enters high refresh rate in the second frame (Frame 2) of the third counting cycle, which is the eighth frame out of twelve frames. Then, it remains in Refresh state in the third frame (Frame 3) of the second counting cycle. Next, starting from the fourth counting cycle, in the first frame (Frame 1), or the starting frame, all row pixels are controlled to synchronously switch refresh rates. In subsequent counting cycles, the first frame (Frame 1) through the third frame (Frame 3) cycle through Refresh, Refresh, Refresh states. This can be understood as entering high refresh rate only in even-numbered frames—the second frame of the third counting cycle.

[0086] For the sixth row (Line 6), firstly, the display refresh rate of the sixth row's pixels is controlled in the first frame (Frame 1) of the fourth counting cycle, which is the tenth frame out of twelve frames. It prepares to switch from a first refresh rate of 40Hz to a second refresh rate of 120Hz, corresponding to the Refresh state. Then, in the second frame (Frame 2) of the fourth counting cycle, it switches to the Refresh state, entering high refresh. In the third frame (Frame 3) of the fourth counting cycle, it remains in the Refresh state. Next, starting from the fifth counting cycle (not shown again), in the first frame (Frame 1) or starting frame of each counting cycle, all row pixels are controlled to synchronously switch refresh rates. In subsequent counting cycles, the first frame (Frame 1) to the third frame (Frame 3) cycle in a Refresh, Refresh, Refresh state. In the third frame (Frame 3) of the third counting cycle, which is the ninth frame out of twelve frames, it remains in the Keep state and does not immediately enter high refresh. This can also be understood as entering high refresh only in even-numbered frames—the second frame of the fourth counting cycle.

[0087] Understandably, taking the third line (Line 3) as an example, combined with... Figure 9As shown in the dashed box, if the high refresh rate is entered directly in the sixth frame (i.e., switching to Refresh state directly in the third frame (Frame3) of the second counting cycle), then in that second counting cycle, the first frame (Frame1) will be of negative polarity, the second frame (Frame2) will remain in the Keep state and retain the negative polarity of the first frame (Frame1), and the third frame (Frame3) will be refreshed to negative polarity due to the switch to Refresh state. This will result in consecutive refresh frames with the same polarity, causing significant brightness variations. In this embodiment, by adding a synchronization frame and delaying the entry into high refresh by one frame, the phenomenon of consecutive refresh frames with the same polarity can be avoided, thus resolving the problem of large brightness variations and improving flickering. Furthermore, it ensures faster entry into high refresh.

[0088] For example, Figure 10 It also schematically shows Figure 9 The timing diagram corresponding to the scheme shown is shown. Figure 10 The diagram illustrates: (1) Total frame count results: from frame 1 to frame 9; (2) Periodic frame count results with 3 frames as a cycle; (3) Polarity changes: from frame 1 to frame 9, the polarity of each adjacent frame is opposite, odd-numbered frames are positive polarity, and even-numbered frames are negative polarity; (4) Changes in the display content of the third line: from frame 1 to frame 9, the sequence is: static, static, static, static, static, static, dynamic, dynamic, dynamic, satisfying the third line (Li ne3) Enter high refresh in the sixth frame (Frame6); (5) High and low refresh flags, when the flag is high, it is in dynamic high refresh state, and when the flag is low, it is in static low refresh state; (6) The clock signal provided by the driving clock terminal CLKC satisfies: it is in a high-potential effective state in each frame; (7) The clock signal provided by the enable clock terminal CLK satisfies: for low refresh scenarios, in the first frame of each counting cycle, it is in a high-potential effective state, that is, in the Refresh state, and in the other frames of each counting cycle, it is in a low-potential ineffective state, that is, in the Keep state, and so on. For high refresh scenarios, in each frame of each counting cycle, it is in a high-potential effective state, that is, in the Refresh state. (8) The corresponding refresh state satisfies: from the first frame (Frame1) to the ninth frame (Frame9), it is refresh, keep, keep, refresh, keep, keep, refresh, refresh, refresh. (9) The corresponding high and low refresh rates are: from the first frame (Frame1) to the ninth frame (Frame9), the refresh rates are low, low, low, low, low, low, low, low, high, high.

[0089] Optionally, in Figure 2 Based on, combined Figure 11 It can also be seen that the detection module 02 described in the embodiments of this application may include: a receiving unit 021 and a detection unit 022.

[0090] The receiving unit 021 can be configured to receive display information.

[0091] The detection unit 022 can be configured to: detect whether the display refresh rate of the display panel meets the refresh rate switching condition from the first refresh rate to the second refresh rate based on the display information.

[0092] For example, the displayed information may include multiple consecutive frames of image data. The detection unit 022 can be configured as follows: The display refresh rate corresponding to the current moment of the image is determined based on the adjacent multiple frames of image data in a series of consecutive frames; Compare the current display refresh rate with the previous display refresh rate to determine the change in display refresh rate. Based on the comparison results, determine whether the display panel's refresh rate meets the refresh rate switching conditions for switching from the first refresh rate to the second refresh rate.

[0093] In other words, firstly, the detection unit 022 can analyze multiple consecutive frames of image data in the displayed information to determine whether the content of the image has changed, thereby determining the display refresh rate requirement of the current display scene and reliably determining the display refresh rate (e.g., high refresh rate or low refresh rate) that the image is currently adapted to. Then, the detection unit 022 can further compare the display refresh rate determined at the current moment with the display refresh rate determined at the adjacent previous moment to determine whether the refresh rate has changed and whether the display refresh rate has switched from a first refresh rate to a second refresh rate.

[0094] Optionally, for multi-frame image data, the detection unit 022 can determine the display refresh rate at the current moment by comparing any two adjacent frames of image data to detect whether the images of any two adjacent frames have changed.

[0095] For example, the detection unit 022 can detect whether the image frames of any two adjacent frames have changed by comparing the differences in pixel values ​​(e.g., RGB values). If the difference is greater than a difference threshold, it can be determined that the image frames have changed, indicating a dynamic image. Accordingly, the display refresh rate adapted to the current image frame should be a high refresh rate to avoid display ghosting, stuttering, or other abnormalities. If the difference is not greater than the difference threshold, it can be determined that the image frames have not changed, indicating a static image. Accordingly, the display refresh rate adapted to the current image frame should be a low refresh rate to avoid unnecessary power consumption. However, the detection method is not limited to the above. For example, in some other embodiments, the detection unit 022 can also calculate the average pixel values ​​of multiple consecutive frames of image data and determine the corresponding display refresh rate at the current moment based on the average. For example, if the average value is greater than a pixel value threshold, it can be determined that the content update rate of the image frame is relatively fast, and accordingly, the display refresh rate adapted to the current image frame should be a high refresh rate. If the average value is not greater than the pixel value threshold, it can be determined that the content update rate of the image is slow. Accordingly, it can be determined that the display refresh rate adapted to the image at the current moment should be a low refresh rate.

[0096] It is understood that the detection unit 022 can determine the refresh rate in the above manner at any given moment. Furthermore, the detection unit 022 can further reliably determine whether the display refresh rate has switched from a low refresh rate to a high refresh rate or from a high refresh rate to a low refresh rate by comparing the display refresh rate determined at the current moment with the display refresh rate determined at the previous moment; that is, reliably determine whether the display refresh rate meets the refresh rate switching conditions described above.

[0097] For example, if the display refresh rate determined at the current moment is different from the display refresh rate determined at the previous moment, the detection unit 022 can determine that the refresh rate has changed. If the display refresh rate determined at the current moment is the same as the display refresh rate determined at the previous moment, the detection unit 022 can determine that the refresh rate has not changed. Furthermore, when the aforementioned comparison result indicates a refresh rate change, the detection unit 022 can also determine whether the refresh rate change is a switch from a low refresh rate to a high refresh rate or a switch from a high refresh rate to a low refresh rate based on whether the display refresh rate determined at the current moment is higher or lower than the display refresh rate determined at the previous moment, i.e., determine the refresh rate switching direction.

[0098] Optionally, the aforementioned difference threshold, first frequency threshold, second frequency threshold, or pixel value threshold can all be thresholds pre-configured in the detection unit 022, and can be dynamically adjusted according to different display modes or application scenarios.

[0099] Optionally, in Figure 11 On this basis, Figure 12 A schematic diagram of a display chip and a display driver circuit is shown. Figure 12 It can be seen that: First, the host computer can transmit images to the Timing Controller (TCON). The transmitted images can include sequentially changing dynamic, static, and other images. Then, the partition control unit in the TCON can transmit control timing sequences such as refresh, refresh, hold, and refresh to the GOA circuit based on the image-related display information transmitted by the host computer. This allows the GOA circuit, in conjunction with the source IC, to drive and control the display panel to display the images sequentially from top to bottom according to the display partitions: dynamic image refresh, dynamic image refresh, static image hold, and dynamic image refresh.

[0100] It is understood that the display chip can refer to the TCON mentioned here. And, as described above, the GOA circuit and the source driver circuit (Source IC) are also the display driver circuit described above. Furthermore, a pixel can include a data write transistor and a drive transistor. Under the timing control of the TCON, the GOA circuit can transmit a gate drive signal to the data write transistor to control its switching. The Source IC can transmit a data signal to the drive transistor via the activated data write transistor. In this way, the drive transistor can be controlled to control the light-emitting element of the pixel to emit light based on the data signal.

[0101] Optionally, as described above, in one embodiment, the first refresh rate may be greater than the second refresh rate. That is, the application scenario of this application embodiment can be a scenario of switching from a high refresh rate to a low refresh rate. Of course, it is not limited to this.

[0102] Optionally, the second refresh rate (i.e., the low refresh rate) can be 1 / n of the first refresh rate (i.e., the high refresh rate), and the counting period can be n, where n can be an integer greater than 1.

[0103] For example, the counting period n can be 3. The first refresh rate can be 120Hz, and the second refresh rate can be 40Hz.

[0104] Optionally, as described above, the display chip described in the embodiments of this application can be used to control the display driving circuit to drive the display panel to display multiple rows of pixels in a manner that reverses the polarity of adjacent frames. However, it is not limited to this.

[0105] As described above, the display chip provided in this application embodiment can ensure that the display panel is free from problems such as blocking and flickering during the process of changing the refresh rate of the partition, thereby improving the image quality and improving power consumption performance, that is, reducing power consumption.

[0106] In summary, this application provides a display chip. Because the control module in this display chip can control the display driver circuit to perform refresh rate switching operations by combining the display refresh rate switching status and the counting position of the counting module, the counting position trigger conditions can be flexibly configured so that the display refresh rate is switched from one refresh rate to another only at a specific position. This ensures that different rows have the same polarity, solves the brightness difference problem caused by different polarities of different rows, and thus avoids display defects, ensuring better display effects.

[0107] This application also provides a display control method, which is applied to the display chip (e.g., timing controller TCON) described above, and the display chip is used to control the display driving circuit to drive the display panel to display multiple rows of pixels in a polarity reversal manner. Figure 13 As shown, the method includes: Step 1301: Count the display frames of the display panel.

[0108] Step 1302: Check whether the display refresh rate of the display panel meets the refresh rate switching condition from the first refresh rate to the second refresh rate, wherein the first refresh rate and the second refresh rate have different values.

[0109] Step 1303: Based on whether the display refresh rate meets the refresh rate switching conditions and the counting position, control the display driver circuit to perform the refresh rate switching operation.

[0110] It is understandable that, since the display control method has essentially the same technical effect as the aforementioned display chip, for the sake of brevity, the technical effect of the display control method will not be described again here.

[0111] This application also provides a display control method, which is applied to the display chip (e.g., timing controller TCON) described above, and the display chip is used to control the display driving circuit to drive the display panel to display multiple rows of pixels in a polarity reversal manner. Figure 14 As shown, the method includes: Step 1401: Receive display information and frame synchronization signal.

[0112] Step 1402: Based on the display information, determine whether the display refresh rate of the display panel meets the refresh rate switching condition from the first refresh rate to the second refresh rate, wherein the first refresh rate and the second refresh rate have different values.

[0113] Step 1403: Count the display frames of the display panel based on the frame synchronization signal.

[0114] Step 1404: When it is determined that the display refresh rate meets the refresh rate switching conditions, a corresponding refresh rate switching control signal is generated and output to the display driver circuit according to the counting position, so as to control the display driver circuit to perform the refresh rate switching operation.

[0115] It is understood that the frame synchronization signal (VSYNC) is a signal used to mark the start of each frame. In this embodiment, the display chip can reliably perform cyclic counting of display frames in response to the valid edge of the frame synchronization signal. For example, when the valid edge arrives, the internal counting module is driven to increment by 1, and the count is accumulated repeatedly in one counting cycle. The valid edge is the transition edge from the invalid potential to the valid potential. For example, the invalid potential can be a low potential, and the valid potential can be a high potential. Correspondingly, the valid edge can be a rising edge from a low potential to a high potential. Optionally, the display information and the frame synchronization signal can be transmitted to the display chip by an upstream device (e.g., a host).

[0116] Optionally, counting the display frames of the display panel (i.e., step 1403 above) may include: cyclically counting the display frames of the display panel at a counting period greater than 1. Based on this, controlling the display driver circuit to perform a refresh rate switching operation (i.e., step 1404 above) may include: In one alternative implementation: the control display driving circuit controls the display refresh rate of the current row of pixels to switch to the second refresh rate at the current counting position, and from the end of the current counting cycle to the beginning of the adjacent counting cycle, controls the display refresh rates of multiple rows of pixels to switch synchronously at the beginning frame of each counting cycle.

[0117] In another alternative implementation: when the counting position reaches the start frame of the next counting cycle adjacent to the current counting cycle, the control display driving circuit controls the display refresh rate of the current row of pixels to switch to the second refresh rate, and from the end of the next counting cycle to the start of the next counting cycle, the display refresh rates of multiple rows of pixels are controlled to switch synchronously at the start frame of each counting cycle.

[0118] In another alternative implementation: when the current counting position is an even frame or the counting position reaches the next even frame adjacent to the current odd frame, the control display driving circuit controls the display refresh rate of the current row of pixels to switch to the second refresh rate, and from the end of the counting period of the even frame, the display refresh rate of multiple rows of pixels is controlled to switch synchronously at the beginning of the first frame of each counting period.

[0119] Optionally, as described above, the display information may include multiple consecutive frames of image data. Accordingly, based on the display information, determining whether the display refresh rate of the display panel meets the refresh rate switching condition from the first refresh rate to the second refresh rate (i.e., step 1402 above) may include: The display refresh rate corresponding to the current moment of the image is determined based on the adjacent multiple frames of image data in a series of consecutive image data.

[0120] Compare the current display refresh rate with the previous display refresh rate to determine the change in display refresh rate.

[0121] Based on the comparison results, determine whether the display panel's refresh rate meets the refresh rate switching conditions for switching from the first refresh rate to the second refresh rate.

[0122] It is understandable that, since the display control method has essentially the same technical effect as the aforementioned display chip, for the sake of brevity, the technical effect of the display control method will not be described again here.

[0123] This application also provides a display chip. This display chip can be used to perform functions such as... Figure 14 The display control method is shown. Optionally, the display chip can be the timing controller TCON described above.

[0124] It is understandable that, since the display chip and the aforementioned display control method have essentially the same technical effects, for the sake of brevity, the technical effects of the display chip will not be described again here.

[0125] This application also provides a display device. (In conjunction with...) Figure 12 The display device includes: a display panel, a display driving circuit, and a display chip as described above.

[0126] Furthermore, the display driving circuit may include, for example, a gate driving circuit (e.g., a GOA circuit) and a source driving circuit (Source IC). The display chip can be connected to the gate driving circuit and the source driving circuit respectively, and is used to transmit control timing to the gate driving circuit and the source driving circuit to control the gate driving circuit to cooperate with the source driving circuit to control the display panel display.

[0127] Optionally, the display device described in this application embodiment can be a liquid crystal display device. Furthermore, the display device can be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and e-books, as well as any product or component with display functionality.

[0128] It is understandable that, since the display device and the aforementioned display chip have essentially the same technical effects, for the sake of brevity, the technical effects of the display device will not be described again here.

[0129] It is understood that the terminology used in the embodiments section of this application is for explaining the embodiments of this application only, and is not intended to limit this application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0130] For example, the terms "first," "second," or "third," and similar words used in the patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one," and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as "comprising" or "including" mean that the element or object preceding "comprising" covers the element or object listed after "comprising" or "including," and does not exclude other elements or objects. "Above," "below," "left," or "right," etc., are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection. "And / or" indicates that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0131] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display control method, characterized in that, Applied to a display chip, the display chip is used to control a display driving circuit to drive a display panel comprising multiple rows of pixels in a polarity-reversed manner; the method includes: Receive display information and frame synchronization signals; Based on the display information, determine whether the display refresh rate of the display panel meets the refresh rate switching condition from the first refresh rate to the second refresh rate, wherein the first refresh rate and the second refresh rate have different values; The display frames of the display panel are counted based on the frame synchronization signal. When it is determined that the display refresh rate meets the refresh rate switching condition, a corresponding refresh rate switching control signal is generated and output to the display driver circuit according to the counting position, so as to control the display driver circuit to perform the refresh rate switching operation.

2. The method according to claim 1, characterized in that, Counting the display frames of the display panel includes: cyclically counting the display frames of the display panel at a counting period greater than 1; and controlling the display driving circuit to perform a refresh rate switching operation, including: The display driving circuit controls the display refresh rate of the current row of pixels to switch to the second refresh rate at the current counting position, and controls the display refresh rate of the multiple rows of pixels to switch synchronously at the beginning frame of each counting cycle, starting from the end of the current counting cycle.

3. The method according to claim 1, characterized in that, Counting the display frames of the display panel includes: cyclically counting the display frames of the display panel at a counting period greater than 1; and controlling the display driving circuit to perform a refresh rate switching operation includes: When the display driving circuit reaches the starting frame of the next counting cycle adjacent to the current counting cycle at the counting position, it controls the display refresh rate of the current row of pixels to switch to the second refresh rate. Starting from the next counting cycle after its end, at the beginning frame of each counting cycle, it controls the display refresh rate of the multiple rows of pixels to switch synchronously.

4. The method according to claim 1, characterized in that, Counting the display frames of the display panel includes: cyclically counting the display frames of the display panel at a counting period greater than 1; and controlling the display driving circuit to perform a refresh rate switching operation includes: When the current counting position is an even frame or the counting position reaches the next even frame adjacent to the current odd frame, the display driving circuit controls the display refresh rate of the current row of pixels to switch to the second refresh rate. Starting from the counting period adjacent to the end of the counting period of the even frame, the display refresh rate of the multiple rows of pixels is controlled to switch synchronously at the beginning frame of each counting period.

5. The method according to any one of claims 1 to 4, characterized in that, The display information includes continuous multi-frame image data; Based on the display information, determining whether the display refresh rate of the display panel meets the refresh rate switching conditions for switching from a first refresh rate to a second refresh rate includes: Based on each adjacent frame of image data in the continuous multi-frame image data, determine the display refresh rate corresponding to the current moment of the image screen; Compare the display refresh rate at the current moment with the display refresh rate at the previous moment to determine the change in the display refresh rate; Based on the comparison results, it is determined whether the display refresh rate of the display panel meets the refresh rate switching condition for switching from the first refresh rate to the second refresh rate.

6. A display chip, characterized in that, The display chip is used to perform the display control method as described in any one of claims 1 to 5.

7. A display chip, characterized in that, The display chip is used to control the display driving circuit to drive the display panel to display multiple rows of pixels in a polarity reversal manner; and the display chip includes: The counting module is configured to count the display frames of the display panel; The detection module is configured to detect whether the display refresh rate of the display panel meets the refresh rate switching condition from the first refresh rate to the second refresh rate, wherein the first refresh rate and the second refresh rate have different values; The control module is configured to control the display driver circuit to perform a refresh rate switching operation based on whether the display refresh rate meets the refresh rate switching conditions and the counting position.

8. The display chip according to claim 7, characterized in that, The counting module is configured to cyclically count the display frames of the display panel according to a counting period greater than 1. The control module is configured to: when the display refresh rate meets the refresh rate switching condition, control the display driving circuit to perform the following refresh rate switching operation: control the display refresh rate of the current row of pixels to switch to the second refresh rate at the current counting position, and control the display refresh rate of the multiple rows of pixels to switch synchronously at the beginning frame of each counting period, starting from the adjacent counting period after the end of the current counting period.

9. The display chip according to claim 7, characterized in that, The counting module is configured to cyclically count the display frames of the display panel according to a counting period greater than 1. The control module is configured to: when the display refresh rate meets the refresh rate switching condition, control the display driving circuit to perform the following refresh rate switching operation: when the counting position reaches the start frame of the next counting cycle adjacent to the current counting cycle, control the display refresh rate of the current row of pixels to switch to the second refresh rate, and from the end of the next counting cycle, start of the next counting cycle, control the display refresh rate of the multiple rows of pixels to switch synchronously at the start frame of each counting cycle.

10. The display chip according to claim 7, characterized in that, The counting module is configured to cyclically count the display frames of the display panel according to a counting period greater than 1. The control module is configured to: when the display refresh rate meets the refresh rate switching condition, control the display driving circuit to perform the following refresh rate switching operation: when the current counting position is an even frame or the counting position reaches the next even frame adjacent to the current odd frame, control the display refresh rate of the current row of pixels to switch to the second refresh rate, and starting from the counting period adjacent to the end of the counting period of the even frame, control the display refresh rate of the multiple rows of pixels to switch synchronously at the beginning frame of each counting period.

11. The display chip according to any one of claims 7 to 10, characterized in that, The detection module includes: The receiving unit is configured to receive display information; The detection unit is configured to: detect, based on the display information, whether the display refresh rate of the display panel meets the refresh rate switching condition for switching from the first refresh rate to the second refresh rate.

12. The display chip according to claim 11, characterized in that, The display information includes multiple consecutive frames of image data; the detection unit is configured as follows: Based on each adjacent frame of image data in the continuous multi-frame image data, determine the display refresh rate corresponding to the current moment of the image screen; Compare the display refresh rate at the current moment with the display refresh rate at the previous moment to determine the change in the display refresh rate; Based on the comparison results, it is determined whether the display refresh rate of the display panel meets the refresh rate switching condition for switching from the first refresh rate to the second refresh rate.

13. The display chip according to any one of claims 7 to 10, characterized in that, The first refresh rate is greater than the second refresh rate.

14. The display chip according to claim 13, characterized in that, The second refresh rate is 1 / n of the first refresh rate, and the counting period is n, where n is an integer greater than 1.

15. The display chip according to any one of claims 7 to 10, characterized in that, The display chip is used to control the display driving circuit to drive the display panel to display multiple rows of pixels in a manner that reverses the polarity of adjacent frames.

16. A display control method, characterized in that, Applied to a display chip, the display chip is used to control a display driving circuit to drive a display panel comprising multiple rows of pixels in a polarity-reversed manner; the method includes: Count the display frames of the display panel; The display panel is checked to see if its refresh rate meets the refresh rate switching condition from the first refresh rate to the second refresh rate, wherein the first refresh rate and the second refresh rate have different values; Based on whether the display refresh rate meets the refresh rate switching conditions and the counting position, the display driver circuit is controlled to perform a refresh rate switching operation.

17. A display device, characterized in that, The display device includes: a display panel, a display driving circuit, and a display chip as described in any one of claims 6 to 15.

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