A gate driving circuit and a display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel. The gate driving circuit comprises N cascaded gate driving units. The nth gate driving unit comprises: a pull-up module configured to charge a pull-up node; a stage transmission output module configured to output a stage transmission signal of a current stage; a first local brush control module configured to generate a voltage on a first local brush control node under the action of a voltage of the pull-up node and the stage transmission signal of the current stage; a second local brush control module configured to control electrical connection between the first local brush control node and a driving control node if the current stage is a refresh row, and configured to control disconnection between the first local brush control node and the driving control node if the current stage is a non-refresh row; and a driving output module configured to output a gate driving signal of the current stage under the action of a voltage on the driving control node and a clock signal of the current stage. The application can reduce the aging speed of the display panel.

Description

Technical Field

[0001] This application belongs to the field of display driver technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] Among related technologies, Gate Driver Less (GDL) is a technical solution based on amorphous silicon (a-SiTFT) fabrication that directly integrates the shift register circuit of an external gate driver integrated circuit onto the display panel array substrate. This solution can completely replace a separate gate driver IC, simplifying the display driver architecture through process integration, thereby significantly reducing device procurement and module assembly costs. However, the frequent pixel refresh control by the gate driver IC will accelerate the aging of the display panel and reduce its lifespan.

[0003] Therefore, how to reduce the aging rate of display panels is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit and a display panel, which solves the problem of how to reduce the aging rate of the display panel.

[0005] In a first aspect, this application provides a gate driving circuit, the gate driving circuit comprising N cascaded gate driving units, wherein the nth stage gate driving unit comprises: a pull-up module connected to the pull-up node of the current stage, configured to: charge the pull-up node in response to the output signal of the nth stage gate driving unit; a stage transmission output module connected to the pull-up node and the clock signal line of the current stage, configured to: output the stage transmission signal of the current stage under the action of the voltage on the pull-up node and the clock signal of the current stage; and a first brush control module connected to the pull-up node, the stage transmission output module of the current stage, and the first brush control node of the current stage, respectively, configured to: charge the pull-up node under the action of the voltage on the pull-up node and the clock signal of the current stage; and a first brush control module connected to the pull-up node, the stage transmission output module of the current stage, and the first brush control node of the current stage, configured to: charge the pull-up node under the action of the voltage on the pull-up node ... module of the current stage, configured to: charge the pull-up node under the action of the voltage on the pull-up node; and a first brush control module connected to the pull-up node, the stage transmission output module of the current stage, and the Under the influence of the voltage and the current stage's transmission signal, a voltage is generated on the first local refresh control node; the second local refresh control module is connected to both the first local refresh control node and the current stage's drive control node. In local refresh mode, if the current stage is a refresh row, it controls the electrical connection between the first local refresh control node and the drive control node; if the current stage is a non-refresh row, it controls the disconnection between the first local refresh control node and the drive control node; the drive output module is connected to the drive control node and the clock signal line of the current stage, and is configured to output the gate drive signal of the current stage under the influence of the voltage on the drive control node and the current stage's clock signal.

[0006] Optionally, the drive output module includes: a control submodule, which is connected to the drive control node, the clock signal line of the current stage, and the drive submodule, and is configured to: control the electrical connection between the clock signal line of the current stage and the drive submodule under the action of the voltage on the drive control node; the drive submodule is also connected to the drive control node and is configured to: output the gate drive signal of the current stage under the action of the voltage of the drive control node and the clock signal of the current stage.

[0007] Optionally, the first local refresh control module includes: a first transistor; the control terminal of the first transistor is connected to the pull-up node, the first terminal of the first transistor is connected to the output terminal of the stage transmission output module, and the second terminal of the first transistor is connected to the first local refresh control node.

[0008] Optionally, the second brush control module includes: a second transistor, a third transistor, a fourth transistor, and a fifth transistor; the control terminal of the second transistor is connected to the first brush control terminal, the first terminal of the second transistor and the first terminal of the third transistor are connected to the first brush control node, and the second terminal of the second transistor, the first terminal of the fourth transistor, and the control terminal of the fifth transistor are connected to the drive control node; the control terminal of the third transistor is connected to the second brush control terminal, and the second terminal of the third transistor, the control terminal of the fourth transistor, and the first terminal of the fifth transistor are connected to the second brush control node; the second terminal of the fourth transistor and the second terminal of the fifth transistor are connected to a low-level terminal.

[0009] Optionally, the control submodule includes: a sixth transistor; the control terminal of the sixth transistor is connected to the drive control node, the first terminal of the sixth transistor is connected to the clock signal line of the current stage, and the second terminal of the sixth transistor is connected to the drive submodule.

[0010] Optionally, the driving submodule includes a seventh transistor and a first capacitor; the control terminal of the seventh transistor is connected to the driving control node and the first terminal of the first capacitor respectively, the first terminal of the seventh transistor is connected to the clock signal line of the current stage, and the second terminal of the seventh transistor is connected to the second terminal of the first capacitor.

[0011] Optionally, the drive output module includes: a control submodule, which is connected to the first local brush control node, the clock signal line of the current stage, and the drive submodule, and is configured to: control the electrical connection between the clock signal line of the current stage and the drive submodule under the action of the voltage on the first local brush control node; the drive submodule is also connected to the drive control node and is configured to: output the gate drive signal of the current stage under the action of the voltage of the drive control node and the clock signal of the current stage.

[0012] Optionally, the control submodule includes: a sixth transistor; the control terminal of the sixth transistor is connected to the first local brush control node, the first terminal of the sixth transistor is connected to the clock signal line of the current stage, and the second terminal of the sixth transistor is connected to the driving submodule.

[0013] Optionally, the stage output module includes: an eighth transistor and a second capacitor; the control terminal of the eighth transistor and the first terminal of the second capacitor are connected to the pull-up node, the first terminal of the eighth transistor is connected to the clock signal line of the current stage, and the second terminal of the eighth transistor is connected to the second terminal of the second capacitor and serves as the output terminal of the stage output signal.

[0014] Secondly, this application provides a display panel including a display area and a non-display area, the display area including a plurality of scan lines, the non-display area including a gate driving circuit as described in any one of the first aspects, and the driving output module of the gate driving circuit being connected to at least one of the scan lines.

[0015] The technical solution provided in this application has at least the following beneficial effects:

[0016] In this application, the pull-up module responds to the output signal of the ni-th stage gate drive unit to charge the pull-up node. The stage transmission output module outputs the stage transmission signal of the current stage under the action of the voltage of the pull-up node and the clock signal of the current stage. The first brush control module generates a voltage on the first brush control node under the action of the voltage of the pull-up node and the stage transmission signal of the current stage. If the current stage is a refresh row, by setting the second brush control module, the first brush control node is electrically connected to the drive control node to transmit the voltage on the first brush control node to the drive control node, so as to control the drive output module to output the gate drive signal of the current stage and refresh the pixels of the current stage. If the current stage is a non-refresh row, by setting the first brush control node to disconnect from the drive control node, the voltage on the first brush control node will not be transmitted to the drive control node, so as to control the drive output module to stop outputting the gate drive signal of the current stage, thereby not refreshing the pixels of the current stage, thus avoiding frequent refresh of non-refresh rows and reducing the aging speed. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 A circuit diagram of a gate driving circuit provided in an embodiment of this application is shown.

[0019] Figure 2 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown.

[0020] Figure 3 A timing diagram of the gate drive circuit provided in an embodiment of this application is shown.

[0021] Figure 4 Another timing diagram of the gate drive circuit provided in an embodiment of this application is shown.

[0022] Figure 5 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown.

[0023] Explanation of reference numerals in the attached figures: 100 Gate drive unit; 110 Pull-up module; 120 Stage output module; 130 First brush control module; 140 Second brush control module; 150 Drive output module; 151 Control submodule; 152 Drive submodule; 160 Pull-down module; 170 Noise reduction module.

[0024] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; C1, first capacitor; C2, second capacitor; SW1, first brush control terminal; SW2, second brush control terminal; VSS, low level terminal. Detailed Implementation

[0025] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0026] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0027] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0028] Figure 1 A circuit diagram of a gate driving circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 1 As shown, the gate driving circuit includes N cascaded gate driving units 100. The nth gate driving unit 100 includes: a pull-up module 110, a stage output module 120, a first brush control module 130, a second brush control module 140, and a drive output module 150. The pull-up module 110 is connected to the pull-up node Qn of the current stage. The stage output module 120 is connected to the pull-up node Qn and the clock signal line CKm of the current stage. The first brush control module 130 is connected to the pull-up node Qn, the stage output module 120 of the current stage, and the first brush control node Qsn of the current stage. The second brush control module 140 is connected to the first brush control node Qsn and the drive control node Bn of the current stage. The drive output module 150 is connected to the drive control node Bn and the clock signal line CKm of the current stage.

[0029] In some embodiments, the pull-up module 110 is configured to charge the pull-up node Qn in response to the output signal of the nth gate drive unit 100.

[0030] For example, the output signal of the ni-th gate drive unit 100 can be the stage transmission signal of the ni-th stage, where i can be 1. When the pull-up module 110 receives the output signal of the ni-th gate drive unit 100, it will be turned on, thereby charging the pull-up node Qn.

[0031] In some embodiments, the stage transmission module 120 is configured to output the stage transmission signal of the current stage under the action of the voltage on the pull-up node Qn and the clock signal of the current stage.

[0032] For example, when a voltage is generated on the pull-up node Qn and the clock signal of the current stage arrives, the stage transmission module 120 will be turned on and output the stage transmission signal of the current stage, which can be applied to the gate drive unit 100 of the adjacent stage.

[0033] In some embodiments, the first brush control module 130 is configured to generate a voltage on the first brush control node Qsn under the action of the voltage of the pull-up node Qn and the transmission signal.

[0034] For example, when the first brush control module 130 receives the transmission signal and the voltage of the pull-up node Qn, the first brush control module 130 will be turned on, generating a voltage on the first brush control node Qsn, so that the voltage on the first brush control node Qsn can be transmitted to the drive control node Bn.

[0035] In some embodiments, the second refresh control module 140, in partial refresh mode, controls the first refresh control node Qsn and the drive control node Bn to be electrically connected if the current level is a refresh row; if the current level is a non-refresh row, controls the first refresh control node Qsn and the drive control node Bn to be disconnected.

[0036] It should be noted that in global refresh mode, each row of gate driving units 100 in the display screen outputs a gate driving signal to refresh the pixels in each row. In partial refresh mode, pixels in a subset of rows in the display screen are refreshed. For example, if it is determined that the nth pixel in the current frame signal is the same as the nth pixel in the previous frame signal, then no gate driving signal is output in the current frame signal, and thus the nth pixel is not refreshed; if it is determined that the nth pixel in the current frame signal is different from the nth pixel in the previous frame signal, then a gate driving signal is output in the current frame signal, thus refreshing the nth pixel.

[0037] For example, if the current level is a refresh row, it means that the current level needs to output a gate drive signal. By setting the second refresh control module 140, the first refresh control node Qsn and the drive control node Bn are electrically connected to transmit the voltage on the first refresh control node Qsn to the drive control node Bn, so as to control the drive output module 150 to output the gate drive signal of the current level and refresh the pixels of the current level.

[0038] For example, if the current level is a non-refresh row, it means that the current level does not need to output a gate drive signal. By setting the first refresh control node Qsn to disconnect from the drive control node Bn, the voltage on the first refresh control node Qsn will not be transmitted to the drive control node Bn, so as to control the drive output module 150 to stop outputting the gate drive signal of the current level, thereby not refreshing the pixels of the current level.

[0039] In some embodiments, the drive output module 150 is configured to output the gate drive signal of the current stage under the action of the voltage on the drive control node Bn and the clock signal of the current stage.

[0040] For example, by setting the drive output module 150, when there is voltage on the drive control node Bn and the clock signal of the current stage arrives, the drive output module 150 will be turned on, outputting the gate drive signal of the current stage to refresh the pixel of the current stage; when there is no voltage on the drive control node Bn, the drive output module 150 will not be turned on, so it will not output the gate drive signal of the current stage, and thus will not refresh the pixel. The pixel of the nth stage can maintain the pixel voltage of the previous frame signal, thereby avoiding frequent pixel refresh.

[0041] It should be noted that in the diagram, CKm-1, CKm, and CKm+1 represent clock signal lines, CKm-1 represents the clock signal line of the (n-1)th stage, CKm represents the clock signal line of the nth stage, and CKm+1 represents the clock signal line of the (n+1)th stage. Fn-i represents the output terminal of the stage transmission signal of the nith stage, Qn represents the pull-up node Qn of the nth stage, Fn represents the output terminal of the stage transmission signal of the nth stage, Qsn represents the first brush control node Qsn of the nth stage; Bn represents the drive control node Bn of the nth stage, and Gn represents the output terminal of the gate drive signal of the nth stage.

[0042] Figure 2 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 As shown, the first brush control module 130 includes: a first transistor T1; the control terminal of the first transistor T1 is connected to the pull-up node Qn, the first terminal of the first transistor T1 is connected to the output terminal of the stage transmission output module 120, and the second terminal of the first transistor T1 is connected to the first brush control node Qsn.

[0043] For example, when there is voltage on the pull-up node Qn and the output terminal of the stage transmission module 120 outputs the current stage transmission signal, the first transistor T1 will be turned on, transmitting the current stage transmission signal to the first brush control node Qsn.

[0044] In some embodiments, please refer to Figure 2As shown, the second brush control module 140 includes: a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5; the control terminal of the second transistor T2 is connected to the first brush control terminal SW1, the first terminal of the second transistor T2 and the first terminal of the third transistor T3 are connected to the first brush control node Qsn, and the second terminal of the second transistor T2, the first terminal of the fourth transistor T4, and the control terminal of the fifth transistor T5 are connected to the drive control node Bn; the control terminal of the third transistor T3 is connected to the second brush control terminal SW2, and the second terminal of the third transistor T3, the control terminal of the fourth transistor T4, and the first terminal of the fifth transistor T5 are connected to the second brush control node An; the second terminal of the fourth transistor T4 and the second terminal of the fifth transistor T5 are connected to the low-level terminal VSS.

[0045] For example, in the figure, An represents the second brush control node of the nth level. The first brush control terminal SW1 and the second brush control terminal SW2 can be the output terminals of the controller. The controller can be a timing controller. The control signal voltages output by the first brush control terminal SW1 and the second brush control terminal SW2 have opposite polarities. When the first brush control signal output by the first brush control terminal SW1 is high and the second brush control signal output by the second brush control terminal SW2 is low, the second transistor T2 and the fifth transistor T5 will be turned on, and the third transistor T3 and the fourth transistor T4 will be turned off. The first brush control node Qsn will be electrically connected to the drive control node Bn through the second transistor T2 to generate a voltage on the drive control node Bn, thereby controlling the drive output module 150 to output the gate drive signal of the current stage. When the first brush control signal output by the first brush control terminal SW1 is low and the second brush control signal output by the second brush control terminal SW2 is high, the second transistor T2 and the fifth transistor T5 will be turned off, and the third transistor T3 and the fourth transistor T4 will be turned on. The first brush control node Qsn will be disconnected from the drive control node Bn, and the drive control node Bn will be pulled down to a low potential through the fourth transistor T4, further ensuring that there is no drive control voltage on the drive control node Bn and that the drive output module 150 will not be turned on.

[0046] In some embodiments, please refer to Figure 2 As shown, the drive output module 150 includes: a control submodule 151, which is connected to the drive control node Bn, the clock signal line CKm of the current stage, and the drive submodule 152, and is configured to: control the electrical connection between the clock signal line CKm of the current stage and the drive submodule 152 under the action of the voltage on the drive control node Bn; and a drive submodule 152, which is also connected to the drive control node Bn and is configured to: output the gate drive signal of the current stage under the action of the voltage on the drive control node Bn and the clock signal of the current stage.

[0047] For example, by setting the control submodule 151 to generate a voltage on the drive control node Bn, the current stage's clock signal line CKm is electrically connected to the drive submodule 152. When the clock signal of the current stage arrives, the clock signal of the current stage is transmitted to the drive submodule 152. The drive submodule 152 is turned on under the action of the voltage on the drive control node Bn and the clock signal of the current stage, thereby outputting the gate drive signal of the current stage to refresh the clock signal of the current stage. When there is no voltage on the drive control node Bn, the clock signal line CKm of the current stage is disconnected from the drive submodule 152. For multiple CK clock signals, when the same clock signal from other stages arrives as the current stage, crosstalk to the drive submodule 152 can be avoided.

[0048] In some embodiments, please refer to Figure 2 As shown, the control submodule 151 includes: a sixth transistor T6; the control terminal of the sixth transistor T6 is connected to the drive control node Bn, the first terminal of the sixth transistor T6 is connected to the clock signal line CKm of the current stage, and the second terminal of the sixth transistor T6 is connected to the drive submodule 152.

[0049] For example, when the control terminal of the sixth transistor T6 receives a voltage from the drive control node Bn, the sixth transistor T6 will turn on, controlling the clock signal line CKm of the current stage to connect with the drive submodule 152. If the current stage is a non-refresh row, there will be no voltage on the drive control node Bn, disconnecting the clock signal line from the drive submodule 152, further ensuring that the current stage will not output a gate drive signal, and avoiding crosstalk to the current stage when the same clock signal from other rows arrives.

[0050] In some embodiments, the driving submodule 152 includes: a seventh transistor T7 and a first capacitor C1; the control terminal of the seventh transistor T7 is connected to the first terminal of the driving control node Bn and the first terminal of the first capacitor C1 respectively, the first terminal of the seventh transistor T7 is connected to the clock signal line CKm of the current stage, and the second terminal of the seventh transistor T7 is connected to the second terminal of the first capacitor C1.

[0051] For example, there is a voltage on the drive control node Bn, which charges the first capacitor C1. When the clock signal of the current stage arrives, the voltage of the first capacitor C1 will bootstrap the seventh transistor T7 to turn on. When the seventh transistor T7 turns on, it will output the gate drive signal of the current stage.

[0052] In some embodiments, the stage transmission output module 120 includes: an eighth transistor T8 and a second capacitor C2; the control terminal of the eighth transistor T8 and the first terminal of the second capacitor C2 are connected to the pull-up node Qn, the first terminal of the eighth transistor T8 is connected to the clock signal line CKm of the current stage, and the second terminal of the eighth transistor T8 is connected to the second terminal of the second capacitor C2 and serves as the output terminal of the stage transmission signal.

[0053] For example, when the pull-up node Qn is precharged, the precharged voltage will be stored in the pull-up node Qn. When the clock signal of the current stage arrives, the voltage of the second capacitor C2 will bootstrap the eighth transistor T8 to turn on, thereby outputting the stage transmission signal of the current stage. By setting the second capacitor C2 to ensure that the eighth transistor T8 is turned on, the stage transmission will not be affected when the current stage does not output the gate drive signal.

[0054] In some embodiments, the pull-up module 110 includes a ninth transistor T9, the control terminal and the first terminal of the ninth transistor T9 are respectively connected to the output terminal of the stage output module 120 of the nth stage, and the second terminal of the ninth transistor T9 is connected to the pull-up node Qn.

[0055] For example, when the control terminal and the first terminal of the ninth transistor T9 receive the stage transmission signal of the ni stage, the ninth transistor T9 will be turned on, thereby charging the pull-up node Qn and generating a voltage on the pull-up node Qn.

[0056] In some embodiments, the nth-stage gate driving unit 100 further includes a pull-down module 160, which includes a tenth transistor T10 and an eleventh transistor T11. The control terminal of the tenth transistor T10 is connected to the control terminal of the eleventh transistor T11 and the output terminal of the stage output module 120 of the (n+i)th stage, respectively. The first terminal of the tenth transistor T10 is connected to the pull-up node Qn of the current stage, and the second terminal of the tenth transistor T10 and the second terminal of the eleventh transistor T11 are connected to the low-level terminal VSS. The first terminal of the eleventh transistor T11 is connected to the output terminal of the drive output module 150 of the current stage.

[0057] For example, when the control terminals of the tenth transistor T10 and the eleventh transistor T11 receive the stage transmission signal of the (n+i)th stage, the tenth transistor T10 pulls the pull-up node Qn down to a low potential so that the pull-up node Qn can be charged again when the next frame signal arrives; the eleventh transistor T11 pulls the output terminal of the stage transmission output module 120 down to a low potential so as to control the output terminal of the drive output module 150 to stop outputting the gate drive signal of the current stage.

[0058] In some embodiments, the nth-stage gate driving unit 100 further includes a noise reduction module 170, which is connected to the first brush control node Qsn, the second brush control node An, the pull-up node Qn of the current stage, the output terminal Gn of the drive output module 150, and the output terminal Fn of the stage transmission output module 120, respectively. The module is configured to pull down the first brush control node Qsn, the second brush control node An, the pull-up node Qn of the current stage, the output terminal Gn of the drive output module 150, and the output terminal Fn of the stage transmission output module 120 to a low potential according to the noise reduction control signal when the pull-up node Qn of the current stage is a low-level signal, so as to perform noise reduction.

[0059] Figure 3 A timing diagram of the gate drive circuit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 and Figure 3 As shown, level n-1 is a non-refreshing row, and level n is a refreshing row. When a non-refreshing row is switched to a refreshing row, its working sequence is as follows.

[0060] For example, for the (n-1)th stage, during the pre-charge period (t1~t2) and working period (t2~t3) of the (n-1)th stage, the first brush control signal output by the first brush control terminal SW1 is a low-level signal, and the second brush control signal output by the second brush control terminal SW2 is a high-level signal. During the pre-charge period, when the ninth transistor T9 receives the stage transmission signal output by the (n-2)th stage and turns on, it charges the pull-up node Qn-1, generating a voltage at the pull-up node Qn-1. During the working period (t2~t3), when the clock signal of the (n-1)th stage arrives, the second terminal of the eighth transistor T8 will output the stage transmission signal of the (n-1)th stage. At the same time, the control of the first transistor T1 receives the voltage on the pull-up node Qn-1, and the first terminal of the first transistor T1 receives the stage transmission signal of the (n-1)th stage and will turn on, generating a voltage at the first stage. A voltage is generated on the local refresh control node Qsn-1, but the first local refresh control signal is a low-level signal and the second local refresh control signal is a high-level signal. The second transistor T2 and the fifth transistor T5 will be turned off, and the third transistor T3 and the fourth transistor T4 will be turned on, generating a high-level signal on the second local refresh control node An-1. The connection between the first local refresh control node Qsn-1 and the drive control node Bn-1 will be disconnected. The drive control node Bn-1 is pulled down to a low potential through the fourth transistor T4, generating a low-level signal on the drive control node Bn-1, that is, there is no voltage on the drive control node Bn-1. The sixth transistor T6 and the seventh transistor T7 will be turned off, and the gate drive signal of the (n-1)th stage will not be output, thus preventing the (n-1)th stage pixel from being refreshed and avoiding frequent refresh of the (n-1)th stage pixel.

[0061] For example, for the nth stage, during the pre-charge period (t2~t3) of the nth stage, the ninth transistor T9 receives the stage transmission signal output from the (n-1)th stage and turns on, charging the pull-up node Qn and generating a voltage at the pull-up node Qn. During the operating period of the nth stage (t3~t4), the first brush control signal output by the first brush control terminal SW1 is a high-level signal, and the second brush control signal output by the second brush control terminal SW2 is a low-level signal. When the clock signal of the nth stage arrives, the second terminal of the eighth transistor T8 will output the stage transmission signal of the nth stage; simultaneously, the control terminal of the first transistor T1 receives the voltage on the pull-up node Qn, and the first terminal of the first transistor T1 receives the stage transmission signal of the nth stage and will turn on, thus... A voltage is generated at the first refresh control node Qsn. Since the first refresh control signal is high and the second refresh control signal is low, the second transistor T2 and the fifth transistor T5 will be turned on, while the third transistor T3 and the fourth transistor T4 will be turned off. A low-level signal is generated at the second refresh control node An. The first refresh control node Qsn and the drive control node Bn will be electrically connected. The voltage of the first refresh control node Qsn will be transmitted to the drive control node Bn. The control terminals of the sixth transistor T6 and the seventh transistor T7 will turn on upon receiving the voltage from the drive control node Bn. When the nth stage clock signal arrives, the gate drive signal of the nth stage will be output, thereby refreshing the pixel of the nth stage.

[0062] Figure 4 Another timing diagram of the gate drive circuit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 and Figure 4 As shown, level n-1 is the refresh row and level n is the non-refresh row. When the refresh row is switched to the non-refresh row, the working sequence is as follows.

[0063] For example, for the (n-1)th stage, during the pre-charge period (t1~t2) of the (n-1)th stage, the ninth transistor T9 receives the stage transmission signal output from the (n-2)th stage and turns on, charging the pull-up node Qn-1 and generating a voltage at the pull-up node Qn-1. During the operating period (t2~t3) of the (n-1)th stage, the first brush control signal output from the first brush control terminal SW1 is a high-level signal, and the second brush control signal output from the second brush control terminal SW2 is a low-level signal. When the clock signal of the (n-1)th stage arrives, and under the action of the voltage at the pull-up node Qn-1, the second terminal of the eighth transistor T8 will output the stage transmission signal of the (n-1)th stage; simultaneously, the control of the first transistor T1 receives the voltage on the pull-up node Qn-1, and the first terminal of the first transistor T1 receives the stage transmission signal of the (n-1)th stage. The transmission signal will be turned on, generating a voltage on the first refresh control node Qsn-1. The first refresh control signal is a high-level signal, and the second refresh control signal is a low-level signal. The second transistor T2 and the fifth transistor T5 will be turned on, while the third transistor T3 and the fourth transistor T4 will be turned off. A low-level signal will be generated on the second refresh control node An-1. The first refresh control node Qsn-1 will be electrically connected to the drive control node Bn-1. The voltage of the first refresh control node Qsn-1 will be transmitted to the drive control node Bn-1. The control terminals of the sixth transistor T6 and the seventh transistor T7 will turn on upon receiving the voltage on the drive control node Bn-1. When the (n-1)th stage clock signal arrives, the gate drive signal of the (n-1)th stage will be output, thereby refreshing the pixel of the (n-1)th stage.

[0064] For example, for the nth stage, during the pre-charge period (t2~t3) and the working period (t3~t4) of the nth stage, the first brush control signal output by the first brush control terminal SW1 is a low-level signal, and the second brush control signal output by the second brush control terminal SW2 is a high-level signal. During the pre-charge period (t2~t3), when the ninth transistor T9 receives the stage transmission signal output by the (n-1)th stage and turns on, it charges the pull-up node Qn, generating a voltage at the pull-up node Qn. During the working period (t3~t4), when the clock signal of the nth stage arrives, the second terminal of the eighth transistor T8 will output the stage transmission signal of the nth stage. At the same time, the control of the first transistor T1 receives the voltage on the pull-up node Qn, and the first terminal of the first transistor T1 receives the stage transmission signal of the nth stage and will conduct... When the first brush control node Qsn is turned on, a voltage will be generated on the first brush control node, but the first brush control signal is a low-level signal. The second brush control signal is a high-level signal, the second transistor T2 and the fifth transistor T5 will be turned off, and the third transistor T3 and the fourth transistor T4 will be turned on, generating a high-level signal on the second brush control node An. The connection between the first brush control node Qsn and the drive control node Bn will be disconnected. The drive control node Bn will be pulled down to a low potential through the fourth transistor T4, generating a low-level signal on the drive control node Bn, that is, there is no voltage on the drive control node Bn. The sixth transistor T6 and the seventh transistor T7 will be turned off, and the gate drive signal of the nth stage will not be output, thus preventing the nth stage pixel from being refreshed and avoiding frequent refresh of the nth stage pixel.

[0065] Figure 5 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 5 As shown, the second brush control module 140 is further configured as follows: the drive output module 150 includes: a control submodule 151, which is connected to the first brush control node Qsn, the clock signal line CKm of the current stage, and the drive submodule 152, respectively, and is configured to: control the electrical connection between the clock signal line CKm of the current stage and the drive submodule 152 under the action of the voltage on the first brush control node Qsn; the drive submodule 152 is also connected to the drive control node Bn, and is configured to: output the gate drive signal of the current stage under the action of the voltage on the drive control node Bn and the clock signal of the current stage.

[0066] For example, when the first brush control node Qsn is electrically connected to the drive control node Bn, a voltage will be generated on the drive control node Bn. Under the action of the voltage of the first brush control node Qsn, the control submodule 151 will control the drive submodule 152 to connect to the clock signal line CKm of the current stage. Thus, the drive submodule 152 will be turned on under the action of the voltage of the drive control node Bn and the clock signal of the current stage, and output the gate drive signal of the current stage. When the first brush control node Qsn is disconnected from the drive control node Bn, there is no voltage on the drive control node Bn, the control submodule 151 will not be turned on, and thus will not output the gate drive signal of the current stage.

[0067] In some embodiments, please refer to Figure 5 As shown, the control submodule 151 includes: a sixth transistor T6; the control terminal of the sixth transistor T6 is connected to the first brush control node Qsn, the first terminal of the sixth transistor T6 is connected to the clock signal line CKm of the current stage, and the second terminal of the sixth transistor T6 is connected to the drive submodule 152.

[0068] For example, when the control terminal of the first brush control node Qsn receives a voltage from Qsn, the sixth transistor T6 will turn on, thereby controlling the connection between the clock signal line CKm of the current stage and the driver submodule 152. When there is no voltage on the first brush control node Qsn, the sixth transistor T6 will turn off, thereby disconnecting the connection between the clock signal line CKm of the current stage and the driver submodule 152, and the driver submodule 152 will not output the gate drive signal of the current stage. By setting the control terminal of the sixth transistor T6 to be connected to the first brush control node Qsn, the stage transmission signal of the current stage will only be generated when the clock signal of the current stage arrives, thereby generating a voltage on the first brush control node Qsn. At other times, the sixth transistor T6 is in the off state, which can avoid crosstalk to the current stage when the same clock signal of other rows arrives.

[0069] Please see Figure 5 and Figure 3 As shown, level n-1 is a non-refreshing row, and level n is a refreshing row. When a non-refreshing row is switched to a refreshing row, its working sequence is as follows.

[0070] For example, for the (n-1)th stage, during the pre-charge period (t1~t2) and working period (t2~t3) of the (n-1)th stage, the first brush control signal output by the first brush control terminal SW1 is a low-level signal, and the second brush control signal output by the second brush control terminal SW2 is a high-level signal. During the pre-charge period (t1~t2), when the ninth transistor T9 receives the stage transmission signal output by the (n-2)th stage and turns on, it charges the pull-up node Qn-1, generating a voltage at the pull-up node Qn-1. During the working period (t2~t3), when the clock signal of the (n-1)th stage arrives, the second terminal of the eighth transistor T8 will output the stage transmission signal of the (n-1)th stage. At the same time, the control of the first transistor T1 receives the voltage on the pull-up node Qn-1, and the first terminal of the first transistor T1 receives the stage transmission signal of the (n-1)th stage and will turn on, generating a voltage at the first stage. A voltage is generated on the local refresh control node Qsn-1, but the first local refresh control signal is a low-level signal and the second local refresh control signal is a high-level signal. The second transistor T2 and the fifth transistor T5 will be turned off, and the third transistor T3 and the fourth transistor T4 will be turned on. A high-level signal is generated on the second local refresh control node An-1, and the connection between the first local refresh control node Qsn-1 and the drive control node Bn-1 will be disconnected. The drive control node Bn-1 is pulled down to a low potential through the fourth transistor T4, generating a low-level signal on the drive control node Bn-1, that is, there is no voltage on the drive control node Bn-1. The seventh transistor T7 will be turned off. When the clock signal of the (n-1)th stage arrives, the gate drive signal of the (n-1)th stage will not be output, so the pixel of the (n-1)th stage will not be refreshed, thus avoiding frequent refresh of the pixel of the (n-1)th stage.

[0071] For example, for the nth stage, during the pre-charge period (t2~t3) of the nth stage, the ninth transistor T9 receives the stage transmission signal output from the (n-1)th stage and turns on, charging the pull-up node Qn and generating a voltage at the pull-up node Qn. During the working period of the nth stage (t3~t4), the first brush control signal output by the first brush control terminal SW1 is a high-level signal, and the second brush control signal output by the second brush control terminal SW2 is a low-level signal. When the clock signal of the nth stage arrives, the second terminal of the eighth transistor T8 will output the stage transmission signal of the nth stage; at the same time, the control terminal of the first transistor T1 receives the voltage on the pull-up node Qn, and the first terminal of the first transistor T1 receives the stage transmission signal of the nth stage and will turn on, which will be applied to the first brush control node Qs. A voltage is generated on node n. Since the first brush control signal is high and the second brush control signal is low, the second transistor T2 and the fifth transistor T5 will be turned on, while the third transistor T3 and the fourth transistor T4 will be turned off. A low-level signal is generated on the second brush control node An. The first brush control node Qsn and the drive control node Bn will be electrically connected. The voltage of the first brush control node Qsn will be transmitted to the drive control node Bn. The control terminal of the sixth transistor T6 receives the voltage on the first brush control node Qsn and turns on. The control terminal of the seventh transistor T7 receives the voltage on the drive control node Bn and turns on. When the nth stage clock signal arrives, the gate drive signal of the nth stage will be output, thereby refreshing the pixel of the nth stage.

[0072] Please see Figure 5 and Figure 4 As shown, level n-1 is the refresh row and level n is the non-refresh row. When the refresh row is switched to the non-refresh row, the working sequence is as follows.

[0073] For example, for the (n-1)th stage, during the pre-charge period (t1~t2) of the (n-1)th stage, the ninth transistor T9 receives the stage transmission signal output from the (n-2)th stage and turns on, charging the pull-up node Qn-1 and generating a voltage at the pull-up node Qn-1. During the operating period (t2~t3) of the (n-1)th stage, the first brush control signal output from the first brush control terminal SW1 is a high-level signal, and the second brush control signal output from the second brush control terminal SW2 is a low-level signal. When the clock signal of the nth stage arrives, under the action of the voltage at the pull-up node Qn-1, the second terminal of the eighth transistor T8 will output the stage transmission signal of the (n-1)th stage; at the same time, the control of the first transistor T1 receives the voltage on the pull-up node Qn-1, and the first terminal of the first transistor T1 receives the stage transmission signal of the (n-1)th stage and will turn on, generating a voltage at the first brush control node Qsn-1. When a voltage is generated, the first brush control signal is high and the second brush control signal is low. The second transistor T2 and the fifth transistor T5 will be turned on, while the third transistor T3 and the fourth transistor T4 will be turned off. A low-level signal is generated at the second brush control node An-1, preventing the drive control node Bn-1 from being pulled down to a low potential. The first brush control node Qsn-1 and the drive control node Bn-1 will be electrically connected, and the voltage of the first brush control node Qsn-1 will be transmitted to the drive control node Bn-1. The control terminal of the sixth transistor T6 receives the voltage from the first brush control node Qsn-1 and turns on. The control terminal of the seventh transistor T7 receives the voltage from the drive control node Bn-1 and turns on. When the (n-1)th stage clock signal arrives, the (n-1)th stage gate drive signal will be output, thereby refreshing the (n-1)th stage pixel.

[0074] For example, for the nth stage, during the pre-charge period (t2~t3) and the working period (t3~t4) of the nth stage, the first brush control signal output by the first brush control terminal SW1 is a low-level signal, and the second brush control signal output by the second brush control terminal SW2 is a high-level signal. During the pre-charge period, when the ninth transistor T9 receives the stage transmission signal output by the (n-1)th stage and turns on, it charges the pull-up node Qn, generating a voltage at the pull-up node Qn. During the working period (t3~t4), when the clock signal of the nth stage arrives, the second terminal of the eighth transistor T8 will output the stage transmission signal of the nth stage. At the same time, the control of the first transistor T1 receives the voltage on the pull-up node Qn, and the first terminal of the first transistor T1 receives the stage transmission signal of the nth stage and will turn on, generating a voltage at the first brush control node Qsn. The voltage is low, but the first brush control signal is low and the second brush control signal is high. The second transistor T2 and the fifth transistor T5 will be turned off, and the third transistor T3 and the fourth transistor T4 will be turned on, generating a high-level signal on the second brush control node An. The connection between the first brush control node Qsn and the drive control node Bn will be disconnected, and the fourth transistor T4 will pull the drive control node Bn down to a low potential. The drive control node Bn is pulled down to a low potential through the fourth transistor T4, generating a low-level signal on the drive control node Bn, that is, there is no voltage on the drive control node Bn. The seventh transistor T7 will be turned off. When the clock signal of the current stage arrives, the gate drive signal of the nth stage will not be output, so the pixel of the nth stage will not be refreshed, thus avoiding frequent refresh of the pixel of the nth stage.

[0075] In some embodiments, a display panel is provided, including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes a gate driving circuit as described above. The drive output module of the gate driving circuit is connected to at least one scan line.

[0076] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0077] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0078] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes N cascaded gate driving units, and the nth gate driving unit includes: The pull-up module, connected to the pull-up node of the current stage, is configured to charge the pull-up node in response to the output signal of the nith stage gate drive unit; The stage transmission output module is connected to the pull-up node and the clock signal line of the current stage, and is configured to output the stage transmission signal of the current stage under the action of the voltage on the pull-up node and the clock signal of the current stage. The first brush control module is connected to the pull-up node, the current stage transmission output module, and the first brush control node of the current stage, respectively, and is configured to generate a voltage on the first brush control node under the action of the voltage of the pull-up node and the transmission signal of the current stage. The second refresh control module is connected to the first refresh control node and the current level drive control node respectively. In partial refresh mode, if the current level is a refresh row, it controls the first refresh control node to be electrically connected to the drive control node; if the current level is a non-refresh row, it controls the first refresh control node to be disconnected from the drive control node. The drive output module, connected to the drive control node and the clock signal line of the current stage, is configured to output the gate drive signal of the current stage under the action of the voltage on the drive control node and the clock signal of the current stage.

2. The gate driving circuit according to claim 1, characterized in that, The drive output module includes: The control submodule, which is connected to the drive control node, the clock signal line of the current stage, and the drive submodule, is configured to control the electrical connection between the clock signal line of the current stage and the drive submodule under the action of the voltage on the drive control node. The driving submodule is also connected to the driving control node and is configured to output the gate driving signal of the current stage under the action of the voltage of the driving control node and the clock signal of the current stage.

3. The gate driving circuit according to claim 1, characterized in that, The first refresh control module includes: a first transistor; The control terminal of the first transistor is connected to the pull-up node, the first terminal of the first transistor is connected to the output terminal of the stage transmission module, and the second terminal of the first transistor is connected to the first local brush control node.

4. The gate driving circuit according to claim 1, characterized in that, The second local refresh control module includes: a second transistor, a third transistor, a fourth transistor, and a fifth transistor; The control terminal of the second transistor is connected to the first brush control terminal, the first terminal of the second transistor and the first terminal of the third transistor are connected to the first brush control node, and the second terminal of the second transistor, the first terminal of the fourth transistor, and the control terminal of the fifth transistor are connected to the drive control node. The control terminal of the third transistor is connected to the control terminal of the second brush, and the second terminal of the third transistor, the control terminal of the fourth transistor, and the first terminal of the fifth transistor are connected to the second brush control node. The second terminal of the fourth transistor and the second terminal of the fifth transistor are connected to the low-level terminal.

5. The gate driving circuit according to claim 2, characterized in that, The control submodule includes: a sixth transistor; The control terminal of the sixth transistor is connected to the drive control node, the first terminal of the sixth transistor is connected to the clock signal line of the current stage, and the second terminal of the sixth transistor is connected to the drive submodule.

6. The gate driving circuit according to claim 2, characterized in that, The driving submodule includes: a seventh transistor and a first capacitor; The control terminal of the seventh transistor is connected to the drive control node and the first terminal of the first capacitor, the first terminal of the seventh transistor is connected to the clock signal line of the current stage, and the second terminal of the seventh transistor is connected to the second terminal of the first capacitor.

7. The gate driving circuit according to claim 2, characterized in that, The drive output module includes: The control submodule is connected to the first local brush control node, the clock signal line of the current stage, and the driver submodule, respectively, and is configured to: control the electrical connection between the clock signal line of the current stage and the driver submodule under the voltage action of the first local brush control node; The driving submodule is also connected to the driving control node and is configured to output the gate driving signal of the current stage under the action of the voltage of the driving control node and the clock signal of the current stage.

8. The gate driving circuit according to claim 7, characterized in that, The control submodule includes: a sixth transistor; The control terminal of the sixth transistor is connected to the first local brush control node, the first terminal of the sixth transistor is connected to the clock signal line of the current stage, and the second terminal of the sixth transistor is connected to the driver submodule.

9. The gate driving circuit according to claim 1, characterized in that, The stage transmission module includes: an eighth transistor and a second capacitor; The control terminal of the eighth transistor and the first terminal of the second capacitor are connected to the pull-up node. The first terminal of the eighth transistor is connected to the clock signal line of the current stage, and the second terminal of the eighth transistor is connected to the second terminal of the second capacitor and serves as the output terminal of the stage signal transmission.

10. A display panel comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-9, wherein the driving output module of the gate driving circuit is connected to at least one of the scan lines.

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