A gate driving circuit and a display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel, which comprises N cascaded gate driving units, each of which comprises: when a low-brushing area is switched to a high-brushing area, a first pre-charging module of a first-stage gate driving unit of the high-brushing area, which has a first pre-charging control node and is configured to charge the first pre-charging control node in a previous frame scanning signal; in a current frame scanning signal, based on a voltage on the first pre-charging control node, the first pre-charging module pre-charges a driving control node; a first pre-charging module of a non-first-stage gate driving unit of the high-brushing area, which is configured to pre-charge the driving control node in response to a stage transmission signal output by a previous-stage gate driving unit; and an output module, which is configured to output the stage transmission signal and a gate driving signal under the action of a voltage of the driving control node; and the driving circuit of the split-screen display panel can be simplified.

Description

Technical Field

[0001] This application belongs to the field of display driver technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] As display terminals evolve towards higher resolution, lower power consumption, and wider application scenarios, split-screen display and differentiated refresh rates are becoming increasingly important requirements. For example, simultaneously displaying static and dynamic content, the main screen and information bar, or reading and interactive areas on the same display panel can significantly reduce overall power consumption by using different refresh rates for different display areas, while maintaining display quality. However, related technologies often require configuring independent drive channels and timing resources for different refresh rate areas, resulting in complex circuit structures, high wiring resource consumption, and poor scalability.

[0003] Therefore, simplifying the driving circuit of the split-screen display panel is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit and a display panel, which solves the problem of how to simplify the driving circuit of a split-screen display panel.

[0005] In a first aspect, this application provides a gate driving circuit, including N cascaded gate driving units. Each gate driving unit includes a first pre-charge module and an output module connected to a driving control node. The N cascaded gate driving units are physically divided into at least one low refresh rate region and at least one high refresh rate region. When the low refresh rate region switches to the high refresh rate region, the first pre-charge module of the first-stage gate driving unit in the high refresh rate region has a first pre-charge control node, configured to: charge the first pre-charge control node in the previous frame scan signal; and pre-charge the driving control node based on the voltage on the first pre-charge control node in the current frame scan signal. The first pre-charge module of the non-first-stage gate driving unit in the high refresh rate region is configured to: pre-charge the driving control node in response to a cascade signal output by the upper-stage gate driving unit. The output module is configured to: output a cascade signal and a gate driving signal under the voltage of the driving control node.

[0006] Optionally, the at least one low refresh rate region includes: a first low refresh rate region, wherein a first pre-charge module of the first gate drive unit of the first low refresh rate region is connected to the frame start signal output terminal and is configured to: pre-charge the drive control node under the action of the frame start signal output terminal in the previous frame scan signal; and stop charging the drive control node under the action of the frame start signal output terminal in the current frame scan signal; wherein, in the previous frame scan signal, the frame start signal is a valid frame start signal.

[0007] Optionally, the at least one low refresh rate region includes: a second low refresh rate region; when the high refresh rate region switches to the second low refresh rate region, the second pre-charge module of the first gate drive unit of the second low refresh rate region has a second pre-charge control node, which is configured to: charge the second pre-charge control node in the previous frame scan signal; and pull the drive control node down to a low potential based on the voltage on the second pre-charge control node in the current frame scan signal.

[0008] Optionally, when the gate driving unit is a non-first-stage gate driving unit in the low-refresh-rate region or a gate driving unit in the high-refresh-rate region, the first pre-charge module includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor; the control terminal of the first transistor is connected to a first pre-charge control terminal, the first terminal of the first transistor is connected to the stage output terminal of the previous i-stage output module, and the second terminal of the first transistor is connected to the first terminal of the first capacitor, the first terminal of the second transistor, and the first terminal of the third transistor to a first pre-charge control node; the control terminal of the second transistor is connected to a second pre-charge control terminal, and the second terminal of the second transistor is connected to the second terminal of the fourth transistor to the drive control node; the control terminal of the third transistor is connected to a frame start signal output terminal, and the second terminal of the third transistor is connected to a low-level terminal; the second terminal of the first capacitor and the first terminal of the fourth transistor are connected to a high-level terminal; the control terminal of the fourth transistor is connected to the stage output terminal of the previous i-stage output module.

[0009] Optionally, when the gate driving unit is the gate driving unit of the high refresh region or the gate driving unit of the second low refresh region, the second precharge module includes: a second capacitor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the first terminal of the second capacitor is connected to a high-level terminal, and the second terminal of the second capacitor is connected to the second terminal of the fifth transistor, the first terminal of the sixth transistor, and the first terminal of the seventh transistor to a second precharge control node; the control terminal of the fifth transistor is connected to a first precharge control terminal, and the first terminal of the fifth transistor is connected to the stage output terminal of the subsequent j-stage output module; the control terminal of the sixth transistor is connected to a third precharge control terminal, and the second terminal of the sixth transistor is connected to the control terminal of the eighth transistor; the control terminal of the seventh transistor is connected to a frame start signal output terminal, and the second terminal of the seventh transistor is connected to a low-level terminal; the first terminal of the eighth transistor is connected to the drive control node, and the second terminal of the eighth transistor is connected to a low-level terminal.

[0010] Optionally, when the gate driving unit is the first-stage driving unit of the first low-refresh-rate region, the first pre-charge module includes: a first transistor, a second transistor, a third transistor, and a first capacitor; the control terminal of the first transistor is connected to a first pre-charge control terminal, and the second terminal of the first transistor is connected to the first terminal of the second transistor, the first terminal of the third transistor, and the first terminal of the first capacitor, respectively; the control terminal of the second transistor is connected to a second pre-charge control terminal, and the second terminal of the second transistor is connected to the driving control node; the control terminal of the third transistor is connected to the stage transmission output terminal of the output module of the non-first-stage gate driving unit of the first low-refresh-rate region, and the second terminal of the third transistor is connected to a low-level terminal; the second terminal of the first capacitor is connected to a high-level terminal.

[0011] Optionally, when the gate driving unit is a non-first-stage gate driving unit in the low-refresh-rate region or a gate driving unit in the high-refresh-rate region, the first pre-charge module includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor; the control terminal of the first transistor is connected to the stage output terminal of the first k-stage output module, the first terminal of the first transistor is connected to a high-level terminal, and the second terminal of the first transistor is connected to the first terminal of the second transistor; the control terminal of the second transistor is connected to the frame start signal output terminal, and the second terminal of the second transistor is connected to the first terminal of the third transistor, the control terminal of the fourth transistor, and the first capacitor, respectively. The first terminal of the third transistor is connected to the first precharge control node; the control terminal of the third transistor is connected to the stage transmission output terminal of the j-th stage output module, and the second terminal of the third transistor is connected to the first terminal of the fifth transistor; the first terminal of the fourth transistor is connected to the frame start signal output terminal, and the second terminal of the fourth transistor and the second terminal of the sixth transistor are connected to the drive control node; the control terminal of the fifth transistor is connected to the frame start signal output terminal, and the second terminal of the fifth transistor is connected to the low-level terminal; the control terminal of the sixth transistor is connected to the stage transmission output terminal of the i-th stage output module, and the first terminal of the sixth transistor is connected to the first terminal of the first capacitor and the high-level terminal respectively.

[0012] Optionally, when the gate driving unit is the first driving unit of the first low refresh region, the first precharge module includes: a first transistor; the control terminal of the first transistor is connected to the frame start signal output terminal, the first terminal of the first transistor is connected to the high-level terminal, and the second terminal of the first transistor is connected to the driving control node.

[0013] Optionally, the output module includes: a ninth transistor, a tenth transistor, and a third capacitor; the control terminal of the ninth transistor is connected to the control terminal of the tenth transistor and the first terminal of the third capacitor respectively to the drive control node; the first terminal of the ninth transistor is connected to the clock signal line of the current stage, and the second terminal of the ninth transistor serves as the stage output terminal; the first terminal of the tenth transistor is connected to the clock signal line of the current stage, and the second terminal of the tenth transistor is connected to the second terminal of the third capacitor respectively and serves as the drive output terminal.

[0014] In a second aspect, this application provides a display panel including a display area and a non-display area, wherein the display area includes a plurality of scan lines, and the non-display area includes a gate driving circuit as described in any one of the first aspects, and the output module of the gate driving circuit is connected to at least one of the scan lines.

[0015] The technical solution provided in this application has at least the following beneficial effects:

[0016] In this application, N cascaded gate driving units are divided into at least one high refresh rate region and at least one low refresh rate region. The low refresh rate region is not refreshed in the current frame scan signal. When the low refresh rate region switches to the high refresh rate region, the first pre-charge module of the first-level gate driving unit of the high refresh rate region charges the first pre-charge control node in the previous frame scan signal and charges the drive control node based on the voltage of the first pre-charge control node in the current frame scan signal to output the stage transmission signal and the gate drive signal. Thus, the non-first-level gate driving units of the high refresh rate region can also output the stage transmission signal and the gate drive signal, realizing the refreshing of the pixels in the high refresh rate region. The high refresh rate region and the low refresh rate region use the same scan signal, and only the first pre-charge control module is configured to realize the split screen refresh. There is no need to set up independent drive channels and timing resources for the high refresh rate region and the low refresh rate region, which simplifies the drive circuit of the display panel. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 This illustration shows a first structural schematic diagram of a gate driving circuit provided in an embodiment of this application.

[0019] Figure 2 This illustration shows a first partition diagram of a gate drive circuit provided in an embodiment of this application.

[0020] Figure 3A schematic diagram of a second partition of a gate drive circuit provided in an embodiment of this application is shown.

[0021] Figure 4 A schematic diagram of a second structure of a gate drive circuit provided in an embodiment of this application is shown.

[0022] Figure 5 A first circuit diagram of the gate driving unit in the first embodiment provided in this application is shown.

[0023] Figure 6 A first operating timing diagram of the gate drive circuit in the first embodiment provided in this application is shown.

[0024] Figure 7 A second circuit diagram of the gate drive unit in the first embodiment provided in this application is shown.

[0025] Figure 8 A second operating timing diagram of the gate drive circuit in the first embodiment provided in this application is shown.

[0026] Figure 9 A circuit diagram of the gate driving unit in the second embodiment provided in this application is shown.

[0027] Figure 10 A first operating timing diagram of the gate drive circuit of the second embodiment provided in this application is shown.

[0028] Figure 11 A second timing diagram of the gate drive circuit in the second embodiment provided in this application is shown.

[0029] Figure 12 A first circuit diagram of the gate driving unit of the third embodiment provided in this application is shown.

[0030] Figure 13 A timing diagram of the gate drive circuit of the third embodiment provided in this application is shown.

[0031] Figure 14 A second circuit diagram of the gate driving unit of the third embodiment provided in this application is shown.

[0032] Explanation of reference numerals in the attached figures: 100 Gate driving unit; 110 First precharge module; 120 Output module; 130 Second precharge module; 140 Pull-down module; 150 Reset module; 160 Noise reduction module.

[0033] AA, Display area; A11, First low refresh rate area; A12, Second low refresh rate area; A2, High refresh rate area; B1, Non-display area; B2, Chip-on-film substrate; B3, Printed circuit board.

[0034] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; VSS, low level terminal; VDD, high level terminal; STV, frame start signal output terminal; SW1, first precharge control terminal; SW2, second precharge control terminal; SW3, third precharge control terminal; A, first precharge control node; B, second precharge control node; Q, drive control node; Reset, reset control terminal; LC, noise reduction signal output terminal. Detailed Implementation

[0035] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0036] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0037] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0038] Figure 1 This paper shows a schematic diagram of a first structure of a gate driving circuit according to an embodiment of this application. Please refer to [link / reference]. Figure 1 As shown, the gate drive circuit includes N cascaded gate drive units 100, each gate drive unit 100 including: a first precharge module 110 and an output module 120 connected to the drive control node Q.

[0039] Figure 2 This illustration shows a first partition diagram of a gate drive circuit according to an embodiment of this application. Please refer to [link / reference]. Figure 2As shown, the display device includes a display panel, a chip-on-film (COF) substrate, and a printed circuit board (PCB). The display panel includes a display area AA and a non-display area B1. A gate drive circuit (GOA) is located in the non-display area B1. N cascaded gate drive units 100 are physically divided into at least one low refresh rate area (first low refresh rate area A11) and at least one high refresh rate area A2. Figure 1 The area above the dashed line corresponds to the low refresh rate zone, and the area below the dashed line corresponds to the high refresh rate zone A2. It should be noted that the specific number of high refresh rate zones (A2) and low refresh rate zones can be set based on whether the pixels of the corresponding rows need to be refreshed. Figure 1 The example uses a high-brush area A2 and a low-brush area, with the low-brush area located near the flip-chip thin film plate B2.

[0040] In some embodiments, when the low refresh rate region switches to the high refresh rate region A2, the first pre-charge module 110 of the first gate drive unit 100 of the high refresh rate region A2 has a first pre-charge control node A, which is configured to: charge the first pre-charge control node A in the previous frame scan signal; and pre-charge the drive control node Q based on the voltage on the first pre-charge control node A in the current frame scan signal.

[0041] It should be noted that the low refresh rate area is the region where pixels do not need to be refreshed in the current frame scan signal, while the high refresh rate area A2 is the region where pixels need to be refreshed in the current frame scan signal. The previous frame scan signal is a global refresh frame, meaning that every level of pixels in the display panel is refreshed. The current frame scan signal is a partial refresh frame, meaning that only the pixels corresponding to the high refresh rate area are refreshed, while the pixels in the low refresh rate area are not refreshed.

[0042] For example, when the current frame scan signal arrives, since the first low refresh region A11 does not refresh, it will not output a stage transmission signal, and the first gate drive unit 100 of the high refresh region A2 will not receive the stage transmission signal. By setting the first precharge control node A in the first precharge module 110 and charging the first precharge control node A of the first gate drive unit 100 in the high refresh region A2 of the previous frame scan signal, when the current frame scan signal arrives, the voltage on the first precharge control node A precharges the drive control node Q of the first gate drive unit 100 so that the output module 120 of the first gate drive unit 100 can output the stage transmission signal and the gate drive signal.

[0043] In some embodiments, the first pre-charge module 110 of the non-first-level gate drive unit 100 in the high refresh region A2 is configured to pre-charge the drive control node Q in response to the stage transmission signal output by the upper-level gate drive unit 100.

[0044] For example, since the output module 120 of the first-level gate drive unit 100 outputs a stage transmission signal, the first pre-charge module 110 of the non-first-level drive unit in the high refresh region A2 will receive the stage transmission signal output by the upper-level gate drive unit 100 and be turned on, thereby charging the drive control node Q.

[0045] In some embodiments, the output module 120 is configured to output a stage transmission signal and a gate drive signal under the voltage of the drive control node Q.

[0046] For example, when there is a voltage on the drive control node Q, the output module 120 will output a stage transmission signal to perform stage transmission under the action of the voltage on the drive control node Q, and output a gate drive signal to refresh the pixel of the current stage.

[0047] In some embodiments, please refer to Figure 1 and Figure 2 As shown, at least one low refresh rate region includes a first low refresh rate region A11. The first pre-charge module 110 of the first gate drive unit 100 of the first low refresh rate region A11 is connected to the frame start signal output terminal STV and is configured to: pre-charge the drive control node Q under the action of the frame start signal output terminal STV in the previous frame scan signal; and stop charging the drive control node Q under the action of the frame start signal output terminal STV in the current frame scan signal; wherein, in the previous frame scan signal, the frame start signal is a valid frame start signal.

[0048] For example, in the previous frame scan signal, all pixels in the display panel are refreshed normally. The first pre-charge module 110 of the first gate drive unit 100 in the first low refresh area A11 charges the drive control node Q when the received frame start signal is a valid frame signal, so as to generate a voltage on the drive control node Q and cause the output module 120 to output the stage transmission signal, so that each stage output module 120 in the first low refresh area A11 in the previous frame scan signal can output the gate drive signal to refresh the pixels. In the current frame scan signal, the frame start signal is an invalid frame, that is, the frame start signal will not act on the first pre-charge module 110, the first pre-charge module 110 will not charge the pre-charge control node, and thus will not output the stage transmission signal. In the current frame scan signal, each stage output module 120 in the first low refresh area A11 will not output the gate drive signal, and thus will not refresh the pixels in the first low refresh area A11.

[0049] Figure 3 This illustration shows a second partitioning diagram of a gate drive circuit according to an embodiment of this application. Figure 4 This paper illustrates a second structural schematic diagram of a gate drive circuit provided in an embodiment of this application. Please refer to [link / reference]. Figure 3 and Figure 4 As shown, at least one low refresh rate region further includes: a second low refresh rate region A12; when the high refresh rate region A2 switches to the second low refresh rate region A12, the second pre-charge module 130 of the first gate drive unit 100 of the second low refresh rate region A12 has a second pre-charge control node B, which is configured to: charge the second pre-charge control node B in the previous frame scan signal; and pull down the drive control node Q to a low potential based on the voltage on the second pre-charge control node B in the current frame scan signal.

[0050] For example, in the figure, the nth stage can be the first-stage gate driving unit of the high refresh rate region, and the mth stage can be the first-stage gate driving unit of the second low refresh rate region. When the high refresh rate region A2 switches to the second low refresh rate region A12, the second pre-charge module 130 of the first-stage gate driving unit 100 of the second low refresh rate region A12 is set to charge the second pre-charge control node B in the previous frame scan signal. When the current frame scan signal arrives, under the action of the voltage on the second pre-charge control node B, the drive control node Q is pulled down to a low potential. The first-stage gate driving unit 100 of the second low refresh rate region A12 will not output the stage transmission signal and the gate driving signal. Therefore, the output module 120 of the non-first-stage driving unit in the second low refresh rate region A12 will not output the gate driving signal and will not refresh the pixels of the second low refresh rate region A12.

[0051] Figure 5 A first circuit diagram of the gate driving unit in the first embodiment provided in this application is shown. Please refer to [link / reference]. Figure 5 As shown, when the gate driving unit 100 is the first-stage driving unit of the first low-refresh-rate region A11, the first pre-charge module 110 includes: a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1; the control terminal of the first transistor T1 is connected to the first pre-charge control terminal SW1, the first terminal of the first transistor T1 is connected to the frame start signal output terminal STV, and the second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2, the first terminal of the third transistor T3, and the first terminal of the first capacitor C1, respectively; the control terminal of the second transistor T2 is connected to the second pre-charge control terminal SW2, and the second terminal of the second transistor T2 is connected to the drive control node Q; the control terminal of the third transistor T3 is connected to the stage transmission output terminal of the output module 120 of the non-first-stage gate driving unit 100 of the first low-refresh-rate region A11, and the second terminal of the third transistor T3 is connected to the low-level terminal VSS; the second terminal of the first capacitor C1 is connected to the high-level terminal VDD.

[0052] For example, Figure 6 A first operating timing diagram of the gate drive circuit in the first embodiment provided in this application is shown. Please refer to [link / reference]. Figure 5 and Figure 6As shown, there can be two first-stage driving units. In this embodiment, the first first-stage driving unit is taken as an example, and an 8CK clock signal is used. The first first-stage driving unit is connected to the clock signal line of the first stage. The first precharge control terminal SW1 outputs the first precharge control signal, and the second precharge control terminal SW2 outputs the second precharge control signal. The working period of each gate driving unit 100 includes: a precharge period, a driving period, and a pull-down period. The precharge period represents the period during which the driving control node Q is precharged, the driving period represents the period during which the current stage clock signal arrives, and the pull-down period represents the period during which the driving control node Q is pulled down. In the previous frame scan signal, i.e., the global refresh frame, during the precharge period and driving period of the first-stage driving unit in the low refresh area, the frame start signal, the first precharge control signal, and the second precharge control signal are valid frame signals, i.e., high-level signals.

[0053] During the pre-charge period, the first transistor T1 and the second transistor T2 are turned on, charging the first capacitor C1 and the drive control node Q. The voltage on the first capacitor C1 ensures that the second transistor T2 is turned on. During the drive period, when the clock signal of the current stage arrives, and under the action of the voltage on the drive control node Q, the output module 120 will output the stage transmission signal and the gate drive signal of the current stage. The stage transmission signal will act on the non-first stage drive signal of the first low refresh region A11, causing the non-first stage drive unit of the first low refresh region A11 to output the gate drive signal to refresh the pixel. During the pull-down period, when the control terminal of the third transistor T3 receives the stage transmission signal of the non-first stage drive unit of the first low refresh region A11 (taking the stage transmission signal of the third stage output module 120 as an example in this embodiment), the third transistor T3 will be turned on, pulling down the first terminal of the first capacitor C1 and the first terminal of the second transistor T2 to a low potential to stop charging the drive control node Q.

[0054] It should be noted that during the working period of the first-stage drive unit in the first low-refresh region A11, the effective frame bandwidth of the frame start signal, the first precharge control signal, and the second precharge signal is greater than the clock signal bandwidth of the first-stage drive unit, so as to ensure that the second terminal of the second transistor T2 continuously outputs voltage to the drive control node Q, thereby ensuring that the output module 120 outputs the stage signal and the gate drive signal.

[0055] Figure 7 A second circuit diagram of the gate driving unit in the first embodiment provided in this application is shown. Please refer to [link / reference]. Figure 7As shown, when the gate driving unit 100 is a non-first-stage gate driving unit 100 in the low-refresh-rate region or a gate driving unit 100 in the high-refresh-rate region A2, the first pre-charge module 110 includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a first capacitor C1; the control terminal of the first transistor T1 is connected to the first pre-charge control terminal SW1, the first terminal of the first transistor T1 is connected to the stage output terminal of the previous i-stage output module 120, and the second terminal of the first transistor T1 is connected to the first terminal of the first capacitor C1, the first terminal of the second transistor T2, and the third transistor T4. The first terminal of transistor T3 is connected to the first precharge control node A; the control terminal of the second transistor T2 is connected to the second precharge control terminal SW2, and the second terminal of the second transistor T2 is connected to the second terminal of the fourth transistor T4 to the drive control node Q; the control terminal of the third transistor T3 is connected to the frame start signal output terminal STV, and the second terminal of the third transistor T3 is connected to the low-level terminal VSS; the second terminal of the first capacitor C1 and the first terminal of the fourth transistor T4 are connected to the high-level terminal VDD; the control terminal of the fourth transistor T4 is connected to the stage transmission output terminal of the previous i-stage output module 120.

[0056] For example, Figure 8 This diagram illustrates a second timing diagram of the gate drive circuit in the first embodiment provided in this application. In this embodiment, i can be 2, the Nth frame is the scan signal of the previous frame, the current frame is the scan signal of the (N+1)th frame, and the Nth frame is the scan signal of the next frame. Please refer to [link / reference]. Figure 6 and Figure 8 As shown.

[0057] In the previous frame of the scan signal, each pixel needs to be refreshed. When the scan reaches the first-stage driving unit of the low refresh rate region, the control terminal of the fourth transistor T4 receives the stage transmission signal of the previous i-stage and turns on, charging the drive control node Q to act on the output module 120 of the current stage, outputting the stage transmission signal and gate drive signal of the current stage. At the same time, during the pre-charging period of the first-stage driving unit of the high refresh rate region A2, the first pre-charging control signal is a valid frame signal, that is, it is a valid frame signal during the stage transmission signal output period of the previous i-stage. The second pre-charging control signal is an invalid frame signal. The first transistor T1 of the first-stage driving unit of the high refresh rate region A2 will receive the first pre-charging control signal and the stage transmission signal of the previous i-stage and turn on, charging the first terminal of the first capacitor C1 of the first-stage driving unit of the high refresh rate region A2, that is, charging the first pre-charging control node A.

[0058] In the current frame scan signal, only the pixels in the high refresh rate region A2 are refreshed. When the low refresh rate region switches to the high refresh rate region A2, for the first-stage driving unit of the high refresh rate region A2, during the pre-charge period of the first-stage driving unit of the high refresh rate region A2, the second pre-charge control signal is a valid frame signal, the second transistor T2 of the first-stage driving unit of the high refresh rate region A2 is turned on, and the driving control node Q is charged based on the voltage of the first pre-charge control node A. When the clock signal of the first-stage driving unit of the high refresh rate region A2 arrives, the output module 120 of the first-stage driving unit of the high refresh rate region A2 will output the stage transmission signal and the gate driving signal under the action of the current stage clock signal and the driving control node Q. When the first frame scan signal arrives, the frame start signal is a valid frame signal during the pre-charge period of the first-stage driving unit of the first low refresh rate region A11, pulling the first pre-charge control node A down to a low potential.

[0059] In the current frame scan signal, for the non-first stage drive unit of the high refresh region A2, the control terminal of the fourth transistor T4 will receive the stage transmission signal of the previous i stage and turn on to charge the drive control node Q, thereby outputting the stage transmission signal and gate drive signal of the current stage.

[0060] Figure 9 A circuit diagram of the gate driving unit 100 in the second embodiment provided in this application is shown. Please refer to [link / reference]. Figure 9 As shown, when the gate driving unit 100 is the gate driving unit 100 of the high refresh region A2 or the gate driving unit 100 of the second low refresh region A12, the second precharge module 130 includes: a second capacitor C2, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8; the first terminal of the second capacitor C2 is connected to the high-level terminal VDD, and the second terminal of the second capacitor C2 is connected to the second terminal of the fifth transistor T5, the first terminal of the sixth transistor T6, and the first terminal of the seventh transistor T7 to the second precharge control node B; the control terminal of the fifth transistor T5 is connected to the first precharge control terminal SW1, and the first terminal of the fifth transistor T5 is connected to the stage transmission output terminal of the subsequent j-stage output module 120; the control terminal of the sixth transistor T6 is connected to the third precharge control terminal SW3, and the second terminal of the sixth transistor T6 is connected to the control terminal of the eighth transistor; the control terminal of the seventh transistor T7 is connected to the frame start signal output terminal, and the second terminal of the seventh transistor T7 is connected to the low-level terminal VSS; the first terminal of the eighth transistor T8 is connected to the drive control node Q, and the second terminal of the eighth transistor is connected to the low-level terminal VSS.

[0061] For example, Figure 10 A first operating timing diagram of the gate drive circuit according to the second embodiment of this application is shown. Please refer to [link / reference]. Figure 9 and Figure 10As shown, in the previous frame scan signal, for the first-stage gate drive unit 100 of the second low refresh region A12, the third precharge control signal output by the third precharge control terminal SW3 is an invalid frame signal, i.e., a low-level signal. The first precharge control signal output by the first precharge control terminal SW1 is an valid frame signal during the driving period of the j-th stage after the first-stage gate drive unit 100 of the second low refresh region A12. The control terminal of the fifth transistor T5 receives the stage transmission signal of the j-th stage and the first precharge control signal and turns on, charging the second terminal of the second capacitor C2, i.e., charging the second precharge control node B.

[0062] Figure 11 A second timing diagram of the gate drive circuit in the second embodiment provided in this application is shown. Please refer to [link / reference]. Figure 9 and Figure 11 As shown, in the current frame scan signal, for the first-stage gate drive unit 100 of the second low refresh region A12, the third precharge control signal output by the third precharge control terminal SW3 is a valid frame signal during the driving period of the first-stage gate drive unit 100 of the second low refresh region A12. The sixth transistor T6 will be turned on, and the voltage on the second precharge control node B will act on the control terminal of the eighth transistor T8 through the sixth transistor T6. The eighth transistor T8 will be turned on, pulling the drive control node Q down to a low potential. The output module 120 will not output the stage transmission signal and the gate drive signal. For the non-first-stage drive units of the second low refresh region A12, they cannot receive the stage transmission signal output by the first-stage drive unit of the second low refresh region A12, and will not be turned on, so they will not output the stage transmission signal and the gate drive signal. The second low refresh region A12 will not refresh the pixels.

[0063] It should be noted that the gate drive unit 100 circuit of the first low refresh region A11 in the second embodiment is the same as that in the first embodiment, and will not be described again here.

[0064] Figure 12 A first circuit diagram of the gate driving unit 100 according to the third embodiment of this application is shown. Please refer to [link / reference]. Figure 12 As shown, when the gate driving unit 100 is a non-first-level driving unit of the first low-brush region A11, the first precharge module 110 includes: a first transistor T1; the control terminal of the first transistor T1 is connected to the frame start signal output terminal STV, the first terminal of the first transistor T1 is connected to the high-level terminal VDD, and the second terminal of the first transistor T1 is connected to the driving control node Q.

[0065] For example, Figure 13 A timing diagram of the gate drive circuit according to the third embodiment provided in this application is shown. Please refer to [link / reference]. Figure 12 and Figure 13As shown, the frame start signal is a valid frame signal during the pre-charge period and the drive period of the first-level drive unit. When the control terminal of the first transistor T1 receives the frame start signal output by the frame start signal terminal, the first transistor T1 will be turned on, thereby charging the drive control node Q.

[0066] Figure 14 A second circuit diagram of the gate driving unit 100 according to the third embodiment provided in this application is shown. Please refer to [link / reference]. Figure 14 As shown, when the gate driving unit 100 is a non-first-stage gate driving unit 100 in the first low-refresh-rate region A11 or a gate driving unit 100 in the high-refresh-rate region A2, the first pre-charge module 110 includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a first capacitor C1; the control terminal of the first transistor T1 is connected to the stage transmission output terminal of the first k-stage output module 120, the first terminal of the first transistor T1 is connected to the high-level terminal VDD, and the second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2; the control terminal of the second transistor T2 is connected to the frame start signal output terminal STV, and the second terminal of the second transistor T2 is connected to the first terminal of the third transistor T3 and the fourth transistor T4, respectively. The control terminal of the first transistor T3 and the first terminal of the first capacitor C1 are connected to the first precharge control node A; the control terminal of the third transistor T3 is connected to the stage transmission output terminal of the j-th stage output module 120, and the second terminal of the third transistor T3 is connected to the first terminal of the fifth transistor T5; the first terminal of the fourth transistor T4 is connected to the frame start signal output terminal STV, and the second terminal of the fourth transistor T4 is connected to the second terminal of the sixth transistor T6 to the drive control node Q; the control terminal of the fifth transistor T5 is connected to the frame start signal output terminal STV, and the second terminal of the fifth transistor T5 is connected to the low-level terminal VSS; the control terminal of the sixth transistor T6 is connected to the stage transmission output terminal of the i-th stage output module 120, and the first terminal of the sixth transistor T6 is connected to the first terminal of the first capacitor C1 and the high-level terminal VDD respectively.

[0067] For example, in this embodiment, i can be 2, j can be 3, and k can be 10. See also... Figure 13 and Figure 14 As shown, in the previous frame scan signal, for the first-stage gate drive unit 100 of the high refresh region A2, the frame start signal is a valid frame signal during the pre-charge period, drive period and pull-down period of the current stage, and is also a valid frame signal during the drive period of the previous k-stage gate drive units 100. The control terminal of the first transistor T1 receives the stage transmission signal of the previous k stages and turns on, and the control terminal of the second transistor T2 receives the frame start signal and turns on, charging the first terminal of the first capacitor C1, that is, charging the first pre-charge control node A.

[0068] In the previous frame of the scan signal, the sixth transistor T6 in the non-first stage drive unit of the first low refresh region A11 and the gate drive unit 100 of the high refresh region A2 charges the drive control node Q by receiving the stage transmission signal of the previous i stage, so that the output module 120 outputs the stage transmission signal and the gate drive signal.

[0069] In the current frame scan signal, since the gate drive unit 100 of the first low refresh region A11 will not output the stage transmission signal and the gate drive signal, for the first-stage gate drive circuit of the high refresh region A2, the frame start signal is a valid frame signal during the precharge period, drive period and pull-down period of the current stage. The fourth transistor T4 will be turned on, and the second precharge control node B charges the drive control node Q. When the clock signal of the current stage arrives, and under the action of the drive control node Q, the output module 120 will output the stage transmission signal and the gate drive signal of the current stage. The frame start signal is also a valid frame signal during the drive period of the gate drive unit 100 of the j-th stage. When the control terminal of the third transistor T3 receives the stage transmission signal of the j-th stage, the fifth transistor T5 receives the frame start signal and turns on, thereby pulling the first precharge control node A down to a low potential to discharge the voltage on the second precharge control node B.

[0070] In some embodiments, please refer to Figure 5 , 7 As shown in Figures 9, 12, and 14, the output module 120 includes: a ninth transistor T9, a tenth transistor T10, and a third capacitor C3; the control terminal of the ninth transistor T9 is connected to the control terminal of the tenth transistor T10 and the first terminal of the third capacitor C3 respectively to the drive control node Q; the first terminal of the ninth transistor T9 is connected to the clock signal line of the current stage, and the second terminal of the ninth transistor T9 serves as the stage transmission output terminal; the first terminal of the tenth transistor T10 is connected to the clock signal line of the current stage, and the second terminal of the tenth transistor T10 is connected to the second terminal of the third capacitor C3 respectively and serves as the drive output terminal.

[0071] For example, when the drive control node Q is charged, the voltage on the drive control node Q will be stored on the third capacitor C3. When the clock signal of the current stage arrives, the third capacitor C3 bootstraps, the ninth transistor T9 and the tenth transistor T10 are turned on, the second terminal of the ninth transistor T9 outputs the stage transmission signal, and the second terminal of the tenth transistor T10 outputs the gate drive signal.

[0072] In some embodiments, please refer to Figure 5 , 7As shown in 9, 12 and 14, the gate drive unit 100 also includes a pull-down module 140. The pull-down module 140 includes an eleventh transistor T11. The control terminal of the eleventh transistor T11 is connected to the stage transmission output terminal of the subsequent j-stage output module 120. The first terminal of the eleventh transistor T11 is connected to the drive control node Q, and the second terminal of the eleventh transistor T11 is connected to the low-level terminal VSS.

[0073] For example, when the eleventh transistor T11 receives the stage transmission signal from the j-th stage, the eleventh transistor T11 will turn on, pulling the drive control node Q down to a low potential, and then charging the drive control node Q again when the next scan signal arrives.

[0074] In some embodiments, please refer to Figure 5 , 7 As shown in Figures 9, 12, and 14, the gate drive unit 100 also includes a reset module 150, which is connected to the reset control terminal Reset and the drive control node Q, respectively, and is configured to reset the drive control node Q according to the reset control signal.

[0075] In some embodiments, please refer to Figure 5 , 7 As shown in 9, 12 and 14, the gate drive unit 100 also includes a noise reduction module 160, which is connected to the noise reduction signal output terminals LC1\LC2, the drive control node Q and the output module 120 respectively, and is configured to: reduce noise on the drive control node Q, the stage transmission output terminal of the output module 120 and the drive output terminal of the output module 120 according to the noise reduction signal output by the noise reduction signal output terminals LC1\LC2.

[0076] In some embodiments, this application also provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the aforementioned gate driving circuit. The output module of the gate driving circuit is connected to at least one scan line.

[0077] In the above figure, G(1) represents the drive output terminal of the output module of the first-stage gate drive unit in the first low-refresh-rate region, F(1) represents the stage transmission output terminal of the output module of the first-stage gate drive unit in the first low-refresh-rate region, F(n) represents the stage transmission output terminal of the nth stage output module, F(n-2) represents the stage transmission output terminal of the (n-2)th stage output module, F(m) represents the stage transmission output terminal of the mth stage output module, F(m-1) represents the stage transmission output terminal of the (m-1)th stage output module, F(m-2) represents the stage transmission output terminal of the (m-2)th stage output module; F(m-3) represents the stage transmission output terminal of the (m-3)th stage output module, G(n) represents the stage transmission output terminal of the nth stage output module, G (n-2) represents the drive output terminal of the (n-2)th stage output module, G(m) represents the drive output terminal of the m-th stage output module, G(m-1) represents the drive output terminal of the (m-1)th stage output module, G(m-2) represents the drive output terminal of the (m-2)th stage output module, CK1···CK8, CKn, CKm represent clock signal lines, A(n-2) represents the first precharge control node of the (n-2)th stage, Q(n-2) represents the drive control node of the (n-2)th stage, B(n+3) represents the second precharge control node of the (n+3)th stage, Q(m+3) represents the drive control node of the (n+3)th stage, and G(m+3) represents the drive output terminal of the (m+3)th stage output module.

[0078] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0079] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0080] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate drive circuit characterized by comprising: It includes N cascaded gate drive units, each gate drive unit including: a first precharge module and an output module connected to the drive control node. The N cascaded gate drive units are physically divided into at least one low refresh region and at least one high refresh region. The at least one low refresh rate region includes: a first low refresh rate region, wherein a first pre-charge module of the first gate drive unit of the first low refresh rate region is connected to the frame start signal output terminal and is configured to: pre-charge the drive control node under the action of the frame start signal output terminal in the previous frame scan signal; and stop charging the drive control node under the action of the frame start signal output terminal in the current frame scan signal; wherein, in the previous frame scan signal, the frame start signal is a valid frame start signal; Specifically, when the low refresh rate zone switches to the high refresh rate zone, The first pre-charge module of the first gate drive unit of the high refresh region has a first pre-charge control node, which is configured to: charge the first pre-charge control node in the previous frame scan signal; and pre-charge the drive control node based on the voltage on the first pre-charge control node in the current frame scan signal. The first pre-charge module of the non-first-stage gate drive unit in the high refresh rate region is configured to pre-charge the drive control node in response to the stage transmission signal output by the upper-stage gate drive unit. The output module is configured to output a stage transmission signal and a gate drive signal under the voltage of the drive control node.

2. The gate driving circuit according to claim 1, characterized in that, The at least one low refresh rate zone includes: a second low refresh rate zone; when the high refresh rate zone switches to the second low refresh rate zone... The second pre-charge module of the first gate drive unit of the second low refresh region has a second pre-charge control node, which is configured to: charge the second pre-charge control node in the previous frame scan signal; and pull the drive control node down to a low potential based on the voltage on the second pre-charge control node in the current frame scan signal.

3. The gate driving circuit according to claim 1, characterized in that, When the gate driving unit is a non-first-stage gate driving unit of the low refresh rate region or a gate driving unit of the high refresh rate region, the first pre-charge module includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor; The control terminal of the first transistor is connected to the first precharge control terminal, the first terminal of the first transistor is connected to the stage output terminal of the first i-stage output module, and the second terminal of the first transistor is connected to the first terminal of the first capacitor, the first terminal of the second transistor, and the first terminal of the third transistor to the first precharge control node. The control terminal of the second transistor is connected to the second precharge control terminal, and the second terminal of the second transistor and the second terminal of the fourth transistor are connected to the drive control node; The control terminal of the third transistor is connected to the frame start signal output terminal, and the second terminal of the third transistor is connected to the low-level terminal. The second terminal of the first capacitor and the first terminal of the fourth transistor are connected to a high-level terminal; The control terminal of the fourth transistor is connected to the stage output terminal of the previous i-stage output module.

4. The gate driving circuit according to claim 2, characterized in that, When the gate driving unit is the gate driving unit of the high refresh region or the gate driving unit of the second low refresh region, the second precharge module includes: a second capacitor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; The first terminal of the second capacitor is connected to the high-level terminal, and the second terminal of the second capacitor is connected to the second terminal of the fifth transistor, the first terminal of the sixth transistor, and the first terminal of the seventh transistor to the second precharge control node; The control terminal of the fifth transistor is connected to the first precharge control terminal, and the first terminal of the fifth transistor is connected to the stage output terminal of the subsequent j-stage output module. The control terminal of the sixth transistor is connected to the third precharge control terminal, and the second terminal of the sixth transistor is connected to the control terminal of the eighth transistor. The control terminal of the seventh transistor is connected to the frame start signal output terminal, and the second terminal of the seventh transistor is connected to the low-level terminal; The first terminal of the eighth transistor is connected to the drive control node, and the second terminal of the eighth transistor is connected to the low-level terminal.

5. The gate driving circuit according to claim 1, characterized in that, When the gate driving unit is the first driving unit of the first low refresh region, the first precharge module includes: a first transistor, a second transistor, a third transistor, and a first capacitor; The control terminal of the first transistor is connected to the first precharge control terminal, and the second terminal of the first transistor is connected to the first terminal of the second transistor, the first terminal of the third transistor, and the first terminal of the first capacitor, respectively. The control terminal of the second transistor is connected to the second precharge control terminal, and the second terminal of the second transistor is connected to the drive control node; The control terminal of the third transistor is connected to the stage transmission output terminal of the output module of the non-first-stage gate drive unit in the first low-brush region, and the second terminal of the third transistor is connected to the low-level terminal. The second terminal of the first capacitor is connected to the high-level terminal.

6. The gate driving circuit according to claim 1, characterized in that, When the gate driving unit is a non-first-stage gate driving unit of the low refresh rate region or a gate driving unit of the high refresh rate region, the first pre-charge module includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor; The control terminal of the first transistor is connected to the stage output terminal of the first k-stage output module, the first terminal of the first transistor is connected to the high-level terminal, and the second terminal of the first transistor is connected to the first terminal of the second transistor. The control terminal of the second transistor is connected to the frame start signal output terminal, and the second terminal of the second transistor is connected to the first terminal of the third transistor, the control terminal of the fourth transistor, and the first terminal of the first capacitor to the first precharge control node. The control terminal of the third transistor is connected to the stage output terminal of the subsequent j-stage output module, and the second terminal of the third transistor is connected to the first terminal of the fifth transistor. The first terminal of the fourth transistor is connected to the frame start signal output terminal, and the second terminal of the fourth transistor and the second terminal of the sixth transistor are connected to the drive control node; The control terminal of the fifth transistor is connected to the frame start signal output terminal, and the second terminal of the fifth transistor is connected to the low-level terminal; The control terminal of the sixth transistor is connected to the stage output terminal of the previous i-stage output module, and the first terminal of the sixth transistor is connected to the first terminal and the high-level terminal of the first capacitor, respectively.

7. The gate driving circuit according to claim 1, characterized in that, When the gate driving unit is the first driving unit of the first low refresh region, the first precharge module includes: a first transistor; The control terminal of the first transistor is connected to the frame start signal output terminal, the first terminal of the first transistor is connected to the high-level terminal, and the second terminal of the first transistor is connected to the drive control node.

8. The gate driving circuit according to claim 1, characterized in that, The output module includes: a ninth transistor, a tenth transistor, and a third capacitor; The control terminal of the ninth transistor is connected to the control terminal of the tenth transistor and the first terminal of the third capacitor, respectively, to the drive control node. The first terminal of the ninth transistor is connected to the clock signal line of the current stage, and the second terminal of the ninth transistor serves as the stage output terminal. The first terminal of the tenth transistor is connected to the clock signal line of the current stage, and the second terminal of the tenth transistor is connected to the second terminal of the third capacitor and serves as the drive output terminal.

9. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-8, wherein the output module of the gate driving circuit is connected to at least one of the scan lines.

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