Non-volatile sram cell based on resistive switching device and control method

Abstract

The present disclosure relates to a nonvolatile SRAM cell based on a resistive switching device, comprising: a field effect transistor; a resistive switching device; and a control line, wherein a first P-type transistor, a first resistive switching device, and a third N-type transistor are sequentially connected in series between a power supply voltage and a voltage line, and a second P-type transistor, a second resistive switching device, and a fourth N-type transistor are sequentially connected in series between the power supply voltage and the voltage line, the second P-type transistor and the fourth N-type transistor are connected at the gate to be connected to a first bit line, and the first P-type transistor and the third N-type transistor are connected at the gate to be connected to a second bit line, and the gate of the first N-type transistor is connected to a first word line, and the gate of the second N-type transistor is connected to a second word line.

Description

Technical Field

[0001] This disclosure relates to the field of memory design, and more specifically to a non-volatile SRAM cell based on resistive switching devices and a control method thereof. Background Technology

[0002] Static Random Access Memory (SRAM) is a type of random access memory (RAM) that features ultra-fast read / write speeds and extremely high durability. However, SRAM data is volatile and is immediately lost when the power is turned off. Adding non-volatile storage devices, such as resistive switching devices, to SRAM cells allows the data to be retained even after power is off. However, reading and writing to resistive switching devices typically requires additional transistors, making the structure of non-volatile SRAM more complex and reducing the area efficiency of the cells. Summary of the Invention

[0003] A brief overview of this disclosure is given below to provide a basic understanding of some aspects of it. However, it should be understood that this overview is not an exhaustive summary of this disclosure. It is not intended to identify key or essential parts of this disclosure, nor is it intended to limit the scope of this disclosure. Its purpose is merely to present certain concepts of this disclosure in a simplified form as a prelude to the more detailed description that follows.

[0004] According to a first aspect of the embodiments of this disclosure, a non-volatile SRAM cell based on a resistive switching device is provided, comprising: a field-effect transistor including a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, and a fourth N-type transistor; a resistive switching device including a first resistive switching device and a second resistive switching device; and control lines including a first word line, a second word line, a first bit line, a second bit line, and a voltage line, wherein the first P-type transistor, the first resistive switching device, and the third N-type transistor are sequentially connected in series between a power supply voltage and a voltage line, and the second P-type transistor, the second resistive switching device, and the fourth N-type transistor are sequentially connected in series between a power supply voltage and a voltage line, the gates of the second P-type transistor and the fourth N-type transistor are connected to the first bit line, and the gates of the first P-type transistor and the third N-type transistor are connected to the second bit line, and the gate of the first N-type transistor is connected to the first word line, and the gate of the second N-type transistor is connected to the second word line, wherein the control lines are adjusted to cause the SRAM cell to perform data read and write operations.

[0005] In some embodiments, the source and drain of the first N-type transistor are respectively connected between the first P-type transistor and the first resistive switching device and to the first bit line; and the source and drain of the second N-type transistor are respectively connected between the second P-type transistor and the second resistive switching device and to the second bit line.

[0006] In some embodiments, a first P-type transistor, a first resistive switching device, and a third N-type transistor constitute a first data unit, and a second P-type transistor, a second resistive switching device, and a fourth N-type transistor constitute a second data unit, wherein the first data unit and the second data unit form a cross-coupled structure.

[0007] In some embodiments, in response to the first resistive switching device being set to a high-resistance state and the second resistive switching device being set to a low-resistance state, the first bit line is set to a high level and the second bit line is set to a low level, thereby causing the SRAM cell to store data bit 1.

[0008] In some embodiments, in response to the first resistive switching device being set to a low-resistance state and the second resistive switching device being set to a high-resistance state, the first bit line is set to a low level and the second bit line is set to a high level, thereby causing the SRAM cell to store data bit 0.

[0009] According to a second aspect of the embodiments of the present disclosure, a control method for an SRAM cell according to the first aspect is provided, comprising: adjusting control lines to cause the SRAM cell to perform data read / write and power-off operations.

[0010] In some embodiments, raising the first word line and the second bit line to a high level turns on the first N-type transistor and the third N-type transistor, thereby raising the first bit line to a high level and lowering the voltage line to a low level, causing the first resistive switching device to switch to a low-impedance state; all control lines fall to a low level; raising the second word line and the first bit line to a high level turns on the second N-type transistor and the fourth N-type transistor, thereby lowering the second bit line to a low level and raising the voltage line to a high level, causing the second resistive switching device to switch to a high-impedance state; and lowering all control lines to a low level causes the SRAM cell to perform a data write operation and store the data bit 0.

[0011] In some embodiments, raising the second word line and the first bit line to a high level turns on the second N-type transistor and the fourth N-type transistor, thereby raising the second bit line to a high level and lowering the voltage line to a low level, so that the second resistive switching device switches to a low-impedance state; lowering all control lines to a low level; raising the first word line and the second bit line to a high level turns on the first N-type transistor and the third N-type transistor, thereby lowering the first bit line to a low level and raising the voltage line to a high level, so that the first resistive switching device switches to a high-impedance state; and lowering all control lines to a low level causes the SRAM cell to perform a data write operation and store a data bit 1.

[0012] In some embodiments, the first word line, the second word line, and the voltage line are raised to a high level, such that the first word line and the second bit line are switched to half of the power supply voltage; and in response to a comparison between the resistance state of the first resistive switching device and the resistance state of the second resistive switching device, the data bits stored in the SRAM cell are read out based on the levels of the first word line and the second bit line.

[0013] In some embodiments, all control lines are brought low to cause the SRAM cell to perform a power-off operation.

[0014] The advantages of embodiments according to this disclosure are that they provide a non-volatile SRAM cell capable of retaining stored data in the event of a power outage. Compared to other non-volatile SRAM cells, this eliminates the need to add additional transistors to the existing 6-transistor-2-resistive-device (6T2R) configuration and provides virtually no static power consumption when data is stable. Since there is no voltage difference across the resistive-device in the SRAM cell, the resistance state of the resistive-device does not change during reading, thus providing stable data read / write functionality.

[0015] It should be recognized that the above advantages do not need to be concentrated in one or a few specific embodiments, but can be partially distributed in different embodiments according to this disclosure. Embodiments according to this disclosure may have one or some of the above advantages, or alternatively or additionally have other advantages. Attached Figure Description

[0016] The foregoing and other features and advantages of this disclosure will become clear from the following description of embodiments illustrated in conjunction with the accompanying drawings. The drawings, incorporated herein and forming a part of the specification, are further used to explain the principles of this disclosure and to enable those skilled in the art to make and use it. Wherein:

[0017] Figure 1 A schematic diagram of a non-volatile SRAM cell based on a resistive switching device according to an embodiment of the present disclosure is shown;

[0018] Figure 2 A schematic diagram of the characteristic curves of a resistive switching device according to an embodiment of the present disclosure is shown;

[0019] Figure 3 A timing diagram of a control method for a non-volatile SRAM cell according to an embodiment of the present disclosure is shown;

[0020] Figure 4 A flowchart is shown illustrating a method for controlling the writing of "0" to a non-volatile SRAM cell according to an embodiment of the present disclosure;

[0021] Figure 5 A flowchart is shown of a method for controlling the reading of data bits from a non-volatile SRAM cell according to an embodiment of the present disclosure.

[0022] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts with the same function, and repeated descriptions are omitted. In some cases, similar reference numerals and letters are used to denote similar items, so once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0023] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, this disclosure is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Detailed Implementation

[0024] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0025] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this disclosure or its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in this disclosure. However, those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and not exhaustive ways. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components.

[0026] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0027] To overcome the volatility of traditional SRAM and improve the area efficiency of non-volatile SRAM, this disclosure proposes a non-volatile SRAM cell structure based on resistive switching devices. The structural features and control method of the non-volatile SRAM cell according to this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the actual memory cell structure may include other additional components, and the control method may also include other additional steps; however, to avoid obscuring the key points of this disclosure, these other additional components or steps will not be discussed herein, and the accompanying drawings do not show them.

[0028] Figure 1 A schematic diagram of a non-volatile SRAM cell based on resistive switching devices according to an embodiment of the present disclosure is shown. As shown, the non-volatile SRAM cell 100 is composed of metal-oxide-semiconductor (MOS) field-effect transistors and resistive switching devices. Its cell structure adopts a 6T2R configuration, consisting of eight components including six field-effect transistors and two resistive switching devices. The field-effect transistors are a first P-type transistor PM1, a second P-type transistor PM2, a first N-type transistor NM1, a second N-type transistor NM2, a third N-type transistor NM3, and a fourth N-type transistor NM4; the resistive switching devices are a first resistive switching device RL and a second resistive switching device RR. Additionally, the non-volatile SRAM cell 100 also includes control lines, including a first word line WLL, a second word line WLR, a first bit line BL, a second bit line BLB, and a voltage line PL.

[0029] In some embodiments, the three devices on the left (first P-type transistor PM1, first resistive switching device RL, and third N-type transistor NM3) constitute the first data unit 110, and the three devices on the right (second P-type transistor PM2, second resistive switching device RR, and fourth N-type transistor NM4) constitute the second data unit 120. For example... Figure 1 As shown, the structure of SRAM cell 100 has a component distribution that is basically symmetrical on the left and right sides, that is, the first data cell 110 and the second data cell 120 form a cross-coupled structure in order to form a bistable data cell circuit.

[0030] In some embodiments, the connection relationship of the bistable data cell circuit in the SRAM cell 100 includes: for the first data cell 110, a first P-type transistor PM1, a first resistive switching device RL, and a third N-type transistor NM3 are sequentially connected in series between the power supply voltage VDD and the voltage line PL. The top of the first P-type transistor PM1 is connected to VDD, and the bottom of the third N-type transistor NM3 is connected to the voltage line PL. Correspondingly, for the second data cell 120, a second P-type transistor PM2, a second resistive switching device RR, and a fourth N-type transistor NM4 are sequentially connected in series between VDD and the voltage line PL, wherein the top of the second P-type transistor PM2 is connected to VDD, and the bottom of the fourth N-type transistor NM4 is connected to the voltage line PL.

[0031] Furthermore, the gates of the second P-type transistor PM2 and the fourth N-type transistor NM4 are connected to the first bit line BL, and the gates of the first P-type transistor PM1 and the third N-type transistor NM3 are connected to the second bit line BLB.

[0032] Additionally, the gate of the first N-type transistor NM1 is connected to the first word line WLL, and the gate of the second N-type transistor NM2 is connected to the second word line WLR.

[0033] In some embodiments, the first N-type transistor NM1 serves as a selection switch transistor in the first data unit 110, with one end of its source and drain connected between the first P-type transistor and the first resistive switching device RL, and the other end connected to the first bit line BL. The second N-type transistor NM2 serves as a selection switch transistor in the second data unit 120, with one end of its source and drain connected between the second P-type transistor and the second resistive switching device, and the other end connected to the second bit line BLB.

[0034] Furthermore, the cross-coupled structure formed by the first data unit 110 and the second data unit 120, as described above, can be used to store data bits. Specifically, the data bits of the SRAM unit 100 are determined by the resistance states of the first resistive switching device RL and the second resistive switching device RR. When the first resistive switching device RL is in a high resistance state (HRS) and the second resistive switching device is in a low resistance state (LRS), after stabilization, the first bit line BL is high and the second bit line BLB is low, at which point the non-volatile SRAM unit stores the data bit "1". Correspondingly, when the first resistive switching device RL is LRS and the second resistive switching device is HRS, after stabilization, the first bit line BL is low and the second bit line BLB is high, at which point the non-volatile SRAM unit stores the data bit "0".

[0035] In some embodiments, applying different voltages to two resistive switching devices can change their resistance state, thereby affecting the levels of the first bit line BL and the second bit line BLB, and thus changing the number of data storage bits. The characteristic curves of the resistive switching devices are shown below. Figure 2 As shown. The operation of changing the resistive switching device from HRS to LRS is called a SET operation, and the operation of changing it from LRS to HRS is called a RESET operation. That is, applying a forward voltage to the resistive switching device is a SET operation, and applying a reverse voltage to the resistive switching device is a RESET operation.

[0036] Understandably, compared to other non-volatile SRAM cells, the non-volatile SRAM cell disclosed herein does not require adding additional transistors to the traditional 6-transistor SRAM (6T-SRAM), and has almost no static power consumption when the data is stable. During the reading of data stored in the SRAM cell, since there is no voltage difference across the resistive switching device, the resistance state of the resistive switching device remains unchanged, ensuring the stability of the read data.

[0037] Based on the above-described unit structure, this disclosure further provides a control method for the aforementioned SRAM unit 100. Specifically, the 6T2R-SRAM in this disclosure mainly achieves different SRAM operations by adjusting the high and low levels of its five control lines, primarily including enabling the SRAM unit to perform data read / write and power-off operations. The data read / write operations can include writing "0", writing "1", reading "0", and reading "1", that is, writing "0" and writing "1" operations are used to change the stored data bits, and reading "0" and reading "1" operations are used to read the stored data bits.

[0038] Please refer to Figure 3 The diagram illustrates a timing diagram of a control method for a non-volatile SRAM cell according to an embodiment of the present disclosure. In chronological order, a write "0" operation 301, a read "0" operation 302, a write "1" operation 303, a read "1" operation 304, and a power-off operation 305 are performed on the SRAM cell, followed by a power-on operation 306 after a power-off.

[0039] In some embodiments, the write operation to the SRAM is described using write "0" operation 301 as an example. It can be understood that the SRAM cell in the initial state has stored data bits of "1", that is, the first resistive switching device RL is HRS and the second resistive switching device RR is LRS. (See reference...) Figure 4The diagram illustrates a flowchart of a method 400 for controlling the writing of "0" to a non-volatile SRAM cell according to an embodiment of the present disclosure. In step S401, the first word line WLL and the second bit line BLB are raised to a high level, turning on the first N-type transistor NM1 and the third N-type transistor NM3. At this time, the first bit line BL is raised to a high level and the voltage line PL is lowered to a low level, resulting in a positive voltage difference and positive current in the first resistive switching device RL, and its resistance state changes from HRS to LRS; while there is no voltage difference across the second resistive switching device RR, and its state remains unchanged. Next, in step S402, all control lines are lowered to a low level, which is equivalent to de-energizing the circuit to preserve the resistance state (LRS) of the first resistive switching device RL. Subsequently, in step S403, the second word line WLR and the first bit line BL are raised to a high level, turning on the second N-type transistor NM2 and the fourth N-type transistor NM4. At this point, the second bit line BLB drops to a low level and the voltage line PL rises to a high level. Therefore, a reverse voltage difference and reverse current exist in the second resistive switching device RR, and its resistance state changes from LRS to HRS. Meanwhile, there is no voltage difference across the first resistive switching device RL, and its state remains unchanged. After completing the above operations, in step S404, all control lines are again dropped to a low level to save the resistance state (HRS) of the second resistive switching device RR. Thus, the resistance states of the resistive switching devices RL and RR have been reversed compared to their initial states, and the data bits store 0, completing the write-"0" operation.

[0040] Correspondingly, if it is necessary to perform a write "1" operation 303 on the SRAM, the second resistive switching device RR can be converted to LRS and the first resistive switching device RL can be converted to HRS in sequence. The process is similar to method 400 and will not be described in detail here.

[0041] In some embodiments, the reading of a "0" operation 302 on the data bits stored in the SRAM cell is described as an example. Please refer to... Figure 5The diagram illustrates a flowchart of a method 500 for controlling the reading of data bits from a non-volatile SRAM cell according to an embodiment of the present disclosure. At this time, the data bit stored in the SRAM cell is "0", i.e., the first resistive switching device RL is LRS and the second resistive switching device RR is HRS. In step S501, the first word line WLL, the second word line WLR, and the voltage line PL are raised to a high level, causing the first bit line BL and the second bit line BLB to also be raised to a high level. In step S502, the voltage line PL is lowered to a low level, causing both the first bit line BL and the second bit line BLB to be pulled to approximately VDD / 2. The entire SRAM cell circuit is in a metastable state. Since the resistance of the first resistive switching device RL is smaller than that of the second resistive switching device RR, the discharge speed is faster. Therefore, the first bit line BL on the left is lowered to a low voltage, while the cross-coupling structure of the circuit causes the second bit line BLB on the right to be raised to a high voltage. Therefore, in step S503, in response to the comparison between the resistance states of the first resistive switching device RL and the second resistive switching device RR, the data bit "0" can be read from the levels on the first bit line BL and the second bit line BLB. Correspondingly, in the read "1" operation 304, since the first resistive switching device RL is HRS and the second resistive switching device RR is LRS at this time, after the operation of method 500, the levels of the first bit line BL and the second bit line BLB are reversed, thus reading the data bit "1". (Continue to refer to...) Figure 3 When performing the data reading operation, the voltage difference across the resistive switching device will only produce a negligible small fluctuation when the voltage line PL is pulled low (step S502), which is insufficient to change the resistance state of the resistive switching device. In other words, this method can accurately read the data bits without causing other effects on the circuit, thus improving the stability of the data reading.

[0042] Further reference Figure 3 During power-off operation 305, all power supplies in the circuit are turned off, and the levels of all control lines are pulled low. However, since the voltage difference across the resistive switching device is not affected, the data in the non-volatile SRAM cell remains valid. The power-off operation depletes the charge within the cell, but upon power-on, the data returns to its state before the power-off operation. For example, when performing a read "1" operation 306, the original data can be restored and read back based on the resistance state of the resistive switching device after power-on.

[0043] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the scope of this disclosure. Unless the context explicitly indicates otherwise, the singular forms “a” and “the” as used herein are intended to include the plural forms as well. It should also be understood that the word “comprising”, as used herein, indicates the presence of the indicated feature, integral, step, operation, unit, and / or component, but does not preclude the presence or addition of one or more other features, integrals, steps, operations, units, and / or components, and / or combinations thereof. Furthermore, in the description of this disclosure, the terms “first,” “second,” etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or order. Additionally, in the description of this disclosure, unless otherwise stated, “a plurality of” means two or more.

[0044] In this specification, references to "embodiment" or similar expressions mean that a specific feature, structure, or characteristic described in connection with that embodiment is included in at least one specific embodiment of this disclosure. Therefore, the use of phrases such as "in an embodiment of this disclosure" and similar expressions in this specification does not necessarily refer to the same embodiment.

[0045] Those skilled in the art will understand that this disclosure can be implemented in various forms, such as a completely hardware embodiment, a completely software embodiment (including firmware, resident software, microprogram code, etc.), or a software and hardware embodiment, hereinafter referred to as a "circuit," "module," "unit," or "system." Furthermore, this disclosure can also be implemented in any tangible media as a computer program product having computer-usable program code stored thereon.

[0046] The description herein is based on flowcharts and / or block diagrams of systems, apparatuses, methods, and computer program products according to specific embodiments of this disclosure. It will be understood that each block in each flowchart and / or block diagram, and any combination of blocks in the flowcharts and / or block diagrams, can be implemented using computer program instructions. These computer program instructions are executable by a machine comprising a processor of a general-purpose computer or a special-purpose computer, or other programmable data processing means, and are processed by the computer or other programmable data processing means to perform the functions or operations described in the flowcharts and / or block diagrams.

[0047] The accompanying drawings illustrate flowcharts and block diagrams showing the architecture, functionality, and operation of systems, apparatuses, methods, and computer program products achievable according to various embodiments of the present disclosure. Thus, each block in a flowchart or block diagram may represent a module, segment, or portion of program code, including one or more executable instructions to implement a specified logical function. It should also be noted that in some other embodiments, the functions described in a block may not be performed in the order shown in the figures. For example, two blocks illustrated as connected may actually be executed simultaneously, or in some cases, depending on the functions involved, they may be executed in the reverse order shown in the figures. Furthermore, it should be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, may be implemented by a system based on dedicated hardware, or by a combination of dedicated hardware and computer instructions, to perform specific functions or operations.

[0048] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technical improvements to market technology of the embodiments, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A non-volatile SRAM cell based on a resistive switching device, comprising: Field-effect transistors, including a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, and a fourth N-type transistor; Resistive switching devices, including a first resistive switching device and a second resistive switching device; and Control lines, including the first word line, second word line, first bit line, second bit line, and voltage lines. In this configuration, the first P-type transistor, the first resistive switching device, and the third N-type transistor are connected in series between the power supply voltage and the voltage line, and the second P-type transistor, the second resistive switching device, and the fourth N-type transistor are connected in series between the power supply voltage and the voltage line. The gates of the second P-type transistor and the fourth N-type transistor are connected to the first bit line, and the gates of the first P-type transistor and the third N-type transistor are connected to the second bit line. The gate of the first N-type transistor is connected to the first word line, and the gate of the second N-type transistor is connected to the second word line.

2. The SRAM cell according to claim 1, wherein: The source and drain of the first N-type transistor are respectively connected between the first P-type transistor and the first resistive switching device, and also connected to the first bit line; as well as The source and drain of the second N-type transistor are connected between the second P-type transistor and the second resistive switching device, and are also connected to the second bit line, respectively.

3. The SRAM cell according to claim 1, wherein: The first P-type transistor, the first resistive switching device, and the third N-type transistor constitute the first data unit, and the second P-type transistor, the second resistive switching device, and the fourth N-type transistor constitute the second data unit. The first data unit and the second data unit form a cross-coupled structure.

4. The SRAM cell according to claim 3, wherein: In response to the first resistive switching device being set to a high-resistance state and the second resistive switching device being set to a low-resistance state, the first bit line is set to a high level and the second bit line is set to a low level, thereby causing the SRAM cell to store data bit 1.

5. The SRAM cell according to claim 3, wherein: In response to the first resistive switching device being set to a low-resistance state and the second resistive switching device being set to a high-resistance state, the first bit line is set to a low level and the second bit line is set to a high level, thereby causing the SRAM cell to store data bit 0.

6. A control method for an SRAM cell as described in any one of claims 1 to 5, comprising: The SRAM cell is made to perform data read / write and power-off operations by adjusting the control lines.

7. The control method according to claim 6, wherein: When the first word line and the second bit line are raised to a high level, the first N-type transistor and the third N-type transistor are turned on, thereby raising the first bit line to a high level and lowering the voltage line to a low level, so that the first resistive switching device is switched to a low-resistance state. Lower all control lines to low level; When the second word line and the first word line are raised to a high level, the second N-type transistor and the fourth N-type transistor are turned on, causing the second bit line to fall to a low level and the voltage line to rise to a high level, thus causing the second resistive switching device to switch to a high-impedance state; and All control lines are brought low to enable the SRAM cell to perform a data write operation and store data bit 0.

8. The control method according to claim 6, wherein: When the second word line and the first word line are raised to a high level, the second N-type transistor and the fourth N-type transistor are turned on, thereby raising the second bit line to a high level and lowering the voltage line to a low level, so that the second resistive switching device is switched to a low-resistance state. Lower all control lines to low level; When the first word line and the second bit line are raised to a high level, the first N-type transistor and the third N-type transistor are turned on, causing the first bit line to drop to a low level and the voltage line to be raised to a high level, thus causing the first resistive switching device to switch to a high-impedance state; and All control lines are brought low to enable the SRAM cell to perform a data write operation and store a data bit 1.

9. The control method according to claim 6, wherein: The first word line, the second word line, and the voltage line are raised to a high level, so that the first bit line and the second bit line are raised to a high level; The voltage line is brought down to a low level, so that the first and second bit lines are switched to half of the power supply voltage; as well as In response to a comparison between the resistance states of the first resistive switching device and the second resistive switching device, the data bits stored in the SRAM cell are read out based on the levels of the first bit line and the second bit line.

10. The control method according to claim 6, wherein: All control lines are brought low to cause the SRAM cell to perform a power-off operation.

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