Bitwise operation method for a SONOS memory array

Abstract

A method for bit-by-bit operation of a SONOS memory array, the array comprising a plurality of memory cells arranged in an array, each cell comprising a select transistor and first and second memory transistors. The array is configured with bit lines, source lines, select word lines and memory word lines. The method comprises: selecting the memory transistors to perform an operation as selected memory transistors and non-selected memory transistors; applying a non-selected bias voltage to the memory word lines, bit lines or source lines connected to the non-selected memory transistors to eliminate the voltage difference or leakage current required to perform the current operation, thereby inhibiting the non-selected memory transistors from performing a write or erase operation. In a read operation, the non-selected memory transistors in the same cell as the selected memory transistors are turned on to provide a conductive path. In an erase or write operation, a negative voltage difference is superimposed on the voltage applied to each control line so that the relative voltage difference between each end point remains unchanged. The present application does not require additional byte select transistors, achieves bit-by-bit operation and greatly saves the silicon area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit design, and more particularly to a bitwise operation method for a SONOS memory array. Background Technology

[0002] SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory devices are non-volatile memories with extremely high reliability and data retention capabilities. Traditional SONOS memory devices require erasing an entire row during the erase operation, rather than erasing bits individually. The principle behind this is that during the erase operation, a negative voltage needs to be applied to the gate of the memory transistor to allow holes in the channel to enter the ONO (Oxide-Nitride-Oxide) layer, thus erasing an entire row of memory transistors sharing the gate. Because a negative voltage is applied to the gate, the channel is closed. Since the gates in the same row are connected together (sharing a word line), when attempting to erase a specific cell in this row, the negative voltage is applied to the entire row. Even if a positive voltage is applied to the drain (or source) terminal where the specific cell (i.e., the one implementing Inhibit erasure) is located, since the channel is closed at this time, this positive voltage cannot be transmitted into the channel and therefore cannot cancel the negative voltage of the gate. Thus, an erase will inevitably erase the entire row.

[0003] In existing technologies, to create an EEPROM (Electrically Erasable Programmable Read-Only Memory) that can be modified byte by byte, an additional byte select transistor must be provided for each byte in the array. This relies on physical switches to block cells that do not need to be erased. This results in the storage array area increasing by about 100%, which is a waste of silicon space. Furthermore, reducing the area of ​​the storage array is not only due to the reduction in the size of the SONOS storage cells, but is also limited by the size of the byte select transistor, which makes it difficult to reduce the size of the EEPROM storage array. Summary of the Invention

[0004] The problem solved by this invention is that traditional SONOS memory devices cannot perform bit-by-bit erasure during erasure, requiring the addition of byte selectors in the array, which leads to a significant increase in the storage array area.

[0005] To address the aforementioned problems, this invention provides a bitwise operation method for a SONOS memory array. The SONOS memory array includes: multiple memory cells arranged in an array, each memory cell including a select transistor and two first and second memory transistors; the array is configured with multiple bit lines, multiple source lines, multiple select word lines, and multiple memory word lines; the select transistor is connected to the corresponding select word line; the first and second memory transistors are respectively connected to the corresponding bit lines, source lines, and memory word lines; the bitwise operation method includes: designating the first or second memory transistor selected to perform the current bitwise operation as the selected memory transistor, and designating the first or second memory transistor not selected to perform the current bitwise operation as the non-selected memory transistor; applying a non-selection bias voltage to the memory word line, bit line, or source line connected to the non-selected memory transistor; the non-selection bias voltage is configured to eliminate the voltage difference or leakage current required to perform the current bitwise operation, thereby suppressing the non-selected memory transistor from performing the current bitwise operation, the current bitwise operation including a write or erase operation.

[0006] Optionally, the bit-by-bit operation method includes: applying a voltage to the select word line to control the select transistor to be in an off or on state; and applying an operation bias voltage to the memory word line, bit line, or source line connected to the selected memory transistor to generate a voltage difference or leakage current required to perform the current bit-by-bit operation on the selected memory transistor.

[0007] Optionally, the bitwise operation further includes a read operation, which includes: turning on a non-selected memory tube located in the same memory cell as the selected memory tube, so as to provide a conductive path for the selected memory tube to perform the current bitwise operation.

[0008] Optionally, each column of the array corresponds to a bit line and a source line; the drain and source of the first and second memory transistors in the same column are respectively connected to the bit line and the source line corresponding to that column; each row of the array corresponds to a select word line and a corresponding memory word line; in the same row of memory cells, the gates of the select transistors are all connected to the select word line corresponding to that row; the gates of the first and second memory transistors in the same memory cell are connected to the same memory word line.

[0009] Optionally, the bit-by-bit operation includes a bit-by-bit erase operation. During the bit-by-bit erase operation: the first memory transistor is the selected memory transistor, and the second memory transistor is the unselected memory transistor; a turn-off voltage is applied to all the selected word lines; an erase voltage is applied to the memory word lines connected to the selected memory transistor, and a ground voltage is applied to the bit lines connected to the selected memory transistor and the first memory transistor in its column, so that the selected memory transistor undergoes gate carrier tunneling; an erase suppression voltage is applied to the source line connected to the second memory transistor located in the same memory cell as the selected memory transistor; an unselected gate voltage is applied to all the remaining memory word lines, and the erase suppression voltage is applied to all the remaining bit lines and source lines, so that the memory transistors that do not undergo erase operation do not undergo gate carrier tunneling; wherein, the erase time of the bit-by-bit erase operation is 1 to 10 milliseconds.

[0010] Optionally, the bitwise operation includes a bitwise write operation. During the bitwise write operation: when the first memory transistor is the selected memory transistor and the second memory transistor is the unselected memory transistor, a write enable voltage is applied to the select word line corresponding to the memory cell where the first memory transistor is located, and a turn-off voltage is applied to all other select word lines; a write gate voltage is applied to the memory word line connected to the first memory transistor, a write bit line voltage is applied to the bit line or source line connected to the first memory transistor, and a write bit line voltage is applied to the second memory word line in the same memory cell as the first memory transistor. A ground voltage is applied to the bit line or source line connected to the storage tube to induce leakage current in the channel where the first storage tube is located, and hot electron injection occurs under the action of the write gate voltage; while the second storage tube in the storage cell does not undergo hot electron injection; a non-selected write gate voltage is applied to all the remaining storage word lines, and the write bit line voltage is applied to the remaining column bit lines and source lines to ensure that there is no voltage difference between the bit lines and source lines in the storage cells where no write operation is performed, so that hot electron injection does not occur; wherein, the write time of the bit-by-bit write operation is 2 to 15 microseconds.

[0011] Optionally, the bitwise operation includes a bitwise read operation. During the bitwise read operation: when the first memory transistor is the selected memory transistor and the second memory transistor is the unselected memory transistor, a read-on voltage is applied to the select word line corresponding to the memory cell where the first memory transistor is located, and a turn-off voltage is applied to all the remaining select word lines; a ground voltage is applied to all the memory word lines; a read-limit voltage is applied to the bit line or source line connected to the second memory transistor located in the same memory cell as the first memory transistor, and a ground voltage is applied to the bit lines and source lines of the remaining columns, so as to turn on the second memory transistor and thereby read the data of the first memory transistor.

[0012] Optionally, each column of the array corresponds to a bit line and a source line; the drain and source of the first and second memory transistors in the same column are respectively connected to the bit line and the source line corresponding to that column; each row of the array corresponds to a select word line and a corresponding memory word line; in the same row of memory cells, the gates of the select transistors are all connected to the select word line corresponding to that row; the gates of the first and second memory transistors in the same memory cell are respectively connected to different memory word lines.

[0013] Optionally, the bit-by-bit operation includes a bit-by-bit erase operation. During the bit-by-bit erase operation: a turn-off voltage is applied to all the select word lines; an erase voltage is applied to the memory word lines connected to the selected memory transistor, and a ground voltage is applied to the bit lines or source lines connected to the selected memory transistor to cause gate carrier tunneling in the selected memory transistor; a non-selected gate voltage is applied to the memory word lines connected to the non-selected memory transistors located in the same memory cell as the selected memory transistor, and an erase suppression voltage is applied to the bit lines or source lines connected to the non-selected memory transistors located in the same memory cell as the selected memory transistor; the non-selected gate voltage is applied to all the remaining memory word lines, and the erase suppression voltage is applied to all the remaining bit lines and source lines to prevent gate carrier tunneling in memory transistors that do not undergo an erase operation; wherein the erase time of the bit-by-bit erase operation is 1 to 10 milliseconds.

[0014] Optionally, the bitwise operation includes a bitwise write operation. During the bitwise write operation: when the first memory transistor is the selected memory transistor and the second memory transistor is the unselected memory transistor, a write enable voltage is applied to the select word line corresponding to the memory cell where the first memory transistor is located, and a turn-off voltage is applied to all other select word lines; a write gate voltage is applied to the memory word line connected to the first memory transistor, and a bypass gate voltage is applied to the memory word line connected to the second memory transistor within the same memory cell; a write bit line voltage is applied to the bit line or source line connected to the first memory transistor, and a ground voltage is applied to the bit line or source line connected to the second memory transistor within the same memory cell as the first memory transistor, so that the first memory transistor performs a write operation, while the second memory transistor within the same memory cell does not perform a write operation; a non-selected write gate voltage is applied to all other memory word lines, and the write bit line voltage is applied to the bit lines and source lines of the remaining columns; wherein the write time of the bitwise write operation is 2~15 microseconds.

[0015] Optionally, the bitwise operation includes a bitwise read operation. During the bitwise read operation: when the first memory transistor is the selected memory transistor and the second memory transistor is the unselected memory transistor, a read-on voltage is applied to the select word line corresponding to the memory cell where the first memory transistor is located, and a turn-off voltage is applied to all other select word lines; a bypass conduction voltage is applied to the memory word line connected to the second memory transistor located in the same memory cell as the first memory transistor, and a ground voltage is applied to all other memory word lines; a read-limit voltage is applied to the bit line or source line connected to the first memory transistor, and a ground voltage is applied to all other bit lines and source lines, so that the second memory transistor is turned on, thereby reading the data from the first memory transistor.

[0016] Optionally, the substrate of the array is a P-type well; during the bit-by-bit erasure operation, the P-type well is grounded or a voltage identical to the turn-off voltage is applied.

[0017] Optionally, in the storage unit, the first storage tube, the selection tube, and the second storage tube are connected in series.

[0018] Optionally, the first and second storage transistors include: an ONO composite layer on the substrate and a storage gate structure on the ONO composite layer; the select transistor includes an oxide layer on the substrate and a select gate on the oxide layer, the select gate being located between the storage gate structures of the first and second storage transistors and isolated by the ONO composite layer; the ONO composite layer is formed by stacking a tunneling oxide layer, a charge storage layer and a barrier oxide layer sequentially from top to bottom.

[0019] Optionally, during a bit-by-bit erase or bit-by-bit write operation, a negative voltage difference is superimposed on the voltages applied to the select word line, the memory word line, the bit line, and the source line to keep the relative voltage difference between the terminals of the selected memory tube and the non-selected memory tube constant.

[0020] Compared with existing technologies, the technical solution of the present invention has the following advantages: The bit-by-bit operation method for a SONOS memory array provided by the present invention, during the erase operation, applies a suppression voltage to the drain (or source) of memory transistors that do not need to be erased. This voltage can be smoothly transmitted into the channel to reduce the voltage difference across the ONO composite layer and prevent FN tunneling. Through this bit-by-bit operation, the present invention can realize the bit-by-bit erase function of the EEPROM array without setting additional byte select transistors in the array, thereby solving the problem of the difficulty in reducing the area of ​​traditional arrays, greatly saving silicon wafer area, and also getting rid of the size constraints of byte select transistors on device miniaturization.

[0021] Furthermore, when the array is configured such that two memory transistors within the same memory cell are connected to the same memory word line (i.e., a shared gate connection), the two row select transistors can share a single memory word line, requiring only one contact hole. Compared to the case where they do not share a gate, this effectively alleviates the congestion problem of contact holes and metal interconnects, and is more conducive to reducing the size of the memory array in the column direction. In addition, the write operation uses a hot carrier injection method combined with different word line, bit line, and source line bias voltage control to ensure that bit-by-bit writing does not interfere with other unselected memory transistors in the same row or column. Attached Figure Description

[0022] Figure 1 The diagram shown is a schematic diagram of the storage cell structure of the present invention. Figure 2 The diagram shows the circuit structure of the SONOS memory array of the present invention when it is connected to a common gate and performing bit-by-bit erasure operation. Figure 3 The diagram shows the circuit structure of the SONOS memory array of the present invention when it is connected to a common gate and performing bit-by-bit write operation. Figure 4 The diagram shows the circuit structure of the SONOS memory array of the present invention when it shares a gate and performs bit-by-bit read operations. Figure 5 The diagram shows the circuit structure of the SONOS memory array of the present invention when it is not connected to a common gate and performs bit-by-bit erasure operation. Figure 6 The diagram shows the circuit structure of the SONOS memory array of the present invention when it is not connected to a common gate and performs bit-by-bit write operation. Figure 7 The diagram shows the circuit structure of the SONOS memory array of the present invention when it is not connected to a common gate and performs bit-by-bit read operation. Figure 8 The diagram shown is a circuit structure schematic of Embodiment 1 of the present invention; Figure 9 The diagram shows a schematic of the structure of each memory cell in Embodiment 1 of the present invention with applied bias voltage; Figure 10 The diagram shown is a circuit structure schematic of Embodiment 2 of the present invention; Figure 11 The diagram shows a schematic of the structure of each memory cell in Embodiment 2 of the present invention with applied bias voltage; Figure 12 The diagram shown is a circuit structure schematic of Embodiment 3 of the present invention; Figure 13 The diagram shows the structure of each memory cell with applied bias voltage in Embodiment 3 of the present invention; Figure 14The diagram shown is a circuit structure schematic of Embodiment 4 of the present invention; Figure 15 The diagram shows the structure of each memory cell with applied bias voltage in Embodiment 4 of the present invention; Figure 16 The diagram shown is a circuit structure schematic of Embodiment 5 of the present invention; Figure 17 The diagram shows a schematic of the structure of each memory cell in Embodiment 5 of the present invention with applied bias voltage; Figure 18 The diagram shown is a circuit structure schematic of Embodiment Six of the present invention; Figure 19 The diagram shows the structure of each memory cell with applied bias voltage in Embodiment Six of the present invention. Detailed Implementation

[0023] As is known from the background art, traditional SONOS memory devices in the prior art are prone to problems such as the inability to erase bits-by-bit, resulting in a significant increase in memory array area and difficulty in miniaturization. To solve these technical problems, the present invention provides a bit-by-bit operation method for a SONOS memory array, comprising: The SONOS memory array includes: multiple memory cells arranged in an array, each memory cell including a select transistor and two first and second memory transistors; the array is configured with multiple bit lines, multiple source lines, multiple select word lines, and multiple memory word lines; the select transistor is connected to the corresponding select word line; the first and second memory transistors are respectively connected to the corresponding bit lines, source lines, and memory word lines; the bitwise operation method includes: designating the first or second memory transistor selected to perform the current bitwise operation as the selected memory transistor, and designating the first or second memory transistor not selected to perform the current bitwise operation as the non-selected memory transistor; applying a non-selection bias voltage to the memory word line, bit line, or source line connected to the non-selected memory transistor; the non-selection bias voltage is configured to eliminate the voltage difference or leakage current required to perform the current bitwise operation, thereby suppressing the non-selected memory transistor from performing the current bitwise operation, the current bitwise operation including a write or erase operation.

[0024] Furthermore, the bit-by-bit operation method includes: applying a voltage to the select word line to control the select transistor to be in an off or on state; applying an operating bias voltage to the memory word line, bit line, or source line connected to the selected memory transistor to generate the voltage difference or leakage current required to perform the current bit-by-bit operation on the selected memory transistor. In this process, the select transistor acts as a master valve, determining whether the entire memory cell combination participates in the current operation; and by applying corresponding operating bias voltages to the bit line, source line, and memory word line, an effective electric field or channel leakage condition can be established at the selected target memory transistor to trigger hot electron injection (to achieve data writing) or gate carrier FN tunneling (to achieve data erasure).

[0025] Furthermore, the bitwise operation also includes a read operation, which involves turning on a non-selected memory transistor located in the same memory cell as the selected memory transistor, thereby providing a conductive path for the selected memory transistor to perform the current bitwise operation. Since within a segmented memory cell, two memory transistors are located on opposite sides of the selected transistor and are connected in series, when reading the data state of one of the selected transistors, the non-selected memory transistors within the same cell that are not being read must be forcibly turned on. After the non-selected memory transistors are turned on, the current in the entire series path is determined by the internal state of the selected memory transistor, thus ensuring the accuracy of data reading.

[0026] Furthermore, each column of the array corresponds to a bit line and a source line; the drain and source of the first and second memory transistors in the same column memory cell are respectively connected to the bit line and the source line corresponding to that column; each row of the array corresponds to a select word line and a corresponding memory word line; in the same row memory cell, the gate of the select transistor is connected to the select word line corresponding to that row; the gates of the first and second memory transistors in the same memory cell are connected to the same memory word line.

[0027] This array connection method uses a shared gate structure, where two memory transistors within the same memory cell share a single memory word line, allowing two rows of select memory transistors to be connected via only one contact hole. Compared to cases where the gates are not shared, this shared gate connection method significantly reduces the number of contact holes, avoiding excessive crowding of contact holes and metal interconnects, which is extremely beneficial for further miniaturization of the memory array in the column direction.

[0028] like Figure 1 As shown, Figure 1The diagram shows a schematic of the storage cell structure of the present invention. In the storage cell of the present invention, the first storage transistor, the select transistor, and the second storage transistor are connected in series. Further, the first and second storage transistors include: an ONO composite layer on the substrate 1, and a storage gate structure 3 on the ONO composite layer; the select transistor includes an oxide layer 2 on the substrate 1 and a select gate 4 on the oxide layer 2, the select gate 4 being located between the storage gate structures 3 of the first and second storage transistors and isolated by the ONO composite layer; the ONO composite layer is formed by stacking a tunneling oxide layer 6, a charge storage layer 7, and a barrier oxide layer 8 from top to bottom.

[0029] Source / drain injection regions 5 are respectively provided on the side of the first and second memory transistors away from the select transistor, and are connected to the channel region by LDD 9. The ONO composite layer not only covers the space between the memory gate structure and the substrate 1, but also extends and covers the sidewall between the memory gate structure and the select gate. The first and second memory transistors share the select transistor, and the three together constitute the memory cell. Further, the substrate of the array in this invention is a P-type well; during the bit-by-bit erase operation, the P-type well is grounded or a voltage of the same as the turn-off voltage is applied.

[0030] Example 1

[0031] This embodiment provides a method for performing bit-by-bit erasure operations when memory cells in a SONOS memory array share a common gate. For example... Figure 2 As shown, Figure 2 The diagram shows the circuit structure of the SONOS memory array of the present invention when it shares a common gate and performs bit-by-bit erasure operations.

[0032] Each column of the array corresponds to a bit line (BL) and a source line (SL); the drain and source of the first and second memory transistors within the same column are respectively connected to the bit line (BL) and the source line (SL) corresponding to that column. For example, the drain of the first memory transistor (e.g., A1 and A2) is connected to bit line BL1, and the drain of the second memory transistor (e.g., A1 and A2) is connected to bit line BL1. and A The source of the first memory transistor (such as B1 and B2) is connected to the source line SL1; the drain of the second memory transistor (such as B1 and B2) is connected to the bit line BL2; and the drain of the third memory transistor (such as B1 and B2) is connected to the bit line BL2. and B The source of the signal is connected to the source line SL2.

[0033] Each row of the array corresponds to a select word line (WL) and a corresponding memory word line (WLS). Within the same row of memory cells, the gates of the select transistors are all connected to the corresponding select word line (WL). The select transistors act as a central valve, controlled by the select word lines (e.g., select word lines WL1 and WL2). The first memory transistor (e.g., A1) and the second memory transistor (e.g., A2) within the same memory cell... The gates of the memory words are connected to the same memory word line (such as WLS1).

[0034] like Figure 2 As shown, during the bit-by-bit erase operation: the first memory tube A1 is the selected memory tube, and the second memory tube A... For the unselected memory transistor, apply a turn-off voltage (i.e., ground voltage Vgnd) to all the select word lines (e.g., WL1, WL2); apply an erase voltage (Vpos) to the memory word line (WLS1) connected to the selected memory transistor; apply ground voltage Vgnd to the bit line (BL1) connected to the selected memory transistor A1 and the first memory transistor in its column (e.g., A2) to cause gate carrier tunneling in the selected memory transistor A1; and apply ground voltage Vgnd to the second memory transistor (e.g., A2) located in the same memory cell as the selected memory transistor A1. An erase suppression voltage (Vinh) is applied to the source line (SL1) connected to the memory word line (e.g., WLS2); a non-selected gate voltage (VposU) is applied to the remaining bit lines and source lines (e.g., BL2, SL2), and the erase suppression voltage (Vinh) is applied to the remaining bit lines and source lines, so that the memory transistors (e.g., A) that do not perform erase operations are not affected. B1, B A2, A B2, B No gate carrier tunneling occurs.

[0035] During the erase operation, a turn-off voltage (ground voltage Vgnd) is applied to all select word lines, and the P-type well (PW) is also connected to Vgnd, thus putting all the selected transistors in the off state. For the selected memory transistor A1: an erase voltage (Vpos) is applied to the memory word line (WLS1) connected to it, and a ground voltage Vgnd is applied to the bit line (BL1, i.e., the selected memory transistor near the BL end) connected to it. At this time, the voltage difference across the selected memory transistor A1 is Vpos, creating a sufficiently downward electric field in its internal ONO composite layer, inducing the injection of holes into the ONO composite layer to cause gate carrier tunneling, thereby realizing the bit-by-bit erase operation. For unselected memory transistors, the voltage difference is controlled to prevent gate carrier tunneling: unselected transistors in the same cell: for the second memory transistor A1 located in the same memory cell as A1... The pressure difference across the tube drops to Vpos–Vinh. For unselected tubes in the same row: for other unselected memory cells in the same row (such as B1, B...), The corresponding bit line (BL2) and source line (SL2) are both subject to the erase suppression voltage (Vinh), so that they are subjected to the same voltage difference of Vpos-Vinh.

[0036] For unselected cell transistors in a row: when an unselected gate voltage (VposU) is applied to the remaining cell word lines (such as WLS2), the voltage difference across these unselected cell transistors in the row is VposU - Vinh or VposU - Vgnd.

[0037] In this embodiment, the values ​​of each bias voltage are in the following ranges: Vpos: 7~9V, VposU: 1-2V, Vinh: 4-5V, vgnd: 0V. Furthermore, the erase time is configured to be 1~10 milliseconds during the bit-by-bit erase operation.

[0038] like Figure 8 As shown Figure 8 The diagram shown is a circuit structure schematic of Embodiment 1 of the present invention; Figure 9 The diagram shows the structure of each memory cell with applied bias voltage in Embodiment 1 of the present invention. Further, in this embodiment, the values ​​of each bias voltage are: Vpos = 9V, VposU: 1.1V, Vinh: 4V.

[0039] The bias conditions for the selected row (first row) are as follows: the bias voltage Vpos of the memory word line WLS1 is 9V, providing a high potential for all memory transistors in this row. The bias voltage Vgnd of the select word line WL1 is 0V, turning off all the select transistors in the middle of this row, ensuring that BL1 and SL1 are physically isolated within the cell.

[0040] VposU is 1.1V, applying a low safety voltage to the unselected row to reduce the voltage difference between the gate and channel. The bias voltage Vgnd of the select word lines WL2 / WLn is 0V, keeping all select transistors in the unselected row off. The bias voltage Vgnd of the bit line BL1 is 0V to match the 9V of the memory word line WLS1, maximizing the voltage difference of memory transistor A1. The bias voltage Vinh of the source line SL1 is 4V to suppress the voltage difference of memory transistor A1 within the same memory cell. Erasing. BL2 / SL2 to BLn / SLn are all connected to 4V to suppress the erasing action of other cells in the same row (such as B1) and other columns of the entire array, while the substrate PW is connected to 0V. During erasure, the gates of all selected transistors are connected to Vgnd, PW is connected to Vgnd, and all selected transistors are turned off; for the selected memory transistor, its BL terminal is connected to Vgnd, the WLS of the selected row is connected to Vpos, the voltage difference is Vpos, and there is a sufficient downward electric field in the ONO composite layer of the selected memory transistor, so that the holes of the gate are injected into the ONO composite layer, realizing the erasure operation; for the unselected memory transistor, BL / SL are both connected to Vinh, the WLS of the unselected row is connected to VposU, then the applied voltage difference is Vpos-Vinh (selected row), or VposU-Vinh (unselected row), there is no sufficient downward electric field in the ONO composite layer, so that the holes of the gate cannot be injected into the ONO composite layer, and the erasure operation cannot be realized.

[0041] Example 2

[0042] This second embodiment provides a method for performing bit-by-bit write operations when the memory cells in a SONOS memory array share a common gate. Figure 3 The diagram shows the circuit structure of the SONOS memory array of the present invention when it shares a common gate and performs bit-by-bit write operations.

[0043] like Figure 10 , Figure 11 As shown, Figure 10 The diagram shown is a circuit structure schematic of Embodiment 2 of the present invention; Figure 11 The diagram shows the structure of each memory cell with applied bias voltages in Embodiment 2 of the present invention. In this embodiment, the values ​​of each bias voltage range are: Vpos: 7~9V, VposU: 1-2V, Vbl: 3-6V, vgnd: 0V. Further, the values ​​of each bias voltage are: Vpos=9V, VposU=1.1V, Vbl=4V, Vwl=0.1V, vgnd=0V. Furthermore, during the bit-by-bit write operation, the write time is configured to be 2~15 microseconds.

[0044] The bitwise operation includes a bitwise write operation. During the bitwise write operation: when the first memory tube (e.g., A1) is the selected memory tube, the second memory tube (e.g., A...)... B A B When the first memory transistor (e.g., A1) is not selected, a write enable voltage Vwl is applied to the select word line WL1 corresponding to the memory cell where the first memory transistor (e.g., A1) is located. (This applies a weak enable voltage. This voltage puts the select transistor in a semi-conducting or slightly conducting state, thereby limiting and controlling the channel current.) A turn-off voltage (vgnd = 0 V) ​​is applied to all other select word lines (WL2…WLn). A write gate voltage WLS1 (Vpos = 9 V, providing a high gate voltage to attract and capture hot electrons) is applied to the memory word line connected to the first memory transistor (e.g., A1). A write bit line voltage (Vbl = 4 V, providing a high potential as the drain terminal) is applied to the bit line BL1 connected to the first memory transistor. A write bit line voltage (Vbl = 4 V, providing a high potential as the drain terminal) is applied to the second memory transistor (e.g., A1) located in the same memory cell as the first memory transistor (e.g., A1). A ground voltage (vgnd=0V) is applied to the source line (SL1 is grounded as the source terminal) connected to the first memory transistor (e.g., A1), causing leakage current to be generated in the channel where the first memory transistor (e.g., A1) is located, and hot electron injection occurs under the action of the write gate voltage; while the second memory transistor (e.g., A1) in the memory cell... No hot electron injection occurs, meaning a potential difference is formed between BL1 (4V) and SL1 (0V). Due to the weak conduction of WL1, a controlled leakage current is generated in the channel.

[0045] A non-selected write gate voltage (VposU=1.1V) is applied to the remaining memory word lines (such as WLS2…WLSn, with extremely low voltage, insufficient to attract electrons into the memory layer), and the write bit line voltage (Vbl=4V, with no voltage difference between the left and right ends of the same cell) is applied to the remaining bit lines and source lines (such as BL2 / SL2…BLn / SLn) to ensure that there is no voltage difference between the bit lines and source lines in memory cells where no write operation is performed, so as to prevent hot electron injection.

[0046] The storage unit includes storage tubes (A1, A...) The first memory transistor A1 performs bit-by-bit writing, with its drain (BL1) at 4V and its gate (WLS1) at 9V. Since WL1 (0.1V) opens the current path, electrons accelerate from SL1 to BL1. In the high electric field region near the gate of A1, electrons gain enough energy to become hot electrons and are attracted by the high voltage of WLS1, crossing the energy barrier and being injected into the ONO composite layer.

[0047] Unselected storage tube A within the same unit Although its gate voltage is also 9V, its proximity to the source (SL1=0V) means that the potential distribution does not provide the energy required for hot electron injection, thus preventing write operations. This cell generates leakage current and hot electron injection occurs under the influence of the write gate voltage.

[0048] In the unselected cells of the same row (such as B1 / B) (Voltage suppression) Although the gate WLS1 is 9V, its bit line BL2 and source line SL2 are both 4V. There is no voltage difference between the bit line and the source line (both are 4V), so no current flows in the channel, and the prerequisite for generating hot electrons is not met, thus suppressing write operations.

[0049] In the same column of unselected cells (e.g., A2 / A) Although BL1 is 4V and SL1 is 0V, creating a voltage difference, the selector line WL2 is 0V. The intermediate selector is turned off, disconnecting A2 from A... There is no leakage current passing through, and the voltage of WLS2 (1.1V) is extremely low, so no hot electron injection occurs.

[0050] In other units, such as B2 / B When the selector transistor WL2 is turned off (0V) and there is no voltage difference between the bit line and the source line (both are 4V), the storage gate voltage is extremely low (1.1V), so it is completely in a quiescent state.

[0051] Example 3

[0052] This third embodiment provides a method for performing bit-by-bit read operations when memory cells in a SONOS memory array share a common gate. For example... Figure 4 As shown, Figure 4 The diagram shows the circuit structure of the SONOS memory array of the present invention when it shares a common gate and performs bit-by-bit read operations. Figure 12 The diagram shown is a circuit structure schematic of Embodiment 3 of the present invention; Figure 13 The diagram shows the structure of each memory cell with applied bias voltage in Embodiment 3 of the present invention. In this embodiment, the value range of each bias voltage is: vgnd: 0 V, Vlim: 0.85-3V, Vpwr: 1-2.5V. Further, the value of each bias voltage is: Vlim=2V, Vpwr=2V, vgnd=0 V.

[0053] In this embodiment, the bitwise operation includes a bitwise read operation. During the bitwise read operation: when the first memory transistor (e.g., A1) is the selected memory transistor and the second memory transistor (e.g., A2) is the unselected memory transistor, a read-on voltage (Vpwr=2V) is applied to the select word line WL1 corresponding to the memory cell where the first memory transistor is located, and a turn-off voltage (vgnd=0V) is applied to all the other select word lines; a ground voltage (vgnd=0V) is applied to all the memory word lines (e.g., WLS1, WLS2, etc.); and a read-off voltage (vgnd=0V) is applied to the second memory transistor (A1) located in the same memory cell as the first memory transistor. A read limit voltage (Vlim=2V) is applied to the source line (SL1) connected to the second memory transistor (A), and a ground voltage is applied to the remaining bit lines and source lines to enable the second memory transistor (A) to read the source line (SL1 ... The selected memory tube (A1) is turned on, thus reading the data from the first memory tube A1. The unselected memory tube (A1) is turned on. Because the applied read limit voltage (Vlim=2V) causes the N+ at the SL1 terminal to expand into a depletion region, lowering the channel barrier, the unselected memory transistor (A) becomes more vulnerable. The selected transistor A1 is turned on, thus reading its state. For unselected transistors in the same row, SL2 and BL2 are both connected to Vgnd, with the same voltage, and there is no current in the channel. For other unselected rows, WL2 and others are grounded, the selected transistors are completely turned off, and there is no current.

[0054] Figure 12 In the process of bit-by-bit reading of the first memory transistor A1, the array voltage distribution is as follows: Row selection: A read-on voltage Vpwr, with a value of 2V, is applied to the select word line WL1 corresponding to the memory cell containing the first memory transistor. This voltage turns on the select transistor in the middle of the selected cell, connecting the internal path. Simultaneously, a ground voltage Vgnd, i.e., 0V, is applied to all memory word lines such as WLS1 and WLS2. Column selection: A second memory transistor A1 located in the same memory cell as the first memory transistor... A read limit voltage Vlim, with a value of 2V, is applied to the source line SL1. Simultaneously, a ground voltage Vgnd, i.e., 0V, is applied to the bit line BL1 connected to the selected memory transistor A1. For unselected rows and columns: a shutdown voltage Vgnd, i.e., 0V, is applied to the remaining select word lines such as WL2, completely turning off the select transistor. A ground voltage Vgnd is applied to the remaining bit lines and source lines such as BL2 and SL2.

[0055] Figure 13 In the middle, select cell A1 / A (Top left image): In this cell, a 2V read limit voltage is applied to the source terminal SL1 of the unselected memory transistor A1. This causes the N+ region at the SL1 terminal to expand into a depletion region, thereby lowering the channel barrier and allowing the unselected memory transistor A1 to... The circuit remains on even when the gate voltage is 0V. Since the intermediate select word line WL1 is already enabled by 2V, the current path of the entire cell is connected. At this point, by measuring the current at the bit line BL1, the data status of the selected memory transistor A1 on the other side can be read.

[0056] For unselected cells B1 / B in the same row (Top right image) Although the select word line WL1 for this row is enabled, since the corresponding bit line BL2 and source line SL2 are both connected to ground voltage Vgnd, the voltages are the same. Therefore, no current is generated in its channel, and it will not interfere with the read operation.

[0057] For the unselected row cell A2 / A (Lower left figure) For the unselected row, although there is a 2V voltage on the source line SL1, the select transistor in the row is completely turned off because the select word line WL2 of that row is grounded by the voltage Vgnd. This cuts off the current path for all memory cells in that row, so no current is generated.

[0058] For the remaining unselected units B2 / B (Lower right figure): The selector tube of this unit is turned off by WL2, and there is no pressure difference between bit line BL2 and source line SL2, so it is in a completely static state.

[0059] Example 4

[0060] This fourth embodiment provides a method for performing bit-by-bit erasure operations when the memory cells in a SONOS memory array do not share a common gate. Figure 5 The diagram shows the circuit structure of the SONOS memory array of the present invention when it is not connected to a common gate and performs bit-by-bit erasure operation. Figure 5 In the array, each column corresponds to a bit line (e.g., BL1, BL2) and a source line (SL1, SL2); the first memory transistor A1 and the second memory transistor A1 within the same column of memory cells... The drain and source of the transistor are respectively connected to the bit line BL1 and the source line SL1 corresponding to the column; each row of the array corresponds to a select word line (e.g., WL1, WL2) and a corresponding memory word line (e.g., WLS1, WLS1, WLS2, WLS2); in the same row of memory cells, the gate of the select transistor is connected to the select word line (e.g., WL1, WL2) corresponding to that row; the gates of the first and second memory transistors in the same memory cell are respectively connected to different memory word lines (e.g., WLS1, WLS2 ... ).

[0061] The first storage tube A1 is the selected storage tube, and the second storage tube A The selected memory transistor A1 is a non-selected memory transistor. The bit-by-bit operation includes a bit-by-bit erase operation. During the bit-by-bit erase operation: a turn-off voltage Vgnd is applied to all the select word lines WL1 and WL2; an erase voltage Vpos is applied to the memory word line WLS1 connected to the selected memory transistor A1; and a ground voltage Vgnd is applied to the bit line BL1 connected to the selected memory transistor A1 to cause gate carrier tunneling in the selected memory transistor A1. The non-selected memory transistor A1, located in the same memory cell as the selected memory transistor A1, is then... The connected storage word line WLS Apply a non-selected gate voltage VposU to the non-selected memory transistor A1, which is located in the same memory cell as the selected memory transistor A1. An erase suppression voltage Vinh is applied to the source line SL1; the unselected gate voltage VposU is applied to the remaining memory word lines WLS2 and WLS2, and the erase suppression voltage Vinh is applied to the remaining bit lines BL2 and source line SL2, so that gate carrier tunneling does not occur in memory transistors that are not being erased.

[0062] Figure 14 The diagram shown is a circuit structure schematic of Embodiment 4 of the present invention; Figure 15 The diagram shown is a schematic diagram of the structure of each memory cell with applied bias voltage in Embodiment 4 of the present invention.

[0063] For the selected memory transistor A1, a turn-off voltage Vgnd (0V) is applied to its selected word line WL1, an erase voltage Vpos (9V) is applied to its memory word line WLS1, and a ground voltage Vgnd (0V) is applied to its bit line BL1. At this time, a sufficiently high potential difference is formed between the gate and channel of the selected memory transistor A1, causing gate carrier tunneling to occur in A1 (as shown by hole h+ injection in the figure), thus completing the erasure of that bit. For the non-selected memory transistor A1 located in the same memory cell as the selected memory transistor A1... The memory word line WLS1 connected to it is subject to an unselected gate voltage VposU (1.1V), and the source line SL1 is subject to an erase suppression voltage Vinh (4V). Because its gate voltage VposU is low and the erase suppression voltage Vinh is applied to the source, the electric field strength between the gate and the channel is insufficient to induce carrier tunneling, thus ensuring that memory transistor A1 does not perform an erase operation. For memory transistors B1 and B2 in the same row of unselected memory cells... Although the memory word line WLS1 is also 9V, the corresponding bit line BL2 and source line SL2 are both subject to an erase suppression voltage Vinh (4V). This reduces the voltage difference between the gate and the channel, suppresses the tunneling effect, and thus prevents accidental erasures. For unselected row memory cells such as A2 / A... and B2 / B When the corresponding select word line WL2 is turned off by a voltage Vgnd (0V), all memory word lines WLS2 and WLS... 、WLsn、WLs A non-selected gate voltage VposU (1.1V) is applied to all transistors. Since the gate potentials of these transistors are all at a low 1.1V, the gate carrier tunneling condition is not met, so no erase operation is performed. A turn-off voltage Vgnd (0V) is applied to all select word lines WL1, WL2, and WLn, turning off all select transistors in the array. A ground voltage Vgnd (0V) is applied to the substrate PW to provide a uniform reference potential. Through the above bias voltage configuration, bit-by-bit erasure is achieved only for the selected transistor A1, and the erase time of this bit-by-bit erasure operation is preferably 1~10 milliseconds.

[0064] Example 5

[0065] This fifth embodiment provides a method for performing bit-by-bit write operations when the memory cells in a SONOS memory array do not share a common gate. Figure 6 The diagram shows the circuit structure of the SONOS memory array of the present invention when it is not connected to a common gate and performs bit-by-bit write operations. Figure 16 The diagram shown is a circuit structure schematic of Embodiment 5 of the present invention; Figure 17 The diagram shown is a schematic diagram of the structure of each memory cell with applied bias voltage in Embodiment 5 of the present invention.

[0066] The bitwise operation includes a bitwise write operation. During the bitwise write operation: when the first memory transistor is the selected memory transistor and the second memory transistor is the unselected memory transistor, a write enable voltage is applied to the select word line corresponding to the memory cell where the first memory transistor is located, and a turn-off voltage is applied to all other select word lines; a write gate voltage is applied to the memory word line connected to the first memory transistor, and a bypass gate voltage is applied to the memory word line connected to the second memory transistor within the same memory cell; a write bit line voltage is applied to the bit line or source line connected to the first memory transistor, and a ground voltage is applied to the bit line or source line connected to the second memory transistor within the same memory cell as the first memory transistor, so that the first memory transistor performs a write operation, while the second memory transistor within the same memory cell does not perform a write operation; an unselected write gate voltage is applied to all other memory word lines, and the write bit line voltage is applied to the bit lines and source lines of the remaining columns.

[0067] When the first storage tube A1 is the selected storage tube, the second storage tube A When the first memory transistor A1 is not selected, a write enable voltage Vwl (0.1V) is applied to the select word line WL1 corresponding to the memory cell where the first memory transistor A1 is located, and a turn-off voltage Vgnd (0V) is applied to the other select word lines WL2 and WLn.

[0068] A write gate voltage Vpos (9V) is applied to the memory word line WLS1 connected to the first memory transistor A1, and a write gate voltage of Vpos (9V) is applied to the second memory transistor A1 in the same memory cell. Connected storage word line WLS Apply a bypass gate voltage Vso (3V).

[0069] A write bit line voltage Vbl (4V) is applied to the bit line BL1 connected to the first memory transistor A1, and a second memory transistor A1 located in the same memory cell as the first memory transistor A1 is applied to the bit line BL1 connected to the first memory transistor A1. The connected source line SL1 is grounded with a voltage Vgnd (0V).

[0070] Under this bias condition, due to the second storage tube A WLS (Memory Word Line) A 3V bypass voltage was applied, turning on the channel. Electrons started from the source line SL1, which was given a 0V voltage, and passed through the bypassed second storage transistor A1. And the selector transistor WL1 is slightly turned on, flowing to the drain side of the first storage transistor A1. Under the 9V high voltage applied to the gate of the first storage transistor A1, electrons gain energy on the side near the selector transistor and are injected into the charge storage layer (such as...). Figure 17 As shown in Figure e-, this causes the first memory tube A1 to perform a write operation, while the second memory tube A1 in the same memory cell... It is used only as a path bypass and no write operation is performed.

[0071] The write bit line voltage Vbl (4V) is applied to the remaining bit lines BL2, BLn and source lines SL2, SLn. Due to the unselected cells B1 / B1 in the same row... Both the bit line BL2 and the source line SL2 are 4V, and there is no voltage difference that generates current, so there will be no accidental writing.

[0072] To the remaining storage word lines WLS2, WLS 、WLsn、WLs A non-selected write gate voltage VposU (1.1V) is applied to all rows. In the non-selected rows, since the select word lines WL2 and WLn are at the ground voltage Vgnd (0V), the select transistor is turned off, cutting off the current path, and the low gate voltage VposU is insufficient to trigger electron injection, thus ensuring that no write operation occurs in the memory transistors of the non-selected rows.

[0073] A ground voltage Vgnd (0V) is applied to the substrate PW to maintain a stable potential. With the above voltage configuration, writing to a specific memory transistor A1 in the array is achieved, and the write time of this bit-by-bit write operation is preferably 2 to 15 microseconds.

[0074] Example 6

[0075] This sixth embodiment provides a method for performing bit-by-bit read operations when the memory cells in a SONOS memory array do not share a common gate. Figure 7 The diagram shows the circuit structure of the SONOS memory array of the present invention when it is not connected to a common gate and performs bit-by-bit read operation. Figure 18 The diagram shown is a circuit structure schematic of Embodiment Six of the present invention; Figure 19 The diagram shows the structure of each memory cell with applied bias voltage in Embodiment Six of the present invention.

[0076] The bitwise operation includes a bitwise read operation. During the bitwise read operation: when the first memory transistor is the selected memory transistor and the second memory transistor is the unselected memory transistor, a read-on voltage is applied to the select word line corresponding to the memory cell where the first memory transistor is located, and a turn-off voltage is applied to all other select word lines; a bypass conduction voltage is applied to the memory word line connected to the second memory transistor located in the same memory cell as the first memory transistor, and a ground voltage is applied to all other memory word lines; a read-limit voltage is applied to the bit line or source line connected to the first memory transistor, and a ground voltage is applied to all other bit lines and source lines, so that the second memory transistor is turned on, thereby reading the data from the first memory transistor.

[0077] When the first storage tube A1 is the selected storage tube A1, the second storage tube A When the first memory transistor A1 is not selected, a read enable voltage Vpwr (2V) is applied to the select word line WL1 corresponding to the memory cell where the first memory transistor A1 is located, and a turn-off voltage Vgnd (0V) is applied to the other select word lines WL2 and WLn.

[0078] To the second storage tube A1 located in the same storage cell as the first storage tube A1 A bypass on-state voltage Vso (3V) is applied to the connected memory word line WLS1, and the remaining memory word lines WLS1, WLS2, and WLS3 are connected to it. WLsn, WLsn A grounding voltage Vgnd (0V) is applied to all of them.

[0079] A read limit voltage Vlim (0.85V) is applied to the bit line BL1 connected to the first memory transistor A1, and a ground voltage Vgnd (0V) is applied to the remaining bit lines BL2, BLn and source lines SL1, SL2, SLn. Under this bias condition, due to the second memory transistor A1 Connected storage word line WLS1 A bypass on-state voltage Vso (3V) was applied, causing the second memory transistor A1 to... It is in the ON state. At the same time, the read enable voltage Vpwr (2V) on the select word line WL1 turns on the select transistor for that row.

[0080] The gate of the first memory transistor A1 is connected to the memory word line WLS1 at the ground voltage Vgnd (0V), and its conduction depends on the charge state stored in the transistor (i.e., the threshold voltage).

[0081] The current starts from bit line BL1, which is subjected to the read limit voltage Vlim (0.85V), and flows through the first memory transistor A1, the selected transistor that is turned on, and the second memory transistor A1 that is bypassed. Finally, it flows to the source line SL1, which is the ground voltage Vgnd (0V).

[0082] By detecting the current magnitude along this path, the data state stored in the first memory transistor A1 can be determined. A ground voltage Vgnd (0V) is applied to the substrate PW to maintain a stable potential. Other unselected rows (such as A2 / A...) When the select word lines WL2 and WLn are 0V, the select transistor is turned off, thus cutting off the current path. Other unselected columns (such as B1 / B1...) Both the bit line BL2 and the source line SL2 are 0V, so there is no voltage difference and therefore no read current is generated, achieving accurate bit-by-bit reading.

[0083] Furthermore, in the bit-by-bit operation method of the present invention, when performing a bit-by-bit erase operation or a bit-by-bit write operation, a negative voltage difference is superimposed on the voltage applied to the select word line, the memory word line, the bit line, and the source line, so as to keep the relative voltage difference between the terminals of the selected memory tube and the non-selected memory tube constant.

[0084] During bit-by-bit erase or bit-by-bit write operations, a single negative voltage difference Vneg is simultaneously applied to all control terminals, including the select word line WL1, storage word line WLS1, bit line BL1, and source line SL1, causing the absolute potentials of each port to decrease synchronously. For the selected memory transistor A1, since the storage word line WLS1 connected to its gate, the bit line BL1 connected to its source / drain, the source line SL1, and the substrate PW are all simultaneously superimposed with the same negative bias, the relative voltage difference (potential difference) between them remains constant. Taking the erase operation as an example, if the storage word line WLS1 is 9V and the bit line BL1 is 0V in the original state, after superimposing a negative voltage difference of 3V, the voltage of the storage word line WLS1 becomes 6V, and the voltage of the bit line BL1 becomes negative 3V. The relative voltage difference between them remains at 9V, so the electric field strength inside the selected memory transistor A1 remains unchanged, and the gate carrier tunneling effect can still occur normally. For the unselected memory transistor A... For the other memory transistors in the array, since the voltages of all their connected control lines are also shifted downwards by the same magnitude, the voltage differences originally used to suppress erasure or write operations (such as the difference between the erase suppression voltage Vinh and the unselected gate voltage VposU) remain unchanged. This voltage superposition method effectively reduces the circuit's dependence on extremely high positive voltages without changing the physical operating state of the memory transistors, helping to alleviate the voltage withstand burden on the external drive circuitry. The substrate PW also needs to simultaneously superimpose this negative voltage difference to ensure that the bias relationship between the source / drain junction and the substrate remains stable, preventing breakdown or leakage. Through voltage shifting, the system can perform bit-by-bit operations on the selected memory transistor A1 within the voltage range.

[0085] This invention enables the bit-by-bit erasure function of an EEPROM array through bit-by-bit operation, eliminating the need for additional byte select transistors in the array. This solves the problem of the traditional array area being difficult to reduce, greatly saving silicon wafer area and freeing the device from the size constraints imposed by byte select transistors on device miniaturization.

[0086] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A bitwise operation method for a SONOS memory array, the SONOS memory array comprising: Multiple memory cells are arranged in an array, each memory cell including a select transistor and two first and second memory transistors; the array is configured with multiple bit lines, multiple source lines, multiple select word lines and multiple memory word lines; the select transistor is connected to the corresponding select word line; the first and second memory transistors are respectively connected to the corresponding bit lines, source lines and memory word lines; The bitwise operation method is characterized by comprising: The first or second memory tube that is selected to perform the current bitwise operation is designated as the selected memory tube, and the first or second memory tube that is not selected to perform the current bitwise operation is designated as the unselected memory tube; An unselected bias voltage is applied to the memory word line, bit line, or source line connected to the unselected memory transistor; the unselected bias voltage is configured to eliminate the voltage difference or leakage current required to perform the current bit operation, thereby suppressing the unselected memory transistor from performing the current bit operation, which includes a write or erase operation.

2. The bitwise operation method according to claim 1, characterized in that, The bit-by-bit operation method includes: applying a voltage to the select word line to control the select transistor to be in an off or on state; and applying an operation bias voltage to the memory word line, bit line, or source line connected to the selected memory transistor to generate a voltage difference or leakage current required to perform the current bit-by-bit operation on the selected memory transistor.

3. The bitwise operation method according to claim 2, characterized in that, The bitwise operation also includes a read operation, which includes: turning on a non-selected memory tube located in the same memory cell as the selected memory tube, so as to provide a conductive path for the selected memory tube to perform the current bitwise operation.

4. The bitwise operation method according to claim 2, characterized in that, Each column of the array corresponds to a bit line and a source line; the drain and source of the first and second memory transistors in the same column are respectively connected to the bit line and the source line corresponding to that column; each row of the array corresponds to a select word line and a corresponding memory word line; In the same row of memory cells, the gates of the select transistors are all connected to the select word line corresponding to that row; the gates of the first and second memory transistors in the same memory cell are connected to the same memory word line.

5. The bitwise operation method according to claim 4, characterized in that, The bit-by-bit operation includes a bit-by-bit erase operation. During the bit-by-bit erase operation: the first memory transistor is the selected memory transistor, and the second memory transistor is the unselected memory transistor; a turn-off voltage is applied to all the selected word lines; an erase voltage is applied to the memory word lines connected to the selected memory transistor; a ground voltage is applied to the bit lines connected to the selected memory transistor and the first memory transistor in its column, so that the selected memory transistor undergoes gate carrier tunneling; and an erase suppression voltage is applied to the source line connected to the second memory transistor located in the same memory cell as the selected memory transistor. A non-selected gate voltage is applied to all the remaining memory word lines, and the erase suppression voltage is applied to all the remaining bit lines and source lines, so that gate carrier tunneling does not occur in memory transistors that are not being erased; wherein the erase time of the bit-by-bit erase operation is 1 to 10 milliseconds.

6. The bitwise operation method according to claim 4, characterized in that, The bitwise operation includes a bitwise write operation. During the bitwise write operation: when the first memory transistor is the selected memory transistor and the second memory transistor is the unselected memory transistor, a write enable voltage is applied to the select word line corresponding to the memory cell where the first memory transistor is located, and a turn-off voltage is applied to the remaining select word lines; a write gate voltage is applied to the memory word line connected to the first memory transistor, a write bit line voltage is applied to the bit line or source line connected to the first memory transistor, and a ground voltage is applied to the bit line or source line connected to the second memory transistor in the same memory cell as the first memory transistor, so that leakage current is generated in the channel where the first memory transistor is located, and hot electron injection occurs under the action of the write gate voltage; while the second memory transistor in the memory cell does not undergo hot electron injection; an unselected write gate voltage is applied to the remaining memory word lines, and the write bit line voltage is applied to the remaining column of bit lines and source lines, so that there is no voltage difference between the bit lines and source lines in the memory cells where no write operation is performed, so that hot electron injection does not occur; wherein, the write time of the bitwise write operation is 2~15 microseconds.

7. The bitwise operation method according to claim 4, characterized in that, The bitwise operation includes a bitwise read operation. When performing the bitwise read operation: when the first memory transistor is the selected memory transistor and the second memory transistor is the unselected memory transistor, a read-on voltage is applied to the select word line corresponding to the memory cell where the first memory transistor is located, and a turn-off voltage is applied to the remaining select word lines; a ground voltage is applied to all the memory word lines; a read-limit voltage is applied to the bit line or source line connected to the second memory transistor located in the same memory cell as the first memory transistor, and a ground voltage is applied to the remaining bit lines and source lines, so as to turn on the second memory transistor, thereby reading the data from the first memory transistor.

8. The bitwise operation method according to claim 3, characterized in that, Each column of the array corresponds to a bit line and a source line; the drain and source of the first and second memory transistors in the same column are respectively connected to the bit line and the source line corresponding to that column; each row of the array corresponds to a select word line and a corresponding memory word line; In the same row of memory cells, the gates of the select transistors are all connected to the select word line corresponding to that row; the gates of the first and second memory transistors in the same memory cell are respectively connected to different memory word lines.

9. The bitwise operation method according to claim 8, characterized in that, The first memory transistor is the selected memory transistor, and the second memory transistor is the unselected memory transistor. The bit-by-bit operation includes a bit-by-bit erase operation. During the bit-by-bit erase operation: a turn-off voltage is applied to all the selected word lines; an erase voltage is applied to the memory word lines connected to the selected memory transistor; a ground voltage is applied to the bit lines or source lines connected to the selected memory transistor to cause gate carrier tunneling in the selected memory transistor; an unselected gate voltage is applied to the memory word lines connected to the unselected memory transistor located in the same memory cell as the selected memory transistor; and an erase suppression voltage is applied to the bit lines or source lines connected to the unselected memory transistor located in the same memory cell as the selected memory transistor. The unselected gate voltage is applied to all the remaining memory word lines, and the erase suppression voltage is applied to all the remaining bit lines and source lines, so that gate carrier tunneling does not occur in memory transistors that do not perform an erase operation; wherein the erase time of the bit-by-bit erase operation is 1 to 10 milliseconds.

10. The bitwise operation method according to claim 8, characterized in that, The bitwise operation includes a bitwise write operation. When performing the bitwise write operation: when the first memory transistor is the selected memory transistor and the second memory transistor is the unselected memory transistor, a write enable voltage is applied to the select word line corresponding to the memory cell where the first memory transistor is located, and a turn-off voltage is applied to all other select word lines; a write gate voltage is applied to the memory word line connected to the first memory transistor, and a bypass gate voltage is applied to the memory word line connected to the second memory transistor in the same memory cell; A write bit line voltage is applied to the bit line or source line connected to the first memory transistor, and a ground voltage is applied to the bit line or source line connected to the second memory transistor in the same memory cell as the first memory transistor, so that the first memory transistor performs a write operation, while the second memory transistor in the same memory cell does not perform a write operation; a non-selected write gate voltage is applied to all the remaining memory word lines, and the write bit line voltage is applied to the bit lines and source lines of the remaining columns; wherein, the write time of the bit-by-bit write operation is 2 to 15 microseconds.

11. The bitwise operation method according to claim 8, characterized in that, The bitwise operation includes a bitwise read operation. During the bitwise read operation: when the first memory transistor is the selected memory transistor and the second memory transistor is the unselected memory transistor, a read-on voltage is applied to the select word line corresponding to the memory cell where the first memory transistor is located, and a turn-off voltage is applied to all other select word lines; a bypass conduction voltage is applied to the memory word line connected to the second memory transistor located in the same memory cell as the first memory transistor, and a ground voltage is applied to all other memory word lines; a read-limit voltage is applied to the bit line or source line connected to the first memory transistor, and a ground voltage is applied to all other bit lines and source lines, so that the second memory transistor is turned on, thereby reading the data from the first memory transistor.

12. The bitwise operation method according to any one of claims 1 to 11, characterized in that, The array is based on a P-type well; during the bit-by-bit erasure operation, the P-type well is grounded or subjected to the same voltage as the turn-off voltage.

13. The bitwise operation method according to any one of claims 1 to 11, characterized in that, In the aforementioned storage unit, the first storage transistor, the selection transistor, and the second storage transistor are connected in series.

14. The bitwise operation method according to claim 13, characterized in that, The first and second storage transistors each include an ONO composite layer on a substrate and a storage gate structure on the ONO composite layer. The selection transistor includes an oxide layer on the substrate and a selection gate on the oxide layer. The selection gate is located between the storage gate structures of the first and second storage transistors and is isolated by the ONO composite layer. The ONO composite layer is formed by stacking a tunneling oxide layer, a charge storage layer, and a barrier oxide layer from top to bottom.

15. The bitwise operation method according to claim 1, characterized in that, During a bit-by-bit erase or bit-by-bit write operation, a negative voltage difference is superimposed on the voltages applied to the select word line, the memory word line, the bit line, and the source line to keep the relative voltage difference between the terminals of the selected memory tube and the non-selected memory tube constant.

Images